1/*
2 *  MIPS emulation for QEMU - nanoMIPS translation routines
3 *
4 *  Copyright (c) 2004-2005 Jocelyn Mayer
5 *  Copyright (c) 2006 Marius Groeger (FPU operations)
6 *  Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 *  Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
8 *  Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
9 *
10 * SPDX-License-Identifier: LGPL-2.1-or-later
11 */
12
13/* MAJOR, P16, and P32 pools opcodes */
14enum {
15    NM_P_ADDIU      = 0x00,
16    NM_ADDIUPC      = 0x01,
17    NM_MOVE_BALC    = 0x02,
18    NM_P16_MV       = 0x04,
19    NM_LW16         = 0x05,
20    NM_BC16         = 0x06,
21    NM_P16_SR       = 0x07,
22
23    NM_POOL32A      = 0x08,
24    NM_P_BAL        = 0x0a,
25    NM_P16_SHIFT    = 0x0c,
26    NM_LWSP16       = 0x0d,
27    NM_BALC16       = 0x0e,
28    NM_P16_4X4      = 0x0f,
29
30    NM_P_GP_W       = 0x10,
31    NM_P_GP_BH      = 0x11,
32    NM_P_J          = 0x12,
33    NM_P16C         = 0x14,
34    NM_LWGP16       = 0x15,
35    NM_P16_LB       = 0x17,
36
37    NM_P48I         = 0x18,
38    NM_P16_A1       = 0x1c,
39    NM_LW4X4        = 0x1d,
40    NM_P16_LH       = 0x1f,
41
42    NM_P_U12        = 0x20,
43    NM_P_LS_U12     = 0x21,
44    NM_P_BR1        = 0x22,
45    NM_P16_A2       = 0x24,
46    NM_SW16         = 0x25,
47    NM_BEQZC16      = 0x26,
48
49    NM_POOL32F      = 0x28,
50    NM_P_LS_S9      = 0x29,
51    NM_P_BR2        = 0x2a,
52
53    NM_P16_ADDU     = 0x2c,
54    NM_SWSP16       = 0x2d,
55    NM_BNEZC16      = 0x2e,
56    NM_MOVEP        = 0x2f,
57
58    NM_POOL32S      = 0x30,
59    NM_P_BRI        = 0x32,
60    NM_LI16         = 0x34,
61    NM_SWGP16       = 0x35,
62    NM_P16_BR       = 0x36,
63
64    NM_P_LUI        = 0x38,
65    NM_ANDI16       = 0x3c,
66    NM_SW4X4        = 0x3d,
67    NM_MOVEPREV     = 0x3f,
68};
69
70/* POOL32A instruction pool */
71enum {
72    NM_POOL32A0    = 0x00,
73    NM_SPECIAL2    = 0x01,
74    NM_COP2_1      = 0x02,
75    NM_UDI         = 0x03,
76    NM_POOL32A5    = 0x05,
77    NM_POOL32A7    = 0x07,
78};
79
80/* P.GP.W instruction pool */
81enum {
82    NM_ADDIUGP_W = 0x00,
83    NM_LWGP      = 0x02,
84    NM_SWGP      = 0x03,
85};
86
87/* P48I instruction pool */
88enum {
89    NM_LI48        = 0x00,
90    NM_ADDIU48     = 0x01,
91    NM_ADDIUGP48   = 0x02,
92    NM_ADDIUPC48   = 0x03,
93    NM_LWPC48      = 0x0b,
94    NM_SWPC48      = 0x0f,
95};
96
97/* P.U12 instruction pool */
98enum {
99    NM_ORI      = 0x00,
100    NM_XORI     = 0x01,
101    NM_ANDI     = 0x02,
102    NM_P_SR     = 0x03,
103    NM_SLTI     = 0x04,
104    NM_SLTIU    = 0x05,
105    NM_SEQI     = 0x06,
106    NM_ADDIUNEG = 0x08,
107    NM_P_SHIFT  = 0x0c,
108    NM_P_ROTX   = 0x0d,
109    NM_P_INS    = 0x0e,
110    NM_P_EXT    = 0x0f,
111};
112
113/* POOL32F instruction pool */
114enum {
115    NM_POOL32F_0   = 0x00,
116    NM_POOL32F_3   = 0x03,
117    NM_POOL32F_5   = 0x05,
118};
119
120/* POOL32S instruction pool */
121enum {
122    NM_POOL32S_0   = 0x00,
123    NM_POOL32S_4   = 0x04,
124};
125
126/* P.LUI instruction pool */
127enum {
128    NM_LUI      = 0x00,
129    NM_ALUIPC   = 0x01,
130};
131
132/* P.GP.BH instruction pool */
133enum {
134    NM_LBGP      = 0x00,
135    NM_SBGP      = 0x01,
136    NM_LBUGP     = 0x02,
137    NM_ADDIUGP_B = 0x03,
138    NM_P_GP_LH   = 0x04,
139    NM_P_GP_SH   = 0x05,
140    NM_P_GP_CP1  = 0x06,
141};
142
143/* P.LS.U12 instruction pool */
144enum {
145    NM_LB        = 0x00,
146    NM_SB        = 0x01,
147    NM_LBU       = 0x02,
148    NM_P_PREFU12 = 0x03,
149    NM_LH        = 0x04,
150    NM_SH        = 0x05,
151    NM_LHU       = 0x06,
152    NM_LWU       = 0x07,
153    NM_LW        = 0x08,
154    NM_SW        = 0x09,
155    NM_LWC1      = 0x0a,
156    NM_SWC1      = 0x0b,
157    NM_LDC1      = 0x0e,
158    NM_SDC1      = 0x0f,
159};
160
161/* P.LS.S9 instruction pool */
162enum {
163    NM_P_LS_S0         = 0x00,
164    NM_P_LS_S1         = 0x01,
165    NM_P_LS_E0         = 0x02,
166    NM_P_LS_WM         = 0x04,
167    NM_P_LS_UAWM       = 0x05,
168};
169
170/* P.BAL instruction pool */
171enum {
172    NM_BC       = 0x00,
173    NM_BALC     = 0x01,
174};
175
176/* P.J instruction pool */
177enum {
178    NM_JALRC    = 0x00,
179    NM_JALRC_HB = 0x01,
180    NM_P_BALRSC = 0x08,
181};
182
183/* P.BR1 instruction pool */
184enum {
185    NM_BEQC     = 0x00,
186    NM_P_BR3A   = 0x01,
187    NM_BGEC     = 0x02,
188    NM_BGEUC    = 0x03,
189};
190
191/* P.BR2 instruction pool */
192enum {
193    NM_BNEC     = 0x00,
194    NM_BLTC     = 0x02,
195    NM_BLTUC    = 0x03,
196};
197
198/* P.BRI instruction pool */
199enum {
200    NM_BEQIC    = 0x00,
201    NM_BBEQZC   = 0x01,
202    NM_BGEIC    = 0x02,
203    NM_BGEIUC   = 0x03,
204    NM_BNEIC    = 0x04,
205    NM_BBNEZC   = 0x05,
206    NM_BLTIC    = 0x06,
207    NM_BLTIUC   = 0x07,
208};
209
210/* P16.SHIFT instruction pool */
211enum {
212    NM_SLL16    = 0x00,
213    NM_SRL16    = 0x01,
214};
215
216/* POOL16C instruction pool */
217enum {
218    NM_POOL16C_0  = 0x00,
219    NM_LWXS16     = 0x01,
220};
221
222/* P16.A1 instruction pool */
223enum {
224    NM_ADDIUR1SP = 0x01,
225};
226
227/* P16.A2 instruction pool */
228enum {
229    NM_ADDIUR2  = 0x00,
230    NM_P_ADDIURS5  = 0x01,
231};
232
233/* P16.ADDU instruction pool */
234enum {
235    NM_ADDU16     = 0x00,
236    NM_SUBU16     = 0x01,
237};
238
239/* P16.SR instruction pool */
240enum {
241    NM_SAVE16        = 0x00,
242    NM_RESTORE_JRC16 = 0x01,
243};
244
245/* P16.4X4 instruction pool */
246enum {
247    NM_ADDU4X4      = 0x00,
248    NM_MUL4X4       = 0x01,
249};
250
251/* P16.LB instruction pool */
252enum {
253    NM_LB16       = 0x00,
254    NM_SB16       = 0x01,
255    NM_LBU16      = 0x02,
256};
257
258/* P16.LH  instruction pool */
259enum {
260    NM_LH16     = 0x00,
261    NM_SH16     = 0x01,
262    NM_LHU16    = 0x02,
263};
264
265/* P.RI instruction pool */
266enum {
267    NM_SIGRIE       = 0x00,
268    NM_P_SYSCALL    = 0x01,
269    NM_BREAK        = 0x02,
270    NM_SDBBP        = 0x03,
271};
272
273/* POOL32A0 instruction pool */
274enum {
275    NM_P_TRAP   = 0x00,
276    NM_SEB      = 0x01,
277    NM_SLLV     = 0x02,
278    NM_MUL      = 0x03,
279    NM_MFC0     = 0x06,
280    NM_MFHC0    = 0x07,
281    NM_SEH      = 0x09,
282    NM_SRLV     = 0x0a,
283    NM_MUH      = 0x0b,
284    NM_MTC0     = 0x0e,
285    NM_MTHC0    = 0x0f,
286    NM_SRAV     = 0x12,
287    NM_MULU     = 0x13,
288    NM_ROTRV    = 0x1a,
289    NM_MUHU     = 0x1b,
290    NM_ADD      = 0x22,
291    NM_DIV      = 0x23,
292    NM_ADDU     = 0x2a,
293    NM_MOD      = 0x2b,
294    NM_SUB      = 0x32,
295    NM_DIVU     = 0x33,
296    NM_RDHWR    = 0x38,
297    NM_SUBU     = 0x3a,
298    NM_MODU     = 0x3b,
299    NM_P_CMOVE  = 0x42,
300    NM_FORK     = 0x45,
301    NM_MFTR     = 0x46,
302    NM_MFHTR    = 0x47,
303    NM_AND      = 0x4a,
304    NM_YIELD    = 0x4d,
305    NM_MTTR     = 0x4e,
306    NM_MTHTR    = 0x4f,
307    NM_OR       = 0x52,
308    NM_D_E_MT_VPE = 0x56,
309    NM_NOR      = 0x5a,
310    NM_XOR      = 0x62,
311    NM_SLT      = 0x6a,
312    NM_P_SLTU   = 0x72,
313    NM_SOV      = 0x7a,
314};
315
316/* CRC32 instruction pool */
317enum {
318    NM_CRC32B   = 0x00,
319    NM_CRC32H   = 0x01,
320    NM_CRC32W   = 0x02,
321    NM_CRC32CB  = 0x04,
322    NM_CRC32CH  = 0x05,
323    NM_CRC32CW  = 0x06,
324};
325
326/* POOL32A5 instruction pool */
327enum {
328    NM_CMP_EQ_PH        = 0x00,
329    NM_CMP_LT_PH        = 0x08,
330    NM_CMP_LE_PH        = 0x10,
331    NM_CMPGU_EQ_QB      = 0x18,
332    NM_CMPGU_LT_QB      = 0x20,
333    NM_CMPGU_LE_QB      = 0x28,
334    NM_CMPGDU_EQ_QB     = 0x30,
335    NM_CMPGDU_LT_QB     = 0x38,
336    NM_CMPGDU_LE_QB     = 0x40,
337    NM_CMPU_EQ_QB       = 0x48,
338    NM_CMPU_LT_QB       = 0x50,
339    NM_CMPU_LE_QB       = 0x58,
340    NM_ADDQ_S_W         = 0x60,
341    NM_SUBQ_S_W         = 0x68,
342    NM_ADDSC            = 0x70,
343    NM_ADDWC            = 0x78,
344
345    NM_ADDQ_S_PH   = 0x01,
346    NM_ADDQH_R_PH  = 0x09,
347    NM_ADDQH_R_W   = 0x11,
348    NM_ADDU_S_QB   = 0x19,
349    NM_ADDU_S_PH   = 0x21,
350    NM_ADDUH_R_QB  = 0x29,
351    NM_SHRAV_R_PH  = 0x31,
352    NM_SHRAV_R_QB  = 0x39,
353    NM_SUBQ_S_PH   = 0x41,
354    NM_SUBQH_R_PH  = 0x49,
355    NM_SUBQH_R_W   = 0x51,
356    NM_SUBU_S_QB   = 0x59,
357    NM_SUBU_S_PH   = 0x61,
358    NM_SUBUH_R_QB  = 0x69,
359    NM_SHLLV_S_PH  = 0x71,
360    NM_PRECR_SRA_R_PH_W = 0x79,
361
362    NM_MULEU_S_PH_QBL   = 0x12,
363    NM_MULEU_S_PH_QBR   = 0x1a,
364    NM_MULQ_RS_PH       = 0x22,
365    NM_MULQ_S_PH        = 0x2a,
366    NM_MULQ_RS_W        = 0x32,
367    NM_MULQ_S_W         = 0x3a,
368    NM_APPEND           = 0x42,
369    NM_MODSUB           = 0x52,
370    NM_SHRAV_R_W        = 0x5a,
371    NM_SHRLV_PH         = 0x62,
372    NM_SHRLV_QB         = 0x6a,
373    NM_SHLLV_QB         = 0x72,
374    NM_SHLLV_S_W        = 0x7a,
375
376    NM_SHILO            = 0x03,
377
378    NM_MULEQ_S_W_PHL    = 0x04,
379    NM_MULEQ_S_W_PHR    = 0x0c,
380
381    NM_MUL_S_PH         = 0x05,
382    NM_PRECR_QB_PH      = 0x0d,
383    NM_PRECRQ_QB_PH     = 0x15,
384    NM_PRECRQ_PH_W      = 0x1d,
385    NM_PRECRQ_RS_PH_W   = 0x25,
386    NM_PRECRQU_S_QB_PH  = 0x2d,
387    NM_PACKRL_PH        = 0x35,
388    NM_PICK_QB          = 0x3d,
389    NM_PICK_PH          = 0x45,
390
391    NM_SHRA_R_W         = 0x5e,
392    NM_SHRA_R_PH        = 0x66,
393    NM_SHLL_S_PH        = 0x76,
394    NM_SHLL_S_W         = 0x7e,
395
396    NM_REPL_PH          = 0x07
397};
398
399/* POOL32A7 instruction pool */
400enum {
401    NM_P_LSX        = 0x00,
402    NM_LSA          = 0x01,
403    NM_EXTW         = 0x03,
404    NM_POOL32AXF    = 0x07,
405};
406
407/* P.SR instruction pool */
408enum {
409    NM_PP_SR           = 0x00,
410    NM_P_SR_F          = 0x01,
411};
412
413/* P.SHIFT instruction pool */
414enum {
415    NM_P_SLL        = 0x00,
416    NM_SRL          = 0x02,
417    NM_SRA          = 0x04,
418    NM_ROTR         = 0x06,
419};
420
421/* P.ROTX instruction pool */
422enum {
423    NM_ROTX         = 0x00,
424};
425
426/* P.INS instruction pool */
427enum {
428    NM_INS          = 0x00,
429};
430
431/* P.EXT instruction pool */
432enum {
433    NM_EXT          = 0x00,
434};
435
436/* POOL32F_0 (fmt) instruction pool */
437enum {
438    NM_RINT_S              = 0x04,
439    NM_RINT_D              = 0x44,
440    NM_ADD_S               = 0x06,
441    NM_SELEQZ_S            = 0x07,
442    NM_SELEQZ_D            = 0x47,
443    NM_CLASS_S             = 0x0c,
444    NM_CLASS_D             = 0x4c,
445    NM_SUB_S               = 0x0e,
446    NM_SELNEZ_S            = 0x0f,
447    NM_SELNEZ_D            = 0x4f,
448    NM_MUL_S               = 0x16,
449    NM_SEL_S               = 0x17,
450    NM_SEL_D               = 0x57,
451    NM_DIV_S               = 0x1e,
452    NM_ADD_D               = 0x26,
453    NM_SUB_D               = 0x2e,
454    NM_MUL_D               = 0x36,
455    NM_MADDF_S             = 0x37,
456    NM_MADDF_D             = 0x77,
457    NM_DIV_D               = 0x3e,
458    NM_MSUBF_S             = 0x3f,
459    NM_MSUBF_D             = 0x7f,
460};
461
462/* POOL32F_3  instruction pool */
463enum {
464    NM_MIN_FMT         = 0x00,
465    NM_MAX_FMT         = 0x01,
466    NM_MINA_FMT        = 0x04,
467    NM_MAXA_FMT        = 0x05,
468    NM_POOL32FXF       = 0x07,
469};
470
471/* POOL32F_5  instruction pool */
472enum {
473    NM_CMP_CONDN_S     = 0x00,
474    NM_CMP_CONDN_D     = 0x02,
475};
476
477/* P.GP.LH instruction pool */
478enum {
479    NM_LHGP    = 0x00,
480    NM_LHUGP   = 0x01,
481};
482
483/* P.GP.SH instruction pool */
484enum {
485    NM_SHGP    = 0x00,
486};
487
488/* P.GP.CP1 instruction pool */
489enum {
490    NM_LWC1GP       = 0x00,
491    NM_SWC1GP       = 0x01,
492    NM_LDC1GP       = 0x02,
493    NM_SDC1GP       = 0x03,
494};
495
496/* P.LS.S0 instruction pool */
497enum {
498    NM_LBS9     = 0x00,
499    NM_LHS9     = 0x04,
500    NM_LWS9     = 0x08,
501    NM_LDS9     = 0x0c,
502
503    NM_SBS9     = 0x01,
504    NM_SHS9     = 0x05,
505    NM_SWS9     = 0x09,
506    NM_SDS9     = 0x0d,
507
508    NM_LBUS9    = 0x02,
509    NM_LHUS9    = 0x06,
510    NM_LWC1S9   = 0x0a,
511    NM_LDC1S9   = 0x0e,
512
513    NM_P_PREFS9 = 0x03,
514    NM_LWUS9    = 0x07,
515    NM_SWC1S9   = 0x0b,
516    NM_SDC1S9   = 0x0f,
517};
518
519/* P.LS.S1 instruction pool */
520enum {
521    NM_ASET_ACLR = 0x02,
522    NM_UALH      = 0x04,
523    NM_UASH      = 0x05,
524    NM_CACHE     = 0x07,
525    NM_P_LL      = 0x0a,
526    NM_P_SC      = 0x0b,
527};
528
529/* P.LS.E0 instruction pool */
530enum {
531    NM_LBE      = 0x00,
532    NM_SBE      = 0x01,
533    NM_LBUE     = 0x02,
534    NM_P_PREFE  = 0x03,
535    NM_LHE      = 0x04,
536    NM_SHE      = 0x05,
537    NM_LHUE     = 0x06,
538    NM_CACHEE   = 0x07,
539    NM_LWE      = 0x08,
540    NM_SWE      = 0x09,
541    NM_P_LLE    = 0x0a,
542    NM_P_SCE    = 0x0b,
543};
544
545/* P.PREFE instruction pool */
546enum {
547    NM_SYNCIE   = 0x00,
548    NM_PREFE    = 0x01,
549};
550
551/* P.LLE instruction pool */
552enum {
553    NM_LLE      = 0x00,
554    NM_LLWPE    = 0x01,
555};
556
557/* P.SCE instruction pool */
558enum {
559    NM_SCE      = 0x00,
560    NM_SCWPE    = 0x01,
561};
562
563/* P.LS.WM instruction pool */
564enum {
565    NM_LWM       = 0x00,
566    NM_SWM       = 0x01,
567};
568
569/* P.LS.UAWM instruction pool */
570enum {
571    NM_UALWM       = 0x00,
572    NM_UASWM       = 0x01,
573};
574
575/* P.BR3A instruction pool */
576enum {
577    NM_BC1EQZC          = 0x00,
578    NM_BC1NEZC          = 0x01,
579    NM_BC2EQZC          = 0x02,
580    NM_BC2NEZC          = 0x03,
581    NM_BPOSGE32C        = 0x04,
582};
583
584/* P16.RI instruction pool */
585enum {
586    NM_P16_SYSCALL  = 0x01,
587    NM_BREAK16      = 0x02,
588    NM_SDBBP16      = 0x03,
589};
590
591/* POOL16C_0 instruction pool */
592enum {
593    NM_POOL16C_00      = 0x00,
594};
595
596/* P16.JRC instruction pool */
597enum {
598    NM_JRC          = 0x00,
599    NM_JALRC16      = 0x01,
600};
601
602/* P.SYSCALL instruction pool */
603enum {
604    NM_SYSCALL      = 0x00,
605    NM_HYPCALL      = 0x01,
606};
607
608/* P.TRAP instruction pool */
609enum {
610    NM_TEQ          = 0x00,
611    NM_TNE          = 0x01,
612};
613
614/* P.CMOVE instruction pool */
615enum {
616    NM_MOVZ            = 0x00,
617    NM_MOVN            = 0x01,
618};
619
620/* POOL32Axf instruction pool */
621enum {
622    NM_POOL32AXF_1 = 0x01,
623    NM_POOL32AXF_2 = 0x02,
624    NM_POOL32AXF_4 = 0x04,
625    NM_POOL32AXF_5 = 0x05,
626    NM_POOL32AXF_7 = 0x07,
627};
628
629/* POOL32Axf_1 instruction pool */
630enum {
631    NM_POOL32AXF_1_0 = 0x00,
632    NM_POOL32AXF_1_1 = 0x01,
633    NM_POOL32AXF_1_3 = 0x03,
634    NM_POOL32AXF_1_4 = 0x04,
635    NM_POOL32AXF_1_5 = 0x05,
636    NM_POOL32AXF_1_7 = 0x07,
637};
638
639/* POOL32Axf_2 instruction pool */
640enum {
641    NM_POOL32AXF_2_0_7     = 0x00,
642    NM_POOL32AXF_2_8_15    = 0x01,
643    NM_POOL32AXF_2_16_23   = 0x02,
644    NM_POOL32AXF_2_24_31   = 0x03,
645};
646
647/* POOL32Axf_7 instruction pool */
648enum {
649    NM_SHRA_R_QB    = 0x0,
650    NM_SHRL_PH      = 0x1,
651    NM_REPL_QB      = 0x2,
652};
653
654/* POOL32Axf_1_0 instruction pool */
655enum {
656    NM_MFHI = 0x0,
657    NM_MFLO = 0x1,
658    NM_MTHI = 0x2,
659    NM_MTLO = 0x3,
660};
661
662/* POOL32Axf_1_1 instruction pool */
663enum {
664    NM_MTHLIP = 0x0,
665    NM_SHILOV = 0x1,
666};
667
668/* POOL32Axf_1_3 instruction pool */
669enum {
670    NM_RDDSP    = 0x0,
671    NM_WRDSP    = 0x1,
672    NM_EXTP     = 0x2,
673    NM_EXTPDP   = 0x3,
674};
675
676/* POOL32Axf_1_4 instruction pool */
677enum {
678    NM_SHLL_QB  = 0x0,
679    NM_SHRL_QB  = 0x1,
680};
681
682/* POOL32Axf_1_5 instruction pool */
683enum {
684    NM_MAQ_S_W_PHR   = 0x0,
685    NM_MAQ_S_W_PHL   = 0x1,
686    NM_MAQ_SA_W_PHR  = 0x2,
687    NM_MAQ_SA_W_PHL  = 0x3,
688};
689
690/* POOL32Axf_1_7 instruction pool */
691enum {
692    NM_EXTR_W       = 0x0,
693    NM_EXTR_R_W     = 0x1,
694    NM_EXTR_RS_W    = 0x2,
695    NM_EXTR_S_H     = 0x3,
696};
697
698/* POOL32Axf_2_0_7 instruction pool */
699enum {
700    NM_DPA_W_PH     = 0x0,
701    NM_DPAQ_S_W_PH  = 0x1,
702    NM_DPS_W_PH     = 0x2,
703    NM_DPSQ_S_W_PH  = 0x3,
704    NM_BALIGN       = 0x4,
705    NM_MADD         = 0x5,
706    NM_MULT         = 0x6,
707    NM_EXTRV_W      = 0x7,
708};
709
710/* POOL32Axf_2_8_15 instruction pool */
711enum {
712    NM_DPAX_W_PH    = 0x0,
713    NM_DPAQ_SA_L_W  = 0x1,
714    NM_DPSX_W_PH    = 0x2,
715    NM_DPSQ_SA_L_W  = 0x3,
716    NM_MADDU        = 0x5,
717    NM_MULTU        = 0x6,
718    NM_EXTRV_R_W    = 0x7,
719};
720
721/* POOL32Axf_2_16_23 instruction pool */
722enum {
723    NM_DPAU_H_QBL       = 0x0,
724    NM_DPAQX_S_W_PH     = 0x1,
725    NM_DPSU_H_QBL       = 0x2,
726    NM_DPSQX_S_W_PH     = 0x3,
727    NM_EXTPV            = 0x4,
728    NM_MSUB             = 0x5,
729    NM_MULSA_W_PH       = 0x6,
730    NM_EXTRV_RS_W       = 0x7,
731};
732
733/* POOL32Axf_2_24_31 instruction pool */
734enum {
735    NM_DPAU_H_QBR       = 0x0,
736    NM_DPAQX_SA_W_PH    = 0x1,
737    NM_DPSU_H_QBR       = 0x2,
738    NM_DPSQX_SA_W_PH    = 0x3,
739    NM_EXTPDPV          = 0x4,
740    NM_MSUBU            = 0x5,
741    NM_MULSAQ_S_W_PH    = 0x6,
742    NM_EXTRV_S_H        = 0x7,
743};
744
745/* POOL32Axf_{4, 5} instruction pool */
746enum {
747    NM_CLO      = 0x25,
748    NM_CLZ      = 0x2d,
749
750    NM_TLBP     = 0x01,
751    NM_TLBR     = 0x09,
752    NM_TLBWI    = 0x11,
753    NM_TLBWR    = 0x19,
754    NM_TLBINV   = 0x03,
755    NM_TLBINVF  = 0x0b,
756    NM_DI       = 0x23,
757    NM_EI       = 0x2b,
758    NM_RDPGPR   = 0x70,
759    NM_WRPGPR   = 0x78,
760    NM_WAIT     = 0x61,
761    NM_DERET    = 0x71,
762    NM_ERETX    = 0x79,
763
764    /* nanoMIPS DSP instructions */
765    NM_ABSQ_S_QB        = 0x00,
766    NM_ABSQ_S_PH        = 0x08,
767    NM_ABSQ_S_W         = 0x10,
768    NM_PRECEQ_W_PHL     = 0x28,
769    NM_PRECEQ_W_PHR     = 0x30,
770    NM_PRECEQU_PH_QBL   = 0x38,
771    NM_PRECEQU_PH_QBR   = 0x48,
772    NM_PRECEU_PH_QBL    = 0x58,
773    NM_PRECEU_PH_QBR    = 0x68,
774    NM_PRECEQU_PH_QBLA  = 0x39,
775    NM_PRECEQU_PH_QBRA  = 0x49,
776    NM_PRECEU_PH_QBLA   = 0x59,
777    NM_PRECEU_PH_QBRA   = 0x69,
778    NM_REPLV_PH         = 0x01,
779    NM_REPLV_QB         = 0x09,
780    NM_BITREV           = 0x18,
781    NM_INSV             = 0x20,
782    NM_RADDU_W_QB       = 0x78,
783
784    NM_BITSWAP          = 0x05,
785    NM_WSBH             = 0x3d,
786};
787
788/* PP.SR instruction pool */
789enum {
790    NM_SAVE         = 0x00,
791    NM_RESTORE      = 0x02,
792    NM_RESTORE_JRC  = 0x03,
793};
794
795/* P.SR.F instruction pool */
796enum {
797    NM_SAVEF        = 0x00,
798    NM_RESTOREF     = 0x01,
799};
800
801/* P16.SYSCALL  instruction pool */
802enum {
803    NM_SYSCALL16     = 0x00,
804    NM_HYPCALL16     = 0x01,
805};
806
807/* POOL16C_00 instruction pool */
808enum {
809    NM_NOT16           = 0x00,
810    NM_XOR16           = 0x01,
811    NM_AND16           = 0x02,
812    NM_OR16            = 0x03,
813};
814
815/* PP.LSX and PP.LSXS instruction pool */
816enum {
817    NM_LBX      = 0x00,
818    NM_LHX      = 0x04,
819    NM_LWX      = 0x08,
820    NM_LDX      = 0x0c,
821
822    NM_SBX      = 0x01,
823    NM_SHX      = 0x05,
824    NM_SWX      = 0x09,
825    NM_SDX      = 0x0d,
826
827    NM_LBUX     = 0x02,
828    NM_LHUX     = 0x06,
829    NM_LWC1X    = 0x0a,
830    NM_LDC1X    = 0x0e,
831
832    NM_LWUX     = 0x07,
833    NM_SWC1X    = 0x0b,
834    NM_SDC1X    = 0x0f,
835
836    NM_LHXS     = 0x04,
837    NM_LWXS     = 0x08,
838    NM_LDXS     = 0x0c,
839
840    NM_SHXS     = 0x05,
841    NM_SWXS     = 0x09,
842    NM_SDXS     = 0x0d,
843
844    NM_LHUXS    = 0x06,
845    NM_LWC1XS   = 0x0a,
846    NM_LDC1XS   = 0x0e,
847
848    NM_LWUXS    = 0x07,
849    NM_SWC1XS   = 0x0b,
850    NM_SDC1XS   = 0x0f,
851};
852
853/* ERETx instruction pool */
854enum {
855    NM_ERET     = 0x00,
856    NM_ERETNC   = 0x01,
857};
858
859/* POOL32FxF_{0, 1} insturction pool */
860enum {
861    NM_CFC1     = 0x40,
862    NM_CTC1     = 0x60,
863    NM_MFC1     = 0x80,
864    NM_MTC1     = 0xa0,
865    NM_MFHC1    = 0xc0,
866    NM_MTHC1    = 0xe0,
867
868    NM_CVT_S_PL = 0x84,
869    NM_CVT_S_PU = 0xa4,
870
871    NM_CVT_L_S     = 0x004,
872    NM_CVT_L_D     = 0x104,
873    NM_CVT_W_S     = 0x024,
874    NM_CVT_W_D     = 0x124,
875
876    NM_RSQRT_S     = 0x008,
877    NM_RSQRT_D     = 0x108,
878
879    NM_SQRT_S      = 0x028,
880    NM_SQRT_D      = 0x128,
881
882    NM_RECIP_S     = 0x048,
883    NM_RECIP_D     = 0x148,
884
885    NM_FLOOR_L_S   = 0x00c,
886    NM_FLOOR_L_D   = 0x10c,
887
888    NM_FLOOR_W_S   = 0x02c,
889    NM_FLOOR_W_D   = 0x12c,
890
891    NM_CEIL_L_S    = 0x04c,
892    NM_CEIL_L_D    = 0x14c,
893    NM_CEIL_W_S    = 0x06c,
894    NM_CEIL_W_D    = 0x16c,
895    NM_TRUNC_L_S   = 0x08c,
896    NM_TRUNC_L_D   = 0x18c,
897    NM_TRUNC_W_S   = 0x0ac,
898    NM_TRUNC_W_D   = 0x1ac,
899    NM_ROUND_L_S   = 0x0cc,
900    NM_ROUND_L_D   = 0x1cc,
901    NM_ROUND_W_S   = 0x0ec,
902    NM_ROUND_W_D   = 0x1ec,
903
904    NM_MOV_S       = 0x01,
905    NM_MOV_D       = 0x81,
906    NM_ABS_S       = 0x0d,
907    NM_ABS_D       = 0x8d,
908    NM_NEG_S       = 0x2d,
909    NM_NEG_D       = 0xad,
910    NM_CVT_D_S     = 0x04d,
911    NM_CVT_D_W     = 0x0cd,
912    NM_CVT_D_L     = 0x14d,
913    NM_CVT_S_D     = 0x06d,
914    NM_CVT_S_W     = 0x0ed,
915    NM_CVT_S_L     = 0x16d,
916};
917
918/* P.LL instruction pool */
919enum {
920    NM_LL       = 0x00,
921    NM_LLWP     = 0x01,
922};
923
924/* P.SC instruction pool */
925enum {
926    NM_SC       = 0x00,
927    NM_SCWP     = 0x01,
928};
929
930/* P.DVP instruction pool */
931enum {
932    NM_DVP      = 0x00,
933    NM_EVP      = 0x01,
934};
935
936
937/*
938 *
939 * nanoMIPS decoding engine
940 *
941 */
942
943
944/* extraction utilities */
945
946#define NANOMIPS_EXTRACT_RT3(op) ((op >> 7) & 0x7)
947#define NANOMIPS_EXTRACT_RS3(op) ((op >> 4) & 0x7)
948#define NANOMIPS_EXTRACT_RD3(op) ((op >> 1) & 0x7)
949#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
950#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
951
952/* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr3'). */
953static inline int decode_gpr_gpr3(int r)
954{
955    static const int map[] = { 16, 17, 18, 19,  4,  5,  6,  7 };
956
957    return map[r & 0x7];
958}
959
960/* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr3.src.store'). */
961static inline int decode_gpr_gpr3_src_store(int r)
962{
963    static const int map[] = {  0, 17, 18, 19,  4,  5,  6,  7 };
964
965    return map[r & 0x7];
966}
967
968/* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr4'). */
969static inline int decode_gpr_gpr4(int r)
970{
971    static const int map[] = {  8,  9, 10, 11,  4,  5,  6,  7,
972                               16, 17, 18, 19, 20, 21, 22, 23 };
973
974    return map[r & 0xf];
975}
976
977/* Implement nanoMIPS pseudocode decode_gpr(encoded_gpr, 'gpr4.zero'). */
978static inline int decode_gpr_gpr4_zero(int r)
979{
980    static const int map[] = {  8,  9, 10,  0,  4,  5,  6,  7,
981                               16, 17, 18, 19, 20, 21, 22, 23 };
982
983    return map[r & 0xf];
984}
985
986static void gen_ext(DisasContext *ctx, int wordsz, int rd, int rs, int rt,
987                    int shift)
988{
989    gen_align_bits(ctx, wordsz, rd, rs, rt, wordsz - shift);
990}
991
992static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
993                    uint32_t reg1, uint32_t reg2)
994{
995    TCGv taddr = tcg_temp_new();
996    TCGv_i64 tval = tcg_temp_new_i64();
997    TCGv tmp1 = tcg_temp_new();
998    TCGv tmp2 = tcg_temp_new();
999
1000    gen_base_offset_addr(ctx, taddr, base, offset);
1001    tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ | MO_ALIGN);
1002    if (cpu_is_bigendian(ctx)) {
1003        tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
1004    } else {
1005        tcg_gen_extr_i64_tl(tmp1, tmp2, tval);
1006    }
1007    gen_store_gpr(tmp1, reg1);
1008    gen_store_gpr(tmp2, reg2);
1009    tcg_gen_st_i64(tval, tcg_env, offsetof(CPUMIPSState, llval_wp));
1010    tcg_gen_st_tl(taddr, tcg_env, offsetof(CPUMIPSState, lladdr));
1011}
1012
1013static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
1014                    uint32_t reg1, uint32_t reg2, bool eva)
1015{
1016    TCGv taddr = tcg_temp_new();
1017    TCGv lladdr = tcg_temp_new();
1018    TCGv_i64 tval = tcg_temp_new_i64();
1019    TCGv_i64 llval = tcg_temp_new_i64();
1020    TCGv_i64 val = tcg_temp_new_i64();
1021    TCGv tmp1 = tcg_temp_new();
1022    TCGv tmp2 = tcg_temp_new();
1023    TCGLabel *lab_fail = gen_new_label();
1024    TCGLabel *lab_done = gen_new_label();
1025
1026    gen_base_offset_addr(ctx, taddr, base, offset);
1027
1028    tcg_gen_ld_tl(lladdr, tcg_env, offsetof(CPUMIPSState, lladdr));
1029    tcg_gen_brcond_tl(TCG_COND_NE, taddr, lladdr, lab_fail);
1030
1031    gen_load_gpr(tmp1, reg1);
1032    gen_load_gpr(tmp2, reg2);
1033
1034    if (cpu_is_bigendian(ctx)) {
1035        tcg_gen_concat_tl_i64(tval, tmp2, tmp1);
1036    } else {
1037        tcg_gen_concat_tl_i64(tval, tmp1, tmp2);
1038    }
1039
1040    tcg_gen_ld_i64(llval, tcg_env, offsetof(CPUMIPSState, llval_wp));
1041    tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
1042                               eva ? MIPS_HFLAG_UM : ctx->mem_idx,
1043                               MO_64 | MO_ALIGN);
1044    if (reg1 != 0) {
1045        tcg_gen_movi_tl(cpu_gpr[reg1], 1);
1046    }
1047    tcg_gen_brcond_i64(TCG_COND_EQ, val, llval, lab_done);
1048
1049    gen_set_label(lab_fail);
1050
1051    if (reg1 != 0) {
1052        tcg_gen_movi_tl(cpu_gpr[reg1], 0);
1053    }
1054    gen_set_label(lab_done);
1055    tcg_gen_movi_tl(lladdr, -1);
1056    tcg_gen_st_tl(lladdr, tcg_env, offsetof(CPUMIPSState, lladdr));
1057}
1058
1059static void gen_adjust_sp(DisasContext *ctx, int u)
1060{
1061    gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], u);
1062}
1063
1064static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count,
1065                     uint8_t gp, uint16_t u)
1066{
1067    int counter = 0;
1068    TCGv va = tcg_temp_new();
1069    TCGv t0 = tcg_temp_new();
1070
1071    while (counter != count) {
1072        bool use_gp = gp && (counter == count - 1);
1073        int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f);
1074        int this_offset = -((counter + 1) << 2);
1075        gen_base_offset_addr(ctx, va, 29, this_offset);
1076        gen_load_gpr(t0, this_rt);
1077        tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx,
1078                           (MO_TEUL | ctx->default_tcg_memop_mask));
1079        counter++;
1080    }
1081
1082    /* adjust stack pointer */
1083    gen_adjust_sp(ctx, -u);
1084}
1085
1086static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
1087                        uint8_t gp, uint16_t u)
1088{
1089    int counter = 0;
1090    TCGv va = tcg_temp_new();
1091    TCGv t0 = tcg_temp_new();
1092
1093    while (counter != count) {
1094        bool use_gp = gp && (counter == count - 1);
1095        int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f);
1096        int this_offset = u - ((counter + 1) << 2);
1097        gen_base_offset_addr(ctx, va, 29, this_offset);
1098        tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TESL |
1099                        ctx->default_tcg_memop_mask);
1100        tcg_gen_ext32s_tl(t0, t0);
1101        gen_store_gpr(t0, this_rt);
1102        counter++;
1103    }
1104
1105    /* adjust stack pointer */
1106    gen_adjust_sp(ctx, u);
1107}
1108
1109static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
1110                                  int insn_bytes,
1111                                  int rs, int rt, int32_t offset)
1112{
1113    target_ulong btgt = -1;
1114    int bcond_compute = 0;
1115    TCGv t0 = tcg_temp_new();
1116    TCGv t1 = tcg_temp_new();
1117
1118    /* Load needed operands */
1119    switch (opc) {
1120    case OPC_BEQ:
1121    case OPC_BNE:
1122        /* Compare two registers */
1123        if (rs != rt) {
1124            gen_load_gpr(t0, rs);
1125            gen_load_gpr(t1, rt);
1126            bcond_compute = 1;
1127        }
1128        btgt = ctx->base.pc_next + insn_bytes + offset;
1129        break;
1130    case OPC_BGEZAL:
1131        /* Compare to zero */
1132        if (rs != 0) {
1133            gen_load_gpr(t0, rs);
1134            bcond_compute = 1;
1135        }
1136        btgt = ctx->base.pc_next + insn_bytes + offset;
1137        break;
1138    case OPC_BPOSGE32:
1139        tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
1140        bcond_compute = 1;
1141        btgt = ctx->base.pc_next + insn_bytes + offset;
1142        break;
1143    case OPC_JR:
1144    case OPC_JALR:
1145        /* Jump to register */
1146        if (offset != 0 && offset != 16) {
1147            /*
1148             * Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
1149             * others are reserved.
1150             */
1151            MIPS_INVAL("jump hint");
1152            gen_reserved_instruction(ctx);
1153            goto out;
1154        }
1155        gen_load_gpr(btarget, rs);
1156        break;
1157    default:
1158        MIPS_INVAL("branch/jump");
1159        gen_reserved_instruction(ctx);
1160        goto out;
1161    }
1162    if (bcond_compute == 0) {
1163        /* No condition to be computed */
1164        switch (opc) {
1165        case OPC_BEQ:     /* rx == rx        */
1166            /* Always take */
1167            ctx->hflags |= MIPS_HFLAG_B;
1168            break;
1169        case OPC_BGEZAL:  /* 0 >= 0          */
1170            /* Always take and link */
1171            tcg_gen_movi_tl(cpu_gpr[31],
1172                            ctx->base.pc_next + insn_bytes);
1173            ctx->hflags |= MIPS_HFLAG_B;
1174            break;
1175        case OPC_BNE:     /* rx != rx        */
1176            tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8);
1177            /* Skip the instruction in the delay slot */
1178            ctx->base.pc_next += 4;
1179            goto out;
1180        case OPC_JR:
1181            ctx->hflags |= MIPS_HFLAG_BR;
1182            break;
1183        case OPC_JALR:
1184            if (rt > 0) {
1185                tcg_gen_movi_tl(cpu_gpr[rt],
1186                                ctx->base.pc_next + insn_bytes);
1187            }
1188            ctx->hflags |= MIPS_HFLAG_BR;
1189            break;
1190        default:
1191            MIPS_INVAL("branch/jump");
1192            gen_reserved_instruction(ctx);
1193            goto out;
1194        }
1195    } else {
1196        switch (opc) {
1197        case OPC_BEQ:
1198            tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
1199            goto not_likely;
1200        case OPC_BNE:
1201            tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
1202            goto not_likely;
1203        case OPC_BGEZAL:
1204            tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
1205            tcg_gen_movi_tl(cpu_gpr[31],
1206                            ctx->base.pc_next + insn_bytes);
1207            goto not_likely;
1208        case OPC_BPOSGE32:
1209            tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32);
1210        not_likely:
1211            ctx->hflags |= MIPS_HFLAG_BC;
1212            break;
1213        default:
1214            MIPS_INVAL("conditional branch/jump");
1215            gen_reserved_instruction(ctx);
1216            goto out;
1217        }
1218    }
1219
1220    ctx->btarget = btgt;
1221
1222 out:
1223    if (insn_bytes == 2) {
1224        ctx->hflags |= MIPS_HFLAG_B16;
1225    }
1226}
1227
1228static void gen_pool16c_nanomips_insn(DisasContext *ctx)
1229{
1230    int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
1231    int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
1232
1233    switch (extract32(ctx->opcode, 2, 2)) {
1234    case NM_NOT16:
1235        gen_logic(ctx, OPC_NOR, rt, rs, 0);
1236        break;
1237    case NM_AND16:
1238        gen_logic(ctx, OPC_AND, rt, rt, rs);
1239        break;
1240    case NM_XOR16:
1241        gen_logic(ctx, OPC_XOR, rt, rt, rs);
1242        break;
1243    case NM_OR16:
1244        gen_logic(ctx, OPC_OR, rt, rt, rs);
1245        break;
1246    }
1247}
1248
1249static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
1250{
1251    int rt = extract32(ctx->opcode, 21, 5);
1252    int rs = extract32(ctx->opcode, 16, 5);
1253    int rd = extract32(ctx->opcode, 11, 5);
1254
1255    switch (extract32(ctx->opcode, 3, 7)) {
1256    case NM_P_TRAP:
1257        switch (extract32(ctx->opcode, 10, 1)) {
1258        case NM_TEQ:
1259            check_nms(ctx);
1260            gen_trap(ctx, OPC_TEQ, rs, rt, -1, rd);
1261            break;
1262        case NM_TNE:
1263            check_nms(ctx);
1264            gen_trap(ctx, OPC_TNE, rs, rt, -1, rd);
1265            break;
1266        }
1267        break;
1268    case NM_RDHWR:
1269        check_nms(ctx);
1270        gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3));
1271        break;
1272    case NM_SEB:
1273        check_nms(ctx);
1274        gen_bshfl(ctx, OPC_SEB, rs, rt);
1275        break;
1276    case NM_SEH:
1277        gen_bshfl(ctx, OPC_SEH, rs, rt);
1278        break;
1279    case NM_SLLV:
1280        gen_shift(ctx, OPC_SLLV, rd, rt, rs);
1281        break;
1282    case NM_SRLV:
1283        gen_shift(ctx, OPC_SRLV, rd, rt, rs);
1284        break;
1285    case NM_SRAV:
1286        gen_shift(ctx, OPC_SRAV, rd, rt, rs);
1287        break;
1288    case NM_ROTRV:
1289        gen_shift(ctx, OPC_ROTRV, rd, rt, rs);
1290        break;
1291    case NM_ADD:
1292        gen_arith(ctx, OPC_ADD, rd, rs, rt);
1293        break;
1294    case NM_ADDU:
1295        gen_arith(ctx, OPC_ADDU, rd, rs, rt);
1296        break;
1297    case NM_SUB:
1298        check_nms(ctx);
1299        gen_arith(ctx, OPC_SUB, rd, rs, rt);
1300        break;
1301    case NM_SUBU:
1302        gen_arith(ctx, OPC_SUBU, rd, rs, rt);
1303        break;
1304    case NM_P_CMOVE:
1305        switch (extract32(ctx->opcode, 10, 1)) {
1306        case NM_MOVZ:
1307            gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt);
1308            break;
1309        case NM_MOVN:
1310            gen_cond_move(ctx, OPC_MOVN, rd, rs, rt);
1311            break;
1312        }
1313        break;
1314    case NM_AND:
1315        gen_logic(ctx, OPC_AND, rd, rs, rt);
1316        break;
1317    case NM_OR:
1318        gen_logic(ctx, OPC_OR, rd, rs, rt);
1319        break;
1320    case NM_NOR:
1321        gen_logic(ctx, OPC_NOR, rd, rs, rt);
1322        break;
1323    case NM_XOR:
1324        gen_logic(ctx, OPC_XOR, rd, rs, rt);
1325        break;
1326    case NM_SLT:
1327        gen_slt(ctx, OPC_SLT, rd, rs, rt);
1328        break;
1329    case NM_P_SLTU:
1330        if (rd == 0) {
1331            /* P_DVP */
1332#ifndef CONFIG_USER_ONLY
1333            TCGv t0 = tcg_temp_new();
1334            switch (extract32(ctx->opcode, 10, 1)) {
1335            case NM_DVP:
1336                if (ctx->vp) {
1337                    check_cp0_enabled(ctx);
1338                    gen_helper_dvp(t0, tcg_env);
1339                    gen_store_gpr(t0, rt);
1340                }
1341                break;
1342            case NM_EVP:
1343                if (ctx->vp) {
1344                    check_cp0_enabled(ctx);
1345                    gen_helper_evp(t0, tcg_env);
1346                    gen_store_gpr(t0, rt);
1347                }
1348                break;
1349            }
1350#endif
1351        } else {
1352            gen_slt(ctx, OPC_SLTU, rd, rs, rt);
1353        }
1354        break;
1355    case NM_SOV:
1356        {
1357            TCGv t0 = tcg_temp_new();
1358            TCGv t1 = tcg_temp_new();
1359            TCGv t2 = tcg_temp_new();
1360
1361            gen_load_gpr(t1, rs);
1362            gen_load_gpr(t2, rt);
1363            tcg_gen_add_tl(t0, t1, t2);
1364            tcg_gen_ext32s_tl(t0, t0);
1365            tcg_gen_xor_tl(t1, t1, t2);
1366            tcg_gen_xor_tl(t2, t0, t2);
1367            tcg_gen_andc_tl(t1, t2, t1);
1368
1369            /* operands of same sign, result different sign */
1370            tcg_gen_setcondi_tl(TCG_COND_LT, t0, t1, 0);
1371            gen_store_gpr(t0, rd);
1372        }
1373        break;
1374    case NM_MUL:
1375        gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt);
1376        break;
1377    case NM_MUH:
1378        gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt);
1379        break;
1380    case NM_MULU:
1381        gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt);
1382        break;
1383    case NM_MUHU:
1384        gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt);
1385        break;
1386    case NM_DIV:
1387        gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt);
1388        break;
1389    case NM_MOD:
1390        gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt);
1391        break;
1392    case NM_DIVU:
1393        gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt);
1394        break;
1395    case NM_MODU:
1396        gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt);
1397        break;
1398#ifndef CONFIG_USER_ONLY
1399    case NM_MFC0:
1400        check_cp0_enabled(ctx);
1401        if (rt == 0) {
1402            /* Treat as NOP. */
1403            break;
1404        }
1405        gen_mfc0(ctx, cpu_gpr[rt], rs, extract32(ctx->opcode, 11, 3));
1406        break;
1407    case NM_MTC0:
1408        check_cp0_enabled(ctx);
1409        {
1410            TCGv t0 = tcg_temp_new();
1411
1412            gen_load_gpr(t0, rt);
1413            gen_mtc0(ctx, t0, rs, extract32(ctx->opcode, 11, 3));
1414        }
1415        break;
1416    case NM_D_E_MT_VPE:
1417        {
1418            uint8_t sc = extract32(ctx->opcode, 10, 1);
1419            TCGv t0 = tcg_temp_new();
1420
1421            switch (sc) {
1422            case 0:
1423                if (rs == 1) {
1424                    /* DMT */
1425                    check_cp0_mt(ctx);
1426                    gen_helper_dmt(t0);
1427                    gen_store_gpr(t0, rt);
1428                } else if (rs == 0) {
1429                    /* DVPE */
1430                    check_cp0_mt(ctx);
1431                    gen_helper_dvpe(t0, tcg_env);
1432                    gen_store_gpr(t0, rt);
1433                } else {
1434                    gen_reserved_instruction(ctx);
1435                }
1436                break;
1437            case 1:
1438                if (rs == 1) {
1439                    /* EMT */
1440                    check_cp0_mt(ctx);
1441                    gen_helper_emt(t0);
1442                    gen_store_gpr(t0, rt);
1443                } else if (rs == 0) {
1444                    /* EVPE */
1445                    check_cp0_mt(ctx);
1446                    gen_helper_evpe(t0, tcg_env);
1447                    gen_store_gpr(t0, rt);
1448                } else {
1449                    gen_reserved_instruction(ctx);
1450                }
1451                break;
1452            }
1453        }
1454        break;
1455    case NM_FORK:
1456        check_mt(ctx);
1457        {
1458            TCGv t0 = tcg_temp_new();
1459            TCGv t1 = tcg_temp_new();
1460
1461            gen_load_gpr(t0, rt);
1462            gen_load_gpr(t1, rs);
1463            gen_helper_fork(t0, t1);
1464        }
1465        break;
1466    case NM_MFTR:
1467    case NM_MFHTR:
1468        check_cp0_enabled(ctx);
1469        if (rd == 0) {
1470            /* Treat as NOP. */
1471            return;
1472        }
1473        gen_mftr(env, ctx, rs, rt, extract32(ctx->opcode, 10, 1),
1474                 extract32(ctx->opcode, 11, 5), extract32(ctx->opcode, 3, 1));
1475        break;
1476    case NM_MTTR:
1477    case NM_MTHTR:
1478        check_cp0_enabled(ctx);
1479        gen_mttr(env, ctx, rs, rt, extract32(ctx->opcode, 10, 1),
1480                 extract32(ctx->opcode, 11, 5), extract32(ctx->opcode, 3, 1));
1481        break;
1482    case NM_YIELD:
1483        check_mt(ctx);
1484        {
1485            TCGv t0 = tcg_temp_new();
1486
1487            gen_load_gpr(t0, rs);
1488            gen_helper_yield(t0, tcg_env, t0);
1489            gen_store_gpr(t0, rt);
1490        }
1491        break;
1492#endif
1493    default:
1494        gen_reserved_instruction(ctx);
1495        break;
1496    }
1497}
1498
1499/* dsp */
1500static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx, uint32_t opc,
1501                                            int ret, int v1, int v2)
1502{
1503    TCGv_i32 t0;
1504    TCGv v0_t;
1505    TCGv v1_t;
1506
1507    t0 = tcg_temp_new_i32();
1508
1509    v0_t = tcg_temp_new();
1510    v1_t = tcg_temp_new();
1511
1512    tcg_gen_movi_i32(t0, v2 >> 3);
1513
1514    gen_load_gpr(v0_t, ret);
1515    gen_load_gpr(v1_t, v1);
1516
1517    switch (opc) {
1518    case NM_MAQ_S_W_PHR:
1519        check_dsp(ctx);
1520        gen_helper_maq_s_w_phr(t0, v1_t, v0_t, tcg_env);
1521        break;
1522    case NM_MAQ_S_W_PHL:
1523        check_dsp(ctx);
1524        gen_helper_maq_s_w_phl(t0, v1_t, v0_t, tcg_env);
1525        break;
1526    case NM_MAQ_SA_W_PHR:
1527        check_dsp(ctx);
1528        gen_helper_maq_sa_w_phr(t0, v1_t, v0_t, tcg_env);
1529        break;
1530    case NM_MAQ_SA_W_PHL:
1531        check_dsp(ctx);
1532        gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, tcg_env);
1533        break;
1534    default:
1535        gen_reserved_instruction(ctx);
1536        break;
1537    }
1538}
1539
1540
1541static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
1542                                    int ret, int v1, int v2)
1543{
1544    int16_t imm;
1545    TCGv t0 = tcg_temp_new();
1546    TCGv t1 = tcg_temp_new();
1547    TCGv v0_t = tcg_temp_new();
1548
1549    gen_load_gpr(v0_t, v1);
1550
1551    switch (opc) {
1552    case NM_POOL32AXF_1_0:
1553        check_dsp(ctx);
1554        switch (extract32(ctx->opcode, 12, 2)) {
1555        case NM_MFHI:
1556            gen_HILO(ctx, OPC_MFHI, v2 >> 3, ret);
1557            break;
1558        case NM_MFLO:
1559            gen_HILO(ctx, OPC_MFLO, v2 >> 3, ret);
1560            break;
1561        case NM_MTHI:
1562            gen_HILO(ctx, OPC_MTHI, v2 >> 3, v1);
1563            break;
1564        case NM_MTLO:
1565            gen_HILO(ctx, OPC_MTLO, v2 >> 3, v1);
1566            break;
1567        }
1568        break;
1569    case NM_POOL32AXF_1_1:
1570        check_dsp(ctx);
1571        switch (extract32(ctx->opcode, 12, 2)) {
1572        case NM_MTHLIP:
1573            tcg_gen_movi_tl(t0, v2 >> 3);
1574            gen_helper_mthlip(t0, v0_t, tcg_env);
1575            break;
1576        case NM_SHILOV:
1577            tcg_gen_movi_tl(t0, v2 >> 3);
1578            gen_helper_shilo(t0, v0_t, tcg_env);
1579            break;
1580        default:
1581            gen_reserved_instruction(ctx);
1582            break;
1583        }
1584        break;
1585    case NM_POOL32AXF_1_3:
1586        check_dsp(ctx);
1587        imm = extract32(ctx->opcode, 14, 7);
1588        switch (extract32(ctx->opcode, 12, 2)) {
1589        case NM_RDDSP:
1590            tcg_gen_movi_tl(t0, imm);
1591            gen_helper_rddsp(t0, t0, tcg_env);
1592            gen_store_gpr(t0, ret);
1593            break;
1594        case NM_WRDSP:
1595            gen_load_gpr(t0, ret);
1596            tcg_gen_movi_tl(t1, imm);
1597            gen_helper_wrdsp(t0, t1, tcg_env);
1598            break;
1599        case NM_EXTP:
1600            tcg_gen_movi_tl(t0, v2 >> 3);
1601            tcg_gen_movi_tl(t1, v1);
1602            gen_helper_extp(t0, t0, t1, tcg_env);
1603            gen_store_gpr(t0, ret);
1604            break;
1605        case NM_EXTPDP:
1606            tcg_gen_movi_tl(t0, v2 >> 3);
1607            tcg_gen_movi_tl(t1, v1);
1608            gen_helper_extpdp(t0, t0, t1, tcg_env);
1609            gen_store_gpr(t0, ret);
1610            break;
1611        }
1612        break;
1613    case NM_POOL32AXF_1_4:
1614        check_dsp(ctx);
1615        tcg_gen_movi_tl(t0, v2 >> 2);
1616        switch (extract32(ctx->opcode, 12, 1)) {
1617        case NM_SHLL_QB:
1618            gen_helper_shll_qb(t0, t0, v0_t, tcg_env);
1619            gen_store_gpr(t0, ret);
1620            break;
1621        case NM_SHRL_QB:
1622            gen_helper_shrl_qb(t0, t0, v0_t);
1623            gen_store_gpr(t0, ret);
1624            break;
1625        }
1626        break;
1627    case NM_POOL32AXF_1_5:
1628        opc = extract32(ctx->opcode, 12, 2);
1629        gen_pool32axf_1_5_nanomips_insn(ctx, opc, ret, v1, v2);
1630        break;
1631    case NM_POOL32AXF_1_7:
1632        check_dsp(ctx);
1633        tcg_gen_movi_tl(t0, v2 >> 3);
1634        tcg_gen_movi_tl(t1, v1);
1635        switch (extract32(ctx->opcode, 12, 2)) {
1636        case NM_EXTR_W:
1637            gen_helper_extr_w(t0, t0, t1, tcg_env);
1638            gen_store_gpr(t0, ret);
1639            break;
1640        case NM_EXTR_R_W:
1641            gen_helper_extr_r_w(t0, t0, t1, tcg_env);
1642            gen_store_gpr(t0, ret);
1643            break;
1644        case NM_EXTR_RS_W:
1645            gen_helper_extr_rs_w(t0, t0, t1, tcg_env);
1646            gen_store_gpr(t0, ret);
1647            break;
1648        case NM_EXTR_S_H:
1649            gen_helper_extr_s_h(t0, t0, t1, tcg_env);
1650            gen_store_gpr(t0, ret);
1651            break;
1652        }
1653        break;
1654    default:
1655        gen_reserved_instruction(ctx);
1656        break;
1657    }
1658}
1659
1660static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
1661                                    TCGv v0, TCGv v1, int rd)
1662{
1663    TCGv_i32 t0;
1664
1665    t0 = tcg_temp_new_i32();
1666
1667    tcg_gen_movi_i32(t0, rd >> 3);
1668
1669    switch (opc) {
1670    case NM_POOL32AXF_2_0_7:
1671        switch (extract32(ctx->opcode, 9, 3)) {
1672        case NM_DPA_W_PH:
1673            check_dsp_r2(ctx);
1674            gen_helper_dpa_w_ph(t0, v1, v0, tcg_env);
1675            break;
1676        case NM_DPAQ_S_W_PH:
1677            check_dsp(ctx);
1678            gen_helper_dpaq_s_w_ph(t0, v1, v0, tcg_env);
1679            break;
1680        case NM_DPS_W_PH:
1681            check_dsp_r2(ctx);
1682            gen_helper_dps_w_ph(t0, v1, v0, tcg_env);
1683            break;
1684        case NM_DPSQ_S_W_PH:
1685            check_dsp(ctx);
1686            gen_helper_dpsq_s_w_ph(t0, v1, v0, tcg_env);
1687            break;
1688        default:
1689            gen_reserved_instruction(ctx);
1690            break;
1691        }
1692        break;
1693    case NM_POOL32AXF_2_8_15:
1694        switch (extract32(ctx->opcode, 9, 3)) {
1695        case NM_DPAX_W_PH:
1696            check_dsp_r2(ctx);
1697            gen_helper_dpax_w_ph(t0, v0, v1, tcg_env);
1698            break;
1699        case NM_DPAQ_SA_L_W:
1700            check_dsp(ctx);
1701            gen_helper_dpaq_sa_l_w(t0, v0, v1, tcg_env);
1702            break;
1703        case NM_DPSX_W_PH:
1704            check_dsp_r2(ctx);
1705            gen_helper_dpsx_w_ph(t0, v0, v1, tcg_env);
1706            break;
1707        case NM_DPSQ_SA_L_W:
1708            check_dsp(ctx);
1709            gen_helper_dpsq_sa_l_w(t0, v0, v1, tcg_env);
1710            break;
1711        default:
1712            gen_reserved_instruction(ctx);
1713            break;
1714        }
1715        break;
1716    case NM_POOL32AXF_2_16_23:
1717        switch (extract32(ctx->opcode, 9, 3)) {
1718        case NM_DPAU_H_QBL:
1719            check_dsp(ctx);
1720            gen_helper_dpau_h_qbl(t0, v0, v1, tcg_env);
1721            break;
1722        case NM_DPAQX_S_W_PH:
1723            check_dsp_r2(ctx);
1724            gen_helper_dpaqx_s_w_ph(t0, v0, v1, tcg_env);
1725            break;
1726        case NM_DPSU_H_QBL:
1727            check_dsp(ctx);
1728            gen_helper_dpsu_h_qbl(t0, v0, v1, tcg_env);
1729            break;
1730        case NM_DPSQX_S_W_PH:
1731            check_dsp_r2(ctx);
1732            gen_helper_dpsqx_s_w_ph(t0, v0, v1, tcg_env);
1733            break;
1734        case NM_MULSA_W_PH:
1735            check_dsp_r2(ctx);
1736            gen_helper_mulsa_w_ph(t0, v0, v1, tcg_env);
1737            break;
1738        default:
1739            gen_reserved_instruction(ctx);
1740            break;
1741        }
1742        break;
1743    case NM_POOL32AXF_2_24_31:
1744        switch (extract32(ctx->opcode, 9, 3)) {
1745        case NM_DPAU_H_QBR:
1746            check_dsp(ctx);
1747            gen_helper_dpau_h_qbr(t0, v1, v0, tcg_env);
1748            break;
1749        case NM_DPAQX_SA_W_PH:
1750            check_dsp_r2(ctx);
1751            gen_helper_dpaqx_sa_w_ph(t0, v1, v0, tcg_env);
1752            break;
1753        case NM_DPSU_H_QBR:
1754            check_dsp(ctx);
1755            gen_helper_dpsu_h_qbr(t0, v1, v0, tcg_env);
1756            break;
1757        case NM_DPSQX_SA_W_PH:
1758            check_dsp_r2(ctx);
1759            gen_helper_dpsqx_sa_w_ph(t0, v1, v0, tcg_env);
1760            break;
1761        case NM_MULSAQ_S_W_PH:
1762            check_dsp(ctx);
1763            gen_helper_mulsaq_s_w_ph(t0, v1, v0, tcg_env);
1764            break;
1765        default:
1766            gen_reserved_instruction(ctx);
1767            break;
1768        }
1769        break;
1770    default:
1771        gen_reserved_instruction(ctx);
1772        break;
1773    }
1774}
1775
1776static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
1777                                          int rt, int rs, int rd)
1778{
1779    int ret = rt;
1780    TCGv t0 = tcg_temp_new();
1781    TCGv t1 = tcg_temp_new();
1782    TCGv v0_t = tcg_temp_new();
1783    TCGv v1_t = tcg_temp_new();
1784
1785    gen_load_gpr(v0_t, rt);
1786    gen_load_gpr(v1_t, rs);
1787
1788    switch (opc) {
1789    case NM_POOL32AXF_2_0_7:
1790        switch (extract32(ctx->opcode, 9, 3)) {
1791        case NM_DPA_W_PH:
1792        case NM_DPAQ_S_W_PH:
1793        case NM_DPS_W_PH:
1794        case NM_DPSQ_S_W_PH:
1795            gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);
1796            break;
1797        case NM_BALIGN:
1798            check_dsp_r2(ctx);
1799            if (rt != 0) {
1800                gen_load_gpr(t0, rs);
1801                rd &= 3;
1802                if (rd != 0 && rd != 2) {
1803                    tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 8 * rd);
1804                    tcg_gen_ext32u_tl(t0, t0);
1805                    tcg_gen_shri_tl(t0, t0, 8 * (4 - rd));
1806                    tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
1807                }
1808                tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
1809            }
1810            break;
1811        case NM_MADD:
1812            check_dsp(ctx);
1813            {
1814                int acc = extract32(ctx->opcode, 14, 2);
1815                TCGv_i64 t2 = tcg_temp_new_i64();
1816                TCGv_i64 t3 = tcg_temp_new_i64();
1817
1818                gen_load_gpr(t0, rt);
1819                gen_load_gpr(t1, rs);
1820                tcg_gen_ext_tl_i64(t2, t0);
1821                tcg_gen_ext_tl_i64(t3, t1);
1822                tcg_gen_mul_i64(t2, t2, t3);
1823                tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
1824                tcg_gen_add_i64(t2, t2, t3);
1825                gen_move_low32(cpu_LO[acc], t2);
1826                gen_move_high32(cpu_HI[acc], t2);
1827            }
1828            break;
1829        case NM_MULT:
1830            check_dsp(ctx);
1831            {
1832                int acc = extract32(ctx->opcode, 14, 2);
1833                TCGv_i32 t2 = tcg_temp_new_i32();
1834                TCGv_i32 t3 = tcg_temp_new_i32();
1835
1836                if (acc || ctx->insn_flags & ISA_MIPS_R6) {
1837                    check_dsp_r2(ctx);
1838                }
1839                gen_load_gpr(t0, rs);
1840                gen_load_gpr(t1, rt);
1841                tcg_gen_trunc_tl_i32(t2, t0);
1842                tcg_gen_trunc_tl_i32(t3, t1);
1843                tcg_gen_muls2_i32(t2, t3, t2, t3);
1844                tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
1845                tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
1846            }
1847            break;
1848        case NM_EXTRV_W:
1849            check_dsp(ctx);
1850            gen_load_gpr(v1_t, rs);
1851            tcg_gen_movi_tl(t0, rd >> 3);
1852            gen_helper_extr_w(t0, t0, v1_t, tcg_env);
1853            gen_store_gpr(t0, ret);
1854            break;
1855        }
1856        break;
1857    case NM_POOL32AXF_2_8_15:
1858        switch (extract32(ctx->opcode, 9, 3)) {
1859        case NM_DPAX_W_PH:
1860        case NM_DPAQ_SA_L_W:
1861        case NM_DPSX_W_PH:
1862        case NM_DPSQ_SA_L_W:
1863            gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);
1864            break;
1865        case NM_MADDU:
1866            check_dsp(ctx);
1867            {
1868                int acc = extract32(ctx->opcode, 14, 2);
1869                TCGv_i64 t2 = tcg_temp_new_i64();
1870                TCGv_i64 t3 = tcg_temp_new_i64();
1871
1872                gen_load_gpr(t0, rs);
1873                gen_load_gpr(t1, rt);
1874                tcg_gen_ext32u_tl(t0, t0);
1875                tcg_gen_ext32u_tl(t1, t1);
1876                tcg_gen_extu_tl_i64(t2, t0);
1877                tcg_gen_extu_tl_i64(t3, t1);
1878                tcg_gen_mul_i64(t2, t2, t3);
1879                tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
1880                tcg_gen_add_i64(t2, t2, t3);
1881                gen_move_low32(cpu_LO[acc], t2);
1882                gen_move_high32(cpu_HI[acc], t2);
1883            }
1884            break;
1885        case NM_MULTU:
1886            check_dsp(ctx);
1887            {
1888                int acc = extract32(ctx->opcode, 14, 2);
1889                TCGv_i32 t2 = tcg_temp_new_i32();
1890                TCGv_i32 t3 = tcg_temp_new_i32();
1891
1892                if (acc || ctx->insn_flags & ISA_MIPS_R6) {
1893                    check_dsp_r2(ctx);
1894                }
1895                gen_load_gpr(t0, rs);
1896                gen_load_gpr(t1, rt);
1897                tcg_gen_trunc_tl_i32(t2, t0);
1898                tcg_gen_trunc_tl_i32(t3, t1);
1899                tcg_gen_mulu2_i32(t2, t3, t2, t3);
1900                tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
1901                tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
1902            }
1903            break;
1904        case NM_EXTRV_R_W:
1905            check_dsp(ctx);
1906            tcg_gen_movi_tl(t0, rd >> 3);
1907            gen_helper_extr_r_w(t0, t0, v1_t, tcg_env);
1908            gen_store_gpr(t0, ret);
1909            break;
1910        default:
1911            gen_reserved_instruction(ctx);
1912            break;
1913        }
1914        break;
1915    case NM_POOL32AXF_2_16_23:
1916        switch (extract32(ctx->opcode, 9, 3)) {
1917        case NM_DPAU_H_QBL:
1918        case NM_DPAQX_S_W_PH:
1919        case NM_DPSU_H_QBL:
1920        case NM_DPSQX_S_W_PH:
1921        case NM_MULSA_W_PH:
1922            gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);
1923            break;
1924        case NM_EXTPV:
1925            check_dsp(ctx);
1926            tcg_gen_movi_tl(t0, rd >> 3);
1927            gen_helper_extp(t0, t0, v1_t, tcg_env);
1928            gen_store_gpr(t0, ret);
1929            break;
1930        case NM_MSUB:
1931            check_dsp(ctx);
1932            {
1933                int acc = extract32(ctx->opcode, 14, 2);
1934                TCGv_i64 t2 = tcg_temp_new_i64();
1935                TCGv_i64 t3 = tcg_temp_new_i64();
1936
1937                gen_load_gpr(t0, rs);
1938                gen_load_gpr(t1, rt);
1939                tcg_gen_ext_tl_i64(t2, t0);
1940                tcg_gen_ext_tl_i64(t3, t1);
1941                tcg_gen_mul_i64(t2, t2, t3);
1942                tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
1943                tcg_gen_sub_i64(t2, t3, t2);
1944                gen_move_low32(cpu_LO[acc], t2);
1945                gen_move_high32(cpu_HI[acc], t2);
1946            }
1947            break;
1948        case NM_EXTRV_RS_W:
1949            check_dsp(ctx);
1950            tcg_gen_movi_tl(t0, rd >> 3);
1951            gen_helper_extr_rs_w(t0, t0, v1_t, tcg_env);
1952            gen_store_gpr(t0, ret);
1953            break;
1954        }
1955        break;
1956    case NM_POOL32AXF_2_24_31:
1957        switch (extract32(ctx->opcode, 9, 3)) {
1958        case NM_DPAU_H_QBR:
1959        case NM_DPAQX_SA_W_PH:
1960        case NM_DPSU_H_QBR:
1961        case NM_DPSQX_SA_W_PH:
1962        case NM_MULSAQ_S_W_PH:
1963            gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);
1964            break;
1965        case NM_EXTPDPV:
1966            check_dsp(ctx);
1967            tcg_gen_movi_tl(t0, rd >> 3);
1968            gen_helper_extpdp(t0, t0, v1_t, tcg_env);
1969            gen_store_gpr(t0, ret);
1970            break;
1971        case NM_MSUBU:
1972            check_dsp(ctx);
1973            {
1974                int acc = extract32(ctx->opcode, 14, 2);
1975                TCGv_i64 t2 = tcg_temp_new_i64();
1976                TCGv_i64 t3 = tcg_temp_new_i64();
1977
1978                gen_load_gpr(t0, rs);
1979                gen_load_gpr(t1, rt);
1980                tcg_gen_ext32u_tl(t0, t0);
1981                tcg_gen_ext32u_tl(t1, t1);
1982                tcg_gen_extu_tl_i64(t2, t0);
1983                tcg_gen_extu_tl_i64(t3, t1);
1984                tcg_gen_mul_i64(t2, t2, t3);
1985                tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
1986                tcg_gen_sub_i64(t2, t3, t2);
1987                gen_move_low32(cpu_LO[acc], t2);
1988                gen_move_high32(cpu_HI[acc], t2);
1989            }
1990            break;
1991        case NM_EXTRV_S_H:
1992            check_dsp(ctx);
1993            tcg_gen_movi_tl(t0, rd >> 3);
1994            gen_helper_extr_s_h(t0, t0, v1_t, tcg_env);
1995            gen_store_gpr(t0, ret);
1996            break;
1997        }
1998        break;
1999    default:
2000        gen_reserved_instruction(ctx);
2001        break;
2002    }
2003}
2004
2005static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
2006                                          int rt, int rs)
2007{
2008    int ret = rt;
2009    TCGv t0 = tcg_temp_new();
2010    TCGv v0_t = tcg_temp_new();
2011
2012    gen_load_gpr(v0_t, rs);
2013
2014    switch (opc) {
2015    case NM_ABSQ_S_QB:
2016        check_dsp_r2(ctx);
2017        gen_helper_absq_s_qb(v0_t, v0_t, tcg_env);
2018        gen_store_gpr(v0_t, ret);
2019        break;
2020    case NM_ABSQ_S_PH:
2021        check_dsp(ctx);
2022        gen_helper_absq_s_ph(v0_t, v0_t, tcg_env);
2023        gen_store_gpr(v0_t, ret);
2024        break;
2025    case NM_ABSQ_S_W:
2026        check_dsp(ctx);
2027        gen_helper_absq_s_w(v0_t, v0_t, tcg_env);
2028        gen_store_gpr(v0_t, ret);
2029        break;
2030    case NM_PRECEQ_W_PHL:
2031        check_dsp(ctx);
2032        tcg_gen_andi_tl(v0_t, v0_t, 0xFFFF0000);
2033        tcg_gen_ext32s_tl(v0_t, v0_t);
2034        gen_store_gpr(v0_t, ret);
2035        break;
2036    case NM_PRECEQ_W_PHR:
2037        check_dsp(ctx);
2038        tcg_gen_andi_tl(v0_t, v0_t, 0x0000FFFF);
2039        tcg_gen_shli_tl(v0_t, v0_t, 16);
2040        tcg_gen_ext32s_tl(v0_t, v0_t);
2041        gen_store_gpr(v0_t, ret);
2042        break;
2043    case NM_PRECEQU_PH_QBL:
2044        check_dsp(ctx);
2045        gen_helper_precequ_ph_qbl(v0_t, v0_t);
2046        gen_store_gpr(v0_t, ret);
2047        break;
2048    case NM_PRECEQU_PH_QBR:
2049        check_dsp(ctx);
2050        gen_helper_precequ_ph_qbr(v0_t, v0_t);
2051        gen_store_gpr(v0_t, ret);
2052        break;
2053    case NM_PRECEQU_PH_QBLA:
2054        check_dsp(ctx);
2055        gen_helper_precequ_ph_qbla(v0_t, v0_t);
2056        gen_store_gpr(v0_t, ret);
2057        break;
2058    case NM_PRECEQU_PH_QBRA:
2059        check_dsp(ctx);
2060        gen_helper_precequ_ph_qbra(v0_t, v0_t);
2061        gen_store_gpr(v0_t, ret);
2062        break;
2063    case NM_PRECEU_PH_QBL:
2064        check_dsp(ctx);
2065        gen_helper_preceu_ph_qbl(v0_t, v0_t);
2066        gen_store_gpr(v0_t, ret);
2067        break;
2068    case NM_PRECEU_PH_QBR:
2069        check_dsp(ctx);
2070        gen_helper_preceu_ph_qbr(v0_t, v0_t);
2071        gen_store_gpr(v0_t, ret);
2072        break;
2073    case NM_PRECEU_PH_QBLA:
2074        check_dsp(ctx);
2075        gen_helper_preceu_ph_qbla(v0_t, v0_t);
2076        gen_store_gpr(v0_t, ret);
2077        break;
2078    case NM_PRECEU_PH_QBRA:
2079        check_dsp(ctx);
2080        gen_helper_preceu_ph_qbra(v0_t, v0_t);
2081        gen_store_gpr(v0_t, ret);
2082        break;
2083    case NM_REPLV_PH:
2084        check_dsp(ctx);
2085        tcg_gen_ext16u_tl(v0_t, v0_t);
2086        tcg_gen_shli_tl(t0, v0_t, 16);
2087        tcg_gen_or_tl(v0_t, v0_t, t0);
2088        tcg_gen_ext32s_tl(v0_t, v0_t);
2089        gen_store_gpr(v0_t, ret);
2090        break;
2091    case NM_REPLV_QB:
2092        check_dsp(ctx);
2093        tcg_gen_ext8u_tl(v0_t, v0_t);
2094        tcg_gen_shli_tl(t0, v0_t, 8);
2095        tcg_gen_or_tl(v0_t, v0_t, t0);
2096        tcg_gen_shli_tl(t0, v0_t, 16);
2097        tcg_gen_or_tl(v0_t, v0_t, t0);
2098        tcg_gen_ext32s_tl(v0_t, v0_t);
2099        gen_store_gpr(v0_t, ret);
2100        break;
2101    case NM_BITREV:
2102        check_dsp(ctx);
2103        gen_helper_bitrev(v0_t, v0_t);
2104        gen_store_gpr(v0_t, ret);
2105        break;
2106    case NM_INSV:
2107        check_dsp(ctx);
2108        {
2109            TCGv tv0 = tcg_temp_new();
2110
2111            gen_load_gpr(tv0, rt);
2112            gen_helper_insv(v0_t, tcg_env, v0_t, tv0);
2113            gen_store_gpr(v0_t, ret);
2114        }
2115        break;
2116    case NM_RADDU_W_QB:
2117        check_dsp(ctx);
2118        gen_helper_raddu_w_qb(v0_t, v0_t);
2119        gen_store_gpr(v0_t, ret);
2120        break;
2121    case NM_BITSWAP:
2122        gen_bitswap(ctx, OPC_BITSWAP, ret, rs);
2123        break;
2124    case NM_CLO:
2125        check_nms(ctx);
2126        gen_cl(ctx, OPC_CLO, ret, rs);
2127        break;
2128    case NM_CLZ:
2129        check_nms(ctx);
2130        gen_cl(ctx, OPC_CLZ, ret, rs);
2131        break;
2132    case NM_WSBH:
2133        gen_bshfl(ctx, OPC_WSBH, ret, rs);
2134        break;
2135    default:
2136        gen_reserved_instruction(ctx);
2137        break;
2138    }
2139}
2140
2141static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
2142                                          int rt, int rs, int rd)
2143{
2144    TCGv t0 = tcg_temp_new();
2145    TCGv rs_t = tcg_temp_new();
2146
2147    gen_load_gpr(rs_t, rs);
2148
2149    switch (opc) {
2150    case NM_SHRA_R_QB:
2151        check_dsp_r2(ctx);
2152        tcg_gen_movi_tl(t0, rd >> 2);
2153        switch (extract32(ctx->opcode, 12, 1)) {
2154        case 0:
2155            /* NM_SHRA_QB */
2156            gen_helper_shra_qb(t0, t0, rs_t);
2157            gen_store_gpr(t0, rt);
2158            break;
2159        case 1:
2160            /* NM_SHRA_R_QB */
2161            gen_helper_shra_r_qb(t0, t0, rs_t);
2162            gen_store_gpr(t0, rt);
2163            break;
2164        }
2165        break;
2166    case NM_SHRL_PH:
2167        check_dsp_r2(ctx);
2168        tcg_gen_movi_tl(t0, rd >> 1);
2169        gen_helper_shrl_ph(t0, t0, rs_t);
2170        gen_store_gpr(t0, rt);
2171        break;
2172    case NM_REPL_QB:
2173        check_dsp(ctx);
2174        {
2175            int16_t imm;
2176            target_long result;
2177            imm = extract32(ctx->opcode, 13, 8);
2178            result = (uint32_t)imm << 24 |
2179                     (uint32_t)imm << 16 |
2180                     (uint32_t)imm << 8  |
2181                     (uint32_t)imm;
2182            result = (int32_t)result;
2183            tcg_gen_movi_tl(t0, result);
2184            gen_store_gpr(t0, rt);
2185        }
2186        break;
2187    default:
2188        gen_reserved_instruction(ctx);
2189        break;
2190    }
2191}
2192
2193
2194static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
2195{
2196    int rt = extract32(ctx->opcode, 21, 5);
2197    int rs = extract32(ctx->opcode, 16, 5);
2198    int rd = extract32(ctx->opcode, 11, 5);
2199
2200    switch (extract32(ctx->opcode, 6, 3)) {
2201    case NM_POOL32AXF_1:
2202        {
2203            int32_t op1 = extract32(ctx->opcode, 9, 3);
2204            gen_pool32axf_1_nanomips_insn(ctx, op1, rt, rs, rd);
2205        }
2206        break;
2207    case NM_POOL32AXF_2:
2208        {
2209            int32_t op1 = extract32(ctx->opcode, 12, 2);
2210            gen_pool32axf_2_nanomips_insn(ctx, op1, rt, rs, rd);
2211        }
2212        break;
2213    case NM_POOL32AXF_4:
2214        {
2215            int32_t op1 = extract32(ctx->opcode, 9, 7);
2216            gen_pool32axf_4_nanomips_insn(ctx, op1, rt, rs);
2217        }
2218        break;
2219    case NM_POOL32AXF_5:
2220        switch (extract32(ctx->opcode, 9, 7)) {
2221#ifndef CONFIG_USER_ONLY
2222        case NM_TLBP:
2223            gen_cp0(env, ctx, OPC_TLBP, 0, 0);
2224            break;
2225        case NM_TLBR:
2226            gen_cp0(env, ctx, OPC_TLBR, 0, 0);
2227            break;
2228        case NM_TLBWI:
2229            gen_cp0(env, ctx, OPC_TLBWI, 0, 0);
2230            break;
2231        case NM_TLBWR:
2232            gen_cp0(env, ctx, OPC_TLBWR, 0, 0);
2233            break;
2234        case NM_TLBINV:
2235            gen_cp0(env, ctx, OPC_TLBINV, 0, 0);
2236            break;
2237        case NM_TLBINVF:
2238            gen_cp0(env, ctx, OPC_TLBINVF, 0, 0);
2239            break;
2240        case NM_DI:
2241            check_cp0_enabled(ctx);
2242            {
2243                TCGv t0 = tcg_temp_new();
2244
2245                save_cpu_state(ctx, 1);
2246                gen_helper_di(t0, tcg_env);
2247                gen_store_gpr(t0, rt);
2248            /* Stop translation as we may have switched the execution mode */
2249                ctx->base.is_jmp = DISAS_STOP;
2250            }
2251            break;
2252        case NM_EI:
2253            check_cp0_enabled(ctx);
2254            {
2255                TCGv t0 = tcg_temp_new();
2256
2257                save_cpu_state(ctx, 1);
2258                gen_helper_ei(t0, tcg_env);
2259                gen_store_gpr(t0, rt);
2260            /* Stop translation as we may have switched the execution mode */
2261                ctx->base.is_jmp = DISAS_STOP;
2262            }
2263            break;
2264        case NM_RDPGPR:
2265            check_cp0_enabled(ctx);
2266            gen_load_srsgpr(rs, rt);
2267            break;
2268        case NM_WRPGPR:
2269            check_cp0_enabled(ctx);
2270            gen_store_srsgpr(rs, rt);
2271            break;
2272        case NM_WAIT:
2273            gen_cp0(env, ctx, OPC_WAIT, 0, 0);
2274            break;
2275        case NM_DERET:
2276            gen_cp0(env, ctx, OPC_DERET, 0, 0);
2277            break;
2278        case NM_ERETX:
2279            gen_cp0(env, ctx, OPC_ERET, 0, 0);
2280            break;
2281#endif
2282        default:
2283            gen_reserved_instruction(ctx);
2284            break;
2285        }
2286        break;
2287    case NM_POOL32AXF_7:
2288        {
2289            int32_t op1 = extract32(ctx->opcode, 9, 3);
2290            gen_pool32axf_7_nanomips_insn(ctx, op1, rt, rs, rd);
2291        }
2292        break;
2293    default:
2294        gen_reserved_instruction(ctx);
2295        break;
2296    }
2297}
2298
2299/* Immediate Value Compact Branches */
2300static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
2301                                   int rt, int32_t imm, int32_t offset)
2302{
2303    TCGCond cond = TCG_COND_ALWAYS;
2304    TCGv t0 = tcg_temp_new();
2305    TCGv t1 = tcg_temp_new();
2306
2307    gen_load_gpr(t0, rt);
2308    tcg_gen_movi_tl(t1, imm);
2309    ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
2310
2311    /* Load needed operands and calculate btarget */
2312    switch (opc) {
2313    case NM_BEQIC:
2314        if (rt == 0 && imm == 0) {
2315            /* Unconditional branch */
2316        } else if (rt == 0 && imm != 0) {
2317            /* Treat as NOP */
2318            return;
2319        } else {
2320            cond = TCG_COND_EQ;
2321        }
2322        break;
2323    case NM_BBEQZC:
2324    case NM_BBNEZC:
2325        check_nms(ctx);
2326        if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) {
2327            gen_reserved_instruction(ctx);
2328            return;
2329        } else if (rt == 0 && opc == NM_BBEQZC) {
2330            /* Unconditional branch */
2331        } else if (rt == 0 && opc == NM_BBNEZC) {
2332            /* Treat as NOP */
2333            return;
2334        } else {
2335            tcg_gen_shri_tl(t0, t0, imm);
2336            tcg_gen_andi_tl(t0, t0, 1);
2337            tcg_gen_movi_tl(t1, 0);
2338            if (opc == NM_BBEQZC) {
2339                cond = TCG_COND_EQ;
2340            } else {
2341                cond = TCG_COND_NE;
2342            }
2343        }
2344        break;
2345    case NM_BNEIC:
2346        if (rt == 0 && imm == 0) {
2347            /* Treat as NOP */
2348            return;
2349        } else if (rt == 0 && imm != 0) {
2350            /* Unconditional branch */
2351        } else {
2352            cond = TCG_COND_NE;
2353        }
2354        break;
2355    case NM_BGEIC:
2356        if (rt == 0 && imm == 0) {
2357            /* Unconditional branch */
2358        } else  {
2359            cond = TCG_COND_GE;
2360        }
2361        break;
2362    case NM_BLTIC:
2363        cond = TCG_COND_LT;
2364        break;
2365    case NM_BGEIUC:
2366        if (rt == 0 && imm == 0) {
2367            /* Unconditional branch */
2368        } else  {
2369            cond = TCG_COND_GEU;
2370        }
2371        break;
2372    case NM_BLTIUC:
2373        cond = TCG_COND_LTU;
2374        break;
2375    default:
2376        MIPS_INVAL("Immediate Value Compact branch");
2377        gen_reserved_instruction(ctx);
2378        return;
2379    }
2380
2381    /* branch completion */
2382    clear_branch_hflags(ctx);
2383    ctx->base.is_jmp = DISAS_NORETURN;
2384
2385    if (cond == TCG_COND_ALWAYS) {
2386        /* Uncoditional compact branch */
2387        gen_goto_tb(ctx, 0, ctx->btarget);
2388    } else {
2389        /* Conditional compact branch */
2390        TCGLabel *fs = gen_new_label();
2391
2392        tcg_gen_brcond_tl(tcg_invert_cond(cond), t0, t1, fs);
2393
2394        gen_goto_tb(ctx, 1, ctx->btarget);
2395        gen_set_label(fs);
2396
2397        gen_goto_tb(ctx, 0, ctx->base.pc_next + 4);
2398    }
2399}
2400
2401/* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */
2402static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,
2403                                                int rt)
2404{
2405    TCGv t0 = tcg_temp_new();
2406    TCGv t1 = tcg_temp_new();
2407
2408    /* load rs */
2409    gen_load_gpr(t0, rs);
2410
2411    /* link */
2412    if (rt != 0) {
2413        tcg_gen_movi_tl(cpu_gpr[rt], ctx->base.pc_next + 4);
2414    }
2415
2416    /* calculate btarget */
2417    tcg_gen_shli_tl(t0, t0, 1);
2418    tcg_gen_movi_tl(t1, ctx->base.pc_next + 4);
2419    gen_op_addr_add(ctx, btarget, t1, t0);
2420
2421    /* branch completion */
2422    clear_branch_hflags(ctx);
2423    ctx->base.is_jmp = DISAS_NORETURN;
2424
2425    /* unconditional branch to register */
2426    tcg_gen_mov_tl(cpu_PC, btarget);
2427    tcg_gen_lookup_and_goto_ptr();
2428}
2429
2430/* nanoMIPS Branches */
2431static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
2432                                       int rs, int rt, int32_t offset)
2433{
2434    int bcond_compute = 0;
2435    TCGv t0 = tcg_temp_new();
2436    TCGv t1 = tcg_temp_new();
2437
2438    /* Load needed operands and calculate btarget */
2439    switch (opc) {
2440    /* compact branch */
2441    case OPC_BGEC:
2442    case OPC_BLTC:
2443        gen_load_gpr(t0, rs);
2444        gen_load_gpr(t1, rt);
2445        bcond_compute = 1;
2446        ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
2447        break;
2448    case OPC_BGEUC:
2449    case OPC_BLTUC:
2450        if (rs == 0 || rs == rt) {
2451            /* OPC_BLEZALC, OPC_BGEZALC */
2452            /* OPC_BGTZALC, OPC_BLTZALC */
2453            tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4);
2454        }
2455        gen_load_gpr(t0, rs);
2456        gen_load_gpr(t1, rt);
2457        bcond_compute = 1;
2458        ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
2459        break;
2460    case OPC_BC:
2461        ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
2462        break;
2463    case OPC_BEQZC:
2464        if (rs != 0) {
2465            /* OPC_BEQZC, OPC_BNEZC */
2466            gen_load_gpr(t0, rs);
2467            bcond_compute = 1;
2468            ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
2469        } else {
2470            /* OPC_JIC, OPC_JIALC */
2471            TCGv tbase = tcg_temp_new();
2472            TCGv toffset = tcg_temp_new();
2473
2474            gen_load_gpr(tbase, rt);
2475            tcg_gen_movi_tl(toffset, offset);
2476            gen_op_addr_add(ctx, btarget, tbase, toffset);
2477        }
2478        break;
2479    default:
2480        MIPS_INVAL("Compact branch/jump");
2481        gen_reserved_instruction(ctx);
2482        return;
2483    }
2484
2485    if (bcond_compute == 0) {
2486        /* Uncoditional compact branch */
2487        switch (opc) {
2488        case OPC_BC:
2489            gen_goto_tb(ctx, 0, ctx->btarget);
2490            break;
2491        default:
2492            MIPS_INVAL("Compact branch/jump");
2493            gen_reserved_instruction(ctx);
2494            return;
2495        }
2496    } else {
2497        /* Conditional compact branch */
2498        TCGLabel *fs = gen_new_label();
2499
2500        switch (opc) {
2501        case OPC_BGEUC:
2502            if (rs == 0 && rt != 0) {
2503                /* OPC_BLEZALC */
2504                tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
2505            } else if (rs != 0 && rt != 0 && rs == rt) {
2506                /* OPC_BGEZALC */
2507                tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
2508            } else {
2509                /* OPC_BGEUC */
2510                tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs);
2511            }
2512            break;
2513        case OPC_BLTUC:
2514            if (rs == 0 && rt != 0) {
2515                /* OPC_BGTZALC */
2516                tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
2517            } else if (rs != 0 && rt != 0 && rs == rt) {
2518                /* OPC_BLTZALC */
2519                tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
2520            } else {
2521                /* OPC_BLTUC */
2522                tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs);
2523            }
2524            break;
2525        case OPC_BGEC:
2526            if (rs == 0 && rt != 0) {
2527                /* OPC_BLEZC */
2528                tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
2529            } else if (rs != 0 && rt != 0 && rs == rt) {
2530                /* OPC_BGEZC */
2531                tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
2532            } else {
2533                /* OPC_BGEC */
2534                tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs);
2535            }
2536            break;
2537        case OPC_BLTC:
2538            if (rs == 0 && rt != 0) {
2539                /* OPC_BGTZC */
2540                tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
2541            } else if (rs != 0 && rt != 0 && rs == rt) {
2542                /* OPC_BLTZC */
2543                tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
2544            } else {
2545                /* OPC_BLTC */
2546                tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs);
2547            }
2548            break;
2549        case OPC_BEQZC:
2550            tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t0, 0, fs);
2551            break;
2552        default:
2553            MIPS_INVAL("Compact conditional branch/jump");
2554            gen_reserved_instruction(ctx);
2555            return;
2556        }
2557
2558        /* branch completion */
2559        clear_branch_hflags(ctx);
2560        ctx->base.is_jmp = DISAS_NORETURN;
2561
2562        /* Generating branch here as compact branches don't have delay slot */
2563        gen_goto_tb(ctx, 1, ctx->btarget);
2564        gen_set_label(fs);
2565
2566        gen_goto_tb(ctx, 0, ctx->base.pc_next + 4);
2567    }
2568}
2569
2570
2571/* nanoMIPS CP1 Branches */
2572static void gen_compute_branch_cp1_nm(DisasContext *ctx, uint32_t op,
2573                                   int32_t ft, int32_t offset)
2574{
2575    target_ulong btarget;
2576    TCGv_i64 t0 = tcg_temp_new_i64();
2577
2578    gen_load_fpr64(ctx, t0, ft);
2579    tcg_gen_andi_i64(t0, t0, 1);
2580
2581    btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
2582
2583    switch (op) {
2584    case NM_BC1EQZC:
2585        tcg_gen_xori_i64(t0, t0, 1);
2586        ctx->hflags |= MIPS_HFLAG_BC;
2587        break;
2588    case NM_BC1NEZC:
2589        /* t0 already set */
2590        ctx->hflags |= MIPS_HFLAG_BC;
2591        break;
2592    default:
2593        MIPS_INVAL("cp1 cond branch");
2594        gen_reserved_instruction(ctx);
2595        return;
2596    }
2597
2598    tcg_gen_trunc_i64_tl(bcond, t0);
2599
2600    ctx->btarget = btarget;
2601}
2602
2603
2604static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
2605{
2606    TCGv t0, t1;
2607    t0 = tcg_temp_new();
2608    t1 = tcg_temp_new();
2609
2610    gen_load_gpr(t0, rs);
2611    gen_load_gpr(t1, rt);
2612
2613    if ((extract32(ctx->opcode, 6, 1)) == 1) {
2614        /* PP.LSXS instructions require shifting */
2615        switch (extract32(ctx->opcode, 7, 4)) {
2616        case NM_SHXS:
2617            check_nms(ctx);
2618            /* fall through */
2619        case NM_LHXS:
2620        case NM_LHUXS:
2621            tcg_gen_shli_tl(t0, t0, 1);
2622            break;
2623        case NM_SWXS:
2624            check_nms(ctx);
2625            /* fall through */
2626        case NM_LWXS:
2627        case NM_LWC1XS:
2628        case NM_SWC1XS:
2629            tcg_gen_shli_tl(t0, t0, 2);
2630            break;
2631        case NM_LDC1XS:
2632        case NM_SDC1XS:
2633            tcg_gen_shli_tl(t0, t0, 3);
2634            break;
2635        default:
2636            gen_reserved_instruction(ctx);
2637            return;
2638        }
2639    }
2640    gen_op_addr_add(ctx, t0, t0, t1);
2641
2642    switch (extract32(ctx->opcode, 7, 4)) {
2643    case NM_LBX:
2644        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
2645        gen_store_gpr(t0, rd);
2646        break;
2647    case NM_LHX:
2648    /*case NM_LHXS:*/
2649        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
2650                           MO_TESW | ctx->default_tcg_memop_mask);
2651        gen_store_gpr(t0, rd);
2652        break;
2653    case NM_LWX:
2654    /*case NM_LWXS:*/
2655        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
2656                           MO_TESL | ctx->default_tcg_memop_mask);
2657        gen_store_gpr(t0, rd);
2658        break;
2659    case NM_LBUX:
2660        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
2661        gen_store_gpr(t0, rd);
2662        break;
2663    case NM_LHUX:
2664    /*case NM_LHUXS:*/
2665        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
2666                           MO_TEUW | ctx->default_tcg_memop_mask);
2667        gen_store_gpr(t0, rd);
2668        break;
2669    case NM_SBX:
2670        check_nms(ctx);
2671        gen_load_gpr(t1, rd);
2672        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_8);
2673        break;
2674    case NM_SHX:
2675    /*case NM_SHXS:*/
2676        check_nms(ctx);
2677        gen_load_gpr(t1, rd);
2678        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
2679                           MO_TEUW | ctx->default_tcg_memop_mask);
2680        break;
2681    case NM_SWX:
2682    /*case NM_SWXS:*/
2683        check_nms(ctx);
2684        gen_load_gpr(t1, rd);
2685        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
2686                           MO_TEUL | ctx->default_tcg_memop_mask);
2687        break;
2688    case NM_LWC1X:
2689    /*case NM_LWC1XS:*/
2690    case NM_LDC1X:
2691    /*case NM_LDC1XS:*/
2692    case NM_SWC1X:
2693    /*case NM_SWC1XS:*/
2694    case NM_SDC1X:
2695    /*case NM_SDC1XS:*/
2696        if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
2697            check_cp1_enabled(ctx);
2698            switch (extract32(ctx->opcode, 7, 4)) {
2699            case NM_LWC1X:
2700            /*case NM_LWC1XS:*/
2701                gen_flt_ldst(ctx, OPC_LWC1, rd, t0);
2702                break;
2703            case NM_LDC1X:
2704            /*case NM_LDC1XS:*/
2705                gen_flt_ldst(ctx, OPC_LDC1, rd, t0);
2706                break;
2707            case NM_SWC1X:
2708            /*case NM_SWC1XS:*/
2709                gen_flt_ldst(ctx, OPC_SWC1, rd, t0);
2710                break;
2711            case NM_SDC1X:
2712            /*case NM_SDC1XS:*/
2713                gen_flt_ldst(ctx, OPC_SDC1, rd, t0);
2714                break;
2715            }
2716        } else {
2717            generate_exception_err(ctx, EXCP_CpU, 1);
2718        }
2719        break;
2720    default:
2721        gen_reserved_instruction(ctx);
2722        break;
2723    }
2724}
2725
2726static void gen_pool32f_nanomips_insn(DisasContext *ctx)
2727{
2728    int rt, rs, rd;
2729
2730    rt = extract32(ctx->opcode, 21, 5);
2731    rs = extract32(ctx->opcode, 16, 5);
2732    rd = extract32(ctx->opcode, 11, 5);
2733
2734    if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) {
2735        gen_reserved_instruction(ctx);
2736        return;
2737    }
2738    check_cp1_enabled(ctx);
2739    switch (extract32(ctx->opcode, 0, 3)) {
2740    case NM_POOL32F_0:
2741        switch (extract32(ctx->opcode, 3, 7)) {
2742        case NM_RINT_S:
2743            gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0);
2744            break;
2745        case NM_RINT_D:
2746            gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0);
2747            break;
2748        case NM_CLASS_S:
2749            gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0);
2750            break;
2751        case NM_CLASS_D:
2752            gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0);
2753            break;
2754        case NM_ADD_S:
2755            gen_farith(ctx, OPC_ADD_S, rt, rs, rd, 0);
2756            break;
2757        case NM_ADD_D:
2758            gen_farith(ctx, OPC_ADD_D, rt, rs, rd, 0);
2759            break;
2760        case NM_SUB_S:
2761            gen_farith(ctx, OPC_SUB_S, rt, rs, rd, 0);
2762            break;
2763        case NM_SUB_D:
2764            gen_farith(ctx, OPC_SUB_D, rt, rs, rd, 0);
2765            break;
2766        case NM_MUL_S:
2767            gen_farith(ctx, OPC_MUL_S, rt, rs, rd, 0);
2768            break;
2769        case NM_MUL_D:
2770            gen_farith(ctx, OPC_MUL_D, rt, rs, rd, 0);
2771            break;
2772        case NM_DIV_S:
2773            gen_farith(ctx, OPC_DIV_S, rt, rs, rd, 0);
2774            break;
2775        case NM_DIV_D:
2776            gen_farith(ctx, OPC_DIV_D, rt, rs, rd, 0);
2777            break;
2778        case NM_SELEQZ_S:
2779            gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
2780            break;
2781        case NM_SELEQZ_D:
2782            gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
2783            break;
2784        case NM_SELNEZ_S:
2785            gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
2786            break;
2787        case NM_SELNEZ_D:
2788            gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
2789            break;
2790        case NM_SEL_S:
2791            gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);
2792            break;
2793        case NM_SEL_D:
2794            gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs);
2795            break;
2796        case NM_MADDF_S:
2797            gen_farith(ctx, OPC_MADDF_S, rt, rs, rd, 0);
2798            break;
2799        case NM_MADDF_D:
2800            gen_farith(ctx, OPC_MADDF_D, rt, rs, rd, 0);
2801            break;
2802        case NM_MSUBF_S:
2803            gen_farith(ctx, OPC_MSUBF_S, rt, rs, rd, 0);
2804            break;
2805        case NM_MSUBF_D:
2806            gen_farith(ctx, OPC_MSUBF_D, rt, rs, rd, 0);
2807            break;
2808        default:
2809            gen_reserved_instruction(ctx);
2810            break;
2811        }
2812        break;
2813    case NM_POOL32F_3:
2814        switch (extract32(ctx->opcode, 3, 3)) {
2815        case NM_MIN_FMT:
2816            switch (extract32(ctx->opcode, 9, 1)) {
2817            case FMT_SDPS_S:
2818                gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);
2819                break;
2820            case FMT_SDPS_D:
2821                gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0);
2822                break;
2823            }
2824            break;
2825        case NM_MAX_FMT:
2826            switch (extract32(ctx->opcode, 9, 1)) {
2827            case FMT_SDPS_S:
2828                gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);
2829                break;
2830            case FMT_SDPS_D:
2831                gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0);
2832                break;
2833            }
2834            break;
2835        case NM_MINA_FMT:
2836            switch (extract32(ctx->opcode, 9, 1)) {
2837            case FMT_SDPS_S:
2838                gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);
2839                break;
2840            case FMT_SDPS_D:
2841                gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0);
2842                break;
2843            }
2844            break;
2845        case NM_MAXA_FMT:
2846            switch (extract32(ctx->opcode, 9, 1)) {
2847            case FMT_SDPS_S:
2848                gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);
2849                break;
2850            case FMT_SDPS_D:
2851                gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0);
2852                break;
2853            }
2854            break;
2855        case NM_POOL32FXF:
2856            switch (extract32(ctx->opcode, 6, 8)) {
2857            case NM_CFC1:
2858                gen_cp1(ctx, OPC_CFC1, rt, rs);
2859                break;
2860            case NM_CTC1:
2861                gen_cp1(ctx, OPC_CTC1, rt, rs);
2862                break;
2863            case NM_MFC1:
2864                gen_cp1(ctx, OPC_MFC1, rt, rs);
2865                break;
2866            case NM_MTC1:
2867                gen_cp1(ctx, OPC_MTC1, rt, rs);
2868                break;
2869            case NM_MFHC1:
2870                gen_cp1(ctx, OPC_MFHC1, rt, rs);
2871                break;
2872            case NM_MTHC1:
2873                gen_cp1(ctx, OPC_MTHC1, rt, rs);
2874                break;
2875            case NM_CVT_S_PL:
2876                gen_farith(ctx, OPC_CVT_S_PL, -1, rs, rt, 0);
2877                break;
2878            case NM_CVT_S_PU:
2879                gen_farith(ctx, OPC_CVT_S_PU, -1, rs, rt, 0);
2880                break;
2881            default:
2882                switch (extract32(ctx->opcode, 6, 9)) {
2883                case NM_CVT_L_S:
2884                    gen_farith(ctx, OPC_CVT_L_S, -1, rs, rt, 0);
2885                    break;
2886                case NM_CVT_L_D:
2887                    gen_farith(ctx, OPC_CVT_L_D, -1, rs, rt, 0);
2888                    break;
2889                case NM_CVT_W_S:
2890                    gen_farith(ctx, OPC_CVT_W_S, -1, rs, rt, 0);
2891                    break;
2892                case NM_CVT_W_D:
2893                    gen_farith(ctx, OPC_CVT_W_D, -1, rs, rt, 0);
2894                    break;
2895                case NM_RSQRT_S:
2896                    gen_farith(ctx, OPC_RSQRT_S, -1, rs, rt, 0);
2897                    break;
2898                case NM_RSQRT_D:
2899                    gen_farith(ctx, OPC_RSQRT_D, -1, rs, rt, 0);
2900                    break;
2901                case NM_SQRT_S:
2902                    gen_farith(ctx, OPC_SQRT_S, -1, rs, rt, 0);
2903                    break;
2904                case NM_SQRT_D:
2905                    gen_farith(ctx, OPC_SQRT_D, -1, rs, rt, 0);
2906                    break;
2907                case NM_RECIP_S:
2908                    gen_farith(ctx, OPC_RECIP_S, -1, rs, rt, 0);
2909                    break;
2910                case NM_RECIP_D:
2911                    gen_farith(ctx, OPC_RECIP_D, -1, rs, rt, 0);
2912                    break;
2913                case NM_FLOOR_L_S:
2914                    gen_farith(ctx, OPC_FLOOR_L_S, -1, rs, rt, 0);
2915                    break;
2916                case NM_FLOOR_L_D:
2917                    gen_farith(ctx, OPC_FLOOR_L_D, -1, rs, rt, 0);
2918                    break;
2919                case NM_FLOOR_W_S:
2920                    gen_farith(ctx, OPC_FLOOR_W_S, -1, rs, rt, 0);
2921                    break;
2922                case NM_FLOOR_W_D:
2923                    gen_farith(ctx, OPC_FLOOR_W_D, -1, rs, rt, 0);
2924                    break;
2925                case NM_CEIL_L_S:
2926                    gen_farith(ctx, OPC_CEIL_L_S, -1, rs, rt, 0);
2927                    break;
2928                case NM_CEIL_L_D:
2929                    gen_farith(ctx, OPC_CEIL_L_D, -1, rs, rt, 0);
2930                    break;
2931                case NM_CEIL_W_S:
2932                    gen_farith(ctx, OPC_CEIL_W_S, -1, rs, rt, 0);
2933                    break;
2934                case NM_CEIL_W_D:
2935                    gen_farith(ctx, OPC_CEIL_W_D, -1, rs, rt, 0);
2936                    break;
2937                case NM_TRUNC_L_S:
2938                    gen_farith(ctx, OPC_TRUNC_L_S, -1, rs, rt, 0);
2939                    break;
2940                case NM_TRUNC_L_D:
2941                    gen_farith(ctx, OPC_TRUNC_L_D, -1, rs, rt, 0);
2942                    break;
2943                case NM_TRUNC_W_S:
2944                    gen_farith(ctx, OPC_TRUNC_W_S, -1, rs, rt, 0);
2945                    break;
2946                case NM_TRUNC_W_D:
2947                    gen_farith(ctx, OPC_TRUNC_W_D, -1, rs, rt, 0);
2948                    break;
2949                case NM_ROUND_L_S:
2950                    gen_farith(ctx, OPC_ROUND_L_S, -1, rs, rt, 0);
2951                    break;
2952                case NM_ROUND_L_D:
2953                    gen_farith(ctx, OPC_ROUND_L_D, -1, rs, rt, 0);
2954                    break;
2955                case NM_ROUND_W_S:
2956                    gen_farith(ctx, OPC_ROUND_W_S, -1, rs, rt, 0);
2957                    break;
2958                case NM_ROUND_W_D:
2959                    gen_farith(ctx, OPC_ROUND_W_D, -1, rs, rt, 0);
2960                    break;
2961                case NM_MOV_S:
2962                    gen_farith(ctx, OPC_MOV_S, -1, rs, rt, 0);
2963                    break;
2964                case NM_MOV_D:
2965                    gen_farith(ctx, OPC_MOV_D, -1, rs, rt, 0);
2966                    break;
2967                case NM_ABS_S:
2968                    gen_farith(ctx, OPC_ABS_S, -1, rs, rt, 0);
2969                    break;
2970                case NM_ABS_D:
2971                    gen_farith(ctx, OPC_ABS_D, -1, rs, rt, 0);
2972                    break;
2973                case NM_NEG_S:
2974                    gen_farith(ctx, OPC_NEG_S, -1, rs, rt, 0);
2975                    break;
2976                case NM_NEG_D:
2977                    gen_farith(ctx, OPC_NEG_D, -1, rs, rt, 0);
2978                    break;
2979                case NM_CVT_D_S:
2980                    gen_farith(ctx, OPC_CVT_D_S, -1, rs, rt, 0);
2981                    break;
2982                case NM_CVT_D_W:
2983                    gen_farith(ctx, OPC_CVT_D_W, -1, rs, rt, 0);
2984                    break;
2985                case NM_CVT_D_L:
2986                    gen_farith(ctx, OPC_CVT_D_L, -1, rs, rt, 0);
2987                    break;
2988                case NM_CVT_S_D:
2989                    gen_farith(ctx, OPC_CVT_S_D, -1, rs, rt, 0);
2990                    break;
2991                case NM_CVT_S_W:
2992                    gen_farith(ctx, OPC_CVT_S_W, -1, rs, rt, 0);
2993                    break;
2994                case NM_CVT_S_L:
2995                    gen_farith(ctx, OPC_CVT_S_L, -1, rs, rt, 0);
2996                    break;
2997                default:
2998                    gen_reserved_instruction(ctx);
2999                    break;
3000                }
3001                break;
3002            }
3003            break;
3004        }
3005        break;
3006    case NM_POOL32F_5:
3007        switch (extract32(ctx->opcode, 3, 3)) {
3008        case NM_CMP_CONDN_S:
3009            gen_r6_cmp_s(ctx, extract32(ctx->opcode, 6, 5), rt, rs, rd);
3010            break;
3011        case NM_CMP_CONDN_D:
3012            gen_r6_cmp_d(ctx, extract32(ctx->opcode, 6, 5), rt, rs, rd);
3013            break;
3014        default:
3015            gen_reserved_instruction(ctx);
3016            break;
3017        }
3018        break;
3019    default:
3020        gen_reserved_instruction(ctx);
3021        break;
3022    }
3023}
3024
3025static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
3026                                       int rd, int rs, int rt)
3027{
3028    int ret = rd;
3029    TCGv t0 = tcg_temp_new();
3030    TCGv v1_t = tcg_temp_new();
3031    TCGv v2_t = tcg_temp_new();
3032
3033    gen_load_gpr(v1_t, rs);
3034    gen_load_gpr(v2_t, rt);
3035
3036    switch (opc) {
3037    case NM_CMP_EQ_PH:
3038        check_dsp(ctx);
3039        gen_helper_cmp_eq_ph(v1_t, v2_t, tcg_env);
3040        break;
3041    case NM_CMP_LT_PH:
3042        check_dsp(ctx);
3043        gen_helper_cmp_lt_ph(v1_t, v2_t, tcg_env);
3044        break;
3045    case NM_CMP_LE_PH:
3046        check_dsp(ctx);
3047        gen_helper_cmp_le_ph(v1_t, v2_t, tcg_env);
3048        break;
3049    case NM_CMPU_EQ_QB:
3050        check_dsp(ctx);
3051        gen_helper_cmpu_eq_qb(v1_t, v2_t, tcg_env);
3052        break;
3053    case NM_CMPU_LT_QB:
3054        check_dsp(ctx);
3055        gen_helper_cmpu_lt_qb(v1_t, v2_t, tcg_env);
3056        break;
3057    case NM_CMPU_LE_QB:
3058        check_dsp(ctx);
3059        gen_helper_cmpu_le_qb(v1_t, v2_t, tcg_env);
3060        break;
3061    case NM_CMPGU_EQ_QB:
3062        check_dsp(ctx);
3063        gen_helper_cmpgu_eq_qb(v1_t, v1_t, v2_t);
3064        gen_store_gpr(v1_t, ret);
3065        break;
3066    case NM_CMPGU_LT_QB:
3067        check_dsp(ctx);
3068        gen_helper_cmpgu_lt_qb(v1_t, v1_t, v2_t);
3069        gen_store_gpr(v1_t, ret);
3070        break;
3071    case NM_CMPGU_LE_QB:
3072        check_dsp(ctx);
3073        gen_helper_cmpgu_le_qb(v1_t, v1_t, v2_t);
3074        gen_store_gpr(v1_t, ret);
3075        break;
3076    case NM_CMPGDU_EQ_QB:
3077        check_dsp_r2(ctx);
3078        gen_helper_cmpgu_eq_qb(v1_t, v1_t, v2_t);
3079        tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);
3080        gen_store_gpr(v1_t, ret);
3081        break;
3082    case NM_CMPGDU_LT_QB:
3083        check_dsp_r2(ctx);
3084        gen_helper_cmpgu_lt_qb(v1_t, v1_t, v2_t);
3085        tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);
3086        gen_store_gpr(v1_t, ret);
3087        break;
3088    case NM_CMPGDU_LE_QB:
3089        check_dsp_r2(ctx);
3090        gen_helper_cmpgu_le_qb(v1_t, v1_t, v2_t);
3091        tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);
3092        gen_store_gpr(v1_t, ret);
3093        break;
3094    case NM_PACKRL_PH:
3095        check_dsp(ctx);
3096        gen_helper_packrl_ph(v1_t, v1_t, v2_t);
3097        gen_store_gpr(v1_t, ret);
3098        break;
3099    case NM_PICK_QB:
3100        check_dsp(ctx);
3101        gen_helper_pick_qb(v1_t, v1_t, v2_t, tcg_env);
3102        gen_store_gpr(v1_t, ret);
3103        break;
3104    case NM_PICK_PH:
3105        check_dsp(ctx);
3106        gen_helper_pick_ph(v1_t, v1_t, v2_t, tcg_env);
3107        gen_store_gpr(v1_t, ret);
3108        break;
3109    case NM_ADDQ_S_W:
3110        check_dsp(ctx);
3111        gen_helper_addq_s_w(v1_t, v1_t, v2_t, tcg_env);
3112        gen_store_gpr(v1_t, ret);
3113        break;
3114    case NM_SUBQ_S_W:
3115        check_dsp(ctx);
3116        gen_helper_subq_s_w(v1_t, v1_t, v2_t, tcg_env);
3117        gen_store_gpr(v1_t, ret);
3118        break;
3119    case NM_ADDSC:
3120        check_dsp(ctx);
3121        gen_helper_addsc(v1_t, v1_t, v2_t, tcg_env);
3122        gen_store_gpr(v1_t, ret);
3123        break;
3124    case NM_ADDWC:
3125        check_dsp(ctx);
3126        gen_helper_addwc(v1_t, v1_t, v2_t, tcg_env);
3127        gen_store_gpr(v1_t, ret);
3128        break;
3129    case NM_ADDQ_S_PH:
3130        check_dsp(ctx);
3131        switch (extract32(ctx->opcode, 10, 1)) {
3132        case 0:
3133            /* ADDQ_PH */
3134            gen_helper_addq_ph(v1_t, v1_t, v2_t, tcg_env);
3135            gen_store_gpr(v1_t, ret);
3136            break;
3137        case 1:
3138            /* ADDQ_S_PH */
3139            gen_helper_addq_s_ph(v1_t, v1_t, v2_t, tcg_env);
3140            gen_store_gpr(v1_t, ret);
3141            break;
3142        }
3143        break;
3144    case NM_ADDQH_R_PH:
3145        check_dsp_r2(ctx);
3146        switch (extract32(ctx->opcode, 10, 1)) {
3147        case 0:
3148            /* ADDQH_PH */
3149            gen_helper_addqh_ph(v1_t, v1_t, v2_t);
3150            gen_store_gpr(v1_t, ret);
3151            break;
3152        case 1:
3153            /* ADDQH_R_PH */
3154            gen_helper_addqh_r_ph(v1_t, v1_t, v2_t);
3155            gen_store_gpr(v1_t, ret);
3156            break;
3157        }
3158        break;
3159    case NM_ADDQH_R_W:
3160        check_dsp_r2(ctx);
3161        switch (extract32(ctx->opcode, 10, 1)) {
3162        case 0:
3163            /* ADDQH_W */
3164            gen_helper_addqh_w(v1_t, v1_t, v2_t);
3165            gen_store_gpr(v1_t, ret);
3166            break;
3167        case 1:
3168            /* ADDQH_R_W */
3169            gen_helper_addqh_r_w(v1_t, v1_t, v2_t);
3170            gen_store_gpr(v1_t, ret);
3171            break;
3172        }
3173        break;
3174    case NM_ADDU_S_QB:
3175        check_dsp(ctx);
3176        switch (extract32(ctx->opcode, 10, 1)) {
3177        case 0:
3178            /* ADDU_QB */
3179            gen_helper_addu_qb(v1_t, v1_t, v2_t, tcg_env);
3180            gen_store_gpr(v1_t, ret);
3181            break;
3182        case 1:
3183            /* ADDU_S_QB */
3184            gen_helper_addu_s_qb(v1_t, v1_t, v2_t, tcg_env);
3185            gen_store_gpr(v1_t, ret);
3186            break;
3187        }
3188        break;
3189    case NM_ADDU_S_PH:
3190        check_dsp_r2(ctx);
3191        switch (extract32(ctx->opcode, 10, 1)) {
3192        case 0:
3193            /* ADDU_PH */
3194            gen_helper_addu_ph(v1_t, v1_t, v2_t, tcg_env);
3195            gen_store_gpr(v1_t, ret);
3196            break;
3197        case 1:
3198            /* ADDU_S_PH */
3199            gen_helper_addu_s_ph(v1_t, v1_t, v2_t, tcg_env);
3200            gen_store_gpr(v1_t, ret);
3201            break;
3202        }
3203        break;
3204    case NM_ADDUH_R_QB:
3205        check_dsp_r2(ctx);
3206        switch (extract32(ctx->opcode, 10, 1)) {
3207        case 0:
3208            /* ADDUH_QB */
3209            gen_helper_adduh_qb(v1_t, v1_t, v2_t);
3210            gen_store_gpr(v1_t, ret);
3211            break;
3212        case 1:
3213            /* ADDUH_R_QB */
3214            gen_helper_adduh_r_qb(v1_t, v1_t, v2_t);
3215            gen_store_gpr(v1_t, ret);
3216            break;
3217        }
3218        break;
3219    case NM_SHRAV_R_PH:
3220        check_dsp(ctx);
3221        switch (extract32(ctx->opcode, 10, 1)) {
3222        case 0:
3223            /* SHRAV_PH */
3224            gen_helper_shra_ph(v1_t, v1_t, v2_t);
3225            gen_store_gpr(v1_t, ret);
3226            break;
3227        case 1:
3228            /* SHRAV_R_PH */
3229            gen_helper_shra_r_ph(v1_t, v1_t, v2_t);
3230            gen_store_gpr(v1_t, ret);
3231            break;
3232        }
3233        break;
3234    case NM_SHRAV_R_QB:
3235        check_dsp_r2(ctx);
3236        switch (extract32(ctx->opcode, 10, 1)) {
3237        case 0:
3238            /* SHRAV_QB */
3239            gen_helper_shra_qb(v1_t, v1_t, v2_t);
3240            gen_store_gpr(v1_t, ret);
3241            break;
3242        case 1:
3243            /* SHRAV_R_QB */
3244            gen_helper_shra_r_qb(v1_t, v1_t, v2_t);
3245            gen_store_gpr(v1_t, ret);
3246            break;
3247        }
3248        break;
3249    case NM_SUBQ_S_PH:
3250        check_dsp(ctx);
3251        switch (extract32(ctx->opcode, 10, 1)) {
3252        case 0:
3253            /* SUBQ_PH */
3254            gen_helper_subq_ph(v1_t, v1_t, v2_t, tcg_env);
3255            gen_store_gpr(v1_t, ret);
3256            break;
3257        case 1:
3258            /* SUBQ_S_PH */
3259            gen_helper_subq_s_ph(v1_t, v1_t, v2_t, tcg_env);
3260            gen_store_gpr(v1_t, ret);
3261            break;
3262        }
3263        break;
3264    case NM_SUBQH_R_PH:
3265        check_dsp_r2(ctx);
3266        switch (extract32(ctx->opcode, 10, 1)) {
3267        case 0:
3268            /* SUBQH_PH */
3269            gen_helper_subqh_ph(v1_t, v1_t, v2_t);
3270            gen_store_gpr(v1_t, ret);
3271            break;
3272        case 1:
3273            /* SUBQH_R_PH */
3274            gen_helper_subqh_r_ph(v1_t, v1_t, v2_t);
3275            gen_store_gpr(v1_t, ret);
3276            break;
3277        }
3278        break;
3279    case NM_SUBQH_R_W:
3280        check_dsp_r2(ctx);
3281        switch (extract32(ctx->opcode, 10, 1)) {
3282        case 0:
3283            /* SUBQH_W */
3284            gen_helper_subqh_w(v1_t, v1_t, v2_t);
3285            gen_store_gpr(v1_t, ret);
3286            break;
3287        case 1:
3288            /* SUBQH_R_W */
3289            gen_helper_subqh_r_w(v1_t, v1_t, v2_t);
3290            gen_store_gpr(v1_t, ret);
3291            break;
3292        }
3293        break;
3294    case NM_SUBU_S_QB:
3295        check_dsp(ctx);
3296        switch (extract32(ctx->opcode, 10, 1)) {
3297        case 0:
3298            /* SUBU_QB */
3299            gen_helper_subu_qb(v1_t, v1_t, v2_t, tcg_env);
3300            gen_store_gpr(v1_t, ret);
3301            break;
3302        case 1:
3303            /* SUBU_S_QB */
3304            gen_helper_subu_s_qb(v1_t, v1_t, v2_t, tcg_env);
3305            gen_store_gpr(v1_t, ret);
3306            break;
3307        }
3308        break;
3309    case NM_SUBU_S_PH:
3310        check_dsp_r2(ctx);
3311        switch (extract32(ctx->opcode, 10, 1)) {
3312        case 0:
3313            /* SUBU_PH */
3314            gen_helper_subu_ph(v1_t, v1_t, v2_t, tcg_env);
3315            gen_store_gpr(v1_t, ret);
3316            break;
3317        case 1:
3318            /* SUBU_S_PH */
3319            gen_helper_subu_s_ph(v1_t, v1_t, v2_t, tcg_env);
3320            gen_store_gpr(v1_t, ret);
3321            break;
3322        }
3323        break;
3324    case NM_SUBUH_R_QB:
3325        check_dsp_r2(ctx);
3326        switch (extract32(ctx->opcode, 10, 1)) {
3327        case 0:
3328            /* SUBUH_QB */
3329            gen_helper_subuh_qb(v1_t, v1_t, v2_t);
3330            gen_store_gpr(v1_t, ret);
3331            break;
3332        case 1:
3333            /* SUBUH_R_QB */
3334            gen_helper_subuh_r_qb(v1_t, v1_t, v2_t);
3335            gen_store_gpr(v1_t, ret);
3336            break;
3337        }
3338        break;
3339    case NM_SHLLV_S_PH:
3340        check_dsp(ctx);
3341        switch (extract32(ctx->opcode, 10, 1)) {
3342        case 0:
3343            /* SHLLV_PH */
3344            gen_helper_shll_ph(v1_t, v1_t, v2_t, tcg_env);
3345            gen_store_gpr(v1_t, ret);
3346            break;
3347        case 1:
3348            /* SHLLV_S_PH */
3349            gen_helper_shll_s_ph(v1_t, v1_t, v2_t, tcg_env);
3350            gen_store_gpr(v1_t, ret);
3351            break;
3352        }
3353        break;
3354    case NM_PRECR_SRA_R_PH_W:
3355        check_dsp_r2(ctx);
3356        switch (extract32(ctx->opcode, 10, 1)) {
3357        case 0:
3358            /* PRECR_SRA_PH_W */
3359            {
3360                TCGv_i32 sa_t = tcg_constant_i32(rd);
3361                gen_helper_precr_sra_ph_w(v1_t, sa_t, v1_t,
3362                                          cpu_gpr[rt]);
3363                gen_store_gpr(v1_t, rt);
3364            }
3365            break;
3366        case 1:
3367            /* PRECR_SRA_R_PH_W */
3368            {
3369                TCGv_i32 sa_t = tcg_constant_i32(rd);
3370                gen_helper_precr_sra_r_ph_w(v1_t, sa_t, v1_t,
3371                                            cpu_gpr[rt]);
3372                gen_store_gpr(v1_t, rt);
3373            }
3374            break;
3375       }
3376        break;
3377    case NM_MULEU_S_PH_QBL:
3378        check_dsp(ctx);
3379        gen_helper_muleu_s_ph_qbl(v1_t, v1_t, v2_t, tcg_env);
3380        gen_store_gpr(v1_t, ret);
3381        break;
3382    case NM_MULEU_S_PH_QBR:
3383        check_dsp(ctx);
3384        gen_helper_muleu_s_ph_qbr(v1_t, v1_t, v2_t, tcg_env);
3385        gen_store_gpr(v1_t, ret);
3386        break;
3387    case NM_MULQ_RS_PH:
3388        check_dsp(ctx);
3389        gen_helper_mulq_rs_ph(v1_t, v1_t, v2_t, tcg_env);
3390        gen_store_gpr(v1_t, ret);
3391        break;
3392    case NM_MULQ_S_PH:
3393        check_dsp_r2(ctx);
3394        gen_helper_mulq_s_ph(v1_t, v1_t, v2_t, tcg_env);
3395        gen_store_gpr(v1_t, ret);
3396        break;
3397    case NM_MULQ_RS_W:
3398        check_dsp_r2(ctx);
3399        gen_helper_mulq_rs_w(v1_t, v1_t, v2_t, tcg_env);
3400        gen_store_gpr(v1_t, ret);
3401        break;
3402    case NM_MULQ_S_W:
3403        check_dsp_r2(ctx);
3404        gen_helper_mulq_s_w(v1_t, v1_t, v2_t, tcg_env);
3405        gen_store_gpr(v1_t, ret);
3406        break;
3407    case NM_APPEND:
3408        check_dsp_r2(ctx);
3409        gen_load_gpr(t0, rs);
3410        if (rd != 0) {
3411            tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], rd, 32 - rd);
3412        }
3413        tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
3414        break;
3415    case NM_MODSUB:
3416        check_dsp(ctx);
3417        gen_helper_modsub(v1_t, v1_t, v2_t);
3418        gen_store_gpr(v1_t, ret);
3419        break;
3420    case NM_SHRAV_R_W:
3421        check_dsp(ctx);
3422        gen_helper_shra_r_w(v1_t, v1_t, v2_t);
3423        gen_store_gpr(v1_t, ret);
3424        break;
3425    case NM_SHRLV_PH:
3426        check_dsp_r2(ctx);
3427        gen_helper_shrl_ph(v1_t, v1_t, v2_t);
3428        gen_store_gpr(v1_t, ret);
3429        break;
3430    case NM_SHRLV_QB:
3431        check_dsp(ctx);
3432        gen_helper_shrl_qb(v1_t, v1_t, v2_t);
3433        gen_store_gpr(v1_t, ret);
3434        break;
3435    case NM_SHLLV_QB:
3436        check_dsp(ctx);
3437        gen_helper_shll_qb(v1_t, v1_t, v2_t, tcg_env);
3438        gen_store_gpr(v1_t, ret);
3439        break;
3440    case NM_SHLLV_S_W:
3441        check_dsp(ctx);
3442        gen_helper_shll_s_w(v1_t, v1_t, v2_t, tcg_env);
3443        gen_store_gpr(v1_t, ret);
3444        break;
3445    case NM_SHILO:
3446        check_dsp(ctx);
3447        {
3448            TCGv tv0 = tcg_temp_new();
3449            TCGv tv1 = tcg_temp_new();
3450            int16_t imm = extract32(ctx->opcode, 16, 7);
3451
3452            tcg_gen_movi_tl(tv0, rd >> 3);
3453            tcg_gen_movi_tl(tv1, imm);
3454            gen_helper_shilo(tv0, tv1, tcg_env);
3455        }
3456        break;
3457    case NM_MULEQ_S_W_PHL:
3458        check_dsp(ctx);
3459        gen_helper_muleq_s_w_phl(v1_t, v1_t, v2_t, tcg_env);
3460        gen_store_gpr(v1_t, ret);
3461        break;
3462    case NM_MULEQ_S_W_PHR:
3463        check_dsp(ctx);
3464        gen_helper_muleq_s_w_phr(v1_t, v1_t, v2_t, tcg_env);
3465        gen_store_gpr(v1_t, ret);
3466        break;
3467    case NM_MUL_S_PH:
3468        check_dsp_r2(ctx);
3469        switch (extract32(ctx->opcode, 10, 1)) {
3470        case 0:
3471            /* MUL_PH */
3472            gen_helper_mul_ph(v1_t, v1_t, v2_t, tcg_env);
3473            gen_store_gpr(v1_t, ret);
3474            break;
3475        case 1:
3476            /* MUL_S_PH */
3477            gen_helper_mul_s_ph(v1_t, v1_t, v2_t, tcg_env);
3478            gen_store_gpr(v1_t, ret);
3479            break;
3480        }
3481        break;
3482    case NM_PRECR_QB_PH:
3483        check_dsp_r2(ctx);
3484        gen_helper_precr_qb_ph(v1_t, v1_t, v2_t);
3485        gen_store_gpr(v1_t, ret);
3486        break;
3487    case NM_PRECRQ_QB_PH:
3488        check_dsp(ctx);
3489        gen_helper_precrq_qb_ph(v1_t, v1_t, v2_t);
3490        gen_store_gpr(v1_t, ret);
3491        break;
3492    case NM_PRECRQ_PH_W:
3493        check_dsp(ctx);
3494        gen_helper_precrq_ph_w(v1_t, v1_t, v2_t);
3495        gen_store_gpr(v1_t, ret);
3496        break;
3497    case NM_PRECRQ_RS_PH_W:
3498        check_dsp(ctx);
3499        gen_helper_precrq_rs_ph_w(v1_t, v1_t, v2_t, tcg_env);
3500        gen_store_gpr(v1_t, ret);
3501        break;
3502    case NM_PRECRQU_S_QB_PH:
3503        check_dsp(ctx);
3504        gen_helper_precrqu_s_qb_ph(v1_t, v1_t, v2_t, tcg_env);
3505        gen_store_gpr(v1_t, ret);
3506        break;
3507    case NM_SHRA_R_W:
3508        check_dsp(ctx);
3509        tcg_gen_movi_tl(t0, rd);
3510        gen_helper_shra_r_w(v1_t, t0, v1_t);
3511        gen_store_gpr(v1_t, rt);
3512        break;
3513    case NM_SHRA_R_PH:
3514        check_dsp(ctx);
3515        tcg_gen_movi_tl(t0, rd >> 1);
3516        switch (extract32(ctx->opcode, 10, 1)) {
3517        case 0:
3518            /* SHRA_PH */
3519            gen_helper_shra_ph(v1_t, t0, v1_t);
3520            gen_store_gpr(v1_t, rt);
3521            break;
3522        case 1:
3523            /* SHRA_R_PH */
3524            gen_helper_shra_r_ph(v1_t, t0, v1_t);
3525            gen_store_gpr(v1_t, rt);
3526            break;
3527        }
3528        break;
3529    case NM_SHLL_S_PH:
3530        check_dsp(ctx);
3531        tcg_gen_movi_tl(t0, rd >> 1);
3532        switch (extract32(ctx->opcode, 10, 2)) {
3533        case 0:
3534            /* SHLL_PH */
3535            gen_helper_shll_ph(v1_t, t0, v1_t, tcg_env);
3536            gen_store_gpr(v1_t, rt);
3537            break;
3538        case 2:
3539            /* SHLL_S_PH */
3540            gen_helper_shll_s_ph(v1_t, t0, v1_t, tcg_env);
3541            gen_store_gpr(v1_t, rt);
3542            break;
3543        default:
3544            gen_reserved_instruction(ctx);
3545            break;
3546        }
3547        break;
3548    case NM_SHLL_S_W:
3549        check_dsp(ctx);
3550        tcg_gen_movi_tl(t0, rd);
3551        gen_helper_shll_s_w(v1_t, t0, v1_t, tcg_env);
3552        gen_store_gpr(v1_t, rt);
3553        break;
3554    case NM_REPL_PH:
3555        check_dsp(ctx);
3556        {
3557            int16_t imm;
3558            imm = sextract32(ctx->opcode, 11, 11);
3559            imm = (int16_t)(imm << 6) >> 6;
3560            if (rt != 0) {
3561                tcg_gen_movi_tl(cpu_gpr[rt], dup_const(MO_16, imm));
3562            }
3563        }
3564        break;
3565    default:
3566        gen_reserved_instruction(ctx);
3567        break;
3568    }
3569}
3570
3571static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
3572{
3573    uint16_t insn;
3574    uint32_t op;
3575    int rt, rs, rd;
3576    int offset;
3577    int imm;
3578
3579    insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
3580    ctx->opcode = (ctx->opcode << 16) | insn;
3581
3582    rt = extract32(ctx->opcode, 21, 5);
3583    rs = extract32(ctx->opcode, 16, 5);
3584    rd = extract32(ctx->opcode, 11, 5);
3585
3586    op = extract32(ctx->opcode, 26, 6);
3587    switch (op) {
3588    case NM_P_ADDIU:
3589        if (rt == 0) {
3590            /* P.RI */
3591            switch (extract32(ctx->opcode, 19, 2)) {
3592            case NM_SIGRIE:
3593            default:
3594                gen_reserved_instruction(ctx);
3595                break;
3596            case NM_P_SYSCALL:
3597                if ((extract32(ctx->opcode, 18, 1)) == NM_SYSCALL) {
3598                    generate_exception_end(ctx, EXCP_SYSCALL);
3599                } else {
3600                    gen_reserved_instruction(ctx);
3601                }
3602                break;
3603            case NM_BREAK:
3604                generate_exception_end(ctx, EXCP_BREAK);
3605                break;
3606            case NM_SDBBP:
3607                if (is_uhi(ctx, extract32(ctx->opcode, 0, 19))) {
3608                    ctx->base.is_jmp = DISAS_SEMIHOST;
3609                } else {
3610                    if (ctx->hflags & MIPS_HFLAG_SBRI) {
3611                        gen_reserved_instruction(ctx);
3612                    } else {
3613                        generate_exception_end(ctx, EXCP_DBp);
3614                    }
3615                }
3616                break;
3617            }
3618        } else {
3619            /* NM_ADDIU */
3620            imm = extract32(ctx->opcode, 0, 16);
3621            if (rs != 0) {
3622                tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm);
3623            } else {
3624                tcg_gen_movi_tl(cpu_gpr[rt], imm);
3625            }
3626            tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
3627        }
3628        break;
3629    case NM_ADDIUPC:
3630        if (rt != 0) {
3631            offset = sextract32(ctx->opcode, 0, 1) << 21 |
3632                     extract32(ctx->opcode, 1, 20) << 1;
3633            target_long addr = addr_add(ctx, ctx->base.pc_next + 4, offset);
3634            tcg_gen_movi_tl(cpu_gpr[rt], addr);
3635        }
3636        break;
3637    case NM_POOL32A:
3638        switch (ctx->opcode & 0x07) {
3639        case NM_POOL32A0:
3640            gen_pool32a0_nanomips_insn(env, ctx);
3641            break;
3642        case NM_POOL32A5:
3643            {
3644                int32_t op1 = extract32(ctx->opcode, 3, 7);
3645                gen_pool32a5_nanomips_insn(ctx, op1, rd, rs, rt);
3646            }
3647            break;
3648        case NM_POOL32A7:
3649            switch (extract32(ctx->opcode, 3, 3)) {
3650            case NM_P_LSX:
3651                gen_p_lsx(ctx, rd, rs, rt);
3652                break;
3653            case NM_LSA:
3654                /*
3655                 * In nanoMIPS, the shift field directly encodes the shift
3656                 * amount, meaning that the supported shift values are in
3657                 * the range 0 to 3 (instead of 1 to 4 in MIPSR6).
3658                 */
3659                gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) - 1);
3660                break;
3661            case NM_EXTW:
3662                gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
3663                break;
3664            case NM_POOL32AXF:
3665                gen_pool32axf_nanomips_insn(env, ctx);
3666                break;
3667            default:
3668                gen_reserved_instruction(ctx);
3669                break;
3670            }
3671            break;
3672        default:
3673            gen_reserved_instruction(ctx);
3674            break;
3675        }
3676        break;
3677    case NM_P_GP_W:
3678        switch (ctx->opcode & 0x03) {
3679        case NM_ADDIUGP_W:
3680            if (rt != 0) {
3681                offset = extract32(ctx->opcode, 0, 21);
3682                gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], offset);
3683            }
3684            break;
3685        case NM_LWGP:
3686            gen_ld(ctx, OPC_LW, rt, 28, extract32(ctx->opcode, 2, 19) << 2);
3687            break;
3688        case NM_SWGP:
3689            gen_st(ctx, OPC_SW, rt, 28, extract32(ctx->opcode, 2, 19) << 2);
3690            break;
3691        default:
3692            gen_reserved_instruction(ctx);
3693            break;
3694        }
3695        break;
3696    case NM_P48I:
3697        {
3698            insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4);
3699            target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;
3700            switch (extract32(ctx->opcode, 16, 5)) {
3701            case NM_LI48:
3702                check_nms(ctx);
3703                if (rt != 0) {
3704                    tcg_gen_movi_tl(cpu_gpr[rt], addr_off);
3705                }
3706                break;
3707            case NM_ADDIU48:
3708                check_nms(ctx);
3709                if (rt != 0) {
3710                    tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rt], addr_off);
3711                    tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
3712                }
3713                break;
3714            case NM_ADDIUGP48:
3715                check_nms(ctx);
3716                if (rt != 0) {
3717                    gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], addr_off);
3718                }
3719                break;
3720            case NM_ADDIUPC48:
3721                check_nms(ctx);
3722                if (rt != 0) {
3723                    target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
3724                                                addr_off);
3725
3726                    tcg_gen_movi_tl(cpu_gpr[rt], addr);
3727                }
3728                break;
3729            case NM_LWPC48:
3730                check_nms(ctx);
3731                if (rt != 0) {
3732                    TCGv t0;
3733                    t0 = tcg_temp_new();
3734
3735                    target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
3736                                                addr_off);
3737
3738                    tcg_gen_movi_tl(t0, addr);
3739                    tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx,
3740                                       MO_TESL | ctx->default_tcg_memop_mask);
3741                }
3742                break;
3743            case NM_SWPC48:
3744                check_nms(ctx);
3745                {
3746                    TCGv t0, t1;
3747                    t0 = tcg_temp_new();
3748                    t1 = tcg_temp_new();
3749
3750                    target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
3751                                                addr_off);
3752
3753                    tcg_gen_movi_tl(t0, addr);
3754                    gen_load_gpr(t1, rt);
3755
3756                    tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
3757                                       MO_TEUL | ctx->default_tcg_memop_mask);
3758                }
3759                break;
3760            default:
3761                gen_reserved_instruction(ctx);
3762                break;
3763            }
3764            return 6;
3765        }
3766    case NM_P_U12:
3767        switch (extract32(ctx->opcode, 12, 4)) {
3768        case NM_ORI:
3769            gen_logic_imm(ctx, OPC_ORI, rt, rs, extract32(ctx->opcode, 0, 12));
3770            break;
3771        case NM_XORI:
3772            gen_logic_imm(ctx, OPC_XORI, rt, rs, extract32(ctx->opcode, 0, 12));
3773            break;
3774        case NM_ANDI:
3775            gen_logic_imm(ctx, OPC_ANDI, rt, rs, extract32(ctx->opcode, 0, 12));
3776            break;
3777        case NM_P_SR:
3778            switch (extract32(ctx->opcode, 20, 1)) {
3779            case NM_PP_SR:
3780                switch (ctx->opcode & 3) {
3781                case NM_SAVE:
3782                    gen_save(ctx, rt, extract32(ctx->opcode, 16, 4),
3783                             extract32(ctx->opcode, 2, 1),
3784                             extract32(ctx->opcode, 3, 9) << 3);
3785                    break;
3786                case NM_RESTORE:
3787                case NM_RESTORE_JRC:
3788                    gen_restore(ctx, rt, extract32(ctx->opcode, 16, 4),
3789                                extract32(ctx->opcode, 2, 1),
3790                                extract32(ctx->opcode, 3, 9) << 3);
3791                    if ((ctx->opcode & 3) == NM_RESTORE_JRC) {
3792                        gen_compute_branch_nm(ctx, OPC_JR, 2, 31, 0, 0);
3793                    }
3794                    break;
3795                default:
3796                    gen_reserved_instruction(ctx);
3797                    break;
3798                }
3799                break;
3800            case NM_P_SR_F:
3801                gen_reserved_instruction(ctx);
3802                break;
3803            }
3804            break;
3805        case NM_SLTI:
3806            gen_slt_imm(ctx, OPC_SLTI, rt, rs, extract32(ctx->opcode, 0, 12));
3807            break;
3808        case NM_SLTIU:
3809            gen_slt_imm(ctx, OPC_SLTIU, rt, rs, extract32(ctx->opcode, 0, 12));
3810            break;
3811        case NM_SEQI:
3812            {
3813                TCGv t0 = tcg_temp_new();
3814
3815                imm = extract32(ctx->opcode, 0, 12);
3816                gen_load_gpr(t0, rs);
3817                tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, imm);
3818                gen_store_gpr(t0, rt);
3819            }
3820            break;
3821        case NM_ADDIUNEG:
3822            imm = (int16_t) extract32(ctx->opcode, 0, 12);
3823            gen_arith_imm(ctx, OPC_ADDIU, rt, rs, -imm);
3824            break;
3825        case NM_P_SHIFT:
3826            {
3827                int shift = extract32(ctx->opcode, 0, 5);
3828                switch (extract32(ctx->opcode, 5, 4)) {
3829                case NM_P_SLL:
3830                    if (rt == 0 && shift == 0) {
3831                        /* NOP */
3832                    } else if (rt == 0 && shift == 3) {
3833                        /* EHB - treat as NOP */
3834                    } else if (rt == 0 && shift == 5) {
3835                        /* PAUSE - treat as NOP */
3836                    } else if (rt == 0 && shift == 6) {
3837                        /* SYNC */
3838                        gen_sync(extract32(ctx->opcode, 16, 5));
3839                    } else {
3840                        /* SLL */
3841                        gen_shift_imm(ctx, OPC_SLL, rt, rs,
3842                                      extract32(ctx->opcode, 0, 5));
3843                    }
3844                    break;
3845                case NM_SRL:
3846                    gen_shift_imm(ctx, OPC_SRL, rt, rs,
3847                                  extract32(ctx->opcode, 0, 5));
3848                    break;
3849                case NM_SRA:
3850                    gen_shift_imm(ctx, OPC_SRA, rt, rs,
3851                                  extract32(ctx->opcode, 0, 5));
3852                    break;
3853                case NM_ROTR:
3854                    gen_shift_imm(ctx, OPC_ROTR, rt, rs,
3855                                  extract32(ctx->opcode, 0, 5));
3856                    break;
3857                default:
3858                    gen_reserved_instruction(ctx);
3859                    break;
3860                }
3861            }
3862            break;
3863        case NM_P_ROTX:
3864            check_nms(ctx);
3865            if (rt != 0) {
3866                TCGv t0 = tcg_temp_new();
3867                TCGv_i32 shift =
3868                    tcg_constant_i32(extract32(ctx->opcode, 0, 5));
3869                TCGv_i32 shiftx =
3870                    tcg_constant_i32(extract32(ctx->opcode, 7, 4) << 1);
3871                TCGv_i32 stripe =
3872                    tcg_constant_i32(extract32(ctx->opcode, 6, 1));
3873
3874                gen_load_gpr(t0, rs);
3875                gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe);
3876            }
3877            break;
3878        case NM_P_INS:
3879            switch (((ctx->opcode >> 10) & 2) |
3880                    (extract32(ctx->opcode, 5, 1))) {
3881            case NM_INS:
3882                check_nms(ctx);
3883                gen_bitops(ctx, OPC_INS, rt, rs, extract32(ctx->opcode, 0, 5),
3884                           extract32(ctx->opcode, 6, 5));
3885                break;
3886            default:
3887                gen_reserved_instruction(ctx);
3888                break;
3889            }
3890            break;
3891        case NM_P_EXT:
3892            switch (((ctx->opcode >> 10) & 2) |
3893                    (extract32(ctx->opcode, 5, 1))) {
3894            case NM_EXT:
3895                check_nms(ctx);
3896                gen_bitops(ctx, OPC_EXT, rt, rs, extract32(ctx->opcode, 0, 5),
3897                           extract32(ctx->opcode, 6, 5));
3898                break;
3899            default:
3900                gen_reserved_instruction(ctx);
3901                break;
3902            }
3903            break;
3904        default:
3905            gen_reserved_instruction(ctx);
3906            break;
3907        }
3908        break;
3909    case NM_POOL32F:
3910        gen_pool32f_nanomips_insn(ctx);
3911        break;
3912    case NM_POOL32S:
3913        break;
3914    case NM_P_LUI:
3915        switch (extract32(ctx->opcode, 1, 1)) {
3916        case NM_LUI:
3917            if (rt != 0) {
3918                tcg_gen_movi_tl(cpu_gpr[rt],
3919                                sextract32(ctx->opcode, 0, 1) << 31 |
3920                                extract32(ctx->opcode, 2, 10) << 21 |
3921                                extract32(ctx->opcode, 12, 9) << 12);
3922            }
3923            break;
3924        case NM_ALUIPC:
3925            if (rt != 0) {
3926                offset = sextract32(ctx->opcode, 0, 1) << 31 |
3927                         extract32(ctx->opcode, 2, 10) << 21 |
3928                         extract32(ctx->opcode, 12, 9) << 12;
3929                target_long addr;
3930                addr = ~0xFFF & addr_add(ctx, ctx->base.pc_next + 4, offset);
3931                tcg_gen_movi_tl(cpu_gpr[rt], addr);
3932            }
3933            break;
3934        }
3935        break;
3936    case NM_P_GP_BH:
3937        {
3938            uint32_t u = extract32(ctx->opcode, 0, 18);
3939
3940            switch (extract32(ctx->opcode, 18, 3)) {
3941            case NM_LBGP:
3942                gen_ld(ctx, OPC_LB, rt, 28, u);
3943                break;
3944            case NM_SBGP:
3945                gen_st(ctx, OPC_SB, rt, 28, u);
3946                break;
3947            case NM_LBUGP:
3948                gen_ld(ctx, OPC_LBU, rt, 28, u);
3949                break;
3950            case NM_ADDIUGP_B:
3951                if (rt != 0) {
3952                    gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], u);
3953                }
3954                break;
3955            case NM_P_GP_LH:
3956                u &= ~1;
3957                switch (ctx->opcode & 1) {
3958                case NM_LHGP:
3959                    gen_ld(ctx, OPC_LH, rt, 28, u);
3960                    break;
3961                case NM_LHUGP:
3962                    gen_ld(ctx, OPC_LHU, rt, 28, u);
3963                    break;
3964                }
3965                break;
3966            case NM_P_GP_SH:
3967                u &= ~1;
3968                switch (ctx->opcode & 1) {
3969                case NM_SHGP:
3970                    gen_st(ctx, OPC_SH, rt, 28, u);
3971                    break;
3972                default:
3973                    gen_reserved_instruction(ctx);
3974                    break;
3975                }
3976                break;
3977            case NM_P_GP_CP1:
3978                u &= ~0x3;
3979                switch (ctx->opcode & 0x3) {
3980                case NM_LWC1GP:
3981                    gen_cop1_ldst(ctx, OPC_LWC1, rt, 28, u);
3982                    break;
3983                case NM_LDC1GP:
3984                    gen_cop1_ldst(ctx, OPC_LDC1, rt, 28, u);
3985                    break;
3986                case NM_SWC1GP:
3987                    gen_cop1_ldst(ctx, OPC_SWC1, rt, 28, u);
3988                    break;
3989                case NM_SDC1GP:
3990                    gen_cop1_ldst(ctx, OPC_SDC1, rt, 28, u);
3991                    break;
3992                }
3993                break;
3994            default:
3995                gen_reserved_instruction(ctx);
3996                break;
3997            }
3998        }
3999        break;
4000    case NM_P_LS_U12:
4001        {
4002            uint32_t u = extract32(ctx->opcode, 0, 12);
4003
4004            switch (extract32(ctx->opcode, 12, 4)) {
4005            case NM_P_PREFU12:
4006                if (rt == 31) {
4007                    /* SYNCI */
4008                    /*
4009                     * Break the TB to be able to sync copied instructions
4010                     * immediately.
4011                     */
4012                    ctx->base.is_jmp = DISAS_STOP;
4013                } else {
4014                    /* PREF */
4015                    /* Treat as NOP. */
4016                }
4017                break;
4018            case NM_LB:
4019                gen_ld(ctx, OPC_LB, rt, rs, u);
4020                break;
4021            case NM_LH:
4022                gen_ld(ctx, OPC_LH, rt, rs, u);
4023                break;
4024            case NM_LW:
4025                gen_ld(ctx, OPC_LW, rt, rs, u);
4026                break;
4027            case NM_LBU:
4028                gen_ld(ctx, OPC_LBU, rt, rs, u);
4029                break;
4030            case NM_LHU:
4031                gen_ld(ctx, OPC_LHU, rt, rs, u);
4032                break;
4033            case NM_SB:
4034                gen_st(ctx, OPC_SB, rt, rs, u);
4035                break;
4036            case NM_SH:
4037                gen_st(ctx, OPC_SH, rt, rs, u);
4038                break;
4039            case NM_SW:
4040                gen_st(ctx, OPC_SW, rt, rs, u);
4041                break;
4042            case NM_LWC1:
4043                gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, u);
4044                break;
4045            case NM_LDC1:
4046                gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, u);
4047                break;
4048            case NM_SWC1:
4049                gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, u);
4050                break;
4051            case NM_SDC1:
4052                gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u);
4053                break;
4054            default:
4055                gen_reserved_instruction(ctx);
4056                break;
4057            }
4058        }
4059        break;
4060    case NM_P_LS_S9:
4061        {
4062            int32_t s = (sextract32(ctx->opcode, 15, 1) << 8) |
4063                        extract32(ctx->opcode, 0, 8);
4064
4065            switch (extract32(ctx->opcode, 8, 3)) {
4066            case NM_P_LS_S0:
4067                switch (extract32(ctx->opcode, 11, 4)) {
4068                case NM_LBS9:
4069                    gen_ld(ctx, OPC_LB, rt, rs, s);
4070                    break;
4071                case NM_LHS9:
4072                    gen_ld(ctx, OPC_LH, rt, rs, s);
4073                    break;
4074                case NM_LWS9:
4075                    gen_ld(ctx, OPC_LW, rt, rs, s);
4076                    break;
4077                case NM_LBUS9:
4078                    gen_ld(ctx, OPC_LBU, rt, rs, s);
4079                    break;
4080                case NM_LHUS9:
4081                    gen_ld(ctx, OPC_LHU, rt, rs, s);
4082                    break;
4083                case NM_SBS9:
4084                    gen_st(ctx, OPC_SB, rt, rs, s);
4085                    break;
4086                case NM_SHS9:
4087                    gen_st(ctx, OPC_SH, rt, rs, s);
4088                    break;
4089                case NM_SWS9:
4090                    gen_st(ctx, OPC_SW, rt, rs, s);
4091                    break;
4092                case NM_LWC1S9:
4093                    gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, s);
4094                    break;
4095                case NM_LDC1S9:
4096                    gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, s);
4097                    break;
4098                case NM_SWC1S9:
4099                    gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, s);
4100                    break;
4101                case NM_SDC1S9:
4102                    gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, s);
4103                    break;
4104                case NM_P_PREFS9:
4105                    if (rt == 31) {
4106                        /* SYNCI */
4107                        /*
4108                         * Break the TB to be able to sync copied instructions
4109                         * immediately.
4110                         */
4111                        ctx->base.is_jmp = DISAS_STOP;
4112                    } else {
4113                        /* PREF */
4114                        /* Treat as NOP. */
4115                    }
4116                    break;
4117                default:
4118                    gen_reserved_instruction(ctx);
4119                    break;
4120                }
4121                break;
4122            case NM_P_LS_S1:
4123                switch (extract32(ctx->opcode, 11, 4)) {
4124                case NM_UALH:
4125                case NM_UASH:
4126                    check_nms(ctx);
4127                    {
4128                        TCGv t0 = tcg_temp_new();
4129                        TCGv t1 = tcg_temp_new();
4130
4131                        gen_base_offset_addr(ctx, t0, rs, s);
4132
4133                        switch (extract32(ctx->opcode, 11, 4)) {
4134                        case NM_UALH:
4135                            tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
4136                                               MO_UNALN);
4137                            gen_store_gpr(t0, rt);
4138                            break;
4139                        case NM_UASH:
4140                            gen_load_gpr(t1, rt);
4141                            tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
4142                                               MO_UNALN);
4143                            break;
4144                        }
4145                    }
4146                    break;
4147                case NM_P_LL:
4148                    switch (ctx->opcode & 0x03) {
4149                    case NM_LL:
4150                        gen_ld(ctx, OPC_LL, rt, rs, s);
4151                        break;
4152                    case NM_LLWP:
4153                        check_xnp(ctx);
4154                        gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
4155                        break;
4156                    default:
4157                        gen_reserved_instruction(ctx);
4158                        break;
4159                    }
4160                    break;
4161                case NM_P_SC:
4162                    switch (ctx->opcode & 0x03) {
4163                    case NM_SC:
4164                        gen_st_cond(ctx, rt, rs, s, MO_TESL, false);
4165                        break;
4166                    case NM_SCWP:
4167                        check_xnp(ctx);
4168                        gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
4169                                 false);
4170                        break;
4171                    default:
4172                        gen_reserved_instruction(ctx);
4173                        break;
4174                    }
4175                    break;
4176                case NM_CACHE:
4177                    check_cp0_enabled(ctx);
4178                    if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
4179                        gen_cache_operation(ctx, rt, rs, s);
4180                    }
4181                    break;
4182                default:
4183                    gen_reserved_instruction(ctx);
4184                    break;
4185                }
4186                break;
4187            case NM_P_LS_E0:
4188                switch (extract32(ctx->opcode, 11, 4)) {
4189                case NM_LBE:
4190                    check_eva(ctx);
4191                    check_cp0_enabled(ctx);
4192                    gen_ld(ctx, OPC_LBE, rt, rs, s);
4193                    break;
4194                case NM_SBE:
4195                    check_eva(ctx);
4196                    check_cp0_enabled(ctx);
4197                    gen_st(ctx, OPC_SBE, rt, rs, s);
4198                    break;
4199                case NM_LBUE:
4200                    check_eva(ctx);
4201                    check_cp0_enabled(ctx);
4202                    gen_ld(ctx, OPC_LBUE, rt, rs, s);
4203                    break;
4204                case NM_P_PREFE:
4205                    if (rt == 31) {
4206                        /* case NM_SYNCIE */
4207                        check_eva(ctx);
4208                        check_cp0_enabled(ctx);
4209                        /*
4210                         * Break the TB to be able to sync copied instructions
4211                         * immediately.
4212                         */
4213                        ctx->base.is_jmp = DISAS_STOP;
4214                    } else {
4215                        /* case NM_PREFE */
4216                        check_eva(ctx);
4217                        check_cp0_enabled(ctx);
4218                        /* Treat as NOP. */
4219                    }
4220                    break;
4221                case NM_LHE:
4222                    check_eva(ctx);
4223                    check_cp0_enabled(ctx);
4224                    gen_ld(ctx, OPC_LHE, rt, rs, s);
4225                    break;
4226                case NM_SHE:
4227                    check_eva(ctx);
4228                    check_cp0_enabled(ctx);
4229                    gen_st(ctx, OPC_SHE, rt, rs, s);
4230                    break;
4231                case NM_LHUE:
4232                    check_eva(ctx);
4233                    check_cp0_enabled(ctx);
4234                    gen_ld(ctx, OPC_LHUE, rt, rs, s);
4235                    break;
4236                case NM_CACHEE:
4237                    check_eva(ctx);
4238                    check_cp0_enabled(ctx);
4239                    check_nms_dl_il_sl_tl_l2c(ctx);
4240                    gen_cache_operation(ctx, rt, rs, s);
4241                    break;
4242                case NM_LWE:
4243                    check_eva(ctx);
4244                    check_cp0_enabled(ctx);
4245                    gen_ld(ctx, OPC_LWE, rt, rs, s);
4246                    break;
4247                case NM_SWE:
4248                    check_eva(ctx);
4249                    check_cp0_enabled(ctx);
4250                    gen_st(ctx, OPC_SWE, rt, rs, s);
4251                    break;
4252                case NM_P_LLE:
4253                    switch (extract32(ctx->opcode, 2, 2)) {
4254                    case NM_LLE:
4255                        check_xnp(ctx);
4256                        check_eva(ctx);
4257                        check_cp0_enabled(ctx);
4258                        gen_ld(ctx, OPC_LLE, rt, rs, s);
4259                        break;
4260                    case NM_LLWPE:
4261                        check_xnp(ctx);
4262                        check_eva(ctx);
4263                        check_cp0_enabled(ctx);
4264                        gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
4265                        break;
4266                    default:
4267                        gen_reserved_instruction(ctx);
4268                        break;
4269                    }
4270                    break;
4271                case NM_P_SCE:
4272                    switch (extract32(ctx->opcode, 2, 2)) {
4273                    case NM_SCE:
4274                        check_xnp(ctx);
4275                        check_eva(ctx);
4276                        check_cp0_enabled(ctx);
4277                        gen_st_cond(ctx, rt, rs, s, MO_TESL, true);
4278                        break;
4279                    case NM_SCWPE:
4280                        check_xnp(ctx);
4281                        check_eva(ctx);
4282                        check_cp0_enabled(ctx);
4283                        gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
4284                                 true);
4285                        break;
4286                    default:
4287                        gen_reserved_instruction(ctx);
4288                        break;
4289                    }
4290                    break;
4291                default:
4292                    gen_reserved_instruction(ctx);
4293                    break;
4294                }
4295                break;
4296            case NM_P_LS_WM:
4297            case NM_P_LS_UAWM:
4298                check_nms(ctx);
4299                {
4300                    int count = extract32(ctx->opcode, 12, 3);
4301                    int counter = 0;
4302
4303                    offset = sextract32(ctx->opcode, 15, 1) << 8 |
4304                             extract32(ctx->opcode, 0, 8);
4305                    TCGv va = tcg_temp_new();
4306                    TCGv t1 = tcg_temp_new();
4307                    MemOp memop = (extract32(ctx->opcode, 8, 3)) ==
4308                                      NM_P_LS_UAWM ? MO_UNALN : MO_ALIGN;
4309
4310                    count = (count == 0) ? 8 : count;
4311                    while (counter != count) {
4312                        int this_rt = ((rt + counter) & 0x1f) | (rt & 0x10);
4313                        int this_offset = offset + (counter << 2);
4314
4315                        gen_base_offset_addr(ctx, va, rs, this_offset);
4316
4317                        switch (extract32(ctx->opcode, 11, 1)) {
4318                        case NM_LWM:
4319                            tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx,
4320                                               memop | MO_TESL);
4321                            gen_store_gpr(t1, this_rt);
4322                            if ((this_rt == rs) &&
4323                                (counter != (count - 1))) {
4324                                /* UNPREDICTABLE */
4325                            }
4326                            break;
4327                        case NM_SWM:
4328                            this_rt = (rt == 0) ? 0 : this_rt;
4329                            gen_load_gpr(t1, this_rt);
4330                            tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx,
4331                                               memop | MO_TEUL);
4332                            break;
4333                        }
4334                        counter++;
4335                    }
4336                }
4337                break;
4338            default:
4339                gen_reserved_instruction(ctx);
4340                break;
4341            }
4342        }
4343        break;
4344    case NM_MOVE_BALC:
4345        check_nms(ctx);
4346        {
4347            TCGv t0 = tcg_temp_new();
4348            int32_t s = sextract32(ctx->opcode, 0, 1) << 21 |
4349                        extract32(ctx->opcode, 1, 20) << 1;
4350            rd = (extract32(ctx->opcode, 24, 1)) == 0 ? 4 : 5;
4351            rt = decode_gpr_gpr4_zero(extract32(ctx->opcode, 25, 1) << 3 |
4352                            extract32(ctx->opcode, 21, 3));
4353            gen_load_gpr(t0, rt);
4354            tcg_gen_mov_tl(cpu_gpr[rd], t0);
4355            gen_compute_branch_nm(ctx, OPC_BGEZAL, 4, 0, 0, s);
4356        }
4357        break;
4358    case NM_P_BAL:
4359        {
4360            int32_t s = sextract32(ctx->opcode, 0, 1) << 25 |
4361                        extract32(ctx->opcode, 1, 24) << 1;
4362
4363            if ((extract32(ctx->opcode, 25, 1)) == 0) {
4364                /* BC */
4365                gen_compute_branch_nm(ctx, OPC_BEQ, 4, 0, 0, s);
4366            } else {
4367                /* BALC */
4368                gen_compute_branch_nm(ctx, OPC_BGEZAL, 4, 0, 0, s);
4369            }
4370        }
4371        break;
4372    case NM_P_J:
4373        switch (extract32(ctx->opcode, 12, 4)) {
4374        case NM_JALRC:
4375        case NM_JALRC_HB:
4376            gen_compute_branch_nm(ctx, OPC_JALR, 4, rs, rt, 0);
4377            break;
4378        case NM_P_BALRSC:
4379            gen_compute_nanomips_pbalrsc_branch(ctx, rs, rt);
4380            break;
4381        default:
4382            gen_reserved_instruction(ctx);
4383            break;
4384        }
4385        break;
4386    case NM_P_BR1:
4387        {
4388            int32_t s = sextract32(ctx->opcode, 0, 1) << 14 |
4389                        extract32(ctx->opcode, 1, 13) << 1;
4390            switch (extract32(ctx->opcode, 14, 2)) {
4391            case NM_BEQC:
4392                check_nms(ctx);
4393                gen_compute_branch_nm(ctx, OPC_BEQ, 4, rs, rt, s);
4394                break;
4395            case NM_P_BR3A:
4396                s = sextract32(ctx->opcode, 0, 1) << 14 |
4397                    extract32(ctx->opcode, 1, 13) << 1;
4398                switch (extract32(ctx->opcode, 16, 5)) {
4399                case NM_BC1EQZC:
4400                    check_cp1_enabled(ctx);
4401                    gen_compute_branch_cp1_nm(ctx, OPC_BC1EQZ, rt, s);
4402                    break;
4403                case NM_BC1NEZC:
4404                    check_cp1_enabled(ctx);
4405                    gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);
4406                    break;
4407                case NM_BPOSGE32C:
4408                    check_dsp_r3(ctx);
4409                    {
4410                        imm = extract32(ctx->opcode, 1, 13)
4411                            | extract32(ctx->opcode, 0, 1) << 13;
4412
4413                        gen_compute_branch_nm(ctx, OPC_BPOSGE32, 4, -1, -2,
4414                                              imm << 1);
4415                    }
4416                    break;
4417                default:
4418                    gen_reserved_instruction(ctx);
4419                    break;
4420                }
4421                break;
4422            case NM_BGEC:
4423                if (rs == rt) {
4424                    gen_compute_compact_branch_nm(ctx, OPC_BC, rs, rt, s);
4425                } else {
4426                    gen_compute_compact_branch_nm(ctx, OPC_BGEC, rs, rt, s);
4427                }
4428                break;
4429            case NM_BGEUC:
4430                if (rs == rt || rt == 0) {
4431                    gen_compute_compact_branch_nm(ctx, OPC_BC, 0, 0, s);
4432                } else if (rs == 0) {
4433                    gen_compute_compact_branch_nm(ctx, OPC_BEQZC, rt, 0, s);
4434                } else {
4435                    gen_compute_compact_branch_nm(ctx, OPC_BGEUC, rs, rt, s);
4436                }
4437                break;
4438            }
4439        }
4440        break;
4441    case NM_P_BR2:
4442        {
4443            int32_t s = sextract32(ctx->opcode, 0, 1) << 14 |
4444                        extract32(ctx->opcode, 1, 13) << 1;
4445            switch (extract32(ctx->opcode, 14, 2)) {
4446            case NM_BNEC:
4447                check_nms(ctx);
4448                if (rs == rt) {
4449                    /* NOP */
4450                    ctx->hflags |= MIPS_HFLAG_FBNSLOT;
4451                } else {
4452                    gen_compute_branch_nm(ctx, OPC_BNE, 4, rs, rt, s);
4453                }
4454                break;
4455            case NM_BLTC:
4456                if (rs != 0 && rt != 0 && rs == rt) {
4457                    /* NOP */
4458                    ctx->hflags |= MIPS_HFLAG_FBNSLOT;
4459                } else {
4460                    gen_compute_compact_branch_nm(ctx, OPC_BLTC, rs, rt, s);
4461                }
4462                break;
4463            case NM_BLTUC:
4464                if (rs == 0 || rs == rt) {
4465                    /* NOP */
4466                    ctx->hflags |= MIPS_HFLAG_FBNSLOT;
4467                } else {
4468                    gen_compute_compact_branch_nm(ctx, OPC_BLTUC, rs, rt, s);
4469                }
4470                break;
4471            default:
4472                gen_reserved_instruction(ctx);
4473                break;
4474            }
4475        }
4476        break;
4477    case NM_P_BRI:
4478        {
4479            int32_t s = sextract32(ctx->opcode, 0, 1) << 11 |
4480                        extract32(ctx->opcode, 1, 10) << 1;
4481            uint32_t u = extract32(ctx->opcode, 11, 7);
4482
4483            gen_compute_imm_branch(ctx, extract32(ctx->opcode, 18, 3),
4484                                   rt, u, s);
4485        }
4486        break;
4487    default:
4488        gen_reserved_instruction(ctx);
4489        break;
4490    }
4491    return 4;
4492}
4493
4494static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
4495{
4496    uint32_t op;
4497    int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RT3(ctx->opcode));
4498    int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
4499    int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD3(ctx->opcode));
4500    int offset;
4501    int imm;
4502
4503    /* make sure instructions are on a halfword boundary */
4504    if (ctx->base.pc_next & 0x1) {
4505        TCGv tmp = tcg_constant_tl(ctx->base.pc_next);
4506        tcg_gen_st_tl(tmp, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr));
4507        generate_exception_end(ctx, EXCP_AdEL);
4508        return 2;
4509    }
4510
4511    op = extract32(ctx->opcode, 10, 6);
4512    switch (op) {
4513    case NM_P16_MV:
4514        rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
4515        if (rt != 0) {
4516            /* MOVE */
4517            rs = NANOMIPS_EXTRACT_RS5(ctx->opcode);
4518            gen_arith(ctx, OPC_ADDU, rt, rs, 0);
4519        } else {
4520            /* P16.RI */
4521            switch (extract32(ctx->opcode, 3, 2)) {
4522            case NM_P16_SYSCALL:
4523                if (extract32(ctx->opcode, 2, 1) == 0) {
4524                    generate_exception_end(ctx, EXCP_SYSCALL);
4525                } else {
4526                    gen_reserved_instruction(ctx);
4527                }
4528                break;
4529            case NM_BREAK16:
4530                generate_exception_end(ctx, EXCP_BREAK);
4531                break;
4532            case NM_SDBBP16:
4533                if (is_uhi(ctx, extract32(ctx->opcode, 0, 3))) {
4534                    ctx->base.is_jmp = DISAS_SEMIHOST;
4535                } else {
4536                    if (ctx->hflags & MIPS_HFLAG_SBRI) {
4537                        gen_reserved_instruction(ctx);
4538                    } else {
4539                        generate_exception_end(ctx, EXCP_DBp);
4540                    }
4541                }
4542                break;
4543            default:
4544                gen_reserved_instruction(ctx);
4545                break;
4546            }
4547        }
4548        break;
4549    case NM_P16_SHIFT:
4550        {
4551            int shift = extract32(ctx->opcode, 0, 3);
4552            uint32_t opc = 0;
4553            shift = (shift == 0) ? 8 : shift;
4554
4555            switch (extract32(ctx->opcode, 3, 1)) {
4556            case NM_SLL16:
4557                opc = OPC_SLL;
4558                break;
4559            case NM_SRL16:
4560                opc = OPC_SRL;
4561                break;
4562            }
4563            gen_shift_imm(ctx, opc, rt, rs, shift);
4564        }
4565        break;
4566    case NM_P16C:
4567        switch (ctx->opcode & 1) {
4568        case NM_POOL16C_0:
4569            gen_pool16c_nanomips_insn(ctx);
4570            break;
4571        case NM_LWXS16:
4572            gen_ldxs(ctx, rt, rs, rd);
4573            break;
4574        }
4575        break;
4576    case NM_P16_A1:
4577        switch (extract32(ctx->opcode, 6, 1)) {
4578        case NM_ADDIUR1SP:
4579            imm = extract32(ctx->opcode, 0, 6) << 2;
4580            gen_arith_imm(ctx, OPC_ADDIU, rt, 29, imm);
4581            break;
4582        default:
4583            gen_reserved_instruction(ctx);
4584            break;
4585        }
4586        break;
4587    case NM_P16_A2:
4588        switch (extract32(ctx->opcode, 3, 1)) {
4589        case NM_ADDIUR2:
4590            imm = extract32(ctx->opcode, 0, 3) << 2;
4591            gen_arith_imm(ctx, OPC_ADDIU, rt, rs, imm);
4592            break;
4593        case NM_P_ADDIURS5:
4594            rt = extract32(ctx->opcode, 5, 5);
4595            if (rt != 0) {
4596                /* imm = sign_extend(s[3] . s[2:0] , from_nbits = 4) */
4597                imm = (sextract32(ctx->opcode, 4, 1) << 3) |
4598                      (extract32(ctx->opcode, 0, 3));
4599                gen_arith_imm(ctx, OPC_ADDIU, rt, rt, imm);
4600            }
4601            break;
4602        }
4603        break;
4604    case NM_P16_ADDU:
4605        switch (ctx->opcode & 0x1) {
4606        case NM_ADDU16:
4607            gen_arith(ctx, OPC_ADDU, rd, rs, rt);
4608            break;
4609        case NM_SUBU16:
4610            gen_arith(ctx, OPC_SUBU, rd, rs, rt);
4611            break;
4612        }
4613        break;
4614    case NM_P16_4X4:
4615        rt = (extract32(ctx->opcode, 9, 1) << 3) |
4616              extract32(ctx->opcode, 5, 3);
4617        rs = (extract32(ctx->opcode, 4, 1) << 3) |
4618              extract32(ctx->opcode, 0, 3);
4619        rt = decode_gpr_gpr4(rt);
4620        rs = decode_gpr_gpr4(rs);
4621        switch ((extract32(ctx->opcode, 7, 2) & 0x2) |
4622                (extract32(ctx->opcode, 3, 1))) {
4623        case NM_ADDU4X4:
4624            check_nms(ctx);
4625            gen_arith(ctx, OPC_ADDU, rt, rs, rt);
4626            break;
4627        case NM_MUL4X4:
4628            check_nms(ctx);
4629            gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt);
4630            break;
4631        default:
4632            gen_reserved_instruction(ctx);
4633            break;
4634        }
4635        break;
4636    case NM_LI16:
4637        {
4638            imm = extract32(ctx->opcode, 0, 7);
4639            imm = (imm == 0x7f ? -1 : imm);
4640            if (rt != 0) {
4641                tcg_gen_movi_tl(cpu_gpr[rt], imm);
4642            }
4643        }
4644        break;
4645    case NM_ANDI16:
4646        {
4647            uint32_t u = extract32(ctx->opcode, 0, 4);
4648            u = (u == 12) ? 0xff :
4649                (u == 13) ? 0xffff : u;
4650            gen_logic_imm(ctx, OPC_ANDI, rt, rs, u);
4651        }
4652        break;
4653    case NM_P16_LB:
4654        offset = extract32(ctx->opcode, 0, 2);
4655        switch (extract32(ctx->opcode, 2, 2)) {
4656        case NM_LB16:
4657            gen_ld(ctx, OPC_LB, rt, rs, offset);
4658            break;
4659        case NM_SB16:
4660            rt = decode_gpr_gpr3_src_store(
4661                     NANOMIPS_EXTRACT_RT3(ctx->opcode));
4662            gen_st(ctx, OPC_SB, rt, rs, offset);
4663            break;
4664        case NM_LBU16:
4665            gen_ld(ctx, OPC_LBU, rt, rs, offset);
4666            break;
4667        default:
4668            gen_reserved_instruction(ctx);
4669            break;
4670        }
4671        break;
4672    case NM_P16_LH:
4673        offset = extract32(ctx->opcode, 1, 2) << 1;
4674        switch ((extract32(ctx->opcode, 3, 1) << 1) | (ctx->opcode & 1)) {
4675        case NM_LH16:
4676            gen_ld(ctx, OPC_LH, rt, rs, offset);
4677            break;
4678        case NM_SH16:
4679            rt = decode_gpr_gpr3_src_store(
4680                     NANOMIPS_EXTRACT_RT3(ctx->opcode));
4681            gen_st(ctx, OPC_SH, rt, rs, offset);
4682            break;
4683        case NM_LHU16:
4684            gen_ld(ctx, OPC_LHU, rt, rs, offset);
4685            break;
4686        default:
4687            gen_reserved_instruction(ctx);
4688            break;
4689        }
4690        break;
4691    case NM_LW16:
4692        offset = extract32(ctx->opcode, 0, 4) << 2;
4693        gen_ld(ctx, OPC_LW, rt, rs, offset);
4694        break;
4695    case NM_LWSP16:
4696        rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
4697        offset = extract32(ctx->opcode, 0, 5) << 2;
4698        gen_ld(ctx, OPC_LW, rt, 29, offset);
4699        break;
4700    case NM_LW4X4:
4701        check_nms(ctx);
4702        rt = (extract32(ctx->opcode, 9, 1) << 3) |
4703             extract32(ctx->opcode, 5, 3);
4704        rs = (extract32(ctx->opcode, 4, 1) << 3) |
4705             extract32(ctx->opcode, 0, 3);
4706        offset = (extract32(ctx->opcode, 3, 1) << 3) |
4707                 (extract32(ctx->opcode, 8, 1) << 2);
4708        rt = decode_gpr_gpr4(rt);
4709        rs = decode_gpr_gpr4(rs);
4710        gen_ld(ctx, OPC_LW, rt, rs, offset);
4711        break;
4712    case NM_SW4X4:
4713        check_nms(ctx);
4714        rt = (extract32(ctx->opcode, 9, 1) << 3) |
4715             extract32(ctx->opcode, 5, 3);
4716        rs = (extract32(ctx->opcode, 4, 1) << 3) |
4717             extract32(ctx->opcode, 0, 3);
4718        offset = (extract32(ctx->opcode, 3, 1) << 3) |
4719                 (extract32(ctx->opcode, 8, 1) << 2);
4720        rt = decode_gpr_gpr4_zero(rt);
4721        rs = decode_gpr_gpr4(rs);
4722        gen_st(ctx, OPC_SW, rt, rs, offset);
4723        break;
4724    case NM_LWGP16:
4725        offset = extract32(ctx->opcode, 0, 7) << 2;
4726        gen_ld(ctx, OPC_LW, rt, 28, offset);
4727        break;
4728    case NM_SWSP16:
4729        rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
4730        offset = extract32(ctx->opcode, 0, 5) << 2;
4731        gen_st(ctx, OPC_SW, rt, 29, offset);
4732        break;
4733    case NM_SW16:
4734        rt = decode_gpr_gpr3_src_store(
4735                 NANOMIPS_EXTRACT_RT3(ctx->opcode));
4736        rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS3(ctx->opcode));
4737        offset = extract32(ctx->opcode, 0, 4) << 2;
4738        gen_st(ctx, OPC_SW, rt, rs, offset);
4739        break;
4740    case NM_SWGP16:
4741        rt = decode_gpr_gpr3_src_store(
4742                 NANOMIPS_EXTRACT_RT3(ctx->opcode));
4743        offset = extract32(ctx->opcode, 0, 7) << 2;
4744        gen_st(ctx, OPC_SW, rt, 28, offset);
4745        break;
4746    case NM_BC16:
4747        gen_compute_branch_nm(ctx, OPC_BEQ, 2, 0, 0,
4748                              (sextract32(ctx->opcode, 0, 1) << 10) |
4749                              (extract32(ctx->opcode, 1, 9) << 1));
4750        break;
4751    case NM_BALC16:
4752        gen_compute_branch_nm(ctx, OPC_BGEZAL, 2, 0, 0,
4753                              (sextract32(ctx->opcode, 0, 1) << 10) |
4754                              (extract32(ctx->opcode, 1, 9) << 1));
4755        break;
4756    case NM_BEQZC16:
4757        gen_compute_branch_nm(ctx, OPC_BEQ, 2, rt, 0,
4758                              (sextract32(ctx->opcode, 0, 1) << 7) |
4759                              (extract32(ctx->opcode, 1, 6) << 1));
4760        break;
4761    case NM_BNEZC16:
4762        gen_compute_branch_nm(ctx, OPC_BNE, 2, rt, 0,
4763                              (sextract32(ctx->opcode, 0, 1) << 7) |
4764                              (extract32(ctx->opcode, 1, 6) << 1));
4765        break;
4766    case NM_P16_BR:
4767        switch (ctx->opcode & 0xf) {
4768        case 0:
4769            /* P16.JRC */
4770            switch (extract32(ctx->opcode, 4, 1)) {
4771            case NM_JRC:
4772                gen_compute_branch_nm(ctx, OPC_JR, 2,
4773                                      extract32(ctx->opcode, 5, 5), 0, 0);
4774                break;
4775            case NM_JALRC16:
4776                gen_compute_branch_nm(ctx, OPC_JALR, 2,
4777                                      extract32(ctx->opcode, 5, 5), 31, 0);
4778                break;
4779            }
4780            break;
4781        default:
4782            {
4783                /* P16.BRI */
4784                uint32_t opc = extract32(ctx->opcode, 4, 3) <
4785                               extract32(ctx->opcode, 7, 3) ? OPC_BEQ : OPC_BNE;
4786                gen_compute_branch_nm(ctx, opc, 2, rs, rt,
4787                                      extract32(ctx->opcode, 0, 4) << 1);
4788            }
4789            break;
4790        }
4791        break;
4792    case NM_P16_SR:
4793        {
4794            int count = extract32(ctx->opcode, 0, 4);
4795            int u = extract32(ctx->opcode, 4, 4) << 4;
4796
4797            rt = 30 + extract32(ctx->opcode, 9, 1);
4798            switch (extract32(ctx->opcode, 8, 1)) {
4799            case NM_SAVE16:
4800                gen_save(ctx, rt, count, 0, u);
4801                break;
4802            case NM_RESTORE_JRC16:
4803                gen_restore(ctx, rt, count, 0, u);
4804                gen_compute_branch_nm(ctx, OPC_JR, 2, 31, 0, 0);
4805                break;
4806            }
4807        }
4808        break;
4809    case NM_MOVEP:
4810    case NM_MOVEPREV:
4811        check_nms(ctx);
4812        {
4813            static const int gpr2reg1[] = {4, 5, 6, 7};
4814            static const int gpr2reg2[] = {5, 6, 7, 8};
4815            int re;
4816            int rd2 = extract32(ctx->opcode, 3, 1) << 1 |
4817                      extract32(ctx->opcode, 8, 1);
4818            int r1 = gpr2reg1[rd2];
4819            int r2 = gpr2reg2[rd2];
4820            int r3 = extract32(ctx->opcode, 4, 1) << 3 |
4821                     extract32(ctx->opcode, 0, 3);
4822            int r4 = extract32(ctx->opcode, 9, 1) << 3 |
4823                     extract32(ctx->opcode, 5, 3);
4824            TCGv t0 = tcg_temp_new();
4825            TCGv t1 = tcg_temp_new();
4826            if (op == NM_MOVEP) {
4827                rd = r1;
4828                re = r2;
4829                rs = decode_gpr_gpr4_zero(r3);
4830                rt = decode_gpr_gpr4_zero(r4);
4831            } else {
4832                rd = decode_gpr_gpr4(r3);
4833                re = decode_gpr_gpr4(r4);
4834                rs = r1;
4835                rt = r2;
4836            }
4837            gen_load_gpr(t0, rs);
4838            gen_load_gpr(t1, rt);
4839            tcg_gen_mov_tl(cpu_gpr[rd], t0);
4840            tcg_gen_mov_tl(cpu_gpr[re], t1);
4841        }
4842        break;
4843    default:
4844        return decode_nanomips_32_48_opc(env, ctx);
4845    }
4846
4847    return 2;
4848}
4849