xref: /qemu/target/mips/tcg/tcg-internal.h (revision b83a80e8)
1 /*
2  * MIPS internal definitions and helpers (TCG accelerator)
3  *
4  * SPDX-License-Identifier: GPL-2.0-or-later
5  *
6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
7  * See the COPYING file in the top-level directory.
8  */
9 
10 #ifndef MIPS_TCG_INTERNAL_H
11 #define MIPS_TCG_INTERNAL_H
12 
13 #include "tcg/tcg.h"
14 #include "exec/memattrs.h"
15 #include "hw/core/cpu.h"
16 #include "cpu.h"
17 
18 void mips_tcg_init(void);
19 
20 void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
21 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
22                                   MMUAccessType access_type, int mmu_idx,
23                                   uintptr_t retaddr) QEMU_NORETURN;
24 
25 const char *mips_exception_name(int32_t exception);
26 
27 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
28                                           int error_code, uintptr_t pc);
29 
30 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
31                                                     uint32_t exception,
32                                                     uintptr_t pc)
33 {
34     do_raise_exception_err(env, exception, 0, pc);
35 }
36 
37 #if !defined(CONFIG_USER_ONLY)
38 
39 void mips_cpu_do_interrupt(CPUState *cpu);
40 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
41 
42 void mmu_init(CPUMIPSState *env, const mips_def_t *def);
43 
44 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
45 
46 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
47 uint32_t cpu_mips_get_random(CPUMIPSState *env);
48 
49 bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb);
50 
51 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
52                                   MMUAccessType access_type, uintptr_t retaddr);
53 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
54                                     vaddr addr, unsigned size,
55                                     MMUAccessType access_type,
56                                     int mmu_idx, MemTxAttrs attrs,
57                                     MemTxResult response, uintptr_t retaddr);
58 void cpu_mips_tlb_flush(CPUMIPSState *env);
59 
60 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
61                        MMUAccessType access_type, int mmu_idx,
62                        bool probe, uintptr_t retaddr);
63 
64 #endif /* !CONFIG_USER_ONLY */
65 
66 #endif
67