1 /* 2 * MIPS emulation for QEMU - main translation routines 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * Copyright (c) 2006 Marius Groeger (FPU operations) 6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) 7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) 8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) 9 * Copyright (c) 2020 Philippe Mathieu-Daudé 10 * 11 * This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU Lesser General Public 13 * License as published by the Free Software Foundation; either 14 * version 2.1 of the License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * Lesser General Public License for more details. 20 * 21 * You should have received a copy of the GNU Lesser General Public 22 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "translate.h" 27 #include "internal.h" 28 #include "exec/helper-proto.h" 29 #include "exec/translation-block.h" 30 #include "semihosting/semihost.h" 31 #include "trace.h" 32 #include "disas/disas.h" 33 #include "fpu_helper.h" 34 35 #define HELPER_H "helper.h" 36 #include "exec/helper-info.c.inc" 37 #undef HELPER_H 38 39 40 /* 41 * Many sysemu-only helpers are not reachable for user-only. 42 * Define stub generators here, so that we need not either sprinkle 43 * ifdefs through the translator, nor provide the helper function. 44 */ 45 #define STUB_HELPER(NAME, ...) \ 46 static inline void gen_helper_##NAME(__VA_ARGS__) \ 47 { g_assert_not_reached(); } 48 49 #ifdef CONFIG_USER_ONLY 50 STUB_HELPER(cache, TCGv_env env, TCGv val, TCGv_i32 reg) 51 #endif 52 53 enum { 54 /* indirect opcode tables */ 55 OPC_SPECIAL = (0x00 << 26), 56 OPC_REGIMM = (0x01 << 26), 57 OPC_CP0 = (0x10 << 26), 58 OPC_CP2 = (0x12 << 26), 59 OPC_CP3 = (0x13 << 26), 60 OPC_SPECIAL2 = (0x1C << 26), 61 OPC_SPECIAL3 = (0x1F << 26), 62 /* arithmetic with immediate */ 63 OPC_ADDI = (0x08 << 26), 64 OPC_ADDIU = (0x09 << 26), 65 OPC_SLTI = (0x0A << 26), 66 OPC_SLTIU = (0x0B << 26), 67 /* logic with immediate */ 68 OPC_ANDI = (0x0C << 26), 69 OPC_ORI = (0x0D << 26), 70 OPC_XORI = (0x0E << 26), 71 OPC_LUI = (0x0F << 26), 72 /* arithmetic with immediate */ 73 OPC_DADDI = (0x18 << 26), 74 OPC_DADDIU = (0x19 << 26), 75 /* Jump and branches */ 76 OPC_J = (0x02 << 26), 77 OPC_JAL = (0x03 << 26), 78 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */ 79 OPC_BEQL = (0x14 << 26), 80 OPC_BNE = (0x05 << 26), 81 OPC_BNEL = (0x15 << 26), 82 OPC_BLEZ = (0x06 << 26), 83 OPC_BLEZL = (0x16 << 26), 84 OPC_BGTZ = (0x07 << 26), 85 OPC_BGTZL = (0x17 << 26), 86 OPC_JALX = (0x1D << 26), 87 OPC_DAUI = (0x1D << 26), 88 /* Load and stores */ 89 OPC_LDL = (0x1A << 26), 90 OPC_LDR = (0x1B << 26), 91 OPC_LB = (0x20 << 26), 92 OPC_LH = (0x21 << 26), 93 OPC_LWL = (0x22 << 26), 94 OPC_LW = (0x23 << 26), 95 OPC_LWPC = OPC_LW | 0x5, 96 OPC_LBU = (0x24 << 26), 97 OPC_LHU = (0x25 << 26), 98 OPC_LWR = (0x26 << 26), 99 OPC_LWU = (0x27 << 26), 100 OPC_SB = (0x28 << 26), 101 OPC_SH = (0x29 << 26), 102 OPC_SWL = (0x2A << 26), 103 OPC_SW = (0x2B << 26), 104 OPC_SDL = (0x2C << 26), 105 OPC_SDR = (0x2D << 26), 106 OPC_SWR = (0x2E << 26), 107 OPC_LL = (0x30 << 26), 108 OPC_LLD = (0x34 << 26), 109 OPC_LD = (0x37 << 26), 110 OPC_LDPC = OPC_LD | 0x5, 111 OPC_SC = (0x38 << 26), 112 OPC_SCD = (0x3C << 26), 113 OPC_SD = (0x3F << 26), 114 /* Floating point load/store */ 115 OPC_LWC1 = (0x31 << 26), 116 OPC_LWC2 = (0x32 << 26), 117 OPC_LDC1 = (0x35 << 26), 118 OPC_LDC2 = (0x36 << 26), 119 OPC_SWC1 = (0x39 << 26), 120 OPC_SWC2 = (0x3A << 26), 121 OPC_SDC1 = (0x3D << 26), 122 OPC_SDC2 = (0x3E << 26), 123 /* Compact Branches */ 124 OPC_BLEZALC = (0x06 << 26), 125 OPC_BGEZALC = (0x06 << 26), 126 OPC_BGEUC = (0x06 << 26), 127 OPC_BGTZALC = (0x07 << 26), 128 OPC_BLTZALC = (0x07 << 26), 129 OPC_BLTUC = (0x07 << 26), 130 OPC_BOVC = (0x08 << 26), 131 OPC_BEQZALC = (0x08 << 26), 132 OPC_BEQC = (0x08 << 26), 133 OPC_BLEZC = (0x16 << 26), 134 OPC_BGEZC = (0x16 << 26), 135 OPC_BGEC = (0x16 << 26), 136 OPC_BGTZC = (0x17 << 26), 137 OPC_BLTZC = (0x17 << 26), 138 OPC_BLTC = (0x17 << 26), 139 OPC_BNVC = (0x18 << 26), 140 OPC_BNEZALC = (0x18 << 26), 141 OPC_BNEC = (0x18 << 26), 142 OPC_BC = (0x32 << 26), 143 OPC_BEQZC = (0x36 << 26), 144 OPC_JIC = (0x36 << 26), 145 OPC_BALC = (0x3A << 26), 146 OPC_BNEZC = (0x3E << 26), 147 OPC_JIALC = (0x3E << 26), 148 /* MDMX ASE specific */ 149 OPC_MDMX = (0x1E << 26), 150 /* Cache and prefetch */ 151 OPC_CACHE = (0x2F << 26), 152 OPC_PREF = (0x33 << 26), 153 /* PC-relative address computation / loads */ 154 OPC_PCREL = (0x3B << 26), 155 }; 156 157 /* PC-relative address computation / loads */ 158 #define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op & (3 << 19))) 159 #define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op & (0x1f << 16))) 160 enum { 161 /* Instructions determined by bits 19 and 20 */ 162 OPC_ADDIUPC = OPC_PCREL | (0 << 19), 163 R6_OPC_LWPC = OPC_PCREL | (1 << 19), 164 OPC_LWUPC = OPC_PCREL | (2 << 19), 165 166 /* Instructions determined by bits 16 ... 20 */ 167 OPC_AUIPC = OPC_PCREL | (0x1e << 16), 168 OPC_ALUIPC = OPC_PCREL | (0x1f << 16), 169 170 /* Other */ 171 R6_OPC_LDPC = OPC_PCREL | (6 << 18), 172 }; 173 174 /* MIPS special opcodes */ 175 #define MASK_SPECIAL(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 176 177 enum { 178 /* Shifts */ 179 OPC_SLL = 0x00 | OPC_SPECIAL, 180 /* NOP is SLL r0, r0, 0 */ 181 /* SSNOP is SLL r0, r0, 1 */ 182 /* EHB is SLL r0, r0, 3 */ 183 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */ 184 OPC_ROTR = OPC_SRL | (1 << 21), 185 OPC_SRA = 0x03 | OPC_SPECIAL, 186 OPC_SLLV = 0x04 | OPC_SPECIAL, 187 OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */ 188 OPC_ROTRV = OPC_SRLV | (1 << 6), 189 OPC_SRAV = 0x07 | OPC_SPECIAL, 190 OPC_DSLLV = 0x14 | OPC_SPECIAL, 191 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */ 192 OPC_DROTRV = OPC_DSRLV | (1 << 6), 193 OPC_DSRAV = 0x17 | OPC_SPECIAL, 194 OPC_DSLL = 0x38 | OPC_SPECIAL, 195 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */ 196 OPC_DROTR = OPC_DSRL | (1 << 21), 197 OPC_DSRA = 0x3B | OPC_SPECIAL, 198 OPC_DSLL32 = 0x3C | OPC_SPECIAL, 199 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */ 200 OPC_DROTR32 = OPC_DSRL32 | (1 << 21), 201 OPC_DSRA32 = 0x3F | OPC_SPECIAL, 202 /* Multiplication / division */ 203 OPC_MULT = 0x18 | OPC_SPECIAL, 204 OPC_MULTU = 0x19 | OPC_SPECIAL, 205 OPC_DIV = 0x1A | OPC_SPECIAL, 206 OPC_DIVU = 0x1B | OPC_SPECIAL, 207 OPC_DMULT = 0x1C | OPC_SPECIAL, 208 OPC_DMULTU = 0x1D | OPC_SPECIAL, 209 OPC_DDIV = 0x1E | OPC_SPECIAL, 210 OPC_DDIVU = 0x1F | OPC_SPECIAL, 211 212 /* 2 registers arithmetic / logic */ 213 OPC_ADD = 0x20 | OPC_SPECIAL, 214 OPC_ADDU = 0x21 | OPC_SPECIAL, 215 OPC_SUB = 0x22 | OPC_SPECIAL, 216 OPC_SUBU = 0x23 | OPC_SPECIAL, 217 OPC_AND = 0x24 | OPC_SPECIAL, 218 OPC_OR = 0x25 | OPC_SPECIAL, 219 OPC_XOR = 0x26 | OPC_SPECIAL, 220 OPC_NOR = 0x27 | OPC_SPECIAL, 221 OPC_SLT = 0x2A | OPC_SPECIAL, 222 OPC_SLTU = 0x2B | OPC_SPECIAL, 223 OPC_DADD = 0x2C | OPC_SPECIAL, 224 OPC_DADDU = 0x2D | OPC_SPECIAL, 225 OPC_DSUB = 0x2E | OPC_SPECIAL, 226 OPC_DSUBU = 0x2F | OPC_SPECIAL, 227 /* Jumps */ 228 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */ 229 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */ 230 /* Traps */ 231 OPC_TGE = 0x30 | OPC_SPECIAL, 232 OPC_TGEU = 0x31 | OPC_SPECIAL, 233 OPC_TLT = 0x32 | OPC_SPECIAL, 234 OPC_TLTU = 0x33 | OPC_SPECIAL, 235 OPC_TEQ = 0x34 | OPC_SPECIAL, 236 OPC_TNE = 0x36 | OPC_SPECIAL, 237 /* HI / LO registers load & stores */ 238 OPC_MFHI = 0x10 | OPC_SPECIAL, 239 OPC_MTHI = 0x11 | OPC_SPECIAL, 240 OPC_MFLO = 0x12 | OPC_SPECIAL, 241 OPC_MTLO = 0x13 | OPC_SPECIAL, 242 /* Conditional moves */ 243 OPC_MOVZ = 0x0A | OPC_SPECIAL, 244 OPC_MOVN = 0x0B | OPC_SPECIAL, 245 246 OPC_SELEQZ = 0x35 | OPC_SPECIAL, 247 OPC_SELNEZ = 0x37 | OPC_SPECIAL, 248 249 OPC_MOVCI = 0x01 | OPC_SPECIAL, 250 251 /* Special */ 252 OPC_PMON = 0x05 | OPC_SPECIAL, /* unofficial */ 253 OPC_SYSCALL = 0x0C | OPC_SPECIAL, 254 OPC_BREAK = 0x0D | OPC_SPECIAL, 255 OPC_SPIM = 0x0E | OPC_SPECIAL, /* unofficial */ 256 OPC_SYNC = 0x0F | OPC_SPECIAL, 257 258 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL, 259 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL, 260 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL, 261 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL, 262 }; 263 264 /* 265 * R6 Multiply and Divide instructions have the same opcode 266 * and function field as legacy OPC_MULT[U]/OPC_DIV[U] 267 */ 268 #define MASK_R6_MULDIV(op) (MASK_SPECIAL(op) | (op & (0x7ff))) 269 270 enum { 271 R6_OPC_MUL = OPC_MULT | (2 << 6), 272 R6_OPC_MUH = OPC_MULT | (3 << 6), 273 R6_OPC_MULU = OPC_MULTU | (2 << 6), 274 R6_OPC_MUHU = OPC_MULTU | (3 << 6), 275 R6_OPC_DIV = OPC_DIV | (2 << 6), 276 R6_OPC_MOD = OPC_DIV | (3 << 6), 277 R6_OPC_DIVU = OPC_DIVU | (2 << 6), 278 R6_OPC_MODU = OPC_DIVU | (3 << 6), 279 280 R6_OPC_DMUL = OPC_DMULT | (2 << 6), 281 R6_OPC_DMUH = OPC_DMULT | (3 << 6), 282 R6_OPC_DMULU = OPC_DMULTU | (2 << 6), 283 R6_OPC_DMUHU = OPC_DMULTU | (3 << 6), 284 R6_OPC_DDIV = OPC_DDIV | (2 << 6), 285 R6_OPC_DMOD = OPC_DDIV | (3 << 6), 286 R6_OPC_DDIVU = OPC_DDIVU | (2 << 6), 287 R6_OPC_DMODU = OPC_DDIVU | (3 << 6), 288 289 R6_OPC_CLZ = 0x10 | OPC_SPECIAL, 290 R6_OPC_CLO = 0x11 | OPC_SPECIAL, 291 R6_OPC_DCLZ = 0x12 | OPC_SPECIAL, 292 R6_OPC_DCLO = 0x13 | OPC_SPECIAL, 293 R6_OPC_SDBBP = 0x0e | OPC_SPECIAL, 294 }; 295 296 /* REGIMM (rt field) opcodes */ 297 #define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16))) 298 299 enum { 300 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM, 301 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM, 302 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM, 303 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM, 304 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM, 305 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM, 306 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM, 307 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM, 308 OPC_TGEI = (0x08 << 16) | OPC_REGIMM, 309 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM, 310 OPC_TLTI = (0x0A << 16) | OPC_REGIMM, 311 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM, 312 OPC_TEQI = (0x0C << 16) | OPC_REGIMM, 313 OPC_TNEI = (0x0E << 16) | OPC_REGIMM, 314 OPC_SIGRIE = (0x17 << 16) | OPC_REGIMM, 315 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM, 316 317 OPC_DAHI = (0x06 << 16) | OPC_REGIMM, 318 OPC_DATI = (0x1e << 16) | OPC_REGIMM, 319 }; 320 321 /* Special2 opcodes */ 322 #define MASK_SPECIAL2(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 323 324 enum { 325 /* Multiply & xxx operations */ 326 OPC_MADD = 0x00 | OPC_SPECIAL2, 327 OPC_MADDU = 0x01 | OPC_SPECIAL2, 328 OPC_MUL = 0x02 | OPC_SPECIAL2, 329 OPC_MSUB = 0x04 | OPC_SPECIAL2, 330 OPC_MSUBU = 0x05 | OPC_SPECIAL2, 331 /* Loongson 2F */ 332 OPC_MULT_G_2F = 0x10 | OPC_SPECIAL2, 333 OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2, 334 OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2, 335 OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2, 336 OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2, 337 OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2, 338 OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2, 339 OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2, 340 OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2, 341 OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2, 342 OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2, 343 OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2, 344 /* Misc */ 345 OPC_CLZ = 0x20 | OPC_SPECIAL2, 346 OPC_CLO = 0x21 | OPC_SPECIAL2, 347 OPC_DCLZ = 0x24 | OPC_SPECIAL2, 348 OPC_DCLO = 0x25 | OPC_SPECIAL2, 349 /* Special */ 350 OPC_SDBBP = 0x3F | OPC_SPECIAL2, 351 }; 352 353 /* Special3 opcodes */ 354 #define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 355 356 enum { 357 OPC_EXT = 0x00 | OPC_SPECIAL3, 358 OPC_DEXTM = 0x01 | OPC_SPECIAL3, 359 OPC_DEXTU = 0x02 | OPC_SPECIAL3, 360 OPC_DEXT = 0x03 | OPC_SPECIAL3, 361 OPC_INS = 0x04 | OPC_SPECIAL3, 362 OPC_DINSM = 0x05 | OPC_SPECIAL3, 363 OPC_DINSU = 0x06 | OPC_SPECIAL3, 364 OPC_DINS = 0x07 | OPC_SPECIAL3, 365 OPC_FORK = 0x08 | OPC_SPECIAL3, 366 OPC_YIELD = 0x09 | OPC_SPECIAL3, 367 OPC_BSHFL = 0x20 | OPC_SPECIAL3, 368 OPC_DBSHFL = 0x24 | OPC_SPECIAL3, 369 OPC_RDHWR = 0x3B | OPC_SPECIAL3, 370 OPC_GINV = 0x3D | OPC_SPECIAL3, 371 372 /* Loongson 2E */ 373 OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3, 374 OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3, 375 OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3, 376 OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3, 377 OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3, 378 OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3, 379 OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3, 380 OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3, 381 OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3, 382 OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, 383 OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, 384 OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, 385 386 /* MIPS DSP Load */ 387 OPC_LX_DSP = 0x0A | OPC_SPECIAL3, 388 /* MIPS DSP Arithmetic */ 389 OPC_ADDU_QB_DSP = 0x10 | OPC_SPECIAL3, 390 OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3, 391 OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3, 392 OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3, 393 /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */ 394 /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */ 395 OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3, 396 OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3, 397 /* MIPS DSP GPR-Based Shift Sub-class */ 398 OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3, 399 OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3, 400 /* MIPS DSP Multiply Sub-class insns */ 401 /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */ 402 /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */ 403 OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3, 404 OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3, 405 /* DSP Bit/Manipulation Sub-class */ 406 OPC_INSV_DSP = 0x0C | OPC_SPECIAL3, 407 OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3, 408 /* MIPS DSP Append Sub-class */ 409 OPC_APPEND_DSP = 0x31 | OPC_SPECIAL3, 410 OPC_DAPPEND_DSP = 0x35 | OPC_SPECIAL3, 411 /* MIPS DSP Accumulator and DSPControl Access Sub-class */ 412 OPC_EXTR_W_DSP = 0x38 | OPC_SPECIAL3, 413 OPC_DEXTR_W_DSP = 0x3C | OPC_SPECIAL3, 414 415 /* EVA */ 416 OPC_LWLE = 0x19 | OPC_SPECIAL3, 417 OPC_LWRE = 0x1A | OPC_SPECIAL3, 418 OPC_CACHEE = 0x1B | OPC_SPECIAL3, 419 OPC_SBE = 0x1C | OPC_SPECIAL3, 420 OPC_SHE = 0x1D | OPC_SPECIAL3, 421 OPC_SCE = 0x1E | OPC_SPECIAL3, 422 OPC_SWE = 0x1F | OPC_SPECIAL3, 423 OPC_SWLE = 0x21 | OPC_SPECIAL3, 424 OPC_SWRE = 0x22 | OPC_SPECIAL3, 425 OPC_PREFE = 0x23 | OPC_SPECIAL3, 426 OPC_LBUE = 0x28 | OPC_SPECIAL3, 427 OPC_LHUE = 0x29 | OPC_SPECIAL3, 428 OPC_LBE = 0x2C | OPC_SPECIAL3, 429 OPC_LHE = 0x2D | OPC_SPECIAL3, 430 OPC_LLE = 0x2E | OPC_SPECIAL3, 431 OPC_LWE = 0x2F | OPC_SPECIAL3, 432 433 /* R6 */ 434 R6_OPC_PREF = 0x35 | OPC_SPECIAL3, 435 R6_OPC_CACHE = 0x25 | OPC_SPECIAL3, 436 R6_OPC_LL = 0x36 | OPC_SPECIAL3, 437 R6_OPC_SC = 0x26 | OPC_SPECIAL3, 438 R6_OPC_LLD = 0x37 | OPC_SPECIAL3, 439 R6_OPC_SCD = 0x27 | OPC_SPECIAL3, 440 }; 441 442 /* Loongson EXT load/store quad word opcodes */ 443 #define MASK_LOONGSON_GSLSQ(op) (MASK_OP_MAJOR(op) | (op & 0x8020)) 444 enum { 445 OPC_GSLQ = 0x0020 | OPC_LWC2, 446 OPC_GSLQC1 = 0x8020 | OPC_LWC2, 447 OPC_GSSHFL = OPC_LWC2, 448 OPC_GSSQ = 0x0020 | OPC_SWC2, 449 OPC_GSSQC1 = 0x8020 | OPC_SWC2, 450 OPC_GSSHFS = OPC_SWC2, 451 }; 452 453 /* Loongson EXT shifted load/store opcodes */ 454 #define MASK_LOONGSON_GSSHFLS(op) (MASK_OP_MAJOR(op) | (op & 0xc03f)) 455 enum { 456 OPC_GSLWLC1 = 0x4 | OPC_GSSHFL, 457 OPC_GSLWRC1 = 0x5 | OPC_GSSHFL, 458 OPC_GSLDLC1 = 0x6 | OPC_GSSHFL, 459 OPC_GSLDRC1 = 0x7 | OPC_GSSHFL, 460 OPC_GSSWLC1 = 0x4 | OPC_GSSHFS, 461 OPC_GSSWRC1 = 0x5 | OPC_GSSHFS, 462 OPC_GSSDLC1 = 0x6 | OPC_GSSHFS, 463 OPC_GSSDRC1 = 0x7 | OPC_GSSHFS, 464 }; 465 466 /* Loongson EXT LDC2/SDC2 opcodes */ 467 #define MASK_LOONGSON_LSDC2(op) (MASK_OP_MAJOR(op) | (op & 0x7)) 468 469 enum { 470 OPC_GSLBX = 0x0 | OPC_LDC2, 471 OPC_GSLHX = 0x1 | OPC_LDC2, 472 OPC_GSLWX = 0x2 | OPC_LDC2, 473 OPC_GSLDX = 0x3 | OPC_LDC2, 474 OPC_GSLWXC1 = 0x6 | OPC_LDC2, 475 OPC_GSLDXC1 = 0x7 | OPC_LDC2, 476 OPC_GSSBX = 0x0 | OPC_SDC2, 477 OPC_GSSHX = 0x1 | OPC_SDC2, 478 OPC_GSSWX = 0x2 | OPC_SDC2, 479 OPC_GSSDX = 0x3 | OPC_SDC2, 480 OPC_GSSWXC1 = 0x6 | OPC_SDC2, 481 OPC_GSSDXC1 = 0x7 | OPC_SDC2, 482 }; 483 484 /* BSHFL opcodes */ 485 #define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 486 487 enum { 488 OPC_WSBH = (0x02 << 6) | OPC_BSHFL, 489 OPC_SEB = (0x10 << 6) | OPC_BSHFL, 490 OPC_SEH = (0x18 << 6) | OPC_BSHFL, 491 OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp (010.00 to 010.11) */ 492 OPC_ALIGN_1 = (0x09 << 6) | OPC_BSHFL, 493 OPC_ALIGN_2 = (0x0A << 6) | OPC_BSHFL, 494 OPC_ALIGN_3 = (0x0B << 6) | OPC_BSHFL, 495 OPC_BITSWAP = (0x00 << 6) | OPC_BSHFL /* 00000 */ 496 }; 497 498 /* DBSHFL opcodes */ 499 #define MASK_DBSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 500 501 enum { 502 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL, 503 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL, 504 OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp (01.000 to 01.111) */ 505 OPC_DALIGN_1 = (0x09 << 6) | OPC_DBSHFL, 506 OPC_DALIGN_2 = (0x0A << 6) | OPC_DBSHFL, 507 OPC_DALIGN_3 = (0x0B << 6) | OPC_DBSHFL, 508 OPC_DALIGN_4 = (0x0C << 6) | OPC_DBSHFL, 509 OPC_DALIGN_5 = (0x0D << 6) | OPC_DBSHFL, 510 OPC_DALIGN_6 = (0x0E << 6) | OPC_DBSHFL, 511 OPC_DALIGN_7 = (0x0F << 6) | OPC_DBSHFL, 512 OPC_DBITSWAP = (0x00 << 6) | OPC_DBSHFL, /* 00000 */ 513 }; 514 515 /* MIPS DSP REGIMM opcodes */ 516 enum { 517 OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM, 518 OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM, 519 }; 520 521 #define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 522 /* MIPS DSP Load */ 523 enum { 524 OPC_LBUX = (0x06 << 6) | OPC_LX_DSP, 525 OPC_LHX = (0x04 << 6) | OPC_LX_DSP, 526 OPC_LWX = (0x00 << 6) | OPC_LX_DSP, 527 OPC_LDX = (0x08 << 6) | OPC_LX_DSP, 528 }; 529 530 #define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 531 enum { 532 /* MIPS DSP Arithmetic Sub-class */ 533 OPC_ADDQ_PH = (0x0A << 6) | OPC_ADDU_QB_DSP, 534 OPC_ADDQ_S_PH = (0x0E << 6) | OPC_ADDU_QB_DSP, 535 OPC_ADDQ_S_W = (0x16 << 6) | OPC_ADDU_QB_DSP, 536 OPC_ADDU_QB = (0x00 << 6) | OPC_ADDU_QB_DSP, 537 OPC_ADDU_S_QB = (0x04 << 6) | OPC_ADDU_QB_DSP, 538 OPC_ADDU_PH = (0x08 << 6) | OPC_ADDU_QB_DSP, 539 OPC_ADDU_S_PH = (0x0C << 6) | OPC_ADDU_QB_DSP, 540 OPC_SUBQ_PH = (0x0B << 6) | OPC_ADDU_QB_DSP, 541 OPC_SUBQ_S_PH = (0x0F << 6) | OPC_ADDU_QB_DSP, 542 OPC_SUBQ_S_W = (0x17 << 6) | OPC_ADDU_QB_DSP, 543 OPC_SUBU_QB = (0x01 << 6) | OPC_ADDU_QB_DSP, 544 OPC_SUBU_S_QB = (0x05 << 6) | OPC_ADDU_QB_DSP, 545 OPC_SUBU_PH = (0x09 << 6) | OPC_ADDU_QB_DSP, 546 OPC_SUBU_S_PH = (0x0D << 6) | OPC_ADDU_QB_DSP, 547 OPC_ADDSC = (0x10 << 6) | OPC_ADDU_QB_DSP, 548 OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP, 549 OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP, 550 OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP, 551 /* MIPS DSP Multiply Sub-class insns */ 552 OPC_MULEU_S_PH_QBL = (0x06 << 6) | OPC_ADDU_QB_DSP, 553 OPC_MULEU_S_PH_QBR = (0x07 << 6) | OPC_ADDU_QB_DSP, 554 OPC_MULQ_RS_PH = (0x1F << 6) | OPC_ADDU_QB_DSP, 555 OPC_MULEQ_S_W_PHL = (0x1C << 6) | OPC_ADDU_QB_DSP, 556 OPC_MULEQ_S_W_PHR = (0x1D << 6) | OPC_ADDU_QB_DSP, 557 OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP, 558 }; 559 560 #define OPC_ADDUH_QB_DSP OPC_MULT_G_2E 561 #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 562 enum { 563 /* MIPS DSP Arithmetic Sub-class */ 564 OPC_ADDUH_QB = (0x00 << 6) | OPC_ADDUH_QB_DSP, 565 OPC_ADDUH_R_QB = (0x02 << 6) | OPC_ADDUH_QB_DSP, 566 OPC_ADDQH_PH = (0x08 << 6) | OPC_ADDUH_QB_DSP, 567 OPC_ADDQH_R_PH = (0x0A << 6) | OPC_ADDUH_QB_DSP, 568 OPC_ADDQH_W = (0x10 << 6) | OPC_ADDUH_QB_DSP, 569 OPC_ADDQH_R_W = (0x12 << 6) | OPC_ADDUH_QB_DSP, 570 OPC_SUBUH_QB = (0x01 << 6) | OPC_ADDUH_QB_DSP, 571 OPC_SUBUH_R_QB = (0x03 << 6) | OPC_ADDUH_QB_DSP, 572 OPC_SUBQH_PH = (0x09 << 6) | OPC_ADDUH_QB_DSP, 573 OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP, 574 OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP, 575 OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP, 576 /* MIPS DSP Multiply Sub-class insns */ 577 OPC_MUL_PH = (0x0C << 6) | OPC_ADDUH_QB_DSP, 578 OPC_MUL_S_PH = (0x0E << 6) | OPC_ADDUH_QB_DSP, 579 OPC_MULQ_S_W = (0x16 << 6) | OPC_ADDUH_QB_DSP, 580 OPC_MULQ_RS_W = (0x17 << 6) | OPC_ADDUH_QB_DSP, 581 }; 582 583 #define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 584 enum { 585 /* MIPS DSP Arithmetic Sub-class */ 586 OPC_ABSQ_S_QB = (0x01 << 6) | OPC_ABSQ_S_PH_DSP, 587 OPC_ABSQ_S_PH = (0x09 << 6) | OPC_ABSQ_S_PH_DSP, 588 OPC_ABSQ_S_W = (0x11 << 6) | OPC_ABSQ_S_PH_DSP, 589 OPC_PRECEQ_W_PHL = (0x0C << 6) | OPC_ABSQ_S_PH_DSP, 590 OPC_PRECEQ_W_PHR = (0x0D << 6) | OPC_ABSQ_S_PH_DSP, 591 OPC_PRECEQU_PH_QBL = (0x04 << 6) | OPC_ABSQ_S_PH_DSP, 592 OPC_PRECEQU_PH_QBR = (0x05 << 6) | OPC_ABSQ_S_PH_DSP, 593 OPC_PRECEQU_PH_QBLA = (0x06 << 6) | OPC_ABSQ_S_PH_DSP, 594 OPC_PRECEQU_PH_QBRA = (0x07 << 6) | OPC_ABSQ_S_PH_DSP, 595 OPC_PRECEU_PH_QBL = (0x1C << 6) | OPC_ABSQ_S_PH_DSP, 596 OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP, 597 OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP, 598 OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP, 599 /* DSP Bit/Manipulation Sub-class */ 600 OPC_BITREV = (0x1B << 6) | OPC_ABSQ_S_PH_DSP, 601 OPC_REPL_QB = (0x02 << 6) | OPC_ABSQ_S_PH_DSP, 602 OPC_REPLV_QB = (0x03 << 6) | OPC_ABSQ_S_PH_DSP, 603 OPC_REPL_PH = (0x0A << 6) | OPC_ABSQ_S_PH_DSP, 604 OPC_REPLV_PH = (0x0B << 6) | OPC_ABSQ_S_PH_DSP, 605 }; 606 607 #define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 608 enum { 609 /* MIPS DSP Arithmetic Sub-class */ 610 OPC_PRECR_QB_PH = (0x0D << 6) | OPC_CMPU_EQ_QB_DSP, 611 OPC_PRECRQ_QB_PH = (0x0C << 6) | OPC_CMPU_EQ_QB_DSP, 612 OPC_PRECR_SRA_PH_W = (0x1E << 6) | OPC_CMPU_EQ_QB_DSP, 613 OPC_PRECR_SRA_R_PH_W = (0x1F << 6) | OPC_CMPU_EQ_QB_DSP, 614 OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP, 615 OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP, 616 OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP, 617 /* DSP Compare-Pick Sub-class */ 618 OPC_CMPU_EQ_QB = (0x00 << 6) | OPC_CMPU_EQ_QB_DSP, 619 OPC_CMPU_LT_QB = (0x01 << 6) | OPC_CMPU_EQ_QB_DSP, 620 OPC_CMPU_LE_QB = (0x02 << 6) | OPC_CMPU_EQ_QB_DSP, 621 OPC_CMPGU_EQ_QB = (0x04 << 6) | OPC_CMPU_EQ_QB_DSP, 622 OPC_CMPGU_LT_QB = (0x05 << 6) | OPC_CMPU_EQ_QB_DSP, 623 OPC_CMPGU_LE_QB = (0x06 << 6) | OPC_CMPU_EQ_QB_DSP, 624 OPC_CMPGDU_EQ_QB = (0x18 << 6) | OPC_CMPU_EQ_QB_DSP, 625 OPC_CMPGDU_LT_QB = (0x19 << 6) | OPC_CMPU_EQ_QB_DSP, 626 OPC_CMPGDU_LE_QB = (0x1A << 6) | OPC_CMPU_EQ_QB_DSP, 627 OPC_CMP_EQ_PH = (0x08 << 6) | OPC_CMPU_EQ_QB_DSP, 628 OPC_CMP_LT_PH = (0x09 << 6) | OPC_CMPU_EQ_QB_DSP, 629 OPC_CMP_LE_PH = (0x0A << 6) | OPC_CMPU_EQ_QB_DSP, 630 OPC_PICK_QB = (0x03 << 6) | OPC_CMPU_EQ_QB_DSP, 631 OPC_PICK_PH = (0x0B << 6) | OPC_CMPU_EQ_QB_DSP, 632 OPC_PACKRL_PH = (0x0E << 6) | OPC_CMPU_EQ_QB_DSP, 633 }; 634 635 #define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 636 enum { 637 /* MIPS DSP GPR-Based Shift Sub-class */ 638 OPC_SHLL_QB = (0x00 << 6) | OPC_SHLL_QB_DSP, 639 OPC_SHLLV_QB = (0x02 << 6) | OPC_SHLL_QB_DSP, 640 OPC_SHLL_PH = (0x08 << 6) | OPC_SHLL_QB_DSP, 641 OPC_SHLLV_PH = (0x0A << 6) | OPC_SHLL_QB_DSP, 642 OPC_SHLL_S_PH = (0x0C << 6) | OPC_SHLL_QB_DSP, 643 OPC_SHLLV_S_PH = (0x0E << 6) | OPC_SHLL_QB_DSP, 644 OPC_SHLL_S_W = (0x14 << 6) | OPC_SHLL_QB_DSP, 645 OPC_SHLLV_S_W = (0x16 << 6) | OPC_SHLL_QB_DSP, 646 OPC_SHRL_QB = (0x01 << 6) | OPC_SHLL_QB_DSP, 647 OPC_SHRLV_QB = (0x03 << 6) | OPC_SHLL_QB_DSP, 648 OPC_SHRL_PH = (0x19 << 6) | OPC_SHLL_QB_DSP, 649 OPC_SHRLV_PH = (0x1B << 6) | OPC_SHLL_QB_DSP, 650 OPC_SHRA_QB = (0x04 << 6) | OPC_SHLL_QB_DSP, 651 OPC_SHRA_R_QB = (0x05 << 6) | OPC_SHLL_QB_DSP, 652 OPC_SHRAV_QB = (0x06 << 6) | OPC_SHLL_QB_DSP, 653 OPC_SHRAV_R_QB = (0x07 << 6) | OPC_SHLL_QB_DSP, 654 OPC_SHRA_PH = (0x09 << 6) | OPC_SHLL_QB_DSP, 655 OPC_SHRAV_PH = (0x0B << 6) | OPC_SHLL_QB_DSP, 656 OPC_SHRA_R_PH = (0x0D << 6) | OPC_SHLL_QB_DSP, 657 OPC_SHRAV_R_PH = (0x0F << 6) | OPC_SHLL_QB_DSP, 658 OPC_SHRA_R_W = (0x15 << 6) | OPC_SHLL_QB_DSP, 659 OPC_SHRAV_R_W = (0x17 << 6) | OPC_SHLL_QB_DSP, 660 }; 661 662 #define MASK_DPA_W_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 663 enum { 664 /* MIPS DSP Multiply Sub-class insns */ 665 OPC_DPAU_H_QBL = (0x03 << 6) | OPC_DPA_W_PH_DSP, 666 OPC_DPAU_H_QBR = (0x07 << 6) | OPC_DPA_W_PH_DSP, 667 OPC_DPSU_H_QBL = (0x0B << 6) | OPC_DPA_W_PH_DSP, 668 OPC_DPSU_H_QBR = (0x0F << 6) | OPC_DPA_W_PH_DSP, 669 OPC_DPA_W_PH = (0x00 << 6) | OPC_DPA_W_PH_DSP, 670 OPC_DPAX_W_PH = (0x08 << 6) | OPC_DPA_W_PH_DSP, 671 OPC_DPAQ_S_W_PH = (0x04 << 6) | OPC_DPA_W_PH_DSP, 672 OPC_DPAQX_S_W_PH = (0x18 << 6) | OPC_DPA_W_PH_DSP, 673 OPC_DPAQX_SA_W_PH = (0x1A << 6) | OPC_DPA_W_PH_DSP, 674 OPC_DPS_W_PH = (0x01 << 6) | OPC_DPA_W_PH_DSP, 675 OPC_DPSX_W_PH = (0x09 << 6) | OPC_DPA_W_PH_DSP, 676 OPC_DPSQ_S_W_PH = (0x05 << 6) | OPC_DPA_W_PH_DSP, 677 OPC_DPSQX_S_W_PH = (0x19 << 6) | OPC_DPA_W_PH_DSP, 678 OPC_DPSQX_SA_W_PH = (0x1B << 6) | OPC_DPA_W_PH_DSP, 679 OPC_MULSAQ_S_W_PH = (0x06 << 6) | OPC_DPA_W_PH_DSP, 680 OPC_DPAQ_SA_L_W = (0x0C << 6) | OPC_DPA_W_PH_DSP, 681 OPC_DPSQ_SA_L_W = (0x0D << 6) | OPC_DPA_W_PH_DSP, 682 OPC_MAQ_S_W_PHL = (0x14 << 6) | OPC_DPA_W_PH_DSP, 683 OPC_MAQ_S_W_PHR = (0x16 << 6) | OPC_DPA_W_PH_DSP, 684 OPC_MAQ_SA_W_PHL = (0x10 << 6) | OPC_DPA_W_PH_DSP, 685 OPC_MAQ_SA_W_PHR = (0x12 << 6) | OPC_DPA_W_PH_DSP, 686 OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP, 687 }; 688 689 #define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 690 enum { 691 /* DSP Bit/Manipulation Sub-class */ 692 OPC_INSV = (0x00 << 6) | OPC_INSV_DSP, 693 }; 694 695 #define MASK_APPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 696 enum { 697 /* MIPS DSP Append Sub-class */ 698 OPC_APPEND = (0x00 << 6) | OPC_APPEND_DSP, 699 OPC_PREPEND = (0x01 << 6) | OPC_APPEND_DSP, 700 OPC_BALIGN = (0x10 << 6) | OPC_APPEND_DSP, 701 }; 702 703 #define MASK_EXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 704 enum { 705 /* MIPS DSP Accumulator and DSPControl Access Sub-class */ 706 OPC_EXTR_W = (0x00 << 6) | OPC_EXTR_W_DSP, 707 OPC_EXTR_R_W = (0x04 << 6) | OPC_EXTR_W_DSP, 708 OPC_EXTR_RS_W = (0x06 << 6) | OPC_EXTR_W_DSP, 709 OPC_EXTR_S_H = (0x0E << 6) | OPC_EXTR_W_DSP, 710 OPC_EXTRV_S_H = (0x0F << 6) | OPC_EXTR_W_DSP, 711 OPC_EXTRV_W = (0x01 << 6) | OPC_EXTR_W_DSP, 712 OPC_EXTRV_R_W = (0x05 << 6) | OPC_EXTR_W_DSP, 713 OPC_EXTRV_RS_W = (0x07 << 6) | OPC_EXTR_W_DSP, 714 OPC_EXTP = (0x02 << 6) | OPC_EXTR_W_DSP, 715 OPC_EXTPV = (0x03 << 6) | OPC_EXTR_W_DSP, 716 OPC_EXTPDP = (0x0A << 6) | OPC_EXTR_W_DSP, 717 OPC_EXTPDPV = (0x0B << 6) | OPC_EXTR_W_DSP, 718 OPC_SHILO = (0x1A << 6) | OPC_EXTR_W_DSP, 719 OPC_SHILOV = (0x1B << 6) | OPC_EXTR_W_DSP, 720 OPC_MTHLIP = (0x1F << 6) | OPC_EXTR_W_DSP, 721 OPC_WRDSP = (0x13 << 6) | OPC_EXTR_W_DSP, 722 OPC_RDDSP = (0x12 << 6) | OPC_EXTR_W_DSP, 723 }; 724 725 #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 726 enum { 727 /* MIPS DSP Arithmetic Sub-class */ 728 OPC_PRECEQ_L_PWL = (0x14 << 6) | OPC_ABSQ_S_QH_DSP, 729 OPC_PRECEQ_L_PWR = (0x15 << 6) | OPC_ABSQ_S_QH_DSP, 730 OPC_PRECEQ_PW_QHL = (0x0C << 6) | OPC_ABSQ_S_QH_DSP, 731 OPC_PRECEQ_PW_QHR = (0x0D << 6) | OPC_ABSQ_S_QH_DSP, 732 OPC_PRECEQ_PW_QHLA = (0x0E << 6) | OPC_ABSQ_S_QH_DSP, 733 OPC_PRECEQ_PW_QHRA = (0x0F << 6) | OPC_ABSQ_S_QH_DSP, 734 OPC_PRECEQU_QH_OBL = (0x04 << 6) | OPC_ABSQ_S_QH_DSP, 735 OPC_PRECEQU_QH_OBR = (0x05 << 6) | OPC_ABSQ_S_QH_DSP, 736 OPC_PRECEQU_QH_OBLA = (0x06 << 6) | OPC_ABSQ_S_QH_DSP, 737 OPC_PRECEQU_QH_OBRA = (0x07 << 6) | OPC_ABSQ_S_QH_DSP, 738 OPC_PRECEU_QH_OBL = (0x1C << 6) | OPC_ABSQ_S_QH_DSP, 739 OPC_PRECEU_QH_OBR = (0x1D << 6) | OPC_ABSQ_S_QH_DSP, 740 OPC_PRECEU_QH_OBLA = (0x1E << 6) | OPC_ABSQ_S_QH_DSP, 741 OPC_PRECEU_QH_OBRA = (0x1F << 6) | OPC_ABSQ_S_QH_DSP, 742 OPC_ABSQ_S_OB = (0x01 << 6) | OPC_ABSQ_S_QH_DSP, 743 OPC_ABSQ_S_PW = (0x11 << 6) | OPC_ABSQ_S_QH_DSP, 744 OPC_ABSQ_S_QH = (0x09 << 6) | OPC_ABSQ_S_QH_DSP, 745 /* DSP Bit/Manipulation Sub-class */ 746 OPC_REPL_OB = (0x02 << 6) | OPC_ABSQ_S_QH_DSP, 747 OPC_REPL_PW = (0x12 << 6) | OPC_ABSQ_S_QH_DSP, 748 OPC_REPL_QH = (0x0A << 6) | OPC_ABSQ_S_QH_DSP, 749 OPC_REPLV_OB = (0x03 << 6) | OPC_ABSQ_S_QH_DSP, 750 OPC_REPLV_PW = (0x13 << 6) | OPC_ABSQ_S_QH_DSP, 751 OPC_REPLV_QH = (0x0B << 6) | OPC_ABSQ_S_QH_DSP, 752 }; 753 754 #define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 755 enum { 756 /* MIPS DSP Multiply Sub-class insns */ 757 OPC_MULEQ_S_PW_QHL = (0x1C << 6) | OPC_ADDU_OB_DSP, 758 OPC_MULEQ_S_PW_QHR = (0x1D << 6) | OPC_ADDU_OB_DSP, 759 OPC_MULEU_S_QH_OBL = (0x06 << 6) | OPC_ADDU_OB_DSP, 760 OPC_MULEU_S_QH_OBR = (0x07 << 6) | OPC_ADDU_OB_DSP, 761 OPC_MULQ_RS_QH = (0x1F << 6) | OPC_ADDU_OB_DSP, 762 /* MIPS DSP Arithmetic Sub-class */ 763 OPC_RADDU_L_OB = (0x14 << 6) | OPC_ADDU_OB_DSP, 764 OPC_SUBQ_PW = (0x13 << 6) | OPC_ADDU_OB_DSP, 765 OPC_SUBQ_S_PW = (0x17 << 6) | OPC_ADDU_OB_DSP, 766 OPC_SUBQ_QH = (0x0B << 6) | OPC_ADDU_OB_DSP, 767 OPC_SUBQ_S_QH = (0x0F << 6) | OPC_ADDU_OB_DSP, 768 OPC_SUBU_OB = (0x01 << 6) | OPC_ADDU_OB_DSP, 769 OPC_SUBU_S_OB = (0x05 << 6) | OPC_ADDU_OB_DSP, 770 OPC_SUBU_QH = (0x09 << 6) | OPC_ADDU_OB_DSP, 771 OPC_SUBU_S_QH = (0x0D << 6) | OPC_ADDU_OB_DSP, 772 OPC_SUBUH_OB = (0x19 << 6) | OPC_ADDU_OB_DSP, 773 OPC_SUBUH_R_OB = (0x1B << 6) | OPC_ADDU_OB_DSP, 774 OPC_ADDQ_PW = (0x12 << 6) | OPC_ADDU_OB_DSP, 775 OPC_ADDQ_S_PW = (0x16 << 6) | OPC_ADDU_OB_DSP, 776 OPC_ADDQ_QH = (0x0A << 6) | OPC_ADDU_OB_DSP, 777 OPC_ADDQ_S_QH = (0x0E << 6) | OPC_ADDU_OB_DSP, 778 OPC_ADDU_OB = (0x00 << 6) | OPC_ADDU_OB_DSP, 779 OPC_ADDU_S_OB = (0x04 << 6) | OPC_ADDU_OB_DSP, 780 OPC_ADDU_QH = (0x08 << 6) | OPC_ADDU_OB_DSP, 781 OPC_ADDU_S_QH = (0x0C << 6) | OPC_ADDU_OB_DSP, 782 OPC_ADDUH_OB = (0x18 << 6) | OPC_ADDU_OB_DSP, 783 OPC_ADDUH_R_OB = (0x1A << 6) | OPC_ADDU_OB_DSP, 784 }; 785 786 #define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 787 enum { 788 /* DSP Compare-Pick Sub-class */ 789 OPC_CMP_EQ_PW = (0x10 << 6) | OPC_CMPU_EQ_OB_DSP, 790 OPC_CMP_LT_PW = (0x11 << 6) | OPC_CMPU_EQ_OB_DSP, 791 OPC_CMP_LE_PW = (0x12 << 6) | OPC_CMPU_EQ_OB_DSP, 792 OPC_CMP_EQ_QH = (0x08 << 6) | OPC_CMPU_EQ_OB_DSP, 793 OPC_CMP_LT_QH = (0x09 << 6) | OPC_CMPU_EQ_OB_DSP, 794 OPC_CMP_LE_QH = (0x0A << 6) | OPC_CMPU_EQ_OB_DSP, 795 OPC_CMPGDU_EQ_OB = (0x18 << 6) | OPC_CMPU_EQ_OB_DSP, 796 OPC_CMPGDU_LT_OB = (0x19 << 6) | OPC_CMPU_EQ_OB_DSP, 797 OPC_CMPGDU_LE_OB = (0x1A << 6) | OPC_CMPU_EQ_OB_DSP, 798 OPC_CMPGU_EQ_OB = (0x04 << 6) | OPC_CMPU_EQ_OB_DSP, 799 OPC_CMPGU_LT_OB = (0x05 << 6) | OPC_CMPU_EQ_OB_DSP, 800 OPC_CMPGU_LE_OB = (0x06 << 6) | OPC_CMPU_EQ_OB_DSP, 801 OPC_CMPU_EQ_OB = (0x00 << 6) | OPC_CMPU_EQ_OB_DSP, 802 OPC_CMPU_LT_OB = (0x01 << 6) | OPC_CMPU_EQ_OB_DSP, 803 OPC_CMPU_LE_OB = (0x02 << 6) | OPC_CMPU_EQ_OB_DSP, 804 OPC_PACKRL_PW = (0x0E << 6) | OPC_CMPU_EQ_OB_DSP, 805 OPC_PICK_OB = (0x03 << 6) | OPC_CMPU_EQ_OB_DSP, 806 OPC_PICK_PW = (0x13 << 6) | OPC_CMPU_EQ_OB_DSP, 807 OPC_PICK_QH = (0x0B << 6) | OPC_CMPU_EQ_OB_DSP, 808 /* MIPS DSP Arithmetic Sub-class */ 809 OPC_PRECR_OB_QH = (0x0D << 6) | OPC_CMPU_EQ_OB_DSP, 810 OPC_PRECR_SRA_QH_PW = (0x1E << 6) | OPC_CMPU_EQ_OB_DSP, 811 OPC_PRECR_SRA_R_QH_PW = (0x1F << 6) | OPC_CMPU_EQ_OB_DSP, 812 OPC_PRECRQ_OB_QH = (0x0C << 6) | OPC_CMPU_EQ_OB_DSP, 813 OPC_PRECRQ_PW_L = (0x1C << 6) | OPC_CMPU_EQ_OB_DSP, 814 OPC_PRECRQ_QH_PW = (0x14 << 6) | OPC_CMPU_EQ_OB_DSP, 815 OPC_PRECRQ_RS_QH_PW = (0x15 << 6) | OPC_CMPU_EQ_OB_DSP, 816 OPC_PRECRQU_S_OB_QH = (0x0F << 6) | OPC_CMPU_EQ_OB_DSP, 817 }; 818 819 #define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 820 enum { 821 /* DSP Append Sub-class */ 822 OPC_DAPPEND = (0x00 << 6) | OPC_DAPPEND_DSP, 823 OPC_PREPENDD = (0x03 << 6) | OPC_DAPPEND_DSP, 824 OPC_PREPENDW = (0x01 << 6) | OPC_DAPPEND_DSP, 825 OPC_DBALIGN = (0x10 << 6) | OPC_DAPPEND_DSP, 826 }; 827 828 #define MASK_DEXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 829 enum { 830 /* MIPS DSP Accumulator and DSPControl Access Sub-class */ 831 OPC_DMTHLIP = (0x1F << 6) | OPC_DEXTR_W_DSP, 832 OPC_DSHILO = (0x1A << 6) | OPC_DEXTR_W_DSP, 833 OPC_DEXTP = (0x02 << 6) | OPC_DEXTR_W_DSP, 834 OPC_DEXTPDP = (0x0A << 6) | OPC_DEXTR_W_DSP, 835 OPC_DEXTPDPV = (0x0B << 6) | OPC_DEXTR_W_DSP, 836 OPC_DEXTPV = (0x03 << 6) | OPC_DEXTR_W_DSP, 837 OPC_DEXTR_L = (0x10 << 6) | OPC_DEXTR_W_DSP, 838 OPC_DEXTR_R_L = (0x14 << 6) | OPC_DEXTR_W_DSP, 839 OPC_DEXTR_RS_L = (0x16 << 6) | OPC_DEXTR_W_DSP, 840 OPC_DEXTR_W = (0x00 << 6) | OPC_DEXTR_W_DSP, 841 OPC_DEXTR_R_W = (0x04 << 6) | OPC_DEXTR_W_DSP, 842 OPC_DEXTR_RS_W = (0x06 << 6) | OPC_DEXTR_W_DSP, 843 OPC_DEXTR_S_H = (0x0E << 6) | OPC_DEXTR_W_DSP, 844 OPC_DEXTRV_L = (0x11 << 6) | OPC_DEXTR_W_DSP, 845 OPC_DEXTRV_R_L = (0x15 << 6) | OPC_DEXTR_W_DSP, 846 OPC_DEXTRV_RS_L = (0x17 << 6) | OPC_DEXTR_W_DSP, 847 OPC_DEXTRV_S_H = (0x0F << 6) | OPC_DEXTR_W_DSP, 848 OPC_DEXTRV_W = (0x01 << 6) | OPC_DEXTR_W_DSP, 849 OPC_DEXTRV_R_W = (0x05 << 6) | OPC_DEXTR_W_DSP, 850 OPC_DEXTRV_RS_W = (0x07 << 6) | OPC_DEXTR_W_DSP, 851 OPC_DSHILOV = (0x1B << 6) | OPC_DEXTR_W_DSP, 852 }; 853 854 #define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 855 enum { 856 /* DSP Bit/Manipulation Sub-class */ 857 OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP, 858 }; 859 860 #define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 861 enum { 862 /* MIPS DSP Multiply Sub-class insns */ 863 OPC_DMADD = (0x19 << 6) | OPC_DPAQ_W_QH_DSP, 864 OPC_DMADDU = (0x1D << 6) | OPC_DPAQ_W_QH_DSP, 865 OPC_DMSUB = (0x1B << 6) | OPC_DPAQ_W_QH_DSP, 866 OPC_DMSUBU = (0x1F << 6) | OPC_DPAQ_W_QH_DSP, 867 OPC_DPA_W_QH = (0x00 << 6) | OPC_DPAQ_W_QH_DSP, 868 OPC_DPAQ_S_W_QH = (0x04 << 6) | OPC_DPAQ_W_QH_DSP, 869 OPC_DPAQ_SA_L_PW = (0x0C << 6) | OPC_DPAQ_W_QH_DSP, 870 OPC_DPAU_H_OBL = (0x03 << 6) | OPC_DPAQ_W_QH_DSP, 871 OPC_DPAU_H_OBR = (0x07 << 6) | OPC_DPAQ_W_QH_DSP, 872 OPC_DPS_W_QH = (0x01 << 6) | OPC_DPAQ_W_QH_DSP, 873 OPC_DPSQ_S_W_QH = (0x05 << 6) | OPC_DPAQ_W_QH_DSP, 874 OPC_DPSQ_SA_L_PW = (0x0D << 6) | OPC_DPAQ_W_QH_DSP, 875 OPC_DPSU_H_OBL = (0x0B << 6) | OPC_DPAQ_W_QH_DSP, 876 OPC_DPSU_H_OBR = (0x0F << 6) | OPC_DPAQ_W_QH_DSP, 877 OPC_MAQ_S_L_PWL = (0x1C << 6) | OPC_DPAQ_W_QH_DSP, 878 OPC_MAQ_S_L_PWR = (0x1E << 6) | OPC_DPAQ_W_QH_DSP, 879 OPC_MAQ_S_W_QHLL = (0x14 << 6) | OPC_DPAQ_W_QH_DSP, 880 OPC_MAQ_SA_W_QHLL = (0x10 << 6) | OPC_DPAQ_W_QH_DSP, 881 OPC_MAQ_S_W_QHLR = (0x15 << 6) | OPC_DPAQ_W_QH_DSP, 882 OPC_MAQ_SA_W_QHLR = (0x11 << 6) | OPC_DPAQ_W_QH_DSP, 883 OPC_MAQ_S_W_QHRL = (0x16 << 6) | OPC_DPAQ_W_QH_DSP, 884 OPC_MAQ_SA_W_QHRL = (0x12 << 6) | OPC_DPAQ_W_QH_DSP, 885 OPC_MAQ_S_W_QHRR = (0x17 << 6) | OPC_DPAQ_W_QH_DSP, 886 OPC_MAQ_SA_W_QHRR = (0x13 << 6) | OPC_DPAQ_W_QH_DSP, 887 OPC_MULSAQ_S_L_PW = (0x0E << 6) | OPC_DPAQ_W_QH_DSP, 888 OPC_MULSAQ_S_W_QH = (0x06 << 6) | OPC_DPAQ_W_QH_DSP, 889 }; 890 891 #define MASK_SHLL_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) 892 enum { 893 /* MIPS DSP GPR-Based Shift Sub-class */ 894 OPC_SHLL_PW = (0x10 << 6) | OPC_SHLL_OB_DSP, 895 OPC_SHLL_S_PW = (0x14 << 6) | OPC_SHLL_OB_DSP, 896 OPC_SHLLV_OB = (0x02 << 6) | OPC_SHLL_OB_DSP, 897 OPC_SHLLV_PW = (0x12 << 6) | OPC_SHLL_OB_DSP, 898 OPC_SHLLV_S_PW = (0x16 << 6) | OPC_SHLL_OB_DSP, 899 OPC_SHLLV_QH = (0x0A << 6) | OPC_SHLL_OB_DSP, 900 OPC_SHLLV_S_QH = (0x0E << 6) | OPC_SHLL_OB_DSP, 901 OPC_SHRA_PW = (0x11 << 6) | OPC_SHLL_OB_DSP, 902 OPC_SHRA_R_PW = (0x15 << 6) | OPC_SHLL_OB_DSP, 903 OPC_SHRAV_OB = (0x06 << 6) | OPC_SHLL_OB_DSP, 904 OPC_SHRAV_R_OB = (0x07 << 6) | OPC_SHLL_OB_DSP, 905 OPC_SHRAV_PW = (0x13 << 6) | OPC_SHLL_OB_DSP, 906 OPC_SHRAV_R_PW = (0x17 << 6) | OPC_SHLL_OB_DSP, 907 OPC_SHRAV_QH = (0x0B << 6) | OPC_SHLL_OB_DSP, 908 OPC_SHRAV_R_QH = (0x0F << 6) | OPC_SHLL_OB_DSP, 909 OPC_SHRLV_OB = (0x03 << 6) | OPC_SHLL_OB_DSP, 910 OPC_SHRLV_QH = (0x1B << 6) | OPC_SHLL_OB_DSP, 911 OPC_SHLL_OB = (0x00 << 6) | OPC_SHLL_OB_DSP, 912 OPC_SHLL_QH = (0x08 << 6) | OPC_SHLL_OB_DSP, 913 OPC_SHLL_S_QH = (0x0C << 6) | OPC_SHLL_OB_DSP, 914 OPC_SHRA_OB = (0x04 << 6) | OPC_SHLL_OB_DSP, 915 OPC_SHRA_R_OB = (0x05 << 6) | OPC_SHLL_OB_DSP, 916 OPC_SHRA_QH = (0x09 << 6) | OPC_SHLL_OB_DSP, 917 OPC_SHRA_R_QH = (0x0D << 6) | OPC_SHLL_OB_DSP, 918 OPC_SHRL_OB = (0x01 << 6) | OPC_SHLL_OB_DSP, 919 OPC_SHRL_QH = (0x19 << 6) | OPC_SHLL_OB_DSP, 920 }; 921 922 /* Coprocessor 0 (rs field) */ 923 #define MASK_CP0(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21))) 924 925 enum { 926 OPC_MFC0 = (0x00 << 21) | OPC_CP0, 927 OPC_DMFC0 = (0x01 << 21) | OPC_CP0, 928 OPC_MFHC0 = (0x02 << 21) | OPC_CP0, 929 OPC_MTC0 = (0x04 << 21) | OPC_CP0, 930 OPC_DMTC0 = (0x05 << 21) | OPC_CP0, 931 OPC_MTHC0 = (0x06 << 21) | OPC_CP0, 932 OPC_MFTR = (0x08 << 21) | OPC_CP0, 933 OPC_RDPGPR = (0x0A << 21) | OPC_CP0, 934 OPC_MFMC0 = (0x0B << 21) | OPC_CP0, 935 OPC_MTTR = (0x0C << 21) | OPC_CP0, 936 OPC_WRPGPR = (0x0E << 21) | OPC_CP0, 937 OPC_C0 = (0x10 << 21) | OPC_CP0, 938 OPC_C0_1 = (0x11 << 21) | OPC_CP0, 939 OPC_C0_2 = (0x12 << 21) | OPC_CP0, 940 OPC_C0_3 = (0x13 << 21) | OPC_CP0, 941 OPC_C0_4 = (0x14 << 21) | OPC_CP0, 942 OPC_C0_5 = (0x15 << 21) | OPC_CP0, 943 OPC_C0_6 = (0x16 << 21) | OPC_CP0, 944 OPC_C0_7 = (0x17 << 21) | OPC_CP0, 945 OPC_C0_8 = (0x18 << 21) | OPC_CP0, 946 OPC_C0_9 = (0x19 << 21) | OPC_CP0, 947 OPC_C0_A = (0x1A << 21) | OPC_CP0, 948 OPC_C0_B = (0x1B << 21) | OPC_CP0, 949 OPC_C0_C = (0x1C << 21) | OPC_CP0, 950 OPC_C0_D = (0x1D << 21) | OPC_CP0, 951 OPC_C0_E = (0x1E << 21) | OPC_CP0, 952 OPC_C0_F = (0x1F << 21) | OPC_CP0, 953 }; 954 955 /* MFMC0 opcodes */ 956 #define MASK_MFMC0(op) (MASK_CP0(op) | (op & 0xFFFF)) 957 958 enum { 959 OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, 960 OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, 961 OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0, 962 OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0, 963 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0, 964 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0, 965 OPC_DVP = 0x04 | (0 << 3) | (1 << 5) | (0 << 11) | OPC_MFMC0, 966 OPC_EVP = 0x04 | (0 << 3) | (0 << 5) | (0 << 11) | OPC_MFMC0, 967 }; 968 969 /* Coprocessor 0 (with rs == C0) */ 970 #define MASK_C0(op) (MASK_CP0(op) | (op & 0x3F)) 971 972 enum { 973 OPC_TLBR = 0x01 | OPC_C0, 974 OPC_TLBWI = 0x02 | OPC_C0, 975 OPC_TLBINV = 0x03 | OPC_C0, 976 OPC_TLBINVF = 0x04 | OPC_C0, 977 OPC_TLBWR = 0x06 | OPC_C0, 978 OPC_TLBP = 0x08 | OPC_C0, 979 OPC_RFE = 0x10 | OPC_C0, 980 OPC_ERET = 0x18 | OPC_C0, 981 OPC_DERET = 0x1F | OPC_C0, 982 OPC_WAIT = 0x20 | OPC_C0, 983 }; 984 985 #define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21))) 986 987 enum { 988 OPC_MFC2 = (0x00 << 21) | OPC_CP2, 989 OPC_DMFC2 = (0x01 << 21) | OPC_CP2, 990 OPC_CFC2 = (0x02 << 21) | OPC_CP2, 991 OPC_MFHC2 = (0x03 << 21) | OPC_CP2, 992 OPC_MTC2 = (0x04 << 21) | OPC_CP2, 993 OPC_DMTC2 = (0x05 << 21) | OPC_CP2, 994 OPC_CTC2 = (0x06 << 21) | OPC_CP2, 995 OPC_MTHC2 = (0x07 << 21) | OPC_CP2, 996 OPC_BC2 = (0x08 << 21) | OPC_CP2, 997 OPC_BC2EQZ = (0x09 << 21) | OPC_CP2, 998 OPC_BC2NEZ = (0x0D << 21) | OPC_CP2, 999 }; 1000 1001 #define MASK_LMMI(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F)) 1002 1003 enum { 1004 OPC_PADDSH = (24 << 21) | (0x00) | OPC_CP2, 1005 OPC_PADDUSH = (25 << 21) | (0x00) | OPC_CP2, 1006 OPC_PADDH = (26 << 21) | (0x00) | OPC_CP2, 1007 OPC_PADDW = (27 << 21) | (0x00) | OPC_CP2, 1008 OPC_PADDSB = (28 << 21) | (0x00) | OPC_CP2, 1009 OPC_PADDUSB = (29 << 21) | (0x00) | OPC_CP2, 1010 OPC_PADDB = (30 << 21) | (0x00) | OPC_CP2, 1011 OPC_PADDD = (31 << 21) | (0x00) | OPC_CP2, 1012 1013 OPC_PSUBSH = (24 << 21) | (0x01) | OPC_CP2, 1014 OPC_PSUBUSH = (25 << 21) | (0x01) | OPC_CP2, 1015 OPC_PSUBH = (26 << 21) | (0x01) | OPC_CP2, 1016 OPC_PSUBW = (27 << 21) | (0x01) | OPC_CP2, 1017 OPC_PSUBSB = (28 << 21) | (0x01) | OPC_CP2, 1018 OPC_PSUBUSB = (29 << 21) | (0x01) | OPC_CP2, 1019 OPC_PSUBB = (30 << 21) | (0x01) | OPC_CP2, 1020 OPC_PSUBD = (31 << 21) | (0x01) | OPC_CP2, 1021 1022 OPC_PSHUFH = (24 << 21) | (0x02) | OPC_CP2, 1023 OPC_PACKSSWH = (25 << 21) | (0x02) | OPC_CP2, 1024 OPC_PACKSSHB = (26 << 21) | (0x02) | OPC_CP2, 1025 OPC_PACKUSHB = (27 << 21) | (0x02) | OPC_CP2, 1026 OPC_XOR_CP2 = (28 << 21) | (0x02) | OPC_CP2, 1027 OPC_NOR_CP2 = (29 << 21) | (0x02) | OPC_CP2, 1028 OPC_AND_CP2 = (30 << 21) | (0x02) | OPC_CP2, 1029 OPC_PANDN = (31 << 21) | (0x02) | OPC_CP2, 1030 1031 OPC_PUNPCKLHW = (24 << 21) | (0x03) | OPC_CP2, 1032 OPC_PUNPCKHHW = (25 << 21) | (0x03) | OPC_CP2, 1033 OPC_PUNPCKLBH = (26 << 21) | (0x03) | OPC_CP2, 1034 OPC_PUNPCKHBH = (27 << 21) | (0x03) | OPC_CP2, 1035 OPC_PINSRH_0 = (28 << 21) | (0x03) | OPC_CP2, 1036 OPC_PINSRH_1 = (29 << 21) | (0x03) | OPC_CP2, 1037 OPC_PINSRH_2 = (30 << 21) | (0x03) | OPC_CP2, 1038 OPC_PINSRH_3 = (31 << 21) | (0x03) | OPC_CP2, 1039 1040 OPC_PAVGH = (24 << 21) | (0x08) | OPC_CP2, 1041 OPC_PAVGB = (25 << 21) | (0x08) | OPC_CP2, 1042 OPC_PMAXSH = (26 << 21) | (0x08) | OPC_CP2, 1043 OPC_PMINSH = (27 << 21) | (0x08) | OPC_CP2, 1044 OPC_PMAXUB = (28 << 21) | (0x08) | OPC_CP2, 1045 OPC_PMINUB = (29 << 21) | (0x08) | OPC_CP2, 1046 1047 OPC_PCMPEQW = (24 << 21) | (0x09) | OPC_CP2, 1048 OPC_PCMPGTW = (25 << 21) | (0x09) | OPC_CP2, 1049 OPC_PCMPEQH = (26 << 21) | (0x09) | OPC_CP2, 1050 OPC_PCMPGTH = (27 << 21) | (0x09) | OPC_CP2, 1051 OPC_PCMPEQB = (28 << 21) | (0x09) | OPC_CP2, 1052 OPC_PCMPGTB = (29 << 21) | (0x09) | OPC_CP2, 1053 1054 OPC_PSLLW = (24 << 21) | (0x0A) | OPC_CP2, 1055 OPC_PSLLH = (25 << 21) | (0x0A) | OPC_CP2, 1056 OPC_PMULLH = (26 << 21) | (0x0A) | OPC_CP2, 1057 OPC_PMULHH = (27 << 21) | (0x0A) | OPC_CP2, 1058 OPC_PMULUW = (28 << 21) | (0x0A) | OPC_CP2, 1059 OPC_PMULHUH = (29 << 21) | (0x0A) | OPC_CP2, 1060 1061 OPC_PSRLW = (24 << 21) | (0x0B) | OPC_CP2, 1062 OPC_PSRLH = (25 << 21) | (0x0B) | OPC_CP2, 1063 OPC_PSRAW = (26 << 21) | (0x0B) | OPC_CP2, 1064 OPC_PSRAH = (27 << 21) | (0x0B) | OPC_CP2, 1065 OPC_PUNPCKLWD = (28 << 21) | (0x0B) | OPC_CP2, 1066 OPC_PUNPCKHWD = (29 << 21) | (0x0B) | OPC_CP2, 1067 1068 OPC_ADDU_CP2 = (24 << 21) | (0x0C) | OPC_CP2, 1069 OPC_OR_CP2 = (25 << 21) | (0x0C) | OPC_CP2, 1070 OPC_ADD_CP2 = (26 << 21) | (0x0C) | OPC_CP2, 1071 OPC_DADD_CP2 = (27 << 21) | (0x0C) | OPC_CP2, 1072 OPC_SEQU_CP2 = (28 << 21) | (0x0C) | OPC_CP2, 1073 OPC_SEQ_CP2 = (29 << 21) | (0x0C) | OPC_CP2, 1074 1075 OPC_SUBU_CP2 = (24 << 21) | (0x0D) | OPC_CP2, 1076 OPC_PASUBUB = (25 << 21) | (0x0D) | OPC_CP2, 1077 OPC_SUB_CP2 = (26 << 21) | (0x0D) | OPC_CP2, 1078 OPC_DSUB_CP2 = (27 << 21) | (0x0D) | OPC_CP2, 1079 OPC_SLTU_CP2 = (28 << 21) | (0x0D) | OPC_CP2, 1080 OPC_SLT_CP2 = (29 << 21) | (0x0D) | OPC_CP2, 1081 1082 OPC_SLL_CP2 = (24 << 21) | (0x0E) | OPC_CP2, 1083 OPC_DSLL_CP2 = (25 << 21) | (0x0E) | OPC_CP2, 1084 OPC_PEXTRH = (26 << 21) | (0x0E) | OPC_CP2, 1085 OPC_PMADDHW = (27 << 21) | (0x0E) | OPC_CP2, 1086 OPC_SLEU_CP2 = (28 << 21) | (0x0E) | OPC_CP2, 1087 OPC_SLE_CP2 = (29 << 21) | (0x0E) | OPC_CP2, 1088 1089 OPC_SRL_CP2 = (24 << 21) | (0x0F) | OPC_CP2, 1090 OPC_DSRL_CP2 = (25 << 21) | (0x0F) | OPC_CP2, 1091 OPC_SRA_CP2 = (26 << 21) | (0x0F) | OPC_CP2, 1092 OPC_DSRA_CP2 = (27 << 21) | (0x0F) | OPC_CP2, 1093 OPC_BIADD = (28 << 21) | (0x0F) | OPC_CP2, 1094 OPC_PMOVMSKB = (29 << 21) | (0x0F) | OPC_CP2, 1095 }; 1096 1097 1098 #define MASK_CP3(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 1099 1100 enum { 1101 OPC_LWXC1 = 0x00 | OPC_CP3, 1102 OPC_LDXC1 = 0x01 | OPC_CP3, 1103 OPC_LUXC1 = 0x05 | OPC_CP3, 1104 OPC_SWXC1 = 0x08 | OPC_CP3, 1105 OPC_SDXC1 = 0x09 | OPC_CP3, 1106 OPC_SUXC1 = 0x0D | OPC_CP3, 1107 OPC_PREFX = 0x0F | OPC_CP3, 1108 OPC_ALNV_PS = 0x1E | OPC_CP3, 1109 OPC_MADD_S = 0x20 | OPC_CP3, 1110 OPC_MADD_D = 0x21 | OPC_CP3, 1111 OPC_MADD_PS = 0x26 | OPC_CP3, 1112 OPC_MSUB_S = 0x28 | OPC_CP3, 1113 OPC_MSUB_D = 0x29 | OPC_CP3, 1114 OPC_MSUB_PS = 0x2E | OPC_CP3, 1115 OPC_NMADD_S = 0x30 | OPC_CP3, 1116 OPC_NMADD_D = 0x31 | OPC_CP3, 1117 OPC_NMADD_PS = 0x36 | OPC_CP3, 1118 OPC_NMSUB_S = 0x38 | OPC_CP3, 1119 OPC_NMSUB_D = 0x39 | OPC_CP3, 1120 OPC_NMSUB_PS = 0x3E | OPC_CP3, 1121 }; 1122 1123 /* 1124 * MMI (MultiMedia Instruction) encodings 1125 * ====================================== 1126 * 1127 * MMI instructions encoding table keys: 1128 * 1129 * * This code is reserved for future use. An attempt to execute it 1130 * causes a Reserved Instruction exception. 1131 * % This code indicates an instruction class. The instruction word 1132 * must be further decoded by examining additional tables that show 1133 * the values for other instruction fields. 1134 * # This code is reserved for the unsupported instructions DMULT, 1135 * DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt 1136 * to execute it causes a Reserved Instruction exception. 1137 * 1138 * MMI instructions encoded by opcode field (MMI, LQ, SQ): 1139 * 1140 * 31 26 0 1141 * +--------+----------------------------------------+ 1142 * | opcode | | 1143 * +--------+----------------------------------------+ 1144 * 1145 * opcode bits 28..26 1146 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 1147 * 31..29 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 1148 * -------+-------+-------+-------+-------+-------+-------+-------+------- 1149 * 0 000 |SPECIAL| REGIMM| J | JAL | BEQ | BNE | BLEZ | BGTZ 1150 * 1 001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI 1151 * 2 010 | COP0 | COP1 | * | * | BEQL | BNEL | BLEZL | BGTZL 1152 * 3 011 | DADDI | DADDIU| LDL | LDR | MMI% | * | LQ | SQ 1153 * 4 100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU 1154 * 5 101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE 1155 * 6 110 | # | LWC1 | # | PREF | # | LDC1 | # | LD 1156 * 7 111 | # | SWC1 | # | * | # | SDC1 | # | SD 1157 */ 1158 1159 enum { 1160 MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */ 1161 MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */ 1162 }; 1163 1164 /* 1165 * MMI instructions with opcode field = MMI: 1166 * 1167 * 31 26 5 0 1168 * +--------+-------------------------------+--------+ 1169 * | MMI | |function| 1170 * +--------+-------------------------------+--------+ 1171 * 1172 * function bits 2..0 1173 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 1174 * 5..3 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 1175 * -------+-------+-------+-------+-------+-------+-------+-------+------- 1176 * 0 000 | MADD | MADDU | * | * | PLZCW | * | * | * 1177 * 1 001 | MMI0% | MMI2% | * | * | * | * | * | * 1178 * 2 010 | MFHI1 | MTHI1 | MFLO1 | MTLO1 | * | * | * | * 1179 * 3 011 | MULT1 | MULTU1| DIV1 | DIVU1 | * | * | * | * 1180 * 4 100 | MADD1 | MADDU1| * | * | * | * | * | * 1181 * 5 101 | MMI1% | MMI3% | * | * | * | * | * | * 1182 * 6 110 | PMFHL | PMTHL | * | * | PSLLH | * | PSRLH | PSRAH 1183 * 7 111 | * | * | * | * | PSLLW | * | PSRLW | PSRAW 1184 */ 1185 1186 #define MASK_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F)) 1187 enum { 1188 MMI_OPC_MADD = 0x00 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADD */ 1189 MMI_OPC_MADDU = 0x01 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADDU */ 1190 MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */ 1191 MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */ 1192 MMI_OPC_DIV1 = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV */ 1193 MMI_OPC_DIVU1 = 0x1B | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIVU */ 1194 MMI_OPC_MADD1 = 0x20 | MMI_OPC_CLASS_MMI, 1195 MMI_OPC_MADDU1 = 0x21 | MMI_OPC_CLASS_MMI, 1196 }; 1197 1198 /* global register indices */ 1199 TCGv cpu_gpr[32], cpu_PC; 1200 /* 1201 * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gpr[]) 1202 * and the upper halves in cpu_gpr_hi[]. 1203 */ 1204 TCGv_i64 cpu_gpr_hi[32]; 1205 TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; 1206 static TCGv cpu_dspctrl, btarget; 1207 TCGv bcond; 1208 static TCGv cpu_lladdr, cpu_llval; 1209 static TCGv_i32 hflags; 1210 TCGv_i32 fpu_fcr0, fpu_fcr31; 1211 TCGv_i64 fpu_f64[32]; 1212 1213 static const char regnames_HI[][4] = { 1214 "HI0", "HI1", "HI2", "HI3", 1215 }; 1216 1217 static const char regnames_LO[][4] = { 1218 "LO0", "LO1", "LO2", "LO3", 1219 }; 1220 1221 /* General purpose registers moves. */ 1222 void gen_load_gpr(TCGv t, int reg) 1223 { 1224 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr)); 1225 if (reg == 0) { 1226 tcg_gen_movi_tl(t, 0); 1227 } else { 1228 tcg_gen_mov_tl(t, cpu_gpr[reg]); 1229 } 1230 } 1231 1232 void gen_store_gpr(TCGv t, int reg) 1233 { 1234 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr)); 1235 if (reg != 0) { 1236 tcg_gen_mov_tl(cpu_gpr[reg], t); 1237 } 1238 } 1239 1240 #if defined(TARGET_MIPS64) 1241 void gen_load_gpr_hi(TCGv_i64 t, int reg) 1242 { 1243 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi)); 1244 if (reg == 0) { 1245 tcg_gen_movi_i64(t, 0); 1246 } else { 1247 tcg_gen_mov_i64(t, cpu_gpr_hi[reg]); 1248 } 1249 } 1250 1251 void gen_store_gpr_hi(TCGv_i64 t, int reg) 1252 { 1253 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi)); 1254 if (reg != 0) { 1255 tcg_gen_mov_i64(cpu_gpr_hi[reg], t); 1256 } 1257 } 1258 #endif /* TARGET_MIPS64 */ 1259 1260 /* Moves to/from shadow registers. */ 1261 static inline void gen_load_srsgpr(int from, int to) 1262 { 1263 TCGv t0 = tcg_temp_new(); 1264 1265 if (from == 0) { 1266 tcg_gen_movi_tl(t0, 0); 1267 } else { 1268 TCGv_i32 t2 = tcg_temp_new_i32(); 1269 TCGv_ptr addr = tcg_temp_new_ptr(); 1270 1271 tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl)); 1272 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); 1273 tcg_gen_andi_i32(t2, t2, 0xf); 1274 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); 1275 tcg_gen_ext_i32_ptr(addr, t2); 1276 tcg_gen_add_ptr(addr, tcg_env, addr); 1277 1278 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from); 1279 } 1280 gen_store_gpr(t0, to); 1281 } 1282 1283 static inline void gen_store_srsgpr(int from, int to) 1284 { 1285 if (to != 0) { 1286 TCGv t0 = tcg_temp_new(); 1287 TCGv_i32 t2 = tcg_temp_new_i32(); 1288 TCGv_ptr addr = tcg_temp_new_ptr(); 1289 1290 gen_load_gpr(t0, from); 1291 tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl)); 1292 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); 1293 tcg_gen_andi_i32(t2, t2, 0xf); 1294 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); 1295 tcg_gen_ext_i32_ptr(addr, t2); 1296 tcg_gen_add_ptr(addr, tcg_env, addr); 1297 1298 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to); 1299 } 1300 } 1301 1302 /* Tests */ 1303 static inline void gen_save_pc(target_ulong pc) 1304 { 1305 tcg_gen_movi_tl(cpu_PC, pc); 1306 } 1307 1308 static inline void save_cpu_state(DisasContext *ctx, int do_save_pc) 1309 { 1310 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags); 1311 if (do_save_pc && ctx->base.pc_next != ctx->saved_pc) { 1312 gen_save_pc(ctx->base.pc_next); 1313 ctx->saved_pc = ctx->base.pc_next; 1314 } 1315 if (ctx->hflags != ctx->saved_hflags) { 1316 tcg_gen_movi_i32(hflags, ctx->hflags); 1317 ctx->saved_hflags = ctx->hflags; 1318 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { 1319 case MIPS_HFLAG_BR: 1320 break; 1321 case MIPS_HFLAG_BC: 1322 case MIPS_HFLAG_BL: 1323 case MIPS_HFLAG_B: 1324 tcg_gen_movi_tl(btarget, ctx->btarget); 1325 break; 1326 } 1327 } 1328 } 1329 1330 static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx) 1331 { 1332 ctx->saved_hflags = ctx->hflags; 1333 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { 1334 case MIPS_HFLAG_BR: 1335 break; 1336 case MIPS_HFLAG_BC: 1337 case MIPS_HFLAG_BL: 1338 case MIPS_HFLAG_B: 1339 ctx->btarget = env->btarget; 1340 break; 1341 } 1342 } 1343 1344 void generate_exception_err(DisasContext *ctx, int excp, int err) 1345 { 1346 save_cpu_state(ctx, 1); 1347 gen_helper_raise_exception_err(tcg_env, tcg_constant_i32(excp), 1348 tcg_constant_i32(err)); 1349 ctx->base.is_jmp = DISAS_NORETURN; 1350 } 1351 1352 void generate_exception(DisasContext *ctx, int excp) 1353 { 1354 gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); 1355 } 1356 1357 void generate_exception_end(DisasContext *ctx, int excp) 1358 { 1359 generate_exception_err(ctx, excp, 0); 1360 } 1361 1362 void generate_exception_break(DisasContext *ctx, int code) 1363 { 1364 #ifdef CONFIG_USER_ONLY 1365 /* Pass the break code along to cpu_loop. */ 1366 tcg_gen_st_i32(tcg_constant_i32(code), tcg_env, 1367 offsetof(CPUMIPSState, error_code)); 1368 #endif 1369 generate_exception_end(ctx, EXCP_BREAK); 1370 } 1371 1372 void gen_reserved_instruction(DisasContext *ctx) 1373 { 1374 generate_exception_end(ctx, EXCP_RI); 1375 } 1376 1377 /* Floating point register moves. */ 1378 void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) 1379 { 1380 if (ctx->hflags & MIPS_HFLAG_FRE) { 1381 generate_exception(ctx, EXCP_RI); 1382 } 1383 tcg_gen_extrl_i64_i32(t, fpu_f64[reg]); 1384 } 1385 1386 void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) 1387 { 1388 TCGv_i64 t64; 1389 if (ctx->hflags & MIPS_HFLAG_FRE) { 1390 generate_exception(ctx, EXCP_RI); 1391 } 1392 t64 = tcg_temp_new_i64(); 1393 tcg_gen_extu_i32_i64(t64, t); 1394 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32); 1395 } 1396 1397 static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) 1398 { 1399 if (ctx->hflags & MIPS_HFLAG_F64) { 1400 tcg_gen_extrh_i64_i32(t, fpu_f64[reg]); 1401 } else { 1402 gen_load_fpr32(ctx, t, reg | 1); 1403 } 1404 } 1405 1406 static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) 1407 { 1408 if (ctx->hflags & MIPS_HFLAG_F64) { 1409 TCGv_i64 t64 = tcg_temp_new_i64(); 1410 tcg_gen_extu_i32_i64(t64, t); 1411 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32); 1412 } else { 1413 gen_store_fpr32(ctx, t, reg | 1); 1414 } 1415 } 1416 1417 void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) 1418 { 1419 if (ctx->hflags & MIPS_HFLAG_F64) { 1420 tcg_gen_mov_i64(t, fpu_f64[reg]); 1421 } else { 1422 tcg_gen_concat32_i64(t, fpu_f64[reg & ~1], fpu_f64[reg | 1]); 1423 } 1424 } 1425 1426 void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) 1427 { 1428 if (ctx->hflags & MIPS_HFLAG_F64) { 1429 tcg_gen_mov_i64(fpu_f64[reg], t); 1430 } else { 1431 TCGv_i64 t0; 1432 tcg_gen_deposit_i64(fpu_f64[reg & ~1], fpu_f64[reg & ~1], t, 0, 32); 1433 t0 = tcg_temp_new_i64(); 1434 tcg_gen_shri_i64(t0, t, 32); 1435 tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32); 1436 } 1437 } 1438 1439 int get_fp_bit(int cc) 1440 { 1441 if (cc) { 1442 return 24 + cc; 1443 } else { 1444 return 23; 1445 } 1446 } 1447 1448 /* Addresses computation */ 1449 void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1) 1450 { 1451 tcg_gen_add_tl(ret, arg0, arg1); 1452 1453 #if defined(TARGET_MIPS64) 1454 if (ctx->hflags & MIPS_HFLAG_AWRAP) { 1455 tcg_gen_ext32s_i64(ret, ret); 1456 } 1457 #endif 1458 } 1459 1460 static inline void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base, 1461 target_long ofs) 1462 { 1463 tcg_gen_addi_tl(ret, base, ofs); 1464 1465 #if defined(TARGET_MIPS64) 1466 if (ctx->hflags & MIPS_HFLAG_AWRAP) { 1467 tcg_gen_ext32s_i64(ret, ret); 1468 } 1469 #endif 1470 } 1471 1472 /* Addresses computation (translation time) */ 1473 static target_long addr_add(DisasContext *ctx, target_long base, 1474 target_long offset) 1475 { 1476 target_long sum = base + offset; 1477 1478 #if defined(TARGET_MIPS64) 1479 if (ctx->hflags & MIPS_HFLAG_AWRAP) { 1480 sum = (int32_t)sum; 1481 } 1482 #endif 1483 return sum; 1484 } 1485 1486 /* Sign-extract the low 32-bits to a target_long. */ 1487 void gen_move_low32(TCGv ret, TCGv_i64 arg) 1488 { 1489 #if defined(TARGET_MIPS64) 1490 tcg_gen_ext32s_i64(ret, arg); 1491 #else 1492 tcg_gen_extrl_i64_i32(ret, arg); 1493 #endif 1494 } 1495 1496 /* Sign-extract the high 32-bits to a target_long. */ 1497 void gen_move_high32(TCGv ret, TCGv_i64 arg) 1498 { 1499 #if defined(TARGET_MIPS64) 1500 tcg_gen_sari_i64(ret, arg, 32); 1501 #else 1502 tcg_gen_extrh_i64_i32(ret, arg); 1503 #endif 1504 } 1505 1506 bool check_cp0_enabled(DisasContext *ctx) 1507 { 1508 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { 1509 generate_exception_end(ctx, EXCP_CpU); 1510 return false; 1511 } 1512 return true; 1513 } 1514 1515 void check_cp1_enabled(DisasContext *ctx) 1516 { 1517 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { 1518 generate_exception_err(ctx, EXCP_CpU, 1); 1519 } 1520 } 1521 1522 /* 1523 * Verify that the processor is running with COP1X instructions enabled. 1524 * This is associated with the nabla symbol in the MIPS32 and MIPS64 1525 * opcode tables. 1526 */ 1527 void check_cop1x(DisasContext *ctx) 1528 { 1529 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { 1530 gen_reserved_instruction(ctx); 1531 } 1532 } 1533 1534 /* 1535 * Verify that the processor is running with 64-bit floating-point 1536 * operations enabled. 1537 */ 1538 void check_cp1_64bitmode(DisasContext *ctx) 1539 { 1540 if (unlikely(~ctx->hflags & MIPS_HFLAG_F64)) { 1541 gen_reserved_instruction(ctx); 1542 } 1543 } 1544 1545 /* 1546 * Verify if floating point register is valid; an operation is not defined 1547 * if bit 0 of any register specification is set and the FR bit in the 1548 * Status register equals zero, since the register numbers specify an 1549 * even-odd pair of adjacent coprocessor general registers. When the FR bit 1550 * in the Status register equals one, both even and odd register numbers 1551 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers. 1552 * 1553 * Multiple 64 bit wide registers can be checked by calling 1554 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN); 1555 */ 1556 void check_cp1_registers(DisasContext *ctx, int regs) 1557 { 1558 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { 1559 gen_reserved_instruction(ctx); 1560 } 1561 } 1562 1563 /* 1564 * Verify that the processor is running with DSP instructions enabled. 1565 * This is enabled by CP0 Status register MX(24) bit. 1566 */ 1567 static inline void check_dsp(DisasContext *ctx) 1568 { 1569 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { 1570 if (ctx->insn_flags & ASE_DSP) { 1571 generate_exception_end(ctx, EXCP_DSPDIS); 1572 } else { 1573 gen_reserved_instruction(ctx); 1574 } 1575 } 1576 } 1577 1578 static inline void check_dsp_r2(DisasContext *ctx) 1579 { 1580 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) { 1581 if (ctx->insn_flags & ASE_DSP) { 1582 generate_exception_end(ctx, EXCP_DSPDIS); 1583 } else { 1584 gen_reserved_instruction(ctx); 1585 } 1586 } 1587 } 1588 1589 static inline void check_dsp_r3(DisasContext *ctx) 1590 { 1591 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) { 1592 if (ctx->insn_flags & ASE_DSP) { 1593 generate_exception_end(ctx, EXCP_DSPDIS); 1594 } else { 1595 gen_reserved_instruction(ctx); 1596 } 1597 } 1598 } 1599 1600 /* 1601 * This code generates a "reserved instruction" exception if the 1602 * CPU does not support the instruction set corresponding to flags. 1603 */ 1604 void check_insn(DisasContext *ctx, uint64_t flags) 1605 { 1606 if (unlikely(!(ctx->insn_flags & flags))) { 1607 gen_reserved_instruction(ctx); 1608 } 1609 } 1610 1611 /* 1612 * This code generates a "reserved instruction" exception if the 1613 * CPU has corresponding flag set which indicates that the instruction 1614 * has been removed. 1615 */ 1616 static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags) 1617 { 1618 if (unlikely(ctx->insn_flags & flags)) { 1619 gen_reserved_instruction(ctx); 1620 } 1621 } 1622 1623 /* 1624 * The Linux kernel traps certain reserved instruction exceptions to 1625 * emulate the corresponding instructions. QEMU is the kernel in user 1626 * mode, so those traps are emulated by accepting the instructions. 1627 * 1628 * A reserved instruction exception is generated for flagged CPUs if 1629 * QEMU runs in system mode. 1630 */ 1631 static inline void check_insn_opc_user_only(DisasContext *ctx, uint64_t flags) 1632 { 1633 #ifndef CONFIG_USER_ONLY 1634 check_insn_opc_removed(ctx, flags); 1635 #endif 1636 } 1637 1638 /* 1639 * This code generates a "reserved instruction" exception if the 1640 * CPU does not support 64-bit paired-single (PS) floating point data type. 1641 */ 1642 static inline void check_ps(DisasContext *ctx) 1643 { 1644 if (unlikely(!ctx->ps)) { 1645 generate_exception(ctx, EXCP_RI); 1646 } 1647 check_cp1_64bitmode(ctx); 1648 } 1649 1650 /* 1651 * This code generates a "reserved instruction" exception if cpu is not 1652 * 64-bit or 64-bit instructions are not enabled. 1653 */ 1654 void check_mips_64(DisasContext *ctx) 1655 { 1656 if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) { 1657 gen_reserved_instruction(ctx); 1658 } 1659 } 1660 1661 #ifndef CONFIG_USER_ONLY 1662 static inline void check_mvh(DisasContext *ctx) 1663 { 1664 if (unlikely(!ctx->mvh)) { 1665 generate_exception(ctx, EXCP_RI); 1666 } 1667 } 1668 #endif 1669 1670 /* 1671 * This code generates a "reserved instruction" exception if the 1672 * Config5 XNP bit is set. 1673 */ 1674 static inline void check_xnp(DisasContext *ctx) 1675 { 1676 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) { 1677 gen_reserved_instruction(ctx); 1678 } 1679 } 1680 1681 #ifndef CONFIG_USER_ONLY 1682 /* 1683 * This code generates a "reserved instruction" exception if the 1684 * Config3 PW bit is NOT set. 1685 */ 1686 static inline void check_pw(DisasContext *ctx) 1687 { 1688 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) { 1689 gen_reserved_instruction(ctx); 1690 } 1691 } 1692 #endif 1693 1694 /* 1695 * This code generates a "reserved instruction" exception if the 1696 * Config3 MT bit is NOT set. 1697 */ 1698 static inline void check_mt(DisasContext *ctx) 1699 { 1700 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { 1701 gen_reserved_instruction(ctx); 1702 } 1703 } 1704 1705 #ifndef CONFIG_USER_ONLY 1706 /* 1707 * This code generates a "coprocessor unusable" exception if CP0 is not 1708 * available, and, if that is not the case, generates a "reserved instruction" 1709 * exception if the Config5 MT bit is NOT set. This is needed for availability 1710 * control of some of MT ASE instructions. 1711 */ 1712 static inline void check_cp0_mt(DisasContext *ctx) 1713 { 1714 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { 1715 generate_exception_end(ctx, EXCP_CpU); 1716 } else { 1717 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { 1718 gen_reserved_instruction(ctx); 1719 } 1720 } 1721 } 1722 #endif 1723 1724 /* 1725 * This code generates a "reserved instruction" exception if the 1726 * Config5 NMS bit is set. 1727 */ 1728 static inline void check_nms(DisasContext *ctx) 1729 { 1730 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) { 1731 gen_reserved_instruction(ctx); 1732 } 1733 } 1734 1735 /* 1736 * This code generates a "reserved instruction" exception if the 1737 * Config5 NMS bit is set, and Config1 DL, Config1 IL, Config2 SL, 1738 * Config2 TL, and Config5 L2C are unset. 1739 */ 1740 static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx) 1741 { 1742 if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) && 1743 !(ctx->CP0_Config1 & (1 << CP0C1_DL)) && 1744 !(ctx->CP0_Config1 & (1 << CP0C1_IL)) && 1745 !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && 1746 !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && 1747 !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) { 1748 gen_reserved_instruction(ctx); 1749 } 1750 } 1751 1752 /* 1753 * This code generates a "reserved instruction" exception if the 1754 * Config5 EVA bit is NOT set. 1755 */ 1756 static inline void check_eva(DisasContext *ctx) 1757 { 1758 if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) { 1759 gen_reserved_instruction(ctx); 1760 } 1761 } 1762 1763 1764 /* 1765 * Define small wrappers for gen_load_fpr* so that we have a uniform 1766 * calling interface for 32 and 64-bit FPRs. No sense in changing 1767 * all callers for gen_load_fpr32 when we need the CTX parameter for 1768 * this one use. 1769 */ 1770 #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y) 1771 #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y) 1772 #define FOP_CONDS(type, abs, fmt, ifmt, bits) \ 1773 static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \ 1774 int ft, int fs, int cc) \ 1775 { \ 1776 TCGv_i##bits fp0 = tcg_temp_new_i##bits(); \ 1777 TCGv_i##bits fp1 = tcg_temp_new_i##bits(); \ 1778 switch (ifmt) { \ 1779 case FMT_PS: \ 1780 check_ps(ctx); \ 1781 break; \ 1782 case FMT_D: \ 1783 if (abs) { \ 1784 check_cop1x(ctx); \ 1785 } \ 1786 check_cp1_registers(ctx, fs | ft); \ 1787 break; \ 1788 case FMT_S: \ 1789 if (abs) { \ 1790 check_cop1x(ctx); \ 1791 } \ 1792 break; \ 1793 } \ 1794 gen_ldcmp_fpr##bits(ctx, fp0, fs); \ 1795 gen_ldcmp_fpr##bits(ctx, fp1, ft); \ 1796 switch (n) { \ 1797 case 0: \ 1798 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); \ 1799 break; \ 1800 case 1: \ 1801 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); \ 1802 break; \ 1803 case 2: \ 1804 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); \ 1805 break; \ 1806 case 3: \ 1807 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); \ 1808 break; \ 1809 case 4: \ 1810 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); \ 1811 break; \ 1812 case 5: \ 1813 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); \ 1814 break; \ 1815 case 6: \ 1816 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); \ 1817 break; \ 1818 case 7: \ 1819 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); \ 1820 break; \ 1821 case 8: \ 1822 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); \ 1823 break; \ 1824 case 9: \ 1825 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); \ 1826 break; \ 1827 case 10: \ 1828 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); \ 1829 break; \ 1830 case 11: \ 1831 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); \ 1832 break; \ 1833 case 12: \ 1834 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); \ 1835 break; \ 1836 case 13: \ 1837 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); \ 1838 break; \ 1839 case 14: \ 1840 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); \ 1841 break; \ 1842 case 15: \ 1843 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); \ 1844 break; \ 1845 default: \ 1846 abort(); \ 1847 } \ 1848 } 1849 1850 FOP_CONDS(, 0, d, FMT_D, 64) 1851 FOP_CONDS(abs, 1, d, FMT_D, 64) 1852 FOP_CONDS(, 0, s, FMT_S, 32) 1853 FOP_CONDS(abs, 1, s, FMT_S, 32) 1854 FOP_CONDS(, 0, ps, FMT_PS, 64) 1855 FOP_CONDS(abs, 1, ps, FMT_PS, 64) 1856 #undef FOP_CONDS 1857 1858 #define FOP_CONDNS(fmt, ifmt, bits, STORE) \ 1859 static inline void gen_r6_cmp_ ## fmt(DisasContext *ctx, int n, \ 1860 int ft, int fs, int fd) \ 1861 { \ 1862 TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(); \ 1863 TCGv_i ## bits fp1 = tcg_temp_new_i ## bits(); \ 1864 if (ifmt == FMT_D) { \ 1865 check_cp1_registers(ctx, fs | ft | fd); \ 1866 } \ 1867 gen_ldcmp_fpr ## bits(ctx, fp0, fs); \ 1868 gen_ldcmp_fpr ## bits(ctx, fp1, ft); \ 1869 switch (n) { \ 1870 case 0: \ 1871 gen_helper_r6_cmp_ ## fmt ## _af(fp0, tcg_env, fp0, fp1); \ 1872 break; \ 1873 case 1: \ 1874 gen_helper_r6_cmp_ ## fmt ## _un(fp0, tcg_env, fp0, fp1); \ 1875 break; \ 1876 case 2: \ 1877 gen_helper_r6_cmp_ ## fmt ## _eq(fp0, tcg_env, fp0, fp1); \ 1878 break; \ 1879 case 3: \ 1880 gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, tcg_env, fp0, fp1); \ 1881 break; \ 1882 case 4: \ 1883 gen_helper_r6_cmp_ ## fmt ## _lt(fp0, tcg_env, fp0, fp1); \ 1884 break; \ 1885 case 5: \ 1886 gen_helper_r6_cmp_ ## fmt ## _ult(fp0, tcg_env, fp0, fp1); \ 1887 break; \ 1888 case 6: \ 1889 gen_helper_r6_cmp_ ## fmt ## _le(fp0, tcg_env, fp0, fp1); \ 1890 break; \ 1891 case 7: \ 1892 gen_helper_r6_cmp_ ## fmt ## _ule(fp0, tcg_env, fp0, fp1); \ 1893 break; \ 1894 case 8: \ 1895 gen_helper_r6_cmp_ ## fmt ## _saf(fp0, tcg_env, fp0, fp1); \ 1896 break; \ 1897 case 9: \ 1898 gen_helper_r6_cmp_ ## fmt ## _sun(fp0, tcg_env, fp0, fp1); \ 1899 break; \ 1900 case 10: \ 1901 gen_helper_r6_cmp_ ## fmt ## _seq(fp0, tcg_env, fp0, fp1); \ 1902 break; \ 1903 case 11: \ 1904 gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, tcg_env, fp0, fp1); \ 1905 break; \ 1906 case 12: \ 1907 gen_helper_r6_cmp_ ## fmt ## _slt(fp0, tcg_env, fp0, fp1); \ 1908 break; \ 1909 case 13: \ 1910 gen_helper_r6_cmp_ ## fmt ## _sult(fp0, tcg_env, fp0, fp1); \ 1911 break; \ 1912 case 14: \ 1913 gen_helper_r6_cmp_ ## fmt ## _sle(fp0, tcg_env, fp0, fp1); \ 1914 break; \ 1915 case 15: \ 1916 gen_helper_r6_cmp_ ## fmt ## _sule(fp0, tcg_env, fp0, fp1); \ 1917 break; \ 1918 case 17: \ 1919 gen_helper_r6_cmp_ ## fmt ## _or(fp0, tcg_env, fp0, fp1); \ 1920 break; \ 1921 case 18: \ 1922 gen_helper_r6_cmp_ ## fmt ## _une(fp0, tcg_env, fp0, fp1); \ 1923 break; \ 1924 case 19: \ 1925 gen_helper_r6_cmp_ ## fmt ## _ne(fp0, tcg_env, fp0, fp1); \ 1926 break; \ 1927 case 25: \ 1928 gen_helper_r6_cmp_ ## fmt ## _sor(fp0, tcg_env, fp0, fp1); \ 1929 break; \ 1930 case 26: \ 1931 gen_helper_r6_cmp_ ## fmt ## _sune(fp0, tcg_env, fp0, fp1); \ 1932 break; \ 1933 case 27: \ 1934 gen_helper_r6_cmp_ ## fmt ## _sne(fp0, tcg_env, fp0, fp1); \ 1935 break; \ 1936 default: \ 1937 abort(); \ 1938 } \ 1939 STORE; \ 1940 } 1941 1942 FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd)) 1943 FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd)) 1944 #undef FOP_CONDNS 1945 #undef gen_ldcmp_fpr32 1946 #undef gen_ldcmp_fpr64 1947 1948 /* load/store instructions. */ 1949 #ifdef CONFIG_USER_ONLY 1950 #define OP_LD_ATOMIC(insn, memop) \ 1951 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ 1952 DisasContext *ctx) \ 1953 { \ 1954 TCGv t0 = tcg_temp_new(); \ 1955 tcg_gen_mov_tl(t0, arg1); \ 1956 tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); \ 1957 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUMIPSState, lladdr)); \ 1958 tcg_gen_st_tl(ret, tcg_env, offsetof(CPUMIPSState, llval)); \ 1959 } 1960 #else 1961 #define OP_LD_ATOMIC(insn, fname) \ 1962 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \ 1963 DisasContext *ctx) \ 1964 { \ 1965 gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \ 1966 } 1967 #endif 1968 OP_LD_ATOMIC(ll, MO_TESL); 1969 #if defined(TARGET_MIPS64) 1970 OP_LD_ATOMIC(lld, MO_TEUQ); 1971 #endif 1972 #undef OP_LD_ATOMIC 1973 1974 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset) 1975 { 1976 if (base == 0) { 1977 tcg_gen_movi_tl(addr, offset); 1978 } else if (offset == 0) { 1979 gen_load_gpr(addr, base); 1980 } else { 1981 tcg_gen_movi_tl(addr, offset); 1982 gen_op_addr_add(ctx, addr, cpu_gpr[base], addr); 1983 } 1984 } 1985 1986 static target_ulong pc_relative_pc(DisasContext *ctx) 1987 { 1988 target_ulong pc = ctx->base.pc_next; 1989 1990 if (ctx->hflags & MIPS_HFLAG_BMASK) { 1991 int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4; 1992 1993 pc -= branch_bytes; 1994 } 1995 1996 pc &= ~(target_ulong)3; 1997 return pc; 1998 } 1999 2000 /* LWL or LDL, depending on MemOp. */ 2001 static void gen_lxl(DisasContext *ctx, TCGv reg, TCGv addr, 2002 int mem_idx, MemOp mop) 2003 { 2004 int sizem1 = memop_size(mop) - 1; 2005 TCGv t0 = tcg_temp_new(); 2006 TCGv t1 = tcg_temp_new(); 2007 2008 /* 2009 * Do a byte access to possibly trigger a page 2010 * fault with the unaligned address. 2011 */ 2012 tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB); 2013 tcg_gen_andi_tl(t1, addr, sizem1); 2014 if (!cpu_is_bigendian(ctx)) { 2015 tcg_gen_xori_tl(t1, t1, sizem1); 2016 } 2017 tcg_gen_shli_tl(t1, t1, 3); 2018 tcg_gen_andi_tl(t0, addr, ~sizem1); 2019 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mop); 2020 tcg_gen_shl_tl(t0, t0, t1); 2021 tcg_gen_shl_tl(t1, tcg_constant_tl(-1), t1); 2022 tcg_gen_andc_tl(t1, reg, t1); 2023 tcg_gen_or_tl(reg, t0, t1); 2024 } 2025 2026 /* LWR or LDR, depending on MemOp. */ 2027 static void gen_lxr(DisasContext *ctx, TCGv reg, TCGv addr, 2028 int mem_idx, MemOp mop) 2029 { 2030 int size = memop_size(mop); 2031 int sizem1 = size - 1; 2032 TCGv t0 = tcg_temp_new(); 2033 TCGv t1 = tcg_temp_new(); 2034 2035 /* 2036 * Do a byte access to possibly trigger a page 2037 * fault with the unaligned address. 2038 */ 2039 tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB); 2040 tcg_gen_andi_tl(t1, addr, sizem1); 2041 if (cpu_is_bigendian(ctx)) { 2042 tcg_gen_xori_tl(t1, t1, sizem1); 2043 } 2044 tcg_gen_shli_tl(t1, t1, 3); 2045 tcg_gen_andi_tl(t0, addr, ~sizem1); 2046 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mop); 2047 tcg_gen_shr_tl(t0, t0, t1); 2048 tcg_gen_xori_tl(t1, t1, size * 8 - 1); 2049 tcg_gen_shl_tl(t1, tcg_constant_tl(~1), t1); 2050 tcg_gen_and_tl(t1, reg, t1); 2051 tcg_gen_or_tl(reg, t0, t1); 2052 } 2053 2054 /* Load */ 2055 static void gen_ld(DisasContext *ctx, uint32_t opc, 2056 int rt, int base, int offset) 2057 { 2058 TCGv t0, t1; 2059 int mem_idx = ctx->mem_idx; 2060 2061 if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F | 2062 INSN_LOONGSON3A)) { 2063 /* 2064 * Loongson CPU uses a load to zero register for prefetch. 2065 * We emulate it as a NOP. On other CPU we must perform the 2066 * actual memory access. 2067 */ 2068 return; 2069 } 2070 2071 t0 = tcg_temp_new(); 2072 gen_base_offset_addr(ctx, t0, base, offset); 2073 2074 switch (opc) { 2075 #if defined(TARGET_MIPS64) 2076 case OPC_LWU: 2077 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL | 2078 ctx->default_tcg_memop_mask); 2079 gen_store_gpr(t0, rt); 2080 break; 2081 case OPC_LD: 2082 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ | 2083 ctx->default_tcg_memop_mask); 2084 gen_store_gpr(t0, rt); 2085 break; 2086 case OPC_LLD: 2087 case R6_OPC_LLD: 2088 op_ld_lld(t0, t0, mem_idx, ctx); 2089 gen_store_gpr(t0, rt); 2090 break; 2091 case OPC_LDL: 2092 t1 = tcg_temp_new(); 2093 gen_load_gpr(t1, rt); 2094 gen_lxl(ctx, t1, t0, mem_idx, MO_TEUQ); 2095 gen_store_gpr(t1, rt); 2096 break; 2097 case OPC_LDR: 2098 t1 = tcg_temp_new(); 2099 gen_load_gpr(t1, rt); 2100 gen_lxr(ctx, t1, t0, mem_idx, MO_TEUQ); 2101 gen_store_gpr(t1, rt); 2102 break; 2103 case OPC_LDPC: 2104 t1 = tcg_constant_tl(pc_relative_pc(ctx)); 2105 gen_op_addr_add(ctx, t0, t0, t1); 2106 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ); 2107 gen_store_gpr(t0, rt); 2108 break; 2109 #endif 2110 case OPC_LWPC: 2111 t1 = tcg_constant_tl(pc_relative_pc(ctx)); 2112 gen_op_addr_add(ctx, t0, t0, t1); 2113 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL); 2114 gen_store_gpr(t0, rt); 2115 break; 2116 case OPC_LWE: 2117 mem_idx = MIPS_HFLAG_UM; 2118 /* fall through */ 2119 case OPC_LW: 2120 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL | 2121 ctx->default_tcg_memop_mask); 2122 gen_store_gpr(t0, rt); 2123 break; 2124 case OPC_LHE: 2125 mem_idx = MIPS_HFLAG_UM; 2126 /* fall through */ 2127 case OPC_LH: 2128 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESW | 2129 ctx->default_tcg_memop_mask); 2130 gen_store_gpr(t0, rt); 2131 break; 2132 case OPC_LHUE: 2133 mem_idx = MIPS_HFLAG_UM; 2134 /* fall through */ 2135 case OPC_LHU: 2136 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUW | 2137 ctx->default_tcg_memop_mask); 2138 gen_store_gpr(t0, rt); 2139 break; 2140 case OPC_LBE: 2141 mem_idx = MIPS_HFLAG_UM; 2142 /* fall through */ 2143 case OPC_LB: 2144 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_SB); 2145 gen_store_gpr(t0, rt); 2146 break; 2147 case OPC_LBUE: 2148 mem_idx = MIPS_HFLAG_UM; 2149 /* fall through */ 2150 case OPC_LBU: 2151 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_UB); 2152 gen_store_gpr(t0, rt); 2153 break; 2154 case OPC_LWLE: 2155 mem_idx = MIPS_HFLAG_UM; 2156 /* fall through */ 2157 case OPC_LWL: 2158 t1 = tcg_temp_new(); 2159 gen_load_gpr(t1, rt); 2160 gen_lxl(ctx, t1, t0, mem_idx, MO_TEUL); 2161 tcg_gen_ext32s_tl(t1, t1); 2162 gen_store_gpr(t1, rt); 2163 break; 2164 case OPC_LWRE: 2165 mem_idx = MIPS_HFLAG_UM; 2166 /* fall through */ 2167 case OPC_LWR: 2168 t1 = tcg_temp_new(); 2169 gen_load_gpr(t1, rt); 2170 gen_lxr(ctx, t1, t0, mem_idx, MO_TEUL); 2171 tcg_gen_ext32s_tl(t1, t1); 2172 gen_store_gpr(t1, rt); 2173 break; 2174 case OPC_LLE: 2175 mem_idx = MIPS_HFLAG_UM; 2176 /* fall through */ 2177 case OPC_LL: 2178 case R6_OPC_LL: 2179 op_ld_ll(t0, t0, mem_idx, ctx); 2180 gen_store_gpr(t0, rt); 2181 break; 2182 } 2183 } 2184 2185 /* Store */ 2186 static void gen_st(DisasContext *ctx, uint32_t opc, int rt, 2187 int base, int offset) 2188 { 2189 TCGv t0 = tcg_temp_new(); 2190 TCGv t1 = tcg_temp_new(); 2191 int mem_idx = ctx->mem_idx; 2192 2193 gen_base_offset_addr(ctx, t0, base, offset); 2194 gen_load_gpr(t1, rt); 2195 switch (opc) { 2196 #if defined(TARGET_MIPS64) 2197 case OPC_SD: 2198 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUQ | 2199 ctx->default_tcg_memop_mask); 2200 break; 2201 case OPC_SDL: 2202 gen_helper_0e2i(sdl, t1, t0, mem_idx); 2203 break; 2204 case OPC_SDR: 2205 gen_helper_0e2i(sdr, t1, t0, mem_idx); 2206 break; 2207 #endif 2208 case OPC_SWE: 2209 mem_idx = MIPS_HFLAG_UM; 2210 /* fall through */ 2211 case OPC_SW: 2212 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUL | 2213 ctx->default_tcg_memop_mask); 2214 break; 2215 case OPC_SHE: 2216 mem_idx = MIPS_HFLAG_UM; 2217 /* fall through */ 2218 case OPC_SH: 2219 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUW | 2220 ctx->default_tcg_memop_mask); 2221 break; 2222 case OPC_SBE: 2223 mem_idx = MIPS_HFLAG_UM; 2224 /* fall through */ 2225 case OPC_SB: 2226 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_8); 2227 break; 2228 case OPC_SWLE: 2229 mem_idx = MIPS_HFLAG_UM; 2230 /* fall through */ 2231 case OPC_SWL: 2232 gen_helper_0e2i(swl, t1, t0, mem_idx); 2233 break; 2234 case OPC_SWRE: 2235 mem_idx = MIPS_HFLAG_UM; 2236 /* fall through */ 2237 case OPC_SWR: 2238 gen_helper_0e2i(swr, t1, t0, mem_idx); 2239 break; 2240 } 2241 } 2242 2243 2244 /* Store conditional */ 2245 static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset, 2246 MemOp tcg_mo, bool eva) 2247 { 2248 TCGv addr, t0, val; 2249 TCGLabel *l1 = gen_new_label(); 2250 TCGLabel *done = gen_new_label(); 2251 2252 t0 = tcg_temp_new(); 2253 addr = tcg_temp_new(); 2254 /* compare the address against that of the preceding LL */ 2255 gen_base_offset_addr(ctx, addr, base, offset); 2256 tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1); 2257 tcg_gen_movi_tl(t0, 0); 2258 gen_store_gpr(t0, rt); 2259 tcg_gen_br(done); 2260 2261 gen_set_label(l1); 2262 /* generate cmpxchg */ 2263 val = tcg_temp_new(); 2264 gen_load_gpr(val, rt); 2265 tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval, val, 2266 eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo); 2267 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval); 2268 gen_store_gpr(t0, rt); 2269 2270 gen_set_label(done); 2271 } 2272 2273 /* Load and store */ 2274 static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, 2275 TCGv t0) 2276 { 2277 /* 2278 * Don't do NOP if destination is zero: we must perform the actual 2279 * memory access. 2280 */ 2281 switch (opc) { 2282 case OPC_LWC1: 2283 { 2284 TCGv_i32 fp0 = tcg_temp_new_i32(); 2285 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | 2286 ctx->default_tcg_memop_mask); 2287 gen_store_fpr32(ctx, fp0, ft); 2288 } 2289 break; 2290 case OPC_SWC1: 2291 { 2292 TCGv_i32 fp0 = tcg_temp_new_i32(); 2293 gen_load_fpr32(ctx, fp0, ft); 2294 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | 2295 ctx->default_tcg_memop_mask); 2296 } 2297 break; 2298 case OPC_LDC1: 2299 { 2300 TCGv_i64 fp0 = tcg_temp_new_i64(); 2301 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | 2302 ctx->default_tcg_memop_mask); 2303 gen_store_fpr64(ctx, fp0, ft); 2304 } 2305 break; 2306 case OPC_SDC1: 2307 { 2308 TCGv_i64 fp0 = tcg_temp_new_i64(); 2309 gen_load_fpr64(ctx, fp0, ft); 2310 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | 2311 ctx->default_tcg_memop_mask); 2312 } 2313 break; 2314 default: 2315 MIPS_INVAL("flt_ldst"); 2316 gen_reserved_instruction(ctx); 2317 break; 2318 } 2319 } 2320 2321 static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt, 2322 int rs, int16_t imm) 2323 { 2324 TCGv t0 = tcg_temp_new(); 2325 2326 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { 2327 check_cp1_enabled(ctx); 2328 switch (op) { 2329 case OPC_LDC1: 2330 case OPC_SDC1: 2331 check_insn(ctx, ISA_MIPS2); 2332 /* Fallthrough */ 2333 default: 2334 gen_base_offset_addr(ctx, t0, rs, imm); 2335 gen_flt_ldst(ctx, op, rt, t0); 2336 } 2337 } else { 2338 generate_exception_err(ctx, EXCP_CpU, 1); 2339 } 2340 } 2341 2342 /* Arithmetic with immediate operand */ 2343 static void gen_arith_imm(DisasContext *ctx, uint32_t opc, 2344 int rt, int rs, int imm) 2345 { 2346 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ 2347 2348 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) { 2349 /* 2350 * If no destination, treat it as a NOP. 2351 * For addi, we must generate the overflow exception when needed. 2352 */ 2353 return; 2354 } 2355 switch (opc) { 2356 case OPC_ADDI: 2357 { 2358 TCGv t0 = tcg_temp_new(); 2359 TCGv t1 = tcg_temp_new(); 2360 TCGv t2 = tcg_temp_new(); 2361 TCGLabel *l1 = gen_new_label(); 2362 2363 gen_load_gpr(t1, rs); 2364 tcg_gen_addi_tl(t0, t1, uimm); 2365 tcg_gen_ext32s_tl(t0, t0); 2366 2367 tcg_gen_xori_tl(t1, t1, ~uimm); 2368 tcg_gen_xori_tl(t2, t0, uimm); 2369 tcg_gen_and_tl(t1, t1, t2); 2370 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2371 /* operands of same sign, result different sign */ 2372 generate_exception(ctx, EXCP_OVERFLOW); 2373 gen_set_label(l1); 2374 tcg_gen_ext32s_tl(t0, t0); 2375 gen_store_gpr(t0, rt); 2376 } 2377 break; 2378 case OPC_ADDIU: 2379 if (rs != 0) { 2380 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2381 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 2382 } else { 2383 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2384 } 2385 break; 2386 #if defined(TARGET_MIPS64) 2387 case OPC_DADDI: 2388 { 2389 TCGv t0 = tcg_temp_new(); 2390 TCGv t1 = tcg_temp_new(); 2391 TCGv t2 = tcg_temp_new(); 2392 TCGLabel *l1 = gen_new_label(); 2393 2394 gen_load_gpr(t1, rs); 2395 tcg_gen_addi_tl(t0, t1, uimm); 2396 2397 tcg_gen_xori_tl(t1, t1, ~uimm); 2398 tcg_gen_xori_tl(t2, t0, uimm); 2399 tcg_gen_and_tl(t1, t1, t2); 2400 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2401 /* operands of same sign, result different sign */ 2402 generate_exception(ctx, EXCP_OVERFLOW); 2403 gen_set_label(l1); 2404 gen_store_gpr(t0, rt); 2405 } 2406 break; 2407 case OPC_DADDIU: 2408 if (rs != 0) { 2409 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2410 } else { 2411 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2412 } 2413 break; 2414 #endif 2415 } 2416 } 2417 2418 /* Logic with immediate operand */ 2419 static void gen_logic_imm(DisasContext *ctx, uint32_t opc, 2420 int rt, int rs, int16_t imm) 2421 { 2422 target_ulong uimm; 2423 2424 if (rt == 0) { 2425 /* If no destination, treat it as a NOP. */ 2426 return; 2427 } 2428 uimm = (uint16_t)imm; 2429 switch (opc) { 2430 case OPC_ANDI: 2431 if (likely(rs != 0)) { 2432 tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2433 } else { 2434 tcg_gen_movi_tl(cpu_gpr[rt], 0); 2435 } 2436 break; 2437 case OPC_ORI: 2438 if (rs != 0) { 2439 tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2440 } else { 2441 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2442 } 2443 break; 2444 case OPC_XORI: 2445 if (likely(rs != 0)) { 2446 tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); 2447 } else { 2448 tcg_gen_movi_tl(cpu_gpr[rt], uimm); 2449 } 2450 break; 2451 case OPC_LUI: 2452 if (rs != 0 && (ctx->insn_flags & ISA_MIPS_R6)) { 2453 /* OPC_AUI */ 2454 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16); 2455 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 2456 } else { 2457 tcg_gen_movi_tl(cpu_gpr[rt], imm << 16); 2458 } 2459 break; 2460 2461 default: 2462 break; 2463 } 2464 } 2465 2466 /* Set on less than with immediate operand */ 2467 static void gen_slt_imm(DisasContext *ctx, uint32_t opc, 2468 int rt, int rs, int16_t imm) 2469 { 2470 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ 2471 TCGv t0; 2472 2473 if (rt == 0) { 2474 /* If no destination, treat it as a NOP. */ 2475 return; 2476 } 2477 t0 = tcg_temp_new(); 2478 gen_load_gpr(t0, rs); 2479 switch (opc) { 2480 case OPC_SLTI: 2481 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, uimm); 2482 break; 2483 case OPC_SLTIU: 2484 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm); 2485 break; 2486 } 2487 } 2488 2489 /* Shifts with immediate operand */ 2490 static void gen_shift_imm(DisasContext *ctx, uint32_t opc, 2491 int rt, int rs, int16_t imm) 2492 { 2493 target_ulong uimm = ((uint16_t)imm) & 0x1f; 2494 TCGv t0; 2495 2496 if (rt == 0) { 2497 /* If no destination, treat it as a NOP. */ 2498 return; 2499 } 2500 2501 t0 = tcg_temp_new(); 2502 gen_load_gpr(t0, rs); 2503 switch (opc) { 2504 case OPC_SLL: 2505 tcg_gen_shli_tl(t0, t0, uimm); 2506 tcg_gen_ext32s_tl(cpu_gpr[rt], t0); 2507 break; 2508 case OPC_SRA: 2509 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); 2510 break; 2511 case OPC_SRL: 2512 if (uimm != 0) { 2513 tcg_gen_ext32u_tl(t0, t0); 2514 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); 2515 } else { 2516 tcg_gen_ext32s_tl(cpu_gpr[rt], t0); 2517 } 2518 break; 2519 case OPC_ROTR: 2520 if (uimm != 0) { 2521 TCGv_i32 t1 = tcg_temp_new_i32(); 2522 2523 tcg_gen_trunc_tl_i32(t1, t0); 2524 tcg_gen_rotri_i32(t1, t1, uimm); 2525 tcg_gen_ext_i32_tl(cpu_gpr[rt], t1); 2526 } else { 2527 tcg_gen_ext32s_tl(cpu_gpr[rt], t0); 2528 } 2529 break; 2530 #if defined(TARGET_MIPS64) 2531 case OPC_DSLL: 2532 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm); 2533 break; 2534 case OPC_DSRA: 2535 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); 2536 break; 2537 case OPC_DSRL: 2538 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); 2539 break; 2540 case OPC_DROTR: 2541 if (uimm != 0) { 2542 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm); 2543 } else { 2544 tcg_gen_mov_tl(cpu_gpr[rt], t0); 2545 } 2546 break; 2547 case OPC_DSLL32: 2548 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32); 2549 break; 2550 case OPC_DSRA32: 2551 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32); 2552 break; 2553 case OPC_DSRL32: 2554 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32); 2555 break; 2556 case OPC_DROTR32: 2557 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32); 2558 break; 2559 #endif 2560 } 2561 } 2562 2563 /* Arithmetic */ 2564 static void gen_arith(DisasContext *ctx, uint32_t opc, 2565 int rd, int rs, int rt) 2566 { 2567 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB 2568 && opc != OPC_DADD && opc != OPC_DSUB) { 2569 /* 2570 * If no destination, treat it as a NOP. 2571 * For add & sub, we must generate the overflow exception when needed. 2572 */ 2573 return; 2574 } 2575 2576 switch (opc) { 2577 case OPC_ADD: 2578 { 2579 TCGv t0 = tcg_temp_new(); 2580 TCGv t1 = tcg_temp_new(); 2581 TCGv t2 = tcg_temp_new(); 2582 TCGLabel *l1 = gen_new_label(); 2583 2584 gen_load_gpr(t1, rs); 2585 gen_load_gpr(t2, rt); 2586 tcg_gen_add_tl(t0, t1, t2); 2587 tcg_gen_ext32s_tl(t0, t0); 2588 tcg_gen_xor_tl(t1, t1, t2); 2589 tcg_gen_xor_tl(t2, t0, t2); 2590 tcg_gen_andc_tl(t1, t2, t1); 2591 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2592 /* operands of same sign, result different sign */ 2593 generate_exception(ctx, EXCP_OVERFLOW); 2594 gen_set_label(l1); 2595 gen_store_gpr(t0, rd); 2596 } 2597 break; 2598 case OPC_ADDU: 2599 if (rs != 0 && rt != 0) { 2600 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2601 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2602 } else if (rs == 0 && rt != 0) { 2603 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2604 } else if (rs != 0 && rt == 0) { 2605 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2606 } else { 2607 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2608 } 2609 break; 2610 case OPC_SUB: 2611 { 2612 TCGv t0 = tcg_temp_new(); 2613 TCGv t1 = tcg_temp_new(); 2614 TCGv t2 = tcg_temp_new(); 2615 TCGLabel *l1 = gen_new_label(); 2616 2617 gen_load_gpr(t1, rs); 2618 gen_load_gpr(t2, rt); 2619 tcg_gen_sub_tl(t0, t1, t2); 2620 tcg_gen_ext32s_tl(t0, t0); 2621 tcg_gen_xor_tl(t2, t1, t2); 2622 tcg_gen_xor_tl(t1, t0, t1); 2623 tcg_gen_and_tl(t1, t1, t2); 2624 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2625 /* 2626 * operands of different sign, first operand and the result 2627 * of different sign 2628 */ 2629 generate_exception(ctx, EXCP_OVERFLOW); 2630 gen_set_label(l1); 2631 gen_store_gpr(t0, rd); 2632 } 2633 break; 2634 case OPC_SUBU: 2635 if (rs != 0 && rt != 0) { 2636 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2637 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2638 } else if (rs == 0 && rt != 0) { 2639 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); 2640 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2641 } else if (rs != 0 && rt == 0) { 2642 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2643 } else { 2644 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2645 } 2646 break; 2647 #if defined(TARGET_MIPS64) 2648 case OPC_DADD: 2649 { 2650 TCGv t0 = tcg_temp_new(); 2651 TCGv t1 = tcg_temp_new(); 2652 TCGv t2 = tcg_temp_new(); 2653 TCGLabel *l1 = gen_new_label(); 2654 2655 gen_load_gpr(t1, rs); 2656 gen_load_gpr(t2, rt); 2657 tcg_gen_add_tl(t0, t1, t2); 2658 tcg_gen_xor_tl(t1, t1, t2); 2659 tcg_gen_xor_tl(t2, t0, t2); 2660 tcg_gen_andc_tl(t1, t2, t1); 2661 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2662 /* operands of same sign, result different sign */ 2663 generate_exception(ctx, EXCP_OVERFLOW); 2664 gen_set_label(l1); 2665 gen_store_gpr(t0, rd); 2666 } 2667 break; 2668 case OPC_DADDU: 2669 if (rs != 0 && rt != 0) { 2670 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2671 } else if (rs == 0 && rt != 0) { 2672 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2673 } else if (rs != 0 && rt == 0) { 2674 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2675 } else { 2676 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2677 } 2678 break; 2679 case OPC_DSUB: 2680 { 2681 TCGv t0 = tcg_temp_new(); 2682 TCGv t1 = tcg_temp_new(); 2683 TCGv t2 = tcg_temp_new(); 2684 TCGLabel *l1 = gen_new_label(); 2685 2686 gen_load_gpr(t1, rs); 2687 gen_load_gpr(t2, rt); 2688 tcg_gen_sub_tl(t0, t1, t2); 2689 tcg_gen_xor_tl(t2, t1, t2); 2690 tcg_gen_xor_tl(t1, t0, t1); 2691 tcg_gen_and_tl(t1, t1, t2); 2692 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 2693 /* 2694 * Operands of different sign, first operand and result different 2695 * sign. 2696 */ 2697 generate_exception(ctx, EXCP_OVERFLOW); 2698 gen_set_label(l1); 2699 gen_store_gpr(t0, rd); 2700 } 2701 break; 2702 case OPC_DSUBU: 2703 if (rs != 0 && rt != 0) { 2704 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2705 } else if (rs == 0 && rt != 0) { 2706 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); 2707 } else if (rs != 0 && rt == 0) { 2708 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2709 } else { 2710 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2711 } 2712 break; 2713 #endif 2714 case OPC_MUL: 2715 if (likely(rs != 0 && rt != 0)) { 2716 tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2717 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 2718 } else { 2719 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2720 } 2721 break; 2722 } 2723 } 2724 2725 /* Conditional move */ 2726 static void gen_cond_move(DisasContext *ctx, uint32_t opc, 2727 int rd, int rs, int rt) 2728 { 2729 TCGv t0, t1, t2; 2730 2731 if (rd == 0) { 2732 /* If no destination, treat it as a NOP. */ 2733 return; 2734 } 2735 2736 t0 = tcg_temp_new(); 2737 gen_load_gpr(t0, rt); 2738 t1 = tcg_constant_tl(0); 2739 t2 = tcg_temp_new(); 2740 gen_load_gpr(t2, rs); 2741 switch (opc) { 2742 case OPC_MOVN: 2743 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]); 2744 break; 2745 case OPC_MOVZ: 2746 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]); 2747 break; 2748 case OPC_SELNEZ: 2749 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1); 2750 break; 2751 case OPC_SELEQZ: 2752 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1); 2753 break; 2754 } 2755 } 2756 2757 /* Logic */ 2758 static void gen_logic(DisasContext *ctx, uint32_t opc, 2759 int rd, int rs, int rt) 2760 { 2761 if (rd == 0) { 2762 /* If no destination, treat it as a NOP. */ 2763 return; 2764 } 2765 2766 switch (opc) { 2767 case OPC_AND: 2768 if (likely(rs != 0 && rt != 0)) { 2769 tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2770 } else { 2771 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2772 } 2773 break; 2774 case OPC_NOR: 2775 if (rs != 0 && rt != 0) { 2776 tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2777 } else if (rs == 0 && rt != 0) { 2778 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]); 2779 } else if (rs != 0 && rt == 0) { 2780 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]); 2781 } else { 2782 tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0)); 2783 } 2784 break; 2785 case OPC_OR: 2786 if (likely(rs != 0 && rt != 0)) { 2787 tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2788 } else if (rs == 0 && rt != 0) { 2789 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2790 } else if (rs != 0 && rt == 0) { 2791 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2792 } else { 2793 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2794 } 2795 break; 2796 case OPC_XOR: 2797 if (likely(rs != 0 && rt != 0)) { 2798 tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); 2799 } else if (rs == 0 && rt != 0) { 2800 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); 2801 } else if (rs != 0 && rt == 0) { 2802 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); 2803 } else { 2804 tcg_gen_movi_tl(cpu_gpr[rd], 0); 2805 } 2806 break; 2807 } 2808 } 2809 2810 /* Set on lower than */ 2811 static void gen_slt(DisasContext *ctx, uint32_t opc, 2812 int rd, int rs, int rt) 2813 { 2814 TCGv t0, t1; 2815 2816 if (rd == 0) { 2817 /* If no destination, treat it as a NOP. */ 2818 return; 2819 } 2820 2821 t0 = tcg_temp_new(); 2822 t1 = tcg_temp_new(); 2823 gen_load_gpr(t0, rs); 2824 gen_load_gpr(t1, rt); 2825 switch (opc) { 2826 case OPC_SLT: 2827 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr[rd], t0, t1); 2828 break; 2829 case OPC_SLTU: 2830 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1); 2831 break; 2832 } 2833 } 2834 2835 /* Shifts */ 2836 static void gen_shift(DisasContext *ctx, uint32_t opc, 2837 int rd, int rs, int rt) 2838 { 2839 TCGv t0, t1; 2840 2841 if (rd == 0) { 2842 /* 2843 * If no destination, treat it as a NOP. 2844 * For add & sub, we must generate the overflow exception when needed. 2845 */ 2846 return; 2847 } 2848 2849 t0 = tcg_temp_new(); 2850 t1 = tcg_temp_new(); 2851 gen_load_gpr(t0, rs); 2852 gen_load_gpr(t1, rt); 2853 switch (opc) { 2854 case OPC_SLLV: 2855 tcg_gen_andi_tl(t0, t0, 0x1f); 2856 tcg_gen_shl_tl(t0, t1, t0); 2857 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 2858 break; 2859 case OPC_SRAV: 2860 tcg_gen_andi_tl(t0, t0, 0x1f); 2861 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); 2862 break; 2863 case OPC_SRLV: 2864 tcg_gen_ext32u_tl(t1, t1); 2865 tcg_gen_andi_tl(t0, t0, 0x1f); 2866 tcg_gen_shr_tl(t0, t1, t0); 2867 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 2868 break; 2869 case OPC_ROTRV: 2870 { 2871 TCGv_i32 t2 = tcg_temp_new_i32(); 2872 TCGv_i32 t3 = tcg_temp_new_i32(); 2873 2874 tcg_gen_trunc_tl_i32(t2, t0); 2875 tcg_gen_trunc_tl_i32(t3, t1); 2876 tcg_gen_andi_i32(t2, t2, 0x1f); 2877 tcg_gen_rotr_i32(t2, t3, t2); 2878 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 2879 } 2880 break; 2881 #if defined(TARGET_MIPS64) 2882 case OPC_DSLLV: 2883 tcg_gen_andi_tl(t0, t0, 0x3f); 2884 tcg_gen_shl_tl(cpu_gpr[rd], t1, t0); 2885 break; 2886 case OPC_DSRAV: 2887 tcg_gen_andi_tl(t0, t0, 0x3f); 2888 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); 2889 break; 2890 case OPC_DSRLV: 2891 tcg_gen_andi_tl(t0, t0, 0x3f); 2892 tcg_gen_shr_tl(cpu_gpr[rd], t1, t0); 2893 break; 2894 case OPC_DROTRV: 2895 tcg_gen_andi_tl(t0, t0, 0x3f); 2896 tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0); 2897 break; 2898 #endif 2899 } 2900 } 2901 2902 /* Arithmetic on HI/LO registers */ 2903 static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) 2904 { 2905 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { 2906 /* Treat as NOP. */ 2907 return; 2908 } 2909 2910 if (acc != 0) { 2911 check_dsp(ctx); 2912 } 2913 2914 switch (opc) { 2915 case OPC_MFHI: 2916 #if defined(TARGET_MIPS64) 2917 if (acc != 0) { 2918 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]); 2919 } else 2920 #endif 2921 { 2922 tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]); 2923 } 2924 break; 2925 case OPC_MFLO: 2926 #if defined(TARGET_MIPS64) 2927 if (acc != 0) { 2928 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]); 2929 } else 2930 #endif 2931 { 2932 tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]); 2933 } 2934 break; 2935 case OPC_MTHI: 2936 if (reg != 0) { 2937 #if defined(TARGET_MIPS64) 2938 if (acc != 0) { 2939 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_gpr[reg]); 2940 } else 2941 #endif 2942 { 2943 tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]); 2944 } 2945 } else { 2946 tcg_gen_movi_tl(cpu_HI[acc], 0); 2947 } 2948 break; 2949 case OPC_MTLO: 2950 if (reg != 0) { 2951 #if defined(TARGET_MIPS64) 2952 if (acc != 0) { 2953 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_gpr[reg]); 2954 } else 2955 #endif 2956 { 2957 tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]); 2958 } 2959 } else { 2960 tcg_gen_movi_tl(cpu_LO[acc], 0); 2961 } 2962 break; 2963 } 2964 } 2965 2966 static inline void gen_r6_ld(target_long addr, int reg, int memidx, 2967 MemOp memop) 2968 { 2969 TCGv t0 = tcg_temp_new(); 2970 tcg_gen_qemu_ld_tl(t0, tcg_constant_tl(addr), memidx, memop); 2971 gen_store_gpr(t0, reg); 2972 } 2973 2974 static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc, 2975 int rs) 2976 { 2977 target_long offset; 2978 target_long addr; 2979 2980 switch (MASK_OPC_PCREL_TOP2BITS(opc)) { 2981 case OPC_ADDIUPC: 2982 if (rs != 0) { 2983 offset = sextract32(ctx->opcode << 2, 0, 21); 2984 addr = addr_add(ctx, pc, offset); 2985 tcg_gen_movi_tl(cpu_gpr[rs], addr); 2986 } 2987 break; 2988 case R6_OPC_LWPC: 2989 offset = sextract32(ctx->opcode << 2, 0, 21); 2990 addr = addr_add(ctx, pc, offset); 2991 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TESL); 2992 break; 2993 #if defined(TARGET_MIPS64) 2994 case OPC_LWUPC: 2995 check_mips_64(ctx); 2996 offset = sextract32(ctx->opcode << 2, 0, 21); 2997 addr = addr_add(ctx, pc, offset); 2998 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUL); 2999 break; 3000 #endif 3001 default: 3002 switch (MASK_OPC_PCREL_TOP5BITS(opc)) { 3003 case OPC_AUIPC: 3004 if (rs != 0) { 3005 offset = sextract32(ctx->opcode, 0, 16) << 16; 3006 addr = addr_add(ctx, pc, offset); 3007 tcg_gen_movi_tl(cpu_gpr[rs], addr); 3008 } 3009 break; 3010 case OPC_ALUIPC: 3011 if (rs != 0) { 3012 offset = sextract32(ctx->opcode, 0, 16) << 16; 3013 addr = ~0xFFFF & addr_add(ctx, pc, offset); 3014 tcg_gen_movi_tl(cpu_gpr[rs], addr); 3015 } 3016 break; 3017 #if defined(TARGET_MIPS64) 3018 case R6_OPC_LDPC: /* bits 16 and 17 are part of immediate */ 3019 case R6_OPC_LDPC + (1 << 16): 3020 case R6_OPC_LDPC + (2 << 16): 3021 case R6_OPC_LDPC + (3 << 16): 3022 check_mips_64(ctx); 3023 offset = sextract32(ctx->opcode << 3, 0, 21); 3024 addr = addr_add(ctx, (pc & ~0x7), offset); 3025 gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUQ); 3026 break; 3027 #endif 3028 default: 3029 MIPS_INVAL("OPC_PCREL"); 3030 gen_reserved_instruction(ctx); 3031 break; 3032 } 3033 break; 3034 } 3035 } 3036 3037 static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) 3038 { 3039 TCGv t0, t1; 3040 3041 if (rd == 0) { 3042 /* Treat as NOP. */ 3043 return; 3044 } 3045 3046 t0 = tcg_temp_new(); 3047 t1 = tcg_temp_new(); 3048 3049 gen_load_gpr(t0, rs); 3050 gen_load_gpr(t1, rt); 3051 3052 switch (opc) { 3053 case R6_OPC_DIV: 3054 { 3055 TCGv t2 = tcg_temp_new(); 3056 TCGv t3 = tcg_temp_new(); 3057 tcg_gen_ext32s_tl(t0, t0); 3058 tcg_gen_ext32s_tl(t1, t1); 3059 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3060 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3061 tcg_gen_and_tl(t2, t2, t3); 3062 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3063 tcg_gen_or_tl(t2, t2, t3); 3064 tcg_gen_movi_tl(t3, 0); 3065 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3066 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3067 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3068 } 3069 break; 3070 case R6_OPC_MOD: 3071 { 3072 TCGv t2 = tcg_temp_new(); 3073 TCGv t3 = tcg_temp_new(); 3074 tcg_gen_ext32s_tl(t0, t0); 3075 tcg_gen_ext32s_tl(t1, t1); 3076 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3077 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3078 tcg_gen_and_tl(t2, t2, t3); 3079 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3080 tcg_gen_or_tl(t2, t2, t3); 3081 tcg_gen_movi_tl(t3, 0); 3082 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3083 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3084 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3085 } 3086 break; 3087 case R6_OPC_DIVU: 3088 { 3089 TCGv t2 = tcg_constant_tl(0); 3090 TCGv t3 = tcg_constant_tl(1); 3091 tcg_gen_ext32u_tl(t0, t0); 3092 tcg_gen_ext32u_tl(t1, t1); 3093 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3094 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); 3095 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3096 } 3097 break; 3098 case R6_OPC_MODU: 3099 { 3100 TCGv t2 = tcg_constant_tl(0); 3101 TCGv t3 = tcg_constant_tl(1); 3102 tcg_gen_ext32u_tl(t0, t0); 3103 tcg_gen_ext32u_tl(t1, t1); 3104 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3105 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); 3106 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3107 } 3108 break; 3109 case R6_OPC_MUL: 3110 { 3111 TCGv_i32 t2 = tcg_temp_new_i32(); 3112 TCGv_i32 t3 = tcg_temp_new_i32(); 3113 tcg_gen_trunc_tl_i32(t2, t0); 3114 tcg_gen_trunc_tl_i32(t3, t1); 3115 tcg_gen_mul_i32(t2, t2, t3); 3116 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3117 } 3118 break; 3119 case R6_OPC_MUH: 3120 { 3121 TCGv_i32 t2 = tcg_temp_new_i32(); 3122 TCGv_i32 t3 = tcg_temp_new_i32(); 3123 tcg_gen_trunc_tl_i32(t2, t0); 3124 tcg_gen_trunc_tl_i32(t3, t1); 3125 tcg_gen_muls2_i32(t2, t3, t2, t3); 3126 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3); 3127 } 3128 break; 3129 case R6_OPC_MULU: 3130 { 3131 TCGv_i32 t2 = tcg_temp_new_i32(); 3132 TCGv_i32 t3 = tcg_temp_new_i32(); 3133 tcg_gen_trunc_tl_i32(t2, t0); 3134 tcg_gen_trunc_tl_i32(t3, t1); 3135 tcg_gen_mul_i32(t2, t2, t3); 3136 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3137 } 3138 break; 3139 case R6_OPC_MUHU: 3140 { 3141 TCGv_i32 t2 = tcg_temp_new_i32(); 3142 TCGv_i32 t3 = tcg_temp_new_i32(); 3143 tcg_gen_trunc_tl_i32(t2, t0); 3144 tcg_gen_trunc_tl_i32(t3, t1); 3145 tcg_gen_mulu2_i32(t2, t3, t2, t3); 3146 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3); 3147 } 3148 break; 3149 #if defined(TARGET_MIPS64) 3150 case R6_OPC_DDIV: 3151 { 3152 TCGv t2 = tcg_temp_new(); 3153 TCGv t3 = tcg_temp_new(); 3154 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); 3155 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); 3156 tcg_gen_and_tl(t2, t2, t3); 3157 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3158 tcg_gen_or_tl(t2, t2, t3); 3159 tcg_gen_movi_tl(t3, 0); 3160 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3161 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3162 } 3163 break; 3164 case R6_OPC_DMOD: 3165 { 3166 TCGv t2 = tcg_temp_new(); 3167 TCGv t3 = tcg_temp_new(); 3168 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); 3169 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); 3170 tcg_gen_and_tl(t2, t2, t3); 3171 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3172 tcg_gen_or_tl(t2, t2, t3); 3173 tcg_gen_movi_tl(t3, 0); 3174 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3175 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3176 } 3177 break; 3178 case R6_OPC_DDIVU: 3179 { 3180 TCGv t2 = tcg_constant_tl(0); 3181 TCGv t3 = tcg_constant_tl(1); 3182 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3183 tcg_gen_divu_i64(cpu_gpr[rd], t0, t1); 3184 } 3185 break; 3186 case R6_OPC_DMODU: 3187 { 3188 TCGv t2 = tcg_constant_tl(0); 3189 TCGv t3 = tcg_constant_tl(1); 3190 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3191 tcg_gen_remu_i64(cpu_gpr[rd], t0, t1); 3192 } 3193 break; 3194 case R6_OPC_DMUL: 3195 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1); 3196 break; 3197 case R6_OPC_DMUH: 3198 { 3199 TCGv t2 = tcg_temp_new(); 3200 tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1); 3201 } 3202 break; 3203 case R6_OPC_DMULU: 3204 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1); 3205 break; 3206 case R6_OPC_DMUHU: 3207 { 3208 TCGv t2 = tcg_temp_new(); 3209 tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1); 3210 } 3211 break; 3212 #endif 3213 default: 3214 MIPS_INVAL("r6 mul/div"); 3215 gen_reserved_instruction(ctx); 3216 break; 3217 } 3218 } 3219 3220 #if defined(TARGET_MIPS64) 3221 static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt) 3222 { 3223 TCGv t0, t1; 3224 3225 t0 = tcg_temp_new(); 3226 t1 = tcg_temp_new(); 3227 3228 gen_load_gpr(t0, rs); 3229 gen_load_gpr(t1, rt); 3230 3231 switch (opc) { 3232 case MMI_OPC_DIV1: 3233 { 3234 TCGv t2 = tcg_temp_new(); 3235 TCGv t3 = tcg_temp_new(); 3236 tcg_gen_ext32s_tl(t0, t0); 3237 tcg_gen_ext32s_tl(t1, t1); 3238 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3239 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3240 tcg_gen_and_tl(t2, t2, t3); 3241 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3242 tcg_gen_or_tl(t2, t2, t3); 3243 tcg_gen_movi_tl(t3, 0); 3244 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3245 tcg_gen_div_tl(cpu_LO[1], t0, t1); 3246 tcg_gen_rem_tl(cpu_HI[1], t0, t1); 3247 tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); 3248 tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); 3249 } 3250 break; 3251 case MMI_OPC_DIVU1: 3252 { 3253 TCGv t2 = tcg_constant_tl(0); 3254 TCGv t3 = tcg_constant_tl(1); 3255 tcg_gen_ext32u_tl(t0, t0); 3256 tcg_gen_ext32u_tl(t1, t1); 3257 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3258 tcg_gen_divu_tl(cpu_LO[1], t0, t1); 3259 tcg_gen_remu_tl(cpu_HI[1], t0, t1); 3260 tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); 3261 tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); 3262 } 3263 break; 3264 default: 3265 MIPS_INVAL("div1 TX79"); 3266 gen_reserved_instruction(ctx); 3267 break; 3268 } 3269 } 3270 #endif 3271 3272 static void gen_muldiv(DisasContext *ctx, uint32_t opc, 3273 int acc, int rs, int rt) 3274 { 3275 TCGv t0, t1; 3276 3277 t0 = tcg_temp_new(); 3278 t1 = tcg_temp_new(); 3279 3280 gen_load_gpr(t0, rs); 3281 gen_load_gpr(t1, rt); 3282 3283 if (acc != 0) { 3284 check_dsp(ctx); 3285 } 3286 3287 switch (opc) { 3288 case OPC_DIV: 3289 { 3290 TCGv t2 = tcg_temp_new(); 3291 TCGv t3 = tcg_temp_new(); 3292 tcg_gen_ext32s_tl(t0, t0); 3293 tcg_gen_ext32s_tl(t1, t1); 3294 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); 3295 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); 3296 tcg_gen_and_tl(t2, t2, t3); 3297 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3298 tcg_gen_or_tl(t2, t2, t3); 3299 tcg_gen_movi_tl(t3, 0); 3300 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3301 tcg_gen_div_tl(cpu_LO[acc], t0, t1); 3302 tcg_gen_rem_tl(cpu_HI[acc], t0, t1); 3303 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); 3304 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]); 3305 } 3306 break; 3307 case OPC_DIVU: 3308 { 3309 TCGv t2 = tcg_constant_tl(0); 3310 TCGv t3 = tcg_constant_tl(1); 3311 tcg_gen_ext32u_tl(t0, t0); 3312 tcg_gen_ext32u_tl(t1, t1); 3313 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3314 tcg_gen_divu_tl(cpu_LO[acc], t0, t1); 3315 tcg_gen_remu_tl(cpu_HI[acc], t0, t1); 3316 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); 3317 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]); 3318 } 3319 break; 3320 case OPC_MULT: 3321 { 3322 TCGv_i32 t2 = tcg_temp_new_i32(); 3323 TCGv_i32 t3 = tcg_temp_new_i32(); 3324 tcg_gen_trunc_tl_i32(t2, t0); 3325 tcg_gen_trunc_tl_i32(t3, t1); 3326 tcg_gen_muls2_i32(t2, t3, t2, t3); 3327 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3328 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3329 } 3330 break; 3331 case OPC_MULTU: 3332 { 3333 TCGv_i32 t2 = tcg_temp_new_i32(); 3334 TCGv_i32 t3 = tcg_temp_new_i32(); 3335 tcg_gen_trunc_tl_i32(t2, t0); 3336 tcg_gen_trunc_tl_i32(t3, t1); 3337 tcg_gen_mulu2_i32(t2, t3, t2, t3); 3338 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3339 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3340 } 3341 break; 3342 #if defined(TARGET_MIPS64) 3343 case OPC_DDIV: 3344 { 3345 TCGv t2 = tcg_temp_new(); 3346 TCGv t3 = tcg_temp_new(); 3347 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); 3348 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); 3349 tcg_gen_and_tl(t2, t2, t3); 3350 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); 3351 tcg_gen_or_tl(t2, t2, t3); 3352 tcg_gen_movi_tl(t3, 0); 3353 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); 3354 tcg_gen_div_tl(cpu_LO[acc], t0, t1); 3355 tcg_gen_rem_tl(cpu_HI[acc], t0, t1); 3356 } 3357 break; 3358 case OPC_DDIVU: 3359 { 3360 TCGv t2 = tcg_constant_tl(0); 3361 TCGv t3 = tcg_constant_tl(1); 3362 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); 3363 tcg_gen_divu_i64(cpu_LO[acc], t0, t1); 3364 tcg_gen_remu_i64(cpu_HI[acc], t0, t1); 3365 } 3366 break; 3367 case OPC_DMULT: 3368 tcg_gen_muls2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1); 3369 break; 3370 case OPC_DMULTU: 3371 tcg_gen_mulu2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1); 3372 break; 3373 #endif 3374 case OPC_MADD: 3375 { 3376 TCGv_i64 t2 = tcg_temp_new_i64(); 3377 TCGv_i64 t3 = tcg_temp_new_i64(); 3378 3379 tcg_gen_ext_tl_i64(t2, t0); 3380 tcg_gen_ext_tl_i64(t3, t1); 3381 tcg_gen_mul_i64(t2, t2, t3); 3382 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3383 tcg_gen_add_i64(t2, t2, t3); 3384 gen_move_low32(cpu_LO[acc], t2); 3385 gen_move_high32(cpu_HI[acc], t2); 3386 } 3387 break; 3388 case OPC_MADDU: 3389 { 3390 TCGv_i64 t2 = tcg_temp_new_i64(); 3391 TCGv_i64 t3 = tcg_temp_new_i64(); 3392 3393 tcg_gen_ext32u_tl(t0, t0); 3394 tcg_gen_ext32u_tl(t1, t1); 3395 tcg_gen_extu_tl_i64(t2, t0); 3396 tcg_gen_extu_tl_i64(t3, t1); 3397 tcg_gen_mul_i64(t2, t2, t3); 3398 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3399 tcg_gen_add_i64(t2, t2, t3); 3400 gen_move_low32(cpu_LO[acc], t2); 3401 gen_move_high32(cpu_HI[acc], t2); 3402 } 3403 break; 3404 case OPC_MSUB: 3405 { 3406 TCGv_i64 t2 = tcg_temp_new_i64(); 3407 TCGv_i64 t3 = tcg_temp_new_i64(); 3408 3409 tcg_gen_ext_tl_i64(t2, t0); 3410 tcg_gen_ext_tl_i64(t3, t1); 3411 tcg_gen_mul_i64(t2, t2, t3); 3412 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3413 tcg_gen_sub_i64(t2, t3, t2); 3414 gen_move_low32(cpu_LO[acc], t2); 3415 gen_move_high32(cpu_HI[acc], t2); 3416 } 3417 break; 3418 case OPC_MSUBU: 3419 { 3420 TCGv_i64 t2 = tcg_temp_new_i64(); 3421 TCGv_i64 t3 = tcg_temp_new_i64(); 3422 3423 tcg_gen_ext32u_tl(t0, t0); 3424 tcg_gen_ext32u_tl(t1, t1); 3425 tcg_gen_extu_tl_i64(t2, t0); 3426 tcg_gen_extu_tl_i64(t3, t1); 3427 tcg_gen_mul_i64(t2, t2, t3); 3428 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3429 tcg_gen_sub_i64(t2, t3, t2); 3430 gen_move_low32(cpu_LO[acc], t2); 3431 gen_move_high32(cpu_HI[acc], t2); 3432 } 3433 break; 3434 default: 3435 MIPS_INVAL("mul/div"); 3436 gen_reserved_instruction(ctx); 3437 break; 3438 } 3439 } 3440 3441 /* 3442 * These MULT[U] and MADD[U] instructions implemented in for example 3443 * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core 3444 * architectures are special three-operand variants with the syntax 3445 * 3446 * MULT[U][1] rd, rs, rt 3447 * 3448 * such that 3449 * 3450 * (rd, LO, HI) <- rs * rt 3451 * 3452 * and 3453 * 3454 * MADD[U][1] rd, rs, rt 3455 * 3456 * such that 3457 * 3458 * (rd, LO, HI) <- (LO, HI) + rs * rt 3459 * 3460 * where the low-order 32-bits of the result is placed into both the 3461 * GPR rd and the special register LO. The high-order 32-bits of the 3462 * result is placed into the special register HI. 3463 * 3464 * If the GPR rd is omitted in assembly language, it is taken to be 0, 3465 * which is the zero register that always reads as 0. 3466 */ 3467 static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, 3468 int rd, int rs, int rt) 3469 { 3470 TCGv t0 = tcg_temp_new(); 3471 TCGv t1 = tcg_temp_new(); 3472 int acc = 0; 3473 3474 gen_load_gpr(t0, rs); 3475 gen_load_gpr(t1, rt); 3476 3477 switch (opc) { 3478 case MMI_OPC_MULT1: 3479 acc = 1; 3480 /* Fall through */ 3481 case OPC_MULT: 3482 { 3483 TCGv_i32 t2 = tcg_temp_new_i32(); 3484 TCGv_i32 t3 = tcg_temp_new_i32(); 3485 tcg_gen_trunc_tl_i32(t2, t0); 3486 tcg_gen_trunc_tl_i32(t3, t1); 3487 tcg_gen_muls2_i32(t2, t3, t2, t3); 3488 if (rd) { 3489 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3490 } 3491 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3492 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3493 } 3494 break; 3495 case MMI_OPC_MULTU1: 3496 acc = 1; 3497 /* Fall through */ 3498 case OPC_MULTU: 3499 { 3500 TCGv_i32 t2 = tcg_temp_new_i32(); 3501 TCGv_i32 t3 = tcg_temp_new_i32(); 3502 tcg_gen_trunc_tl_i32(t2, t0); 3503 tcg_gen_trunc_tl_i32(t3, t1); 3504 tcg_gen_mulu2_i32(t2, t3, t2, t3); 3505 if (rd) { 3506 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); 3507 } 3508 tcg_gen_ext_i32_tl(cpu_LO[acc], t2); 3509 tcg_gen_ext_i32_tl(cpu_HI[acc], t3); 3510 } 3511 break; 3512 case MMI_OPC_MADD1: 3513 acc = 1; 3514 /* Fall through */ 3515 case MMI_OPC_MADD: 3516 { 3517 TCGv_i64 t2 = tcg_temp_new_i64(); 3518 TCGv_i64 t3 = tcg_temp_new_i64(); 3519 3520 tcg_gen_ext_tl_i64(t2, t0); 3521 tcg_gen_ext_tl_i64(t3, t1); 3522 tcg_gen_mul_i64(t2, t2, t3); 3523 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3524 tcg_gen_add_i64(t2, t2, t3); 3525 gen_move_low32(cpu_LO[acc], t2); 3526 gen_move_high32(cpu_HI[acc], t2); 3527 if (rd) { 3528 gen_move_low32(cpu_gpr[rd], t2); 3529 } 3530 } 3531 break; 3532 case MMI_OPC_MADDU1: 3533 acc = 1; 3534 /* Fall through */ 3535 case MMI_OPC_MADDU: 3536 { 3537 TCGv_i64 t2 = tcg_temp_new_i64(); 3538 TCGv_i64 t3 = tcg_temp_new_i64(); 3539 3540 tcg_gen_ext32u_tl(t0, t0); 3541 tcg_gen_ext32u_tl(t1, t1); 3542 tcg_gen_extu_tl_i64(t2, t0); 3543 tcg_gen_extu_tl_i64(t3, t1); 3544 tcg_gen_mul_i64(t2, t2, t3); 3545 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); 3546 tcg_gen_add_i64(t2, t2, t3); 3547 gen_move_low32(cpu_LO[acc], t2); 3548 gen_move_high32(cpu_HI[acc], t2); 3549 if (rd) { 3550 gen_move_low32(cpu_gpr[rd], t2); 3551 } 3552 } 3553 break; 3554 default: 3555 MIPS_INVAL("mul/madd TXx9"); 3556 gen_reserved_instruction(ctx); 3557 break; 3558 } 3559 } 3560 3561 static void gen_cl(DisasContext *ctx, uint32_t opc, 3562 int rd, int rs) 3563 { 3564 TCGv t0; 3565 3566 if (rd == 0) { 3567 /* Treat as NOP. */ 3568 return; 3569 } 3570 t0 = cpu_gpr[rd]; 3571 gen_load_gpr(t0, rs); 3572 3573 switch (opc) { 3574 case OPC_CLO: 3575 case R6_OPC_CLO: 3576 #if defined(TARGET_MIPS64) 3577 case OPC_DCLO: 3578 case R6_OPC_DCLO: 3579 #endif 3580 tcg_gen_not_tl(t0, t0); 3581 break; 3582 } 3583 3584 switch (opc) { 3585 case OPC_CLO: 3586 case R6_OPC_CLO: 3587 case OPC_CLZ: 3588 case R6_OPC_CLZ: 3589 tcg_gen_ext32u_tl(t0, t0); 3590 tcg_gen_clzi_tl(t0, t0, TARGET_LONG_BITS); 3591 tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32); 3592 break; 3593 #if defined(TARGET_MIPS64) 3594 case OPC_DCLO: 3595 case R6_OPC_DCLO: 3596 case OPC_DCLZ: 3597 case R6_OPC_DCLZ: 3598 tcg_gen_clzi_i64(t0, t0, 64); 3599 break; 3600 #endif 3601 } 3602 } 3603 3604 /* Godson integer instructions */ 3605 static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, 3606 int rd, int rs, int rt) 3607 { 3608 TCGv t0, t1; 3609 3610 if (rd == 0) { 3611 /* Treat as NOP. */ 3612 return; 3613 } 3614 3615 t0 = tcg_temp_new(); 3616 t1 = tcg_temp_new(); 3617 gen_load_gpr(t0, rs); 3618 gen_load_gpr(t1, rt); 3619 3620 switch (opc) { 3621 case OPC_MULT_G_2E: 3622 case OPC_MULT_G_2F: 3623 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3624 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3625 break; 3626 case OPC_MULTU_G_2E: 3627 case OPC_MULTU_G_2F: 3628 tcg_gen_ext32u_tl(t0, t0); 3629 tcg_gen_ext32u_tl(t1, t1); 3630 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3631 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3632 break; 3633 case OPC_DIV_G_2E: 3634 case OPC_DIV_G_2F: 3635 { 3636 TCGLabel *l1 = gen_new_label(); 3637 TCGLabel *l2 = gen_new_label(); 3638 TCGLabel *l3 = gen_new_label(); 3639 tcg_gen_ext32s_tl(t0, t0); 3640 tcg_gen_ext32s_tl(t1, t1); 3641 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3642 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3643 tcg_gen_br(l3); 3644 gen_set_label(l1); 3645 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); 3646 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); 3647 tcg_gen_mov_tl(cpu_gpr[rd], t0); 3648 tcg_gen_br(l3); 3649 gen_set_label(l2); 3650 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3651 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3652 gen_set_label(l3); 3653 } 3654 break; 3655 case OPC_DIVU_G_2E: 3656 case OPC_DIVU_G_2F: 3657 { 3658 TCGLabel *l1 = gen_new_label(); 3659 TCGLabel *l2 = gen_new_label(); 3660 tcg_gen_ext32u_tl(t0, t0); 3661 tcg_gen_ext32u_tl(t1, t1); 3662 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3663 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3664 tcg_gen_br(l2); 3665 gen_set_label(l1); 3666 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); 3667 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3668 gen_set_label(l2); 3669 } 3670 break; 3671 case OPC_MOD_G_2E: 3672 case OPC_MOD_G_2F: 3673 { 3674 TCGLabel *l1 = gen_new_label(); 3675 TCGLabel *l2 = gen_new_label(); 3676 TCGLabel *l3 = gen_new_label(); 3677 tcg_gen_ext32u_tl(t0, t0); 3678 tcg_gen_ext32u_tl(t1, t1); 3679 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 3680 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); 3681 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); 3682 gen_set_label(l1); 3683 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3684 tcg_gen_br(l3); 3685 gen_set_label(l2); 3686 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3687 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3688 gen_set_label(l3); 3689 } 3690 break; 3691 case OPC_MODU_G_2E: 3692 case OPC_MODU_G_2F: 3693 { 3694 TCGLabel *l1 = gen_new_label(); 3695 TCGLabel *l2 = gen_new_label(); 3696 tcg_gen_ext32u_tl(t0, t0); 3697 tcg_gen_ext32u_tl(t1, t1); 3698 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3699 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3700 tcg_gen_br(l2); 3701 gen_set_label(l1); 3702 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); 3703 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 3704 gen_set_label(l2); 3705 } 3706 break; 3707 #if defined(TARGET_MIPS64) 3708 case OPC_DMULT_G_2E: 3709 case OPC_DMULT_G_2F: 3710 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3711 break; 3712 case OPC_DMULTU_G_2E: 3713 case OPC_DMULTU_G_2F: 3714 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); 3715 break; 3716 case OPC_DDIV_G_2E: 3717 case OPC_DDIV_G_2F: 3718 { 3719 TCGLabel *l1 = gen_new_label(); 3720 TCGLabel *l2 = gen_new_label(); 3721 TCGLabel *l3 = gen_new_label(); 3722 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3723 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3724 tcg_gen_br(l3); 3725 gen_set_label(l1); 3726 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); 3727 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); 3728 tcg_gen_mov_tl(cpu_gpr[rd], t0); 3729 tcg_gen_br(l3); 3730 gen_set_label(l2); 3731 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); 3732 gen_set_label(l3); 3733 } 3734 break; 3735 case OPC_DDIVU_G_2E: 3736 case OPC_DDIVU_G_2F: 3737 { 3738 TCGLabel *l1 = gen_new_label(); 3739 TCGLabel *l2 = gen_new_label(); 3740 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3741 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3742 tcg_gen_br(l2); 3743 gen_set_label(l1); 3744 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); 3745 gen_set_label(l2); 3746 } 3747 break; 3748 case OPC_DMOD_G_2E: 3749 case OPC_DMOD_G_2F: 3750 { 3751 TCGLabel *l1 = gen_new_label(); 3752 TCGLabel *l2 = gen_new_label(); 3753 TCGLabel *l3 = gen_new_label(); 3754 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 3755 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); 3756 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); 3757 gen_set_label(l1); 3758 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3759 tcg_gen_br(l3); 3760 gen_set_label(l2); 3761 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); 3762 gen_set_label(l3); 3763 } 3764 break; 3765 case OPC_DMODU_G_2E: 3766 case OPC_DMODU_G_2F: 3767 { 3768 TCGLabel *l1 = gen_new_label(); 3769 TCGLabel *l2 = gen_new_label(); 3770 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); 3771 tcg_gen_movi_tl(cpu_gpr[rd], 0); 3772 tcg_gen_br(l2); 3773 gen_set_label(l1); 3774 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); 3775 gen_set_label(l2); 3776 } 3777 break; 3778 #endif 3779 } 3780 } 3781 3782 /* Loongson multimedia instructions */ 3783 static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) 3784 { 3785 uint32_t opc, shift_max; 3786 TCGv_i64 t0, t1; 3787 TCGCond cond; 3788 3789 opc = MASK_LMMI(ctx->opcode); 3790 check_cp1_enabled(ctx); 3791 3792 t0 = tcg_temp_new_i64(); 3793 t1 = tcg_temp_new_i64(); 3794 gen_load_fpr64(ctx, t0, rs); 3795 gen_load_fpr64(ctx, t1, rt); 3796 3797 switch (opc) { 3798 case OPC_PADDSH: 3799 gen_helper_paddsh(t0, t0, t1); 3800 break; 3801 case OPC_PADDUSH: 3802 gen_helper_paddush(t0, t0, t1); 3803 break; 3804 case OPC_PADDH: 3805 gen_helper_paddh(t0, t0, t1); 3806 break; 3807 case OPC_PADDW: 3808 gen_helper_paddw(t0, t0, t1); 3809 break; 3810 case OPC_PADDSB: 3811 gen_helper_paddsb(t0, t0, t1); 3812 break; 3813 case OPC_PADDUSB: 3814 gen_helper_paddusb(t0, t0, t1); 3815 break; 3816 case OPC_PADDB: 3817 gen_helper_paddb(t0, t0, t1); 3818 break; 3819 3820 case OPC_PSUBSH: 3821 gen_helper_psubsh(t0, t0, t1); 3822 break; 3823 case OPC_PSUBUSH: 3824 gen_helper_psubush(t0, t0, t1); 3825 break; 3826 case OPC_PSUBH: 3827 gen_helper_psubh(t0, t0, t1); 3828 break; 3829 case OPC_PSUBW: 3830 gen_helper_psubw(t0, t0, t1); 3831 break; 3832 case OPC_PSUBSB: 3833 gen_helper_psubsb(t0, t0, t1); 3834 break; 3835 case OPC_PSUBUSB: 3836 gen_helper_psubusb(t0, t0, t1); 3837 break; 3838 case OPC_PSUBB: 3839 gen_helper_psubb(t0, t0, t1); 3840 break; 3841 3842 case OPC_PSHUFH: 3843 gen_helper_pshufh(t0, t0, t1); 3844 break; 3845 case OPC_PACKSSWH: 3846 gen_helper_packsswh(t0, t0, t1); 3847 break; 3848 case OPC_PACKSSHB: 3849 gen_helper_packsshb(t0, t0, t1); 3850 break; 3851 case OPC_PACKUSHB: 3852 gen_helper_packushb(t0, t0, t1); 3853 break; 3854 3855 case OPC_PUNPCKLHW: 3856 gen_helper_punpcklhw(t0, t0, t1); 3857 break; 3858 case OPC_PUNPCKHHW: 3859 gen_helper_punpckhhw(t0, t0, t1); 3860 break; 3861 case OPC_PUNPCKLBH: 3862 gen_helper_punpcklbh(t0, t0, t1); 3863 break; 3864 case OPC_PUNPCKHBH: 3865 gen_helper_punpckhbh(t0, t0, t1); 3866 break; 3867 case OPC_PUNPCKLWD: 3868 gen_helper_punpcklwd(t0, t0, t1); 3869 break; 3870 case OPC_PUNPCKHWD: 3871 gen_helper_punpckhwd(t0, t0, t1); 3872 break; 3873 3874 case OPC_PAVGH: 3875 gen_helper_pavgh(t0, t0, t1); 3876 break; 3877 case OPC_PAVGB: 3878 gen_helper_pavgb(t0, t0, t1); 3879 break; 3880 case OPC_PMAXSH: 3881 gen_helper_pmaxsh(t0, t0, t1); 3882 break; 3883 case OPC_PMINSH: 3884 gen_helper_pminsh(t0, t0, t1); 3885 break; 3886 case OPC_PMAXUB: 3887 gen_helper_pmaxub(t0, t0, t1); 3888 break; 3889 case OPC_PMINUB: 3890 gen_helper_pminub(t0, t0, t1); 3891 break; 3892 3893 case OPC_PCMPEQW: 3894 gen_helper_pcmpeqw(t0, t0, t1); 3895 break; 3896 case OPC_PCMPGTW: 3897 gen_helper_pcmpgtw(t0, t0, t1); 3898 break; 3899 case OPC_PCMPEQH: 3900 gen_helper_pcmpeqh(t0, t0, t1); 3901 break; 3902 case OPC_PCMPGTH: 3903 gen_helper_pcmpgth(t0, t0, t1); 3904 break; 3905 case OPC_PCMPEQB: 3906 gen_helper_pcmpeqb(t0, t0, t1); 3907 break; 3908 case OPC_PCMPGTB: 3909 gen_helper_pcmpgtb(t0, t0, t1); 3910 break; 3911 3912 case OPC_PSLLW: 3913 gen_helper_psllw(t0, t0, t1); 3914 break; 3915 case OPC_PSLLH: 3916 gen_helper_psllh(t0, t0, t1); 3917 break; 3918 case OPC_PSRLW: 3919 gen_helper_psrlw(t0, t0, t1); 3920 break; 3921 case OPC_PSRLH: 3922 gen_helper_psrlh(t0, t0, t1); 3923 break; 3924 case OPC_PSRAW: 3925 gen_helper_psraw(t0, t0, t1); 3926 break; 3927 case OPC_PSRAH: 3928 gen_helper_psrah(t0, t0, t1); 3929 break; 3930 3931 case OPC_PMULLH: 3932 gen_helper_pmullh(t0, t0, t1); 3933 break; 3934 case OPC_PMULHH: 3935 gen_helper_pmulhh(t0, t0, t1); 3936 break; 3937 case OPC_PMULHUH: 3938 gen_helper_pmulhuh(t0, t0, t1); 3939 break; 3940 case OPC_PMADDHW: 3941 gen_helper_pmaddhw(t0, t0, t1); 3942 break; 3943 3944 case OPC_PASUBUB: 3945 gen_helper_pasubub(t0, t0, t1); 3946 break; 3947 case OPC_BIADD: 3948 gen_helper_biadd(t0, t0); 3949 break; 3950 case OPC_PMOVMSKB: 3951 gen_helper_pmovmskb(t0, t0); 3952 break; 3953 3954 case OPC_PADDD: 3955 tcg_gen_add_i64(t0, t0, t1); 3956 break; 3957 case OPC_PSUBD: 3958 tcg_gen_sub_i64(t0, t0, t1); 3959 break; 3960 case OPC_XOR_CP2: 3961 tcg_gen_xor_i64(t0, t0, t1); 3962 break; 3963 case OPC_NOR_CP2: 3964 tcg_gen_nor_i64(t0, t0, t1); 3965 break; 3966 case OPC_AND_CP2: 3967 tcg_gen_and_i64(t0, t0, t1); 3968 break; 3969 case OPC_OR_CP2: 3970 tcg_gen_or_i64(t0, t0, t1); 3971 break; 3972 3973 case OPC_PANDN: 3974 tcg_gen_andc_i64(t0, t1, t0); 3975 break; 3976 3977 case OPC_PINSRH_0: 3978 tcg_gen_deposit_i64(t0, t0, t1, 0, 16); 3979 break; 3980 case OPC_PINSRH_1: 3981 tcg_gen_deposit_i64(t0, t0, t1, 16, 16); 3982 break; 3983 case OPC_PINSRH_2: 3984 tcg_gen_deposit_i64(t0, t0, t1, 32, 16); 3985 break; 3986 case OPC_PINSRH_3: 3987 tcg_gen_deposit_i64(t0, t0, t1, 48, 16); 3988 break; 3989 3990 case OPC_PEXTRH: 3991 tcg_gen_andi_i64(t1, t1, 3); 3992 tcg_gen_shli_i64(t1, t1, 4); 3993 tcg_gen_shr_i64(t0, t0, t1); 3994 tcg_gen_ext16u_i64(t0, t0); 3995 break; 3996 3997 case OPC_ADDU_CP2: 3998 tcg_gen_add_i64(t0, t0, t1); 3999 tcg_gen_ext32s_i64(t0, t0); 4000 break; 4001 case OPC_SUBU_CP2: 4002 tcg_gen_sub_i64(t0, t0, t1); 4003 tcg_gen_ext32s_i64(t0, t0); 4004 break; 4005 4006 case OPC_SLL_CP2: 4007 shift_max = 32; 4008 goto do_shift; 4009 case OPC_SRL_CP2: 4010 shift_max = 32; 4011 goto do_shift; 4012 case OPC_SRA_CP2: 4013 shift_max = 32; 4014 goto do_shift; 4015 case OPC_DSLL_CP2: 4016 shift_max = 64; 4017 goto do_shift; 4018 case OPC_DSRL_CP2: 4019 shift_max = 64; 4020 goto do_shift; 4021 case OPC_DSRA_CP2: 4022 shift_max = 64; 4023 goto do_shift; 4024 do_shift: 4025 /* Make sure shift count isn't TCG undefined behaviour. */ 4026 tcg_gen_andi_i64(t1, t1, shift_max - 1); 4027 4028 switch (opc) { 4029 case OPC_SLL_CP2: 4030 case OPC_DSLL_CP2: 4031 tcg_gen_shl_i64(t0, t0, t1); 4032 break; 4033 case OPC_SRA_CP2: 4034 case OPC_DSRA_CP2: 4035 /* 4036 * Since SRA is UndefinedResult without sign-extended inputs, 4037 * we can treat SRA and DSRA the same. 4038 */ 4039 tcg_gen_sar_i64(t0, t0, t1); 4040 break; 4041 case OPC_SRL_CP2: 4042 /* We want to shift in zeros for SRL; zero-extend first. */ 4043 tcg_gen_ext32u_i64(t0, t0); 4044 /* FALLTHRU */ 4045 case OPC_DSRL_CP2: 4046 tcg_gen_shr_i64(t0, t0, t1); 4047 break; 4048 } 4049 4050 if (shift_max == 32) { 4051 tcg_gen_ext32s_i64(t0, t0); 4052 } 4053 4054 /* Shifts larger than MAX produce zero. */ 4055 tcg_gen_setcondi_i64(TCG_COND_LTU, t1, t1, shift_max); 4056 tcg_gen_neg_i64(t1, t1); 4057 tcg_gen_and_i64(t0, t0, t1); 4058 break; 4059 4060 case OPC_ADD_CP2: 4061 case OPC_DADD_CP2: 4062 { 4063 TCGv_i64 t2 = tcg_temp_new_i64(); 4064 TCGLabel *lab = gen_new_label(); 4065 4066 tcg_gen_mov_i64(t2, t0); 4067 tcg_gen_add_i64(t0, t1, t2); 4068 if (opc == OPC_ADD_CP2) { 4069 tcg_gen_ext32s_i64(t0, t0); 4070 } 4071 tcg_gen_xor_i64(t1, t1, t2); 4072 tcg_gen_xor_i64(t2, t2, t0); 4073 tcg_gen_andc_i64(t1, t2, t1); 4074 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); 4075 generate_exception(ctx, EXCP_OVERFLOW); 4076 gen_set_label(lab); 4077 break; 4078 } 4079 4080 case OPC_SUB_CP2: 4081 case OPC_DSUB_CP2: 4082 { 4083 TCGv_i64 t2 = tcg_temp_new_i64(); 4084 TCGLabel *lab = gen_new_label(); 4085 4086 tcg_gen_mov_i64(t2, t0); 4087 tcg_gen_sub_i64(t0, t1, t2); 4088 if (opc == OPC_SUB_CP2) { 4089 tcg_gen_ext32s_i64(t0, t0); 4090 } 4091 tcg_gen_xor_i64(t1, t1, t2); 4092 tcg_gen_xor_i64(t2, t2, t0); 4093 tcg_gen_and_i64(t1, t1, t2); 4094 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); 4095 generate_exception(ctx, EXCP_OVERFLOW); 4096 gen_set_label(lab); 4097 break; 4098 } 4099 4100 case OPC_PMULUW: 4101 tcg_gen_ext32u_i64(t0, t0); 4102 tcg_gen_ext32u_i64(t1, t1); 4103 tcg_gen_mul_i64(t0, t0, t1); 4104 break; 4105 4106 case OPC_SEQU_CP2: 4107 case OPC_SEQ_CP2: 4108 cond = TCG_COND_EQ; 4109 goto do_cc_cond; 4110 break; 4111 case OPC_SLTU_CP2: 4112 cond = TCG_COND_LTU; 4113 goto do_cc_cond; 4114 break; 4115 case OPC_SLT_CP2: 4116 cond = TCG_COND_LT; 4117 goto do_cc_cond; 4118 break; 4119 case OPC_SLEU_CP2: 4120 cond = TCG_COND_LEU; 4121 goto do_cc_cond; 4122 break; 4123 case OPC_SLE_CP2: 4124 cond = TCG_COND_LE; 4125 do_cc_cond: 4126 { 4127 int cc = (ctx->opcode >> 8) & 0x7; 4128 TCGv_i64 t64 = tcg_temp_new_i64(); 4129 TCGv_i32 t32 = tcg_temp_new_i32(); 4130 4131 tcg_gen_setcond_i64(cond, t64, t0, t1); 4132 tcg_gen_extrl_i64_i32(t32, t64); 4133 tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32, 4134 get_fp_bit(cc), 1); 4135 } 4136 return; 4137 default: 4138 MIPS_INVAL("loongson_cp2"); 4139 gen_reserved_instruction(ctx); 4140 return; 4141 } 4142 4143 gen_store_fpr64(ctx, t0, rd); 4144 } 4145 4146 static void gen_loongson_lswc2(DisasContext *ctx, int rt, 4147 int rs, int rd) 4148 { 4149 TCGv t0, t1; 4150 TCGv_i32 fp0; 4151 #if defined(TARGET_MIPS64) 4152 int lsq_rt1 = ctx->opcode & 0x1f; 4153 int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4; 4154 #endif 4155 int shf_offset = sextract32(ctx->opcode, 6, 8); 4156 4157 t0 = tcg_temp_new(); 4158 4159 switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) { 4160 #if defined(TARGET_MIPS64) 4161 case OPC_GSLQ: 4162 t1 = tcg_temp_new(); 4163 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4164 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4165 ctx->default_tcg_memop_mask); 4166 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4167 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | 4168 ctx->default_tcg_memop_mask); 4169 gen_store_gpr(t1, rt); 4170 gen_store_gpr(t0, lsq_rt1); 4171 break; 4172 case OPC_GSLQC1: 4173 check_cp1_enabled(ctx); 4174 t1 = tcg_temp_new(); 4175 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4176 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4177 ctx->default_tcg_memop_mask); 4178 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4179 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | 4180 ctx->default_tcg_memop_mask); 4181 gen_store_fpr64(ctx, t1, rt); 4182 gen_store_fpr64(ctx, t0, lsq_rt1); 4183 break; 4184 case OPC_GSSQ: 4185 t1 = tcg_temp_new(); 4186 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4187 gen_load_gpr(t1, rt); 4188 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4189 ctx->default_tcg_memop_mask); 4190 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4191 gen_load_gpr(t1, lsq_rt1); 4192 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4193 ctx->default_tcg_memop_mask); 4194 break; 4195 case OPC_GSSQC1: 4196 check_cp1_enabled(ctx); 4197 t1 = tcg_temp_new(); 4198 gen_base_offset_addr(ctx, t0, rs, lsq_offset); 4199 gen_load_fpr64(ctx, t1, rt); 4200 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4201 ctx->default_tcg_memop_mask); 4202 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); 4203 gen_load_fpr64(ctx, t1, lsq_rt1); 4204 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4205 ctx->default_tcg_memop_mask); 4206 break; 4207 #endif 4208 case OPC_GSSHFL: 4209 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { 4210 case OPC_GSLWLC1: 4211 check_cp1_enabled(ctx); 4212 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4213 fp0 = tcg_temp_new_i32(); 4214 gen_load_fpr32(ctx, fp0, rt); 4215 t1 = tcg_temp_new(); 4216 tcg_gen_ext_i32_tl(t1, fp0); 4217 gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUL); 4218 tcg_gen_trunc_tl_i32(fp0, t1); 4219 gen_store_fpr32(ctx, fp0, rt); 4220 break; 4221 case OPC_GSLWRC1: 4222 check_cp1_enabled(ctx); 4223 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4224 fp0 = tcg_temp_new_i32(); 4225 gen_load_fpr32(ctx, fp0, rt); 4226 t1 = tcg_temp_new(); 4227 tcg_gen_ext_i32_tl(t1, fp0); 4228 gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUL); 4229 tcg_gen_trunc_tl_i32(fp0, t1); 4230 gen_store_fpr32(ctx, fp0, rt); 4231 break; 4232 #if defined(TARGET_MIPS64) 4233 case OPC_GSLDLC1: 4234 check_cp1_enabled(ctx); 4235 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4236 t1 = tcg_temp_new(); 4237 gen_load_fpr64(ctx, t1, rt); 4238 gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUQ); 4239 gen_store_fpr64(ctx, t1, rt); 4240 break; 4241 case OPC_GSLDRC1: 4242 check_cp1_enabled(ctx); 4243 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4244 t1 = tcg_temp_new(); 4245 gen_load_fpr64(ctx, t1, rt); 4246 gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUQ); 4247 gen_store_fpr64(ctx, t1, rt); 4248 break; 4249 #endif 4250 default: 4251 MIPS_INVAL("loongson_gsshfl"); 4252 gen_reserved_instruction(ctx); 4253 break; 4254 } 4255 break; 4256 case OPC_GSSHFS: 4257 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { 4258 case OPC_GSSWLC1: 4259 check_cp1_enabled(ctx); 4260 t1 = tcg_temp_new(); 4261 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4262 fp0 = tcg_temp_new_i32(); 4263 gen_load_fpr32(ctx, fp0, rt); 4264 tcg_gen_ext_i32_tl(t1, fp0); 4265 gen_helper_0e2i(swl, t1, t0, ctx->mem_idx); 4266 break; 4267 case OPC_GSSWRC1: 4268 check_cp1_enabled(ctx); 4269 t1 = tcg_temp_new(); 4270 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4271 fp0 = tcg_temp_new_i32(); 4272 gen_load_fpr32(ctx, fp0, rt); 4273 tcg_gen_ext_i32_tl(t1, fp0); 4274 gen_helper_0e2i(swr, t1, t0, ctx->mem_idx); 4275 break; 4276 #if defined(TARGET_MIPS64) 4277 case OPC_GSSDLC1: 4278 check_cp1_enabled(ctx); 4279 t1 = tcg_temp_new(); 4280 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4281 gen_load_fpr64(ctx, t1, rt); 4282 gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx); 4283 break; 4284 case OPC_GSSDRC1: 4285 check_cp1_enabled(ctx); 4286 t1 = tcg_temp_new(); 4287 gen_base_offset_addr(ctx, t0, rs, shf_offset); 4288 gen_load_fpr64(ctx, t1, rt); 4289 gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx); 4290 break; 4291 #endif 4292 default: 4293 MIPS_INVAL("loongson_gsshfs"); 4294 gen_reserved_instruction(ctx); 4295 break; 4296 } 4297 break; 4298 default: 4299 MIPS_INVAL("loongson_gslsq"); 4300 gen_reserved_instruction(ctx); 4301 break; 4302 } 4303 } 4304 4305 /* Loongson EXT LDC2/SDC2 */ 4306 static void gen_loongson_lsdc2(DisasContext *ctx, int rt, 4307 int rs, int rd) 4308 { 4309 int offset = sextract32(ctx->opcode, 3, 8); 4310 uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode); 4311 TCGv t0, t1; 4312 TCGv_i32 fp0; 4313 4314 /* Pre-conditions */ 4315 switch (opc) { 4316 case OPC_GSLBX: 4317 case OPC_GSLHX: 4318 case OPC_GSLWX: 4319 case OPC_GSLDX: 4320 /* prefetch, implement as NOP */ 4321 if (rt == 0) { 4322 return; 4323 } 4324 break; 4325 case OPC_GSSBX: 4326 case OPC_GSSHX: 4327 case OPC_GSSWX: 4328 case OPC_GSSDX: 4329 break; 4330 case OPC_GSLWXC1: 4331 #if defined(TARGET_MIPS64) 4332 case OPC_GSLDXC1: 4333 #endif 4334 check_cp1_enabled(ctx); 4335 /* prefetch, implement as NOP */ 4336 if (rt == 0) { 4337 return; 4338 } 4339 break; 4340 case OPC_GSSWXC1: 4341 #if defined(TARGET_MIPS64) 4342 case OPC_GSSDXC1: 4343 #endif 4344 check_cp1_enabled(ctx); 4345 break; 4346 default: 4347 MIPS_INVAL("loongson_lsdc2"); 4348 gen_reserved_instruction(ctx); 4349 return; 4350 break; 4351 } 4352 4353 t0 = tcg_temp_new(); 4354 4355 gen_base_offset_addr(ctx, t0, rs, offset); 4356 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4357 4358 switch (opc) { 4359 case OPC_GSLBX: 4360 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB); 4361 gen_store_gpr(t0, rt); 4362 break; 4363 case OPC_GSLHX: 4364 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW | 4365 ctx->default_tcg_memop_mask); 4366 gen_store_gpr(t0, rt); 4367 break; 4368 case OPC_GSLWX: 4369 gen_base_offset_addr(ctx, t0, rs, offset); 4370 if (rd) { 4371 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4372 } 4373 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL | 4374 ctx->default_tcg_memop_mask); 4375 gen_store_gpr(t0, rt); 4376 break; 4377 #if defined(TARGET_MIPS64) 4378 case OPC_GSLDX: 4379 gen_base_offset_addr(ctx, t0, rs, offset); 4380 if (rd) { 4381 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4382 } 4383 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | 4384 ctx->default_tcg_memop_mask); 4385 gen_store_gpr(t0, rt); 4386 break; 4387 #endif 4388 case OPC_GSLWXC1: 4389 gen_base_offset_addr(ctx, t0, rs, offset); 4390 if (rd) { 4391 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4392 } 4393 fp0 = tcg_temp_new_i32(); 4394 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | 4395 ctx->default_tcg_memop_mask); 4396 gen_store_fpr32(ctx, fp0, rt); 4397 break; 4398 #if defined(TARGET_MIPS64) 4399 case OPC_GSLDXC1: 4400 gen_base_offset_addr(ctx, t0, rs, offset); 4401 if (rd) { 4402 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0); 4403 } 4404 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ | 4405 ctx->default_tcg_memop_mask); 4406 gen_store_fpr64(ctx, t0, rt); 4407 break; 4408 #endif 4409 case OPC_GSSBX: 4410 t1 = tcg_temp_new(); 4411 gen_load_gpr(t1, rt); 4412 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB); 4413 break; 4414 case OPC_GSSHX: 4415 t1 = tcg_temp_new(); 4416 gen_load_gpr(t1, rt); 4417 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW | 4418 ctx->default_tcg_memop_mask); 4419 break; 4420 case OPC_GSSWX: 4421 t1 = tcg_temp_new(); 4422 gen_load_gpr(t1, rt); 4423 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | 4424 ctx->default_tcg_memop_mask); 4425 break; 4426 #if defined(TARGET_MIPS64) 4427 case OPC_GSSDX: 4428 t1 = tcg_temp_new(); 4429 gen_load_gpr(t1, rt); 4430 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | 4431 ctx->default_tcg_memop_mask); 4432 break; 4433 #endif 4434 case OPC_GSSWXC1: 4435 fp0 = tcg_temp_new_i32(); 4436 gen_load_fpr32(ctx, fp0, rt); 4437 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | 4438 ctx->default_tcg_memop_mask); 4439 break; 4440 #if defined(TARGET_MIPS64) 4441 case OPC_GSSDXC1: 4442 t1 = tcg_temp_new(); 4443 gen_load_fpr64(ctx, t1, rt); 4444 tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEUQ | 4445 ctx->default_tcg_memop_mask); 4446 break; 4447 #endif 4448 default: 4449 break; 4450 } 4451 } 4452 4453 /* Traps */ 4454 static void gen_trap(DisasContext *ctx, uint32_t opc, 4455 int rs, int rt, int16_t imm, int code) 4456 { 4457 int cond; 4458 TCGv t0 = tcg_temp_new(); 4459 TCGv t1 = tcg_temp_new(); 4460 4461 cond = 0; 4462 /* Load needed operands */ 4463 switch (opc) { 4464 case OPC_TEQ: 4465 case OPC_TGE: 4466 case OPC_TGEU: 4467 case OPC_TLT: 4468 case OPC_TLTU: 4469 case OPC_TNE: 4470 /* Compare two registers */ 4471 if (rs != rt) { 4472 gen_load_gpr(t0, rs); 4473 gen_load_gpr(t1, rt); 4474 cond = 1; 4475 } 4476 break; 4477 case OPC_TEQI: 4478 case OPC_TGEI: 4479 case OPC_TGEIU: 4480 case OPC_TLTI: 4481 case OPC_TLTIU: 4482 case OPC_TNEI: 4483 /* Compare register to immediate */ 4484 if (rs != 0 || imm != 0) { 4485 gen_load_gpr(t0, rs); 4486 tcg_gen_movi_tl(t1, (int32_t)imm); 4487 cond = 1; 4488 } 4489 break; 4490 } 4491 if (cond == 0) { 4492 switch (opc) { 4493 case OPC_TEQ: /* rs == rs */ 4494 case OPC_TEQI: /* r0 == 0 */ 4495 case OPC_TGE: /* rs >= rs */ 4496 case OPC_TGEI: /* r0 >= 0 */ 4497 case OPC_TGEU: /* rs >= rs unsigned */ 4498 case OPC_TGEIU: /* r0 >= 0 unsigned */ 4499 /* Always trap */ 4500 #ifdef CONFIG_USER_ONLY 4501 /* Pass the break code along to cpu_loop. */ 4502 tcg_gen_st_i32(tcg_constant_i32(code), tcg_env, 4503 offsetof(CPUMIPSState, error_code)); 4504 #endif 4505 generate_exception_end(ctx, EXCP_TRAP); 4506 break; 4507 case OPC_TLT: /* rs < rs */ 4508 case OPC_TLTI: /* r0 < 0 */ 4509 case OPC_TLTU: /* rs < rs unsigned */ 4510 case OPC_TLTIU: /* r0 < 0 unsigned */ 4511 case OPC_TNE: /* rs != rs */ 4512 case OPC_TNEI: /* r0 != 0 */ 4513 /* Never trap: treat as NOP. */ 4514 break; 4515 } 4516 } else { 4517 TCGLabel *l1 = gen_new_label(); 4518 4519 switch (opc) { 4520 case OPC_TEQ: 4521 case OPC_TEQI: 4522 tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1); 4523 break; 4524 case OPC_TGE: 4525 case OPC_TGEI: 4526 tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1); 4527 break; 4528 case OPC_TGEU: 4529 case OPC_TGEIU: 4530 tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1); 4531 break; 4532 case OPC_TLT: 4533 case OPC_TLTI: 4534 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 4535 break; 4536 case OPC_TLTU: 4537 case OPC_TLTIU: 4538 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 4539 break; 4540 case OPC_TNE: 4541 case OPC_TNEI: 4542 tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1); 4543 break; 4544 } 4545 #ifdef CONFIG_USER_ONLY 4546 /* Pass the break code along to cpu_loop. */ 4547 tcg_gen_st_i32(tcg_constant_i32(code), tcg_env, 4548 offsetof(CPUMIPSState, error_code)); 4549 #endif 4550 /* Like save_cpu_state, only don't update saved values. */ 4551 if (ctx->base.pc_next != ctx->saved_pc) { 4552 gen_save_pc(ctx->base.pc_next); 4553 } 4554 if (ctx->hflags != ctx->saved_hflags) { 4555 tcg_gen_movi_i32(hflags, ctx->hflags); 4556 } 4557 generate_exception(ctx, EXCP_TRAP); 4558 gen_set_label(l1); 4559 } 4560 } 4561 4562 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4563 { 4564 if (translator_use_goto_tb(&ctx->base, dest)) { 4565 tcg_gen_goto_tb(n); 4566 gen_save_pc(dest); 4567 tcg_gen_exit_tb(ctx->base.tb, n); 4568 } else { 4569 gen_save_pc(dest); 4570 tcg_gen_lookup_and_goto_ptr(); 4571 } 4572 } 4573 4574 /* Branches (before delay slot) */ 4575 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, 4576 int insn_bytes, 4577 int rs, int rt, int32_t offset, 4578 int delayslot_size) 4579 { 4580 target_ulong btgt = -1; 4581 int blink = 0; 4582 int bcond_compute = 0; 4583 TCGv t0 = tcg_temp_new(); 4584 TCGv t1 = tcg_temp_new(); 4585 4586 if (ctx->hflags & MIPS_HFLAG_BMASK) { 4587 #ifdef MIPS_DEBUG_DISAS 4588 LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" 4589 VADDR_PRIx "\n", ctx->base.pc_next); 4590 #endif 4591 gen_reserved_instruction(ctx); 4592 goto out; 4593 } 4594 4595 /* Load needed operands */ 4596 switch (opc) { 4597 case OPC_BEQ: 4598 case OPC_BEQL: 4599 case OPC_BNE: 4600 case OPC_BNEL: 4601 /* Compare two registers */ 4602 if (rs != rt) { 4603 gen_load_gpr(t0, rs); 4604 gen_load_gpr(t1, rt); 4605 bcond_compute = 1; 4606 } 4607 btgt = ctx->base.pc_next + insn_bytes + offset; 4608 break; 4609 case OPC_BGEZ: 4610 case OPC_BGEZAL: 4611 case OPC_BGEZALL: 4612 case OPC_BGEZL: 4613 case OPC_BGTZ: 4614 case OPC_BGTZL: 4615 case OPC_BLEZ: 4616 case OPC_BLEZL: 4617 case OPC_BLTZ: 4618 case OPC_BLTZAL: 4619 case OPC_BLTZALL: 4620 case OPC_BLTZL: 4621 /* Compare to zero */ 4622 if (rs != 0) { 4623 gen_load_gpr(t0, rs); 4624 bcond_compute = 1; 4625 } 4626 btgt = ctx->base.pc_next + insn_bytes + offset; 4627 break; 4628 case OPC_BPOSGE32: 4629 #if defined(TARGET_MIPS64) 4630 case OPC_BPOSGE64: 4631 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F); 4632 #else 4633 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F); 4634 #endif 4635 bcond_compute = 1; 4636 btgt = ctx->base.pc_next + insn_bytes + offset; 4637 break; 4638 case OPC_J: 4639 case OPC_JAL: 4640 { 4641 /* Jump to immediate */ 4642 int jal_mask = ctx->hflags & MIPS_HFLAG_M16 ? 0xF8000000 4643 : 0xF0000000; 4644 btgt = ((ctx->base.pc_next + insn_bytes) & jal_mask) 4645 | (uint32_t)offset; 4646 break; 4647 } 4648 case OPC_JALX: 4649 /* Jump to immediate */ 4650 btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) | 4651 (uint32_t)offset; 4652 break; 4653 case OPC_JR: 4654 case OPC_JALR: 4655 /* Jump to register */ 4656 if (offset != 0 && offset != 16) { 4657 /* 4658 * Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the 4659 * others are reserved. 4660 */ 4661 MIPS_INVAL("jump hint"); 4662 gen_reserved_instruction(ctx); 4663 goto out; 4664 } 4665 gen_load_gpr(btarget, rs); 4666 break; 4667 default: 4668 MIPS_INVAL("branch/jump"); 4669 gen_reserved_instruction(ctx); 4670 goto out; 4671 } 4672 if (bcond_compute == 0) { 4673 /* No condition to be computed */ 4674 switch (opc) { 4675 case OPC_BEQ: /* rx == rx */ 4676 case OPC_BEQL: /* rx == rx likely */ 4677 case OPC_BGEZ: /* 0 >= 0 */ 4678 case OPC_BGEZL: /* 0 >= 0 likely */ 4679 case OPC_BLEZ: /* 0 <= 0 */ 4680 case OPC_BLEZL: /* 0 <= 0 likely */ 4681 /* Always take */ 4682 ctx->hflags |= MIPS_HFLAG_B; 4683 break; 4684 case OPC_BGEZAL: /* 0 >= 0 */ 4685 case OPC_BGEZALL: /* 0 >= 0 likely */ 4686 /* Always take and link */ 4687 blink = 31; 4688 ctx->hflags |= MIPS_HFLAG_B; 4689 break; 4690 case OPC_BNE: /* rx != rx */ 4691 case OPC_BGTZ: /* 0 > 0 */ 4692 case OPC_BLTZ: /* 0 < 0 */ 4693 /* Treat as NOP. */ 4694 goto out; 4695 case OPC_BLTZAL: /* 0 < 0 */ 4696 /* 4697 * Handle as an unconditional branch to get correct delay 4698 * slot checking. 4699 */ 4700 blink = 31; 4701 btgt = ctx->base.pc_next + insn_bytes + delayslot_size; 4702 ctx->hflags |= MIPS_HFLAG_B; 4703 break; 4704 case OPC_BLTZALL: /* 0 < 0 likely */ 4705 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8); 4706 /* Skip the instruction in the delay slot */ 4707 ctx->base.pc_next += 4; 4708 goto out; 4709 case OPC_BNEL: /* rx != rx likely */ 4710 case OPC_BGTZL: /* 0 > 0 likely */ 4711 case OPC_BLTZL: /* 0 < 0 likely */ 4712 /* Skip the instruction in the delay slot */ 4713 ctx->base.pc_next += 4; 4714 goto out; 4715 case OPC_J: 4716 ctx->hflags |= MIPS_HFLAG_B; 4717 break; 4718 case OPC_JALX: 4719 ctx->hflags |= MIPS_HFLAG_BX; 4720 /* Fallthrough */ 4721 case OPC_JAL: 4722 blink = 31; 4723 ctx->hflags |= MIPS_HFLAG_B; 4724 break; 4725 case OPC_JR: 4726 ctx->hflags |= MIPS_HFLAG_BR; 4727 break; 4728 case OPC_JALR: 4729 blink = rt; 4730 ctx->hflags |= MIPS_HFLAG_BR; 4731 break; 4732 default: 4733 MIPS_INVAL("branch/jump"); 4734 gen_reserved_instruction(ctx); 4735 goto out; 4736 } 4737 } else { 4738 switch (opc) { 4739 case OPC_BEQ: 4740 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1); 4741 goto not_likely; 4742 case OPC_BEQL: 4743 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1); 4744 goto likely; 4745 case OPC_BNE: 4746 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1); 4747 goto not_likely; 4748 case OPC_BNEL: 4749 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1); 4750 goto likely; 4751 case OPC_BGEZ: 4752 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4753 goto not_likely; 4754 case OPC_BGEZL: 4755 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4756 goto likely; 4757 case OPC_BGEZAL: 4758 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4759 blink = 31; 4760 goto not_likely; 4761 case OPC_BGEZALL: 4762 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); 4763 blink = 31; 4764 goto likely; 4765 case OPC_BGTZ: 4766 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0); 4767 goto not_likely; 4768 case OPC_BGTZL: 4769 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0); 4770 goto likely; 4771 case OPC_BLEZ: 4772 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0); 4773 goto not_likely; 4774 case OPC_BLEZL: 4775 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0); 4776 goto likely; 4777 case OPC_BLTZ: 4778 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4779 goto not_likely; 4780 case OPC_BLTZL: 4781 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4782 goto likely; 4783 case OPC_BPOSGE32: 4784 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32); 4785 goto not_likely; 4786 #if defined(TARGET_MIPS64) 4787 case OPC_BPOSGE64: 4788 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64); 4789 goto not_likely; 4790 #endif 4791 case OPC_BLTZAL: 4792 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4793 blink = 31; 4794 not_likely: 4795 ctx->hflags |= MIPS_HFLAG_BC; 4796 break; 4797 case OPC_BLTZALL: 4798 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); 4799 blink = 31; 4800 likely: 4801 ctx->hflags |= MIPS_HFLAG_BL; 4802 break; 4803 default: 4804 MIPS_INVAL("conditional branch/jump"); 4805 gen_reserved_instruction(ctx); 4806 goto out; 4807 } 4808 } 4809 4810 ctx->btarget = btgt; 4811 4812 switch (delayslot_size) { 4813 case 2: 4814 ctx->hflags |= MIPS_HFLAG_BDS16; 4815 break; 4816 case 4: 4817 ctx->hflags |= MIPS_HFLAG_BDS32; 4818 break; 4819 } 4820 4821 if (blink > 0) { 4822 int post_delay = insn_bytes + delayslot_size; 4823 int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16); 4824 4825 tcg_gen_movi_tl(cpu_gpr[blink], 4826 ctx->base.pc_next + post_delay + lowbit); 4827 } 4828 4829 out: 4830 if (insn_bytes == 2) { 4831 ctx->hflags |= MIPS_HFLAG_B16; 4832 } 4833 } 4834 4835 4836 /* special3 bitfield operations */ 4837 static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt, 4838 int rs, int lsb, int msb) 4839 { 4840 TCGv t0 = tcg_temp_new(); 4841 TCGv t1 = tcg_temp_new(); 4842 4843 gen_load_gpr(t1, rs); 4844 switch (opc) { 4845 case OPC_EXT: 4846 if (lsb + msb > 31) { 4847 goto fail; 4848 } 4849 if (msb != 31) { 4850 tcg_gen_extract_tl(t0, t1, lsb, msb + 1); 4851 } else { 4852 /* 4853 * The two checks together imply that lsb == 0, 4854 * so this is a simple sign-extension. 4855 */ 4856 tcg_gen_ext32s_tl(t0, t1); 4857 } 4858 break; 4859 #if defined(TARGET_MIPS64) 4860 case OPC_DEXTU: 4861 lsb += 32; 4862 goto do_dext; 4863 case OPC_DEXTM: 4864 msb += 32; 4865 goto do_dext; 4866 case OPC_DEXT: 4867 do_dext: 4868 if (lsb + msb > 63) { 4869 goto fail; 4870 } 4871 tcg_gen_extract_tl(t0, t1, lsb, msb + 1); 4872 break; 4873 #endif 4874 case OPC_INS: 4875 if (lsb > msb) { 4876 goto fail; 4877 } 4878 gen_load_gpr(t0, rt); 4879 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); 4880 tcg_gen_ext32s_tl(t0, t0); 4881 break; 4882 #if defined(TARGET_MIPS64) 4883 case OPC_DINSU: 4884 lsb += 32; 4885 /* FALLTHRU */ 4886 case OPC_DINSM: 4887 msb += 32; 4888 /* FALLTHRU */ 4889 case OPC_DINS: 4890 if (lsb > msb) { 4891 goto fail; 4892 } 4893 gen_load_gpr(t0, rt); 4894 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); 4895 break; 4896 #endif 4897 default: 4898 fail: 4899 MIPS_INVAL("bitops"); 4900 gen_reserved_instruction(ctx); 4901 return; 4902 } 4903 gen_store_gpr(t0, rt); 4904 } 4905 4906 static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd) 4907 { 4908 TCGv t0; 4909 4910 if (rd == 0) { 4911 /* If no destination, treat it as a NOP. */ 4912 return; 4913 } 4914 4915 t0 = tcg_temp_new(); 4916 gen_load_gpr(t0, rt); 4917 switch (op2) { 4918 case OPC_WSBH: 4919 { 4920 TCGv t1 = tcg_temp_new(); 4921 TCGv t2 = tcg_constant_tl(0x00FF00FF); 4922 4923 tcg_gen_shri_tl(t1, t0, 8); 4924 tcg_gen_and_tl(t1, t1, t2); 4925 tcg_gen_and_tl(t0, t0, t2); 4926 tcg_gen_shli_tl(t0, t0, 8); 4927 tcg_gen_or_tl(t0, t0, t1); 4928 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 4929 } 4930 break; 4931 case OPC_SEB: 4932 tcg_gen_ext8s_tl(cpu_gpr[rd], t0); 4933 break; 4934 case OPC_SEH: 4935 tcg_gen_ext16s_tl(cpu_gpr[rd], t0); 4936 break; 4937 #if defined(TARGET_MIPS64) 4938 case OPC_DSBH: 4939 { 4940 TCGv t1 = tcg_temp_new(); 4941 TCGv t2 = tcg_constant_tl(0x00FF00FF00FF00FFULL); 4942 4943 tcg_gen_shri_tl(t1, t0, 8); 4944 tcg_gen_and_tl(t1, t1, t2); 4945 tcg_gen_and_tl(t0, t0, t2); 4946 tcg_gen_shli_tl(t0, t0, 8); 4947 tcg_gen_or_tl(cpu_gpr[rd], t0, t1); 4948 } 4949 break; 4950 case OPC_DSHD: 4951 { 4952 TCGv t1 = tcg_temp_new(); 4953 TCGv t2 = tcg_constant_tl(0x0000FFFF0000FFFFULL); 4954 4955 tcg_gen_shri_tl(t1, t0, 16); 4956 tcg_gen_and_tl(t1, t1, t2); 4957 tcg_gen_and_tl(t0, t0, t2); 4958 tcg_gen_shli_tl(t0, t0, 16); 4959 tcg_gen_or_tl(t0, t0, t1); 4960 tcg_gen_shri_tl(t1, t0, 32); 4961 tcg_gen_shli_tl(t0, t0, 32); 4962 tcg_gen_or_tl(cpu_gpr[rd], t0, t1); 4963 } 4964 break; 4965 #endif 4966 default: 4967 MIPS_INVAL("bsfhl"); 4968 gen_reserved_instruction(ctx); 4969 return; 4970 } 4971 } 4972 4973 static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs, 4974 int rt, int bits) 4975 { 4976 TCGv t0; 4977 if (rd == 0) { 4978 /* Treat as NOP. */ 4979 return; 4980 } 4981 t0 = tcg_temp_new(); 4982 if (bits == 0 || bits == wordsz) { 4983 if (bits == 0) { 4984 gen_load_gpr(t0, rt); 4985 } else { 4986 gen_load_gpr(t0, rs); 4987 } 4988 switch (wordsz) { 4989 case 32: 4990 tcg_gen_ext32s_tl(cpu_gpr[rd], t0); 4991 break; 4992 #if defined(TARGET_MIPS64) 4993 case 64: 4994 tcg_gen_mov_tl(cpu_gpr[rd], t0); 4995 break; 4996 #endif 4997 } 4998 } else { 4999 TCGv t1 = tcg_temp_new(); 5000 gen_load_gpr(t0, rt); 5001 gen_load_gpr(t1, rs); 5002 switch (wordsz) { 5003 case 32: 5004 { 5005 TCGv_i64 t2 = tcg_temp_new_i64(); 5006 tcg_gen_concat_tl_i64(t2, t1, t0); 5007 tcg_gen_shri_i64(t2, t2, 32 - bits); 5008 gen_move_low32(cpu_gpr[rd], t2); 5009 } 5010 break; 5011 #if defined(TARGET_MIPS64) 5012 case 64: 5013 tcg_gen_shli_tl(t0, t0, bits); 5014 tcg_gen_shri_tl(t1, t1, 64 - bits); 5015 tcg_gen_or_tl(cpu_gpr[rd], t1, t0); 5016 break; 5017 #endif 5018 } 5019 } 5020 } 5021 5022 void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp) 5023 { 5024 gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8); 5025 } 5026 5027 static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt) 5028 { 5029 TCGv t0; 5030 if (rd == 0) { 5031 /* Treat as NOP. */ 5032 return; 5033 } 5034 t0 = tcg_temp_new(); 5035 gen_load_gpr(t0, rt); 5036 switch (opc) { 5037 case OPC_BITSWAP: 5038 gen_helper_bitswap(cpu_gpr[rd], t0); 5039 break; 5040 #if defined(TARGET_MIPS64) 5041 case OPC_DBITSWAP: 5042 gen_helper_dbitswap(cpu_gpr[rd], t0); 5043 break; 5044 #endif 5045 } 5046 } 5047 5048 #ifndef CONFIG_USER_ONLY 5049 /* CP0 (MMU and control) */ 5050 static inline void gen_mthc0_entrylo(TCGv arg, target_ulong off) 5051 { 5052 TCGv_i64 t0 = tcg_temp_new_i64(); 5053 TCGv_i64 t1 = tcg_temp_new_i64(); 5054 5055 tcg_gen_ext_tl_i64(t0, arg); 5056 tcg_gen_ld_i64(t1, tcg_env, off); 5057 #if defined(TARGET_MIPS64) 5058 tcg_gen_deposit_i64(t1, t1, t0, 30, 32); 5059 #else 5060 tcg_gen_concat32_i64(t1, t1, t0); 5061 #endif 5062 tcg_gen_st_i64(t1, tcg_env, off); 5063 } 5064 5065 static inline void gen_mthc0_store64(TCGv arg, target_ulong off) 5066 { 5067 TCGv_i64 t0 = tcg_temp_new_i64(); 5068 TCGv_i64 t1 = tcg_temp_new_i64(); 5069 5070 tcg_gen_ext_tl_i64(t0, arg); 5071 tcg_gen_ld_i64(t1, tcg_env, off); 5072 tcg_gen_concat32_i64(t1, t1, t0); 5073 tcg_gen_st_i64(t1, tcg_env, off); 5074 } 5075 5076 static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off) 5077 { 5078 TCGv_i64 t0 = tcg_temp_new_i64(); 5079 5080 tcg_gen_ld_i64(t0, tcg_env, off); 5081 #if defined(TARGET_MIPS64) 5082 tcg_gen_shri_i64(t0, t0, 30); 5083 #else 5084 tcg_gen_shri_i64(t0, t0, 32); 5085 #endif 5086 gen_move_low32(arg, t0); 5087 } 5088 5089 static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift) 5090 { 5091 TCGv_i64 t0 = tcg_temp_new_i64(); 5092 5093 tcg_gen_ld_i64(t0, tcg_env, off); 5094 tcg_gen_shri_i64(t0, t0, 32 + shift); 5095 gen_move_low32(arg, t0); 5096 } 5097 5098 static inline void gen_mfc0_load32(TCGv arg, target_ulong off) 5099 { 5100 TCGv_i32 t0 = tcg_temp_new_i32(); 5101 5102 tcg_gen_ld_i32(t0, tcg_env, off); 5103 tcg_gen_ext_i32_tl(arg, t0); 5104 } 5105 5106 static inline void gen_mfc0_load64(TCGv arg, target_ulong off) 5107 { 5108 tcg_gen_ld_tl(arg, tcg_env, off); 5109 tcg_gen_ext32s_tl(arg, arg); 5110 } 5111 5112 static inline void gen_mtc0_store32(TCGv arg, target_ulong off) 5113 { 5114 TCGv_i32 t0 = tcg_temp_new_i32(); 5115 5116 tcg_gen_trunc_tl_i32(t0, arg); 5117 tcg_gen_st_i32(t0, tcg_env, off); 5118 } 5119 5120 #define CP0_CHECK(c) \ 5121 do { \ 5122 if (!(c)) { \ 5123 goto cp0_unimplemented; \ 5124 } \ 5125 } while (0) 5126 5127 static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) 5128 { 5129 const char *register_name = "invalid"; 5130 5131 switch (reg) { 5132 case CP0_REGISTER_02: 5133 switch (sel) { 5134 case 0: 5135 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5136 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0)); 5137 register_name = "EntryLo0"; 5138 break; 5139 default: 5140 goto cp0_unimplemented; 5141 } 5142 break; 5143 case CP0_REGISTER_03: 5144 switch (sel) { 5145 case CP0_REG03__ENTRYLO1: 5146 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5147 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1)); 5148 register_name = "EntryLo1"; 5149 break; 5150 default: 5151 goto cp0_unimplemented; 5152 } 5153 break; 5154 case CP0_REGISTER_17: 5155 switch (sel) { 5156 case CP0_REG17__LLADDR: 5157 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr), 5158 ctx->CP0_LLAddr_shift); 5159 register_name = "LLAddr"; 5160 break; 5161 case CP0_REG17__MAAR: 5162 CP0_CHECK(ctx->mrp); 5163 gen_helper_mfhc0_maar(arg, tcg_env); 5164 register_name = "MAAR"; 5165 break; 5166 default: 5167 goto cp0_unimplemented; 5168 } 5169 break; 5170 case CP0_REGISTER_19: 5171 switch (sel) { 5172 case CP0_REG19__WATCHHI0: 5173 case CP0_REG19__WATCHHI1: 5174 case CP0_REG19__WATCHHI2: 5175 case CP0_REG19__WATCHHI3: 5176 case CP0_REG19__WATCHHI4: 5177 case CP0_REG19__WATCHHI5: 5178 case CP0_REG19__WATCHHI6: 5179 case CP0_REG19__WATCHHI7: 5180 /* upper 32 bits are only available when Config5MI != 0 */ 5181 CP0_CHECK(ctx->mi); 5182 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_WatchHi[sel]), 0); 5183 register_name = "WatchHi"; 5184 break; 5185 default: 5186 goto cp0_unimplemented; 5187 } 5188 break; 5189 case CP0_REGISTER_28: 5190 switch (sel) { 5191 case 0: 5192 case 2: 5193 case 4: 5194 case 6: 5195 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_TagLo), 0); 5196 register_name = "TagLo"; 5197 break; 5198 default: 5199 goto cp0_unimplemented; 5200 } 5201 break; 5202 default: 5203 goto cp0_unimplemented; 5204 } 5205 trace_mips_translate_c0("mfhc0", register_name, reg, sel); 5206 return; 5207 5208 cp0_unimplemented: 5209 qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n", 5210 register_name, reg, sel); 5211 tcg_gen_movi_tl(arg, 0); 5212 } 5213 5214 static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) 5215 { 5216 const char *register_name = "invalid"; 5217 uint64_t mask = ctx->PAMask >> 36; 5218 5219 switch (reg) { 5220 case CP0_REGISTER_02: 5221 switch (sel) { 5222 case 0: 5223 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5224 tcg_gen_andi_tl(arg, arg, mask); 5225 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0)); 5226 register_name = "EntryLo0"; 5227 break; 5228 default: 5229 goto cp0_unimplemented; 5230 } 5231 break; 5232 case CP0_REGISTER_03: 5233 switch (sel) { 5234 case CP0_REG03__ENTRYLO1: 5235 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); 5236 tcg_gen_andi_tl(arg, arg, mask); 5237 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1)); 5238 register_name = "EntryLo1"; 5239 break; 5240 default: 5241 goto cp0_unimplemented; 5242 } 5243 break; 5244 case CP0_REGISTER_17: 5245 switch (sel) { 5246 case CP0_REG17__LLADDR: 5247 /* 5248 * LLAddr is read-only (the only exception is bit 0 if LLB is 5249 * supported); the CP0_LLAddr_rw_bitmask does not seem to be 5250 * relevant for modern MIPS cores supporting MTHC0, therefore 5251 * treating MTHC0 to LLAddr as NOP. 5252 */ 5253 register_name = "LLAddr"; 5254 break; 5255 case CP0_REG17__MAAR: 5256 CP0_CHECK(ctx->mrp); 5257 gen_helper_mthc0_maar(tcg_env, arg); 5258 register_name = "MAAR"; 5259 break; 5260 default: 5261 goto cp0_unimplemented; 5262 } 5263 break; 5264 case CP0_REGISTER_19: 5265 switch (sel) { 5266 case CP0_REG19__WATCHHI0: 5267 case CP0_REG19__WATCHHI1: 5268 case CP0_REG19__WATCHHI2: 5269 case CP0_REG19__WATCHHI3: 5270 case CP0_REG19__WATCHHI4: 5271 case CP0_REG19__WATCHHI5: 5272 case CP0_REG19__WATCHHI6: 5273 case CP0_REG19__WATCHHI7: 5274 /* upper 32 bits are only available when Config5MI != 0 */ 5275 CP0_CHECK(ctx->mi); 5276 gen_helper_0e1i(mthc0_watchhi, arg, sel); 5277 register_name = "WatchHi"; 5278 break; 5279 default: 5280 goto cp0_unimplemented; 5281 } 5282 break; 5283 case CP0_REGISTER_28: 5284 switch (sel) { 5285 case 0: 5286 case 2: 5287 case 4: 5288 case 6: 5289 tcg_gen_andi_tl(arg, arg, mask); 5290 gen_mthc0_store64(arg, offsetof(CPUMIPSState, CP0_TagLo)); 5291 register_name = "TagLo"; 5292 break; 5293 default: 5294 goto cp0_unimplemented; 5295 } 5296 break; 5297 default: 5298 goto cp0_unimplemented; 5299 } 5300 trace_mips_translate_c0("mthc0", register_name, reg, sel); 5301 return; 5302 5303 cp0_unimplemented: 5304 qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", 5305 register_name, reg, sel); 5306 } 5307 5308 static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg) 5309 { 5310 if (ctx->insn_flags & ISA_MIPS_R6) { 5311 tcg_gen_movi_tl(arg, 0); 5312 } else { 5313 tcg_gen_movi_tl(arg, ~0); 5314 } 5315 } 5316 5317 static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 5318 { 5319 const char *register_name = "invalid"; 5320 5321 if (sel != 0) { 5322 check_insn(ctx, ISA_MIPS_R1); 5323 } 5324 5325 switch (reg) { 5326 case CP0_REGISTER_00: 5327 switch (sel) { 5328 case CP0_REG00__INDEX: 5329 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index)); 5330 register_name = "Index"; 5331 break; 5332 case CP0_REG00__MVPCONTROL: 5333 CP0_CHECK(ctx->insn_flags & ASE_MT); 5334 gen_helper_mfc0_mvpcontrol(arg, tcg_env); 5335 register_name = "MVPControl"; 5336 break; 5337 case CP0_REG00__MVPCONF0: 5338 CP0_CHECK(ctx->insn_flags & ASE_MT); 5339 gen_helper_mfc0_mvpconf0(arg, tcg_env); 5340 register_name = "MVPConf0"; 5341 break; 5342 case CP0_REG00__MVPCONF1: 5343 CP0_CHECK(ctx->insn_flags & ASE_MT); 5344 gen_helper_mfc0_mvpconf1(arg, tcg_env); 5345 register_name = "MVPConf1"; 5346 break; 5347 case CP0_REG00__VPCONTROL: 5348 CP0_CHECK(ctx->vp); 5349 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl)); 5350 register_name = "VPControl"; 5351 break; 5352 default: 5353 goto cp0_unimplemented; 5354 } 5355 break; 5356 case CP0_REGISTER_01: 5357 switch (sel) { 5358 case CP0_REG01__RANDOM: 5359 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 5360 gen_helper_mfc0_random(arg, tcg_env); 5361 register_name = "Random"; 5362 break; 5363 case CP0_REG01__VPECONTROL: 5364 CP0_CHECK(ctx->insn_flags & ASE_MT); 5365 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl)); 5366 register_name = "VPEControl"; 5367 break; 5368 case CP0_REG01__VPECONF0: 5369 CP0_CHECK(ctx->insn_flags & ASE_MT); 5370 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0)); 5371 register_name = "VPEConf0"; 5372 break; 5373 case CP0_REG01__VPECONF1: 5374 CP0_CHECK(ctx->insn_flags & ASE_MT); 5375 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1)); 5376 register_name = "VPEConf1"; 5377 break; 5378 case CP0_REG01__YQMASK: 5379 CP0_CHECK(ctx->insn_flags & ASE_MT); 5380 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask)); 5381 register_name = "YQMask"; 5382 break; 5383 case CP0_REG01__VPESCHEDULE: 5384 CP0_CHECK(ctx->insn_flags & ASE_MT); 5385 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule)); 5386 register_name = "VPESchedule"; 5387 break; 5388 case CP0_REG01__VPESCHEFBACK: 5389 CP0_CHECK(ctx->insn_flags & ASE_MT); 5390 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack)); 5391 register_name = "VPEScheFBack"; 5392 break; 5393 case CP0_REG01__VPEOPT: 5394 CP0_CHECK(ctx->insn_flags & ASE_MT); 5395 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt)); 5396 register_name = "VPEOpt"; 5397 break; 5398 default: 5399 goto cp0_unimplemented; 5400 } 5401 break; 5402 case CP0_REGISTER_02: 5403 switch (sel) { 5404 case CP0_REG02__ENTRYLO0: 5405 { 5406 TCGv_i64 tmp = tcg_temp_new_i64(); 5407 tcg_gen_ld_i64(tmp, tcg_env, 5408 offsetof(CPUMIPSState, CP0_EntryLo0)); 5409 #if defined(TARGET_MIPS64) 5410 if (ctx->rxi) { 5411 /* Move RI/XI fields to bits 31:30 */ 5412 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI); 5413 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2); 5414 } 5415 #endif 5416 gen_move_low32(arg, tmp); 5417 } 5418 register_name = "EntryLo0"; 5419 break; 5420 case CP0_REG02__TCSTATUS: 5421 CP0_CHECK(ctx->insn_flags & ASE_MT); 5422 gen_helper_mfc0_tcstatus(arg, tcg_env); 5423 register_name = "TCStatus"; 5424 break; 5425 case CP0_REG02__TCBIND: 5426 CP0_CHECK(ctx->insn_flags & ASE_MT); 5427 gen_helper_mfc0_tcbind(arg, tcg_env); 5428 register_name = "TCBind"; 5429 break; 5430 case CP0_REG02__TCRESTART: 5431 CP0_CHECK(ctx->insn_flags & ASE_MT); 5432 gen_helper_mfc0_tcrestart(arg, tcg_env); 5433 register_name = "TCRestart"; 5434 break; 5435 case CP0_REG02__TCHALT: 5436 CP0_CHECK(ctx->insn_flags & ASE_MT); 5437 gen_helper_mfc0_tchalt(arg, tcg_env); 5438 register_name = "TCHalt"; 5439 break; 5440 case CP0_REG02__TCCONTEXT: 5441 CP0_CHECK(ctx->insn_flags & ASE_MT); 5442 gen_helper_mfc0_tccontext(arg, tcg_env); 5443 register_name = "TCContext"; 5444 break; 5445 case CP0_REG02__TCSCHEDULE: 5446 CP0_CHECK(ctx->insn_flags & ASE_MT); 5447 gen_helper_mfc0_tcschedule(arg, tcg_env); 5448 register_name = "TCSchedule"; 5449 break; 5450 case CP0_REG02__TCSCHEFBACK: 5451 CP0_CHECK(ctx->insn_flags & ASE_MT); 5452 gen_helper_mfc0_tcschefback(arg, tcg_env); 5453 register_name = "TCScheFBack"; 5454 break; 5455 default: 5456 goto cp0_unimplemented; 5457 } 5458 break; 5459 case CP0_REGISTER_03: 5460 switch (sel) { 5461 case CP0_REG03__ENTRYLO1: 5462 { 5463 TCGv_i64 tmp = tcg_temp_new_i64(); 5464 tcg_gen_ld_i64(tmp, tcg_env, 5465 offsetof(CPUMIPSState, CP0_EntryLo1)); 5466 #if defined(TARGET_MIPS64) 5467 if (ctx->rxi) { 5468 /* Move RI/XI fields to bits 31:30 */ 5469 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI); 5470 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2); 5471 } 5472 #endif 5473 gen_move_low32(arg, tmp); 5474 } 5475 register_name = "EntryLo1"; 5476 break; 5477 case CP0_REG03__GLOBALNUM: 5478 CP0_CHECK(ctx->vp); 5479 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber)); 5480 register_name = "GlobalNumber"; 5481 break; 5482 default: 5483 goto cp0_unimplemented; 5484 } 5485 break; 5486 case CP0_REGISTER_04: 5487 switch (sel) { 5488 case CP0_REG04__CONTEXT: 5489 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_Context)); 5490 tcg_gen_ext32s_tl(arg, arg); 5491 register_name = "Context"; 5492 break; 5493 case CP0_REG04__CONTEXTCONFIG: 5494 /* SmartMIPS ASE */ 5495 /* gen_helper_mfc0_contextconfig(arg); */ 5496 register_name = "ContextConfig"; 5497 goto cp0_unimplemented; 5498 case CP0_REG04__USERLOCAL: 5499 CP0_CHECK(ctx->ulri); 5500 tcg_gen_ld_tl(arg, tcg_env, 5501 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 5502 tcg_gen_ext32s_tl(arg, arg); 5503 register_name = "UserLocal"; 5504 break; 5505 case CP0_REG04__MMID: 5506 CP0_CHECK(ctx->mi); 5507 gen_helper_mtc0_memorymapid(tcg_env, arg); 5508 register_name = "MMID"; 5509 break; 5510 default: 5511 goto cp0_unimplemented; 5512 } 5513 break; 5514 case CP0_REGISTER_05: 5515 switch (sel) { 5516 case CP0_REG05__PAGEMASK: 5517 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); 5518 register_name = "PageMask"; 5519 break; 5520 case CP0_REG05__PAGEGRAIN: 5521 check_insn(ctx, ISA_MIPS_R2); 5522 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); 5523 register_name = "PageGrain"; 5524 break; 5525 case CP0_REG05__SEGCTL0: 5526 CP0_CHECK(ctx->sc); 5527 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl0)); 5528 tcg_gen_ext32s_tl(arg, arg); 5529 register_name = "SegCtl0"; 5530 break; 5531 case CP0_REG05__SEGCTL1: 5532 CP0_CHECK(ctx->sc); 5533 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl1)); 5534 tcg_gen_ext32s_tl(arg, arg); 5535 register_name = "SegCtl1"; 5536 break; 5537 case CP0_REG05__SEGCTL2: 5538 CP0_CHECK(ctx->sc); 5539 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl2)); 5540 tcg_gen_ext32s_tl(arg, arg); 5541 register_name = "SegCtl2"; 5542 break; 5543 case CP0_REG05__PWBASE: 5544 check_pw(ctx); 5545 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase)); 5546 register_name = "PWBase"; 5547 break; 5548 case CP0_REG05__PWFIELD: 5549 check_pw(ctx); 5550 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField)); 5551 register_name = "PWField"; 5552 break; 5553 case CP0_REG05__PWSIZE: 5554 check_pw(ctx); 5555 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize)); 5556 register_name = "PWSize"; 5557 break; 5558 default: 5559 goto cp0_unimplemented; 5560 } 5561 break; 5562 case CP0_REGISTER_06: 5563 switch (sel) { 5564 case CP0_REG06__WIRED: 5565 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); 5566 register_name = "Wired"; 5567 break; 5568 case CP0_REG06__SRSCONF0: 5569 check_insn(ctx, ISA_MIPS_R2); 5570 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); 5571 register_name = "SRSConf0"; 5572 break; 5573 case CP0_REG06__SRSCONF1: 5574 check_insn(ctx, ISA_MIPS_R2); 5575 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); 5576 register_name = "SRSConf1"; 5577 break; 5578 case CP0_REG06__SRSCONF2: 5579 check_insn(ctx, ISA_MIPS_R2); 5580 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); 5581 register_name = "SRSConf2"; 5582 break; 5583 case CP0_REG06__SRSCONF3: 5584 check_insn(ctx, ISA_MIPS_R2); 5585 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); 5586 register_name = "SRSConf3"; 5587 break; 5588 case CP0_REG06__SRSCONF4: 5589 check_insn(ctx, ISA_MIPS_R2); 5590 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); 5591 register_name = "SRSConf4"; 5592 break; 5593 case CP0_REG06__PWCTL: 5594 check_pw(ctx); 5595 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); 5596 register_name = "PWCtl"; 5597 break; 5598 default: 5599 goto cp0_unimplemented; 5600 } 5601 break; 5602 case CP0_REGISTER_07: 5603 switch (sel) { 5604 case CP0_REG07__HWRENA: 5605 check_insn(ctx, ISA_MIPS_R2); 5606 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); 5607 register_name = "HWREna"; 5608 break; 5609 default: 5610 goto cp0_unimplemented; 5611 } 5612 break; 5613 case CP0_REGISTER_08: 5614 switch (sel) { 5615 case CP0_REG08__BADVADDR: 5616 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr)); 5617 tcg_gen_ext32s_tl(arg, arg); 5618 register_name = "BadVAddr"; 5619 break; 5620 case CP0_REG08__BADINSTR: 5621 CP0_CHECK(ctx->bi); 5622 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr)); 5623 register_name = "BadInstr"; 5624 break; 5625 case CP0_REG08__BADINSTRP: 5626 CP0_CHECK(ctx->bp); 5627 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); 5628 register_name = "BadInstrP"; 5629 break; 5630 case CP0_REG08__BADINSTRX: 5631 CP0_CHECK(ctx->bi); 5632 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX)); 5633 tcg_gen_andi_tl(arg, arg, ~0xffff); 5634 register_name = "BadInstrX"; 5635 break; 5636 default: 5637 goto cp0_unimplemented; 5638 } 5639 break; 5640 case CP0_REGISTER_09: 5641 switch (sel) { 5642 case CP0_REG09__COUNT: 5643 /* Mark as an IO operation because we read the time. */ 5644 translator_io_start(&ctx->base); 5645 5646 gen_helper_mfc0_count(arg, tcg_env); 5647 /* 5648 * Break the TB to be able to take timer interrupts immediately 5649 * after reading count. DISAS_STOP isn't sufficient, we need to 5650 * ensure we break completely out of translated code. 5651 */ 5652 gen_save_pc(ctx->base.pc_next + 4); 5653 ctx->base.is_jmp = DISAS_EXIT; 5654 register_name = "Count"; 5655 break; 5656 default: 5657 goto cp0_unimplemented; 5658 } 5659 break; 5660 case CP0_REGISTER_10: 5661 switch (sel) { 5662 case CP0_REG10__ENTRYHI: 5663 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryHi)); 5664 tcg_gen_ext32s_tl(arg, arg); 5665 register_name = "EntryHi"; 5666 break; 5667 default: 5668 goto cp0_unimplemented; 5669 } 5670 break; 5671 case CP0_REGISTER_11: 5672 switch (sel) { 5673 case CP0_REG11__COMPARE: 5674 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare)); 5675 register_name = "Compare"; 5676 break; 5677 /* 6,7 are implementation dependent */ 5678 default: 5679 goto cp0_unimplemented; 5680 } 5681 break; 5682 case CP0_REGISTER_12: 5683 switch (sel) { 5684 case CP0_REG12__STATUS: 5685 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); 5686 register_name = "Status"; 5687 break; 5688 case CP0_REG12__INTCTL: 5689 check_insn(ctx, ISA_MIPS_R2); 5690 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); 5691 register_name = "IntCtl"; 5692 break; 5693 case CP0_REG12__SRSCTL: 5694 check_insn(ctx, ISA_MIPS_R2); 5695 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); 5696 register_name = "SRSCtl"; 5697 break; 5698 case CP0_REG12__SRSMAP: 5699 check_insn(ctx, ISA_MIPS_R2); 5700 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 5701 register_name = "SRSMap"; 5702 break; 5703 default: 5704 goto cp0_unimplemented; 5705 } 5706 break; 5707 case CP0_REGISTER_13: 5708 switch (sel) { 5709 case CP0_REG13__CAUSE: 5710 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause)); 5711 register_name = "Cause"; 5712 break; 5713 default: 5714 goto cp0_unimplemented; 5715 } 5716 break; 5717 case CP0_REGISTER_14: 5718 switch (sel) { 5719 case CP0_REG14__EPC: 5720 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC)); 5721 tcg_gen_ext32s_tl(arg, arg); 5722 register_name = "EPC"; 5723 break; 5724 default: 5725 goto cp0_unimplemented; 5726 } 5727 break; 5728 case CP0_REGISTER_15: 5729 switch (sel) { 5730 case CP0_REG15__PRID: 5731 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); 5732 register_name = "PRid"; 5733 break; 5734 case CP0_REG15__EBASE: 5735 check_insn(ctx, ISA_MIPS_R2); 5736 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EBase)); 5737 tcg_gen_ext32s_tl(arg, arg); 5738 register_name = "EBase"; 5739 break; 5740 case CP0_REG15__CMGCRBASE: 5741 check_insn(ctx, ISA_MIPS_R2); 5742 CP0_CHECK(ctx->cmgcr); 5743 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); 5744 tcg_gen_ext32s_tl(arg, arg); 5745 register_name = "CMGCRBase"; 5746 break; 5747 default: 5748 goto cp0_unimplemented; 5749 } 5750 break; 5751 case CP0_REGISTER_16: 5752 switch (sel) { 5753 case CP0_REG16__CONFIG: 5754 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0)); 5755 register_name = "Config"; 5756 break; 5757 case CP0_REG16__CONFIG1: 5758 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1)); 5759 register_name = "Config1"; 5760 break; 5761 case CP0_REG16__CONFIG2: 5762 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2)); 5763 register_name = "Config2"; 5764 break; 5765 case CP0_REG16__CONFIG3: 5766 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3)); 5767 register_name = "Config3"; 5768 break; 5769 case CP0_REG16__CONFIG4: 5770 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4)); 5771 register_name = "Config4"; 5772 break; 5773 case CP0_REG16__CONFIG5: 5774 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); 5775 register_name = "Config5"; 5776 break; 5777 /* 6,7 are implementation dependent */ 5778 case CP0_REG16__CONFIG6: 5779 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); 5780 register_name = "Config6"; 5781 break; 5782 case CP0_REG16__CONFIG7: 5783 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7)); 5784 register_name = "Config7"; 5785 break; 5786 default: 5787 goto cp0_unimplemented; 5788 } 5789 break; 5790 case CP0_REGISTER_17: 5791 switch (sel) { 5792 case CP0_REG17__LLADDR: 5793 gen_helper_mfc0_lladdr(arg, tcg_env); 5794 register_name = "LLAddr"; 5795 break; 5796 case CP0_REG17__MAAR: 5797 CP0_CHECK(ctx->mrp); 5798 gen_helper_mfc0_maar(arg, tcg_env); 5799 register_name = "MAAR"; 5800 break; 5801 case CP0_REG17__MAARI: 5802 CP0_CHECK(ctx->mrp); 5803 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI)); 5804 register_name = "MAARI"; 5805 break; 5806 default: 5807 goto cp0_unimplemented; 5808 } 5809 break; 5810 case CP0_REGISTER_18: 5811 switch (sel) { 5812 case CP0_REG18__WATCHLO0: 5813 case CP0_REG18__WATCHLO1: 5814 case CP0_REG18__WATCHLO2: 5815 case CP0_REG18__WATCHLO3: 5816 case CP0_REG18__WATCHLO4: 5817 case CP0_REG18__WATCHLO5: 5818 case CP0_REG18__WATCHLO6: 5819 case CP0_REG18__WATCHLO7: 5820 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 5821 gen_helper_1e0i(mfc0_watchlo, arg, sel); 5822 register_name = "WatchLo"; 5823 break; 5824 default: 5825 goto cp0_unimplemented; 5826 } 5827 break; 5828 case CP0_REGISTER_19: 5829 switch (sel) { 5830 case CP0_REG19__WATCHHI0: 5831 case CP0_REG19__WATCHHI1: 5832 case CP0_REG19__WATCHHI2: 5833 case CP0_REG19__WATCHHI3: 5834 case CP0_REG19__WATCHHI4: 5835 case CP0_REG19__WATCHHI5: 5836 case CP0_REG19__WATCHHI6: 5837 case CP0_REG19__WATCHHI7: 5838 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 5839 gen_helper_1e0i(mfc0_watchhi, arg, sel); 5840 register_name = "WatchHi"; 5841 break; 5842 default: 5843 goto cp0_unimplemented; 5844 } 5845 break; 5846 case CP0_REGISTER_20: 5847 switch (sel) { 5848 case CP0_REG20__XCONTEXT: 5849 #if defined(TARGET_MIPS64) 5850 check_insn(ctx, ISA_MIPS3); 5851 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_XContext)); 5852 tcg_gen_ext32s_tl(arg, arg); 5853 register_name = "XContext"; 5854 break; 5855 #endif 5856 default: 5857 goto cp0_unimplemented; 5858 } 5859 break; 5860 case CP0_REGISTER_21: 5861 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 5862 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 5863 switch (sel) { 5864 case 0: 5865 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); 5866 register_name = "Framemask"; 5867 break; 5868 default: 5869 goto cp0_unimplemented; 5870 } 5871 break; 5872 case CP0_REGISTER_22: 5873 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 5874 register_name = "'Diagnostic"; /* implementation dependent */ 5875 break; 5876 case CP0_REGISTER_23: 5877 switch (sel) { 5878 case CP0_REG23__DEBUG: 5879 gen_helper_mfc0_debug(arg, tcg_env); /* EJTAG support */ 5880 register_name = "Debug"; 5881 break; 5882 case CP0_REG23__TRACECONTROL: 5883 /* PDtrace support */ 5884 /* gen_helper_mfc0_tracecontrol(arg); */ 5885 register_name = "TraceControl"; 5886 goto cp0_unimplemented; 5887 case CP0_REG23__TRACECONTROL2: 5888 /* PDtrace support */ 5889 /* gen_helper_mfc0_tracecontrol2(arg); */ 5890 register_name = "TraceControl2"; 5891 goto cp0_unimplemented; 5892 case CP0_REG23__USERTRACEDATA1: 5893 /* PDtrace support */ 5894 /* gen_helper_mfc0_usertracedata1(arg);*/ 5895 register_name = "UserTraceData1"; 5896 goto cp0_unimplemented; 5897 case CP0_REG23__TRACEIBPC: 5898 /* PDtrace support */ 5899 /* gen_helper_mfc0_traceibpc(arg); */ 5900 register_name = "TraceIBPC"; 5901 goto cp0_unimplemented; 5902 case CP0_REG23__TRACEDBPC: 5903 /* PDtrace support */ 5904 /* gen_helper_mfc0_tracedbpc(arg); */ 5905 register_name = "TraceDBPC"; 5906 goto cp0_unimplemented; 5907 default: 5908 goto cp0_unimplemented; 5909 } 5910 break; 5911 case CP0_REGISTER_24: 5912 switch (sel) { 5913 case CP0_REG24__DEPC: 5914 /* EJTAG support */ 5915 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC)); 5916 tcg_gen_ext32s_tl(arg, arg); 5917 register_name = "DEPC"; 5918 break; 5919 default: 5920 goto cp0_unimplemented; 5921 } 5922 break; 5923 case CP0_REGISTER_25: 5924 switch (sel) { 5925 case CP0_REG25__PERFCTL0: 5926 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0)); 5927 register_name = "Performance0"; 5928 break; 5929 case CP0_REG25__PERFCNT0: 5930 /* gen_helper_mfc0_performance1(arg); */ 5931 register_name = "Performance1"; 5932 goto cp0_unimplemented; 5933 case CP0_REG25__PERFCTL1: 5934 /* gen_helper_mfc0_performance2(arg); */ 5935 register_name = "Performance2"; 5936 goto cp0_unimplemented; 5937 case CP0_REG25__PERFCNT1: 5938 /* gen_helper_mfc0_performance3(arg); */ 5939 register_name = "Performance3"; 5940 goto cp0_unimplemented; 5941 case CP0_REG25__PERFCTL2: 5942 /* gen_helper_mfc0_performance4(arg); */ 5943 register_name = "Performance4"; 5944 goto cp0_unimplemented; 5945 case CP0_REG25__PERFCNT2: 5946 /* gen_helper_mfc0_performance5(arg); */ 5947 register_name = "Performance5"; 5948 goto cp0_unimplemented; 5949 case CP0_REG25__PERFCTL3: 5950 /* gen_helper_mfc0_performance6(arg); */ 5951 register_name = "Performance6"; 5952 goto cp0_unimplemented; 5953 case CP0_REG25__PERFCNT3: 5954 /* gen_helper_mfc0_performance7(arg); */ 5955 register_name = "Performance7"; 5956 goto cp0_unimplemented; 5957 default: 5958 goto cp0_unimplemented; 5959 } 5960 break; 5961 case CP0_REGISTER_26: 5962 switch (sel) { 5963 case CP0_REG26__ERRCTL: 5964 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl)); 5965 register_name = "ErrCtl"; 5966 break; 5967 default: 5968 goto cp0_unimplemented; 5969 } 5970 break; 5971 case CP0_REGISTER_27: 5972 switch (sel) { 5973 case CP0_REG27__CACHERR: 5974 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 5975 register_name = "CacheErr"; 5976 break; 5977 default: 5978 goto cp0_unimplemented; 5979 } 5980 break; 5981 case CP0_REGISTER_28: 5982 switch (sel) { 5983 case CP0_REG28__TAGLO: 5984 case CP0_REG28__TAGLO1: 5985 case CP0_REG28__TAGLO2: 5986 case CP0_REG28__TAGLO3: 5987 { 5988 TCGv_i64 tmp = tcg_temp_new_i64(); 5989 tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUMIPSState, CP0_TagLo)); 5990 gen_move_low32(arg, tmp); 5991 } 5992 register_name = "TagLo"; 5993 break; 5994 case CP0_REG28__DATALO: 5995 case CP0_REG28__DATALO1: 5996 case CP0_REG28__DATALO2: 5997 case CP0_REG28__DATALO3: 5998 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo)); 5999 register_name = "DataLo"; 6000 break; 6001 default: 6002 goto cp0_unimplemented; 6003 } 6004 break; 6005 case CP0_REGISTER_29: 6006 switch (sel) { 6007 case CP0_REG29__TAGHI: 6008 case CP0_REG29__TAGHI1: 6009 case CP0_REG29__TAGHI2: 6010 case CP0_REG29__TAGHI3: 6011 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi)); 6012 register_name = "TagHi"; 6013 break; 6014 case CP0_REG29__DATAHI: 6015 case CP0_REG29__DATAHI1: 6016 case CP0_REG29__DATAHI2: 6017 case CP0_REG29__DATAHI3: 6018 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi)); 6019 register_name = "DataHi"; 6020 break; 6021 default: 6022 goto cp0_unimplemented; 6023 } 6024 break; 6025 case CP0_REGISTER_30: 6026 switch (sel) { 6027 case CP0_REG30__ERROREPC: 6028 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 6029 tcg_gen_ext32s_tl(arg, arg); 6030 register_name = "ErrorEPC"; 6031 break; 6032 default: 6033 goto cp0_unimplemented; 6034 } 6035 break; 6036 case CP0_REGISTER_31: 6037 switch (sel) { 6038 case CP0_REG31__DESAVE: 6039 /* EJTAG support */ 6040 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 6041 register_name = "DESAVE"; 6042 break; 6043 case CP0_REG31__KSCRATCH1: 6044 case CP0_REG31__KSCRATCH2: 6045 case CP0_REG31__KSCRATCH3: 6046 case CP0_REG31__KSCRATCH4: 6047 case CP0_REG31__KSCRATCH5: 6048 case CP0_REG31__KSCRATCH6: 6049 CP0_CHECK(ctx->kscrexist & (1 << sel)); 6050 tcg_gen_ld_tl(arg, tcg_env, 6051 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 6052 tcg_gen_ext32s_tl(arg, arg); 6053 register_name = "KScratch"; 6054 break; 6055 default: 6056 goto cp0_unimplemented; 6057 } 6058 break; 6059 default: 6060 goto cp0_unimplemented; 6061 } 6062 trace_mips_translate_c0("mfc0", register_name, reg, sel); 6063 return; 6064 6065 cp0_unimplemented: 6066 qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n", 6067 register_name, reg, sel); 6068 gen_mfc0_unimplemented(ctx, arg); 6069 } 6070 6071 static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 6072 { 6073 const char *register_name = "invalid"; 6074 bool icount; 6075 6076 if (sel != 0) { 6077 check_insn(ctx, ISA_MIPS_R1); 6078 } 6079 6080 icount = translator_io_start(&ctx->base); 6081 6082 switch (reg) { 6083 case CP0_REGISTER_00: 6084 switch (sel) { 6085 case CP0_REG00__INDEX: 6086 gen_helper_mtc0_index(tcg_env, arg); 6087 register_name = "Index"; 6088 break; 6089 case CP0_REG00__MVPCONTROL: 6090 CP0_CHECK(ctx->insn_flags & ASE_MT); 6091 gen_helper_mtc0_mvpcontrol(tcg_env, arg); 6092 register_name = "MVPControl"; 6093 break; 6094 case CP0_REG00__MVPCONF0: 6095 CP0_CHECK(ctx->insn_flags & ASE_MT); 6096 /* ignored */ 6097 register_name = "MVPConf0"; 6098 break; 6099 case CP0_REG00__MVPCONF1: 6100 CP0_CHECK(ctx->insn_flags & ASE_MT); 6101 /* ignored */ 6102 register_name = "MVPConf1"; 6103 break; 6104 case CP0_REG00__VPCONTROL: 6105 CP0_CHECK(ctx->vp); 6106 /* ignored */ 6107 register_name = "VPControl"; 6108 break; 6109 default: 6110 goto cp0_unimplemented; 6111 } 6112 break; 6113 case CP0_REGISTER_01: 6114 switch (sel) { 6115 case CP0_REG01__RANDOM: 6116 /* ignored */ 6117 register_name = "Random"; 6118 break; 6119 case CP0_REG01__VPECONTROL: 6120 CP0_CHECK(ctx->insn_flags & ASE_MT); 6121 gen_helper_mtc0_vpecontrol(tcg_env, arg); 6122 register_name = "VPEControl"; 6123 break; 6124 case CP0_REG01__VPECONF0: 6125 CP0_CHECK(ctx->insn_flags & ASE_MT); 6126 gen_helper_mtc0_vpeconf0(tcg_env, arg); 6127 register_name = "VPEConf0"; 6128 break; 6129 case CP0_REG01__VPECONF1: 6130 CP0_CHECK(ctx->insn_flags & ASE_MT); 6131 gen_helper_mtc0_vpeconf1(tcg_env, arg); 6132 register_name = "VPEConf1"; 6133 break; 6134 case CP0_REG01__YQMASK: 6135 CP0_CHECK(ctx->insn_flags & ASE_MT); 6136 gen_helper_mtc0_yqmask(tcg_env, arg); 6137 register_name = "YQMask"; 6138 break; 6139 case CP0_REG01__VPESCHEDULE: 6140 CP0_CHECK(ctx->insn_flags & ASE_MT); 6141 tcg_gen_st_tl(arg, tcg_env, 6142 offsetof(CPUMIPSState, CP0_VPESchedule)); 6143 register_name = "VPESchedule"; 6144 break; 6145 case CP0_REG01__VPESCHEFBACK: 6146 CP0_CHECK(ctx->insn_flags & ASE_MT); 6147 tcg_gen_st_tl(arg, tcg_env, 6148 offsetof(CPUMIPSState, CP0_VPEScheFBack)); 6149 register_name = "VPEScheFBack"; 6150 break; 6151 case CP0_REG01__VPEOPT: 6152 CP0_CHECK(ctx->insn_flags & ASE_MT); 6153 gen_helper_mtc0_vpeopt(tcg_env, arg); 6154 register_name = "VPEOpt"; 6155 break; 6156 default: 6157 goto cp0_unimplemented; 6158 } 6159 break; 6160 case CP0_REGISTER_02: 6161 switch (sel) { 6162 case CP0_REG02__ENTRYLO0: 6163 gen_helper_mtc0_entrylo0(tcg_env, arg); 6164 register_name = "EntryLo0"; 6165 break; 6166 case CP0_REG02__TCSTATUS: 6167 CP0_CHECK(ctx->insn_flags & ASE_MT); 6168 gen_helper_mtc0_tcstatus(tcg_env, arg); 6169 register_name = "TCStatus"; 6170 break; 6171 case CP0_REG02__TCBIND: 6172 CP0_CHECK(ctx->insn_flags & ASE_MT); 6173 gen_helper_mtc0_tcbind(tcg_env, arg); 6174 register_name = "TCBind"; 6175 break; 6176 case CP0_REG02__TCRESTART: 6177 CP0_CHECK(ctx->insn_flags & ASE_MT); 6178 gen_helper_mtc0_tcrestart(tcg_env, arg); 6179 register_name = "TCRestart"; 6180 break; 6181 case CP0_REG02__TCHALT: 6182 CP0_CHECK(ctx->insn_flags & ASE_MT); 6183 gen_helper_mtc0_tchalt(tcg_env, arg); 6184 register_name = "TCHalt"; 6185 break; 6186 case CP0_REG02__TCCONTEXT: 6187 CP0_CHECK(ctx->insn_flags & ASE_MT); 6188 gen_helper_mtc0_tccontext(tcg_env, arg); 6189 register_name = "TCContext"; 6190 break; 6191 case CP0_REG02__TCSCHEDULE: 6192 CP0_CHECK(ctx->insn_flags & ASE_MT); 6193 gen_helper_mtc0_tcschedule(tcg_env, arg); 6194 register_name = "TCSchedule"; 6195 break; 6196 case CP0_REG02__TCSCHEFBACK: 6197 CP0_CHECK(ctx->insn_flags & ASE_MT); 6198 gen_helper_mtc0_tcschefback(tcg_env, arg); 6199 register_name = "TCScheFBack"; 6200 break; 6201 default: 6202 goto cp0_unimplemented; 6203 } 6204 break; 6205 case CP0_REGISTER_03: 6206 switch (sel) { 6207 case CP0_REG03__ENTRYLO1: 6208 gen_helper_mtc0_entrylo1(tcg_env, arg); 6209 register_name = "EntryLo1"; 6210 break; 6211 case CP0_REG03__GLOBALNUM: 6212 CP0_CHECK(ctx->vp); 6213 /* ignored */ 6214 register_name = "GlobalNumber"; 6215 break; 6216 default: 6217 goto cp0_unimplemented; 6218 } 6219 break; 6220 case CP0_REGISTER_04: 6221 switch (sel) { 6222 case CP0_REG04__CONTEXT: 6223 gen_helper_mtc0_context(tcg_env, arg); 6224 register_name = "Context"; 6225 break; 6226 case CP0_REG04__CONTEXTCONFIG: 6227 /* SmartMIPS ASE */ 6228 /* gen_helper_mtc0_contextconfig(arg); */ 6229 register_name = "ContextConfig"; 6230 goto cp0_unimplemented; 6231 case CP0_REG04__USERLOCAL: 6232 CP0_CHECK(ctx->ulri); 6233 tcg_gen_st_tl(arg, tcg_env, 6234 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 6235 register_name = "UserLocal"; 6236 break; 6237 case CP0_REG04__MMID: 6238 CP0_CHECK(ctx->mi); 6239 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID)); 6240 register_name = "MMID"; 6241 break; 6242 default: 6243 goto cp0_unimplemented; 6244 } 6245 break; 6246 case CP0_REGISTER_05: 6247 switch (sel) { 6248 case CP0_REG05__PAGEMASK: 6249 gen_helper_mtc0_pagemask(tcg_env, arg); 6250 register_name = "PageMask"; 6251 break; 6252 case CP0_REG05__PAGEGRAIN: 6253 check_insn(ctx, ISA_MIPS_R2); 6254 gen_helper_mtc0_pagegrain(tcg_env, arg); 6255 register_name = "PageGrain"; 6256 ctx->base.is_jmp = DISAS_STOP; 6257 break; 6258 case CP0_REG05__SEGCTL0: 6259 CP0_CHECK(ctx->sc); 6260 gen_helper_mtc0_segctl0(tcg_env, arg); 6261 register_name = "SegCtl0"; 6262 break; 6263 case CP0_REG05__SEGCTL1: 6264 CP0_CHECK(ctx->sc); 6265 gen_helper_mtc0_segctl1(tcg_env, arg); 6266 register_name = "SegCtl1"; 6267 break; 6268 case CP0_REG05__SEGCTL2: 6269 CP0_CHECK(ctx->sc); 6270 gen_helper_mtc0_segctl2(tcg_env, arg); 6271 register_name = "SegCtl2"; 6272 break; 6273 case CP0_REG05__PWBASE: 6274 check_pw(ctx); 6275 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase)); 6276 register_name = "PWBase"; 6277 break; 6278 case CP0_REG05__PWFIELD: 6279 check_pw(ctx); 6280 gen_helper_mtc0_pwfield(tcg_env, arg); 6281 register_name = "PWField"; 6282 break; 6283 case CP0_REG05__PWSIZE: 6284 check_pw(ctx); 6285 gen_helper_mtc0_pwsize(tcg_env, arg); 6286 register_name = "PWSize"; 6287 break; 6288 default: 6289 goto cp0_unimplemented; 6290 } 6291 break; 6292 case CP0_REGISTER_06: 6293 switch (sel) { 6294 case CP0_REG06__WIRED: 6295 gen_helper_mtc0_wired(tcg_env, arg); 6296 register_name = "Wired"; 6297 break; 6298 case CP0_REG06__SRSCONF0: 6299 check_insn(ctx, ISA_MIPS_R2); 6300 gen_helper_mtc0_srsconf0(tcg_env, arg); 6301 register_name = "SRSConf0"; 6302 break; 6303 case CP0_REG06__SRSCONF1: 6304 check_insn(ctx, ISA_MIPS_R2); 6305 gen_helper_mtc0_srsconf1(tcg_env, arg); 6306 register_name = "SRSConf1"; 6307 break; 6308 case CP0_REG06__SRSCONF2: 6309 check_insn(ctx, ISA_MIPS_R2); 6310 gen_helper_mtc0_srsconf2(tcg_env, arg); 6311 register_name = "SRSConf2"; 6312 break; 6313 case CP0_REG06__SRSCONF3: 6314 check_insn(ctx, ISA_MIPS_R2); 6315 gen_helper_mtc0_srsconf3(tcg_env, arg); 6316 register_name = "SRSConf3"; 6317 break; 6318 case CP0_REG06__SRSCONF4: 6319 check_insn(ctx, ISA_MIPS_R2); 6320 gen_helper_mtc0_srsconf4(tcg_env, arg); 6321 register_name = "SRSConf4"; 6322 break; 6323 case CP0_REG06__PWCTL: 6324 check_pw(ctx); 6325 gen_helper_mtc0_pwctl(tcg_env, arg); 6326 register_name = "PWCtl"; 6327 break; 6328 default: 6329 goto cp0_unimplemented; 6330 } 6331 break; 6332 case CP0_REGISTER_07: 6333 switch (sel) { 6334 case CP0_REG07__HWRENA: 6335 check_insn(ctx, ISA_MIPS_R2); 6336 gen_helper_mtc0_hwrena(tcg_env, arg); 6337 ctx->base.is_jmp = DISAS_STOP; 6338 register_name = "HWREna"; 6339 break; 6340 default: 6341 goto cp0_unimplemented; 6342 } 6343 break; 6344 case CP0_REGISTER_08: 6345 switch (sel) { 6346 case CP0_REG08__BADVADDR: 6347 /* ignored */ 6348 register_name = "BadVAddr"; 6349 break; 6350 case CP0_REG08__BADINSTR: 6351 /* ignored */ 6352 register_name = "BadInstr"; 6353 break; 6354 case CP0_REG08__BADINSTRP: 6355 /* ignored */ 6356 register_name = "BadInstrP"; 6357 break; 6358 case CP0_REG08__BADINSTRX: 6359 /* ignored */ 6360 register_name = "BadInstrX"; 6361 break; 6362 default: 6363 goto cp0_unimplemented; 6364 } 6365 break; 6366 case CP0_REGISTER_09: 6367 switch (sel) { 6368 case CP0_REG09__COUNT: 6369 gen_helper_mtc0_count(tcg_env, arg); 6370 register_name = "Count"; 6371 break; 6372 default: 6373 goto cp0_unimplemented; 6374 } 6375 break; 6376 case CP0_REGISTER_10: 6377 switch (sel) { 6378 case CP0_REG10__ENTRYHI: 6379 gen_helper_mtc0_entryhi(tcg_env, arg); 6380 register_name = "EntryHi"; 6381 break; 6382 default: 6383 goto cp0_unimplemented; 6384 } 6385 break; 6386 case CP0_REGISTER_11: 6387 switch (sel) { 6388 case CP0_REG11__COMPARE: 6389 gen_helper_mtc0_compare(tcg_env, arg); 6390 register_name = "Compare"; 6391 break; 6392 /* 6,7 are implementation dependent */ 6393 default: 6394 goto cp0_unimplemented; 6395 } 6396 break; 6397 case CP0_REGISTER_12: 6398 switch (sel) { 6399 case CP0_REG12__STATUS: 6400 save_cpu_state(ctx, 1); 6401 gen_helper_mtc0_status(tcg_env, arg); 6402 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 6403 gen_save_pc(ctx->base.pc_next + 4); 6404 ctx->base.is_jmp = DISAS_EXIT; 6405 register_name = "Status"; 6406 break; 6407 case CP0_REG12__INTCTL: 6408 check_insn(ctx, ISA_MIPS_R2); 6409 gen_helper_mtc0_intctl(tcg_env, arg); 6410 /* Stop translation as we may have switched the execution mode */ 6411 ctx->base.is_jmp = DISAS_STOP; 6412 register_name = "IntCtl"; 6413 break; 6414 case CP0_REG12__SRSCTL: 6415 check_insn(ctx, ISA_MIPS_R2); 6416 gen_helper_mtc0_srsctl(tcg_env, arg); 6417 /* Stop translation as we may have switched the execution mode */ 6418 ctx->base.is_jmp = DISAS_STOP; 6419 register_name = "SRSCtl"; 6420 break; 6421 case CP0_REG12__SRSMAP: 6422 check_insn(ctx, ISA_MIPS_R2); 6423 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 6424 /* Stop translation as we may have switched the execution mode */ 6425 ctx->base.is_jmp = DISAS_STOP; 6426 register_name = "SRSMap"; 6427 break; 6428 default: 6429 goto cp0_unimplemented; 6430 } 6431 break; 6432 case CP0_REGISTER_13: 6433 switch (sel) { 6434 case CP0_REG13__CAUSE: 6435 save_cpu_state(ctx, 1); 6436 gen_helper_mtc0_cause(tcg_env, arg); 6437 /* 6438 * Stop translation as we may have triggered an interrupt. 6439 * DISAS_STOP isn't sufficient, we need to ensure we break out of 6440 * translated code to check for pending interrupts. 6441 */ 6442 gen_save_pc(ctx->base.pc_next + 4); 6443 ctx->base.is_jmp = DISAS_EXIT; 6444 register_name = "Cause"; 6445 break; 6446 default: 6447 goto cp0_unimplemented; 6448 } 6449 break; 6450 case CP0_REGISTER_14: 6451 switch (sel) { 6452 case CP0_REG14__EPC: 6453 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC)); 6454 register_name = "EPC"; 6455 break; 6456 default: 6457 goto cp0_unimplemented; 6458 } 6459 break; 6460 case CP0_REGISTER_15: 6461 switch (sel) { 6462 case CP0_REG15__PRID: 6463 /* ignored */ 6464 register_name = "PRid"; 6465 break; 6466 case CP0_REG15__EBASE: 6467 check_insn(ctx, ISA_MIPS_R2); 6468 gen_helper_mtc0_ebase(tcg_env, arg); 6469 register_name = "EBase"; 6470 break; 6471 default: 6472 goto cp0_unimplemented; 6473 } 6474 break; 6475 case CP0_REGISTER_16: 6476 switch (sel) { 6477 case CP0_REG16__CONFIG: 6478 gen_helper_mtc0_config0(tcg_env, arg); 6479 register_name = "Config"; 6480 /* Stop translation as we may have switched the execution mode */ 6481 ctx->base.is_jmp = DISAS_STOP; 6482 break; 6483 case CP0_REG16__CONFIG1: 6484 /* ignored, read only */ 6485 register_name = "Config1"; 6486 break; 6487 case CP0_REG16__CONFIG2: 6488 gen_helper_mtc0_config2(tcg_env, arg); 6489 register_name = "Config2"; 6490 /* Stop translation as we may have switched the execution mode */ 6491 ctx->base.is_jmp = DISAS_STOP; 6492 break; 6493 case CP0_REG16__CONFIG3: 6494 gen_helper_mtc0_config3(tcg_env, arg); 6495 register_name = "Config3"; 6496 /* Stop translation as we may have switched the execution mode */ 6497 ctx->base.is_jmp = DISAS_STOP; 6498 break; 6499 case CP0_REG16__CONFIG4: 6500 gen_helper_mtc0_config4(tcg_env, arg); 6501 register_name = "Config4"; 6502 ctx->base.is_jmp = DISAS_STOP; 6503 break; 6504 case CP0_REG16__CONFIG5: 6505 gen_helper_mtc0_config5(tcg_env, arg); 6506 register_name = "Config5"; 6507 /* Stop translation as we may have switched the execution mode */ 6508 ctx->base.is_jmp = DISAS_STOP; 6509 break; 6510 /* 6,7 are implementation dependent */ 6511 case CP0_REG16__CONFIG6: 6512 /* ignored */ 6513 register_name = "Config6"; 6514 break; 6515 case CP0_REG16__CONFIG7: 6516 /* ignored */ 6517 register_name = "Config7"; 6518 break; 6519 default: 6520 register_name = "Invalid config selector"; 6521 goto cp0_unimplemented; 6522 } 6523 break; 6524 case CP0_REGISTER_17: 6525 switch (sel) { 6526 case CP0_REG17__LLADDR: 6527 gen_helper_mtc0_lladdr(tcg_env, arg); 6528 register_name = "LLAddr"; 6529 break; 6530 case CP0_REG17__MAAR: 6531 CP0_CHECK(ctx->mrp); 6532 gen_helper_mtc0_maar(tcg_env, arg); 6533 register_name = "MAAR"; 6534 break; 6535 case CP0_REG17__MAARI: 6536 CP0_CHECK(ctx->mrp); 6537 gen_helper_mtc0_maari(tcg_env, arg); 6538 register_name = "MAARI"; 6539 break; 6540 default: 6541 goto cp0_unimplemented; 6542 } 6543 break; 6544 case CP0_REGISTER_18: 6545 switch (sel) { 6546 case CP0_REG18__WATCHLO0: 6547 case CP0_REG18__WATCHLO1: 6548 case CP0_REG18__WATCHLO2: 6549 case CP0_REG18__WATCHLO3: 6550 case CP0_REG18__WATCHLO4: 6551 case CP0_REG18__WATCHLO5: 6552 case CP0_REG18__WATCHLO6: 6553 case CP0_REG18__WATCHLO7: 6554 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 6555 gen_helper_0e1i(mtc0_watchlo, arg, sel); 6556 register_name = "WatchLo"; 6557 break; 6558 default: 6559 goto cp0_unimplemented; 6560 } 6561 break; 6562 case CP0_REGISTER_19: 6563 switch (sel) { 6564 case CP0_REG19__WATCHHI0: 6565 case CP0_REG19__WATCHHI1: 6566 case CP0_REG19__WATCHHI2: 6567 case CP0_REG19__WATCHHI3: 6568 case CP0_REG19__WATCHHI4: 6569 case CP0_REG19__WATCHHI5: 6570 case CP0_REG19__WATCHHI6: 6571 case CP0_REG19__WATCHHI7: 6572 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 6573 gen_helper_0e1i(mtc0_watchhi, arg, sel); 6574 register_name = "WatchHi"; 6575 break; 6576 default: 6577 goto cp0_unimplemented; 6578 } 6579 break; 6580 case CP0_REGISTER_20: 6581 switch (sel) { 6582 case CP0_REG20__XCONTEXT: 6583 #if defined(TARGET_MIPS64) 6584 check_insn(ctx, ISA_MIPS3); 6585 gen_helper_mtc0_xcontext(tcg_env, arg); 6586 register_name = "XContext"; 6587 break; 6588 #endif 6589 default: 6590 goto cp0_unimplemented; 6591 } 6592 break; 6593 case CP0_REGISTER_21: 6594 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 6595 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 6596 switch (sel) { 6597 case 0: 6598 gen_helper_mtc0_framemask(tcg_env, arg); 6599 register_name = "Framemask"; 6600 break; 6601 default: 6602 goto cp0_unimplemented; 6603 } 6604 break; 6605 case CP0_REGISTER_22: 6606 /* ignored */ 6607 register_name = "Diagnostic"; /* implementation dependent */ 6608 break; 6609 case CP0_REGISTER_23: 6610 switch (sel) { 6611 case CP0_REG23__DEBUG: 6612 gen_helper_mtc0_debug(tcg_env, arg); /* EJTAG support */ 6613 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 6614 gen_save_pc(ctx->base.pc_next + 4); 6615 ctx->base.is_jmp = DISAS_EXIT; 6616 register_name = "Debug"; 6617 break; 6618 case CP0_REG23__TRACECONTROL: 6619 /* PDtrace support */ 6620 /* gen_helper_mtc0_tracecontrol(tcg_env, arg); */ 6621 register_name = "TraceControl"; 6622 /* Stop translation as we may have switched the execution mode */ 6623 ctx->base.is_jmp = DISAS_STOP; 6624 goto cp0_unimplemented; 6625 case CP0_REG23__TRACECONTROL2: 6626 /* PDtrace support */ 6627 /* gen_helper_mtc0_tracecontrol2(tcg_env, arg); */ 6628 register_name = "TraceControl2"; 6629 /* Stop translation as we may have switched the execution mode */ 6630 ctx->base.is_jmp = DISAS_STOP; 6631 goto cp0_unimplemented; 6632 case CP0_REG23__USERTRACEDATA1: 6633 /* Stop translation as we may have switched the execution mode */ 6634 ctx->base.is_jmp = DISAS_STOP; 6635 /* PDtrace support */ 6636 /* gen_helper_mtc0_usertracedata1(tcg_env, arg);*/ 6637 register_name = "UserTraceData"; 6638 /* Stop translation as we may have switched the execution mode */ 6639 ctx->base.is_jmp = DISAS_STOP; 6640 goto cp0_unimplemented; 6641 case CP0_REG23__TRACEIBPC: 6642 /* PDtrace support */ 6643 /* gen_helper_mtc0_traceibpc(tcg_env, arg); */ 6644 /* Stop translation as we may have switched the execution mode */ 6645 ctx->base.is_jmp = DISAS_STOP; 6646 register_name = "TraceIBPC"; 6647 goto cp0_unimplemented; 6648 case CP0_REG23__TRACEDBPC: 6649 /* PDtrace support */ 6650 /* gen_helper_mtc0_tracedbpc(tcg_env, arg); */ 6651 /* Stop translation as we may have switched the execution mode */ 6652 ctx->base.is_jmp = DISAS_STOP; 6653 register_name = "TraceDBPC"; 6654 goto cp0_unimplemented; 6655 default: 6656 goto cp0_unimplemented; 6657 } 6658 break; 6659 case CP0_REGISTER_24: 6660 switch (sel) { 6661 case CP0_REG24__DEPC: 6662 /* EJTAG support */ 6663 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC)); 6664 register_name = "DEPC"; 6665 break; 6666 default: 6667 goto cp0_unimplemented; 6668 } 6669 break; 6670 case CP0_REGISTER_25: 6671 switch (sel) { 6672 case CP0_REG25__PERFCTL0: 6673 gen_helper_mtc0_performance0(tcg_env, arg); 6674 register_name = "Performance0"; 6675 break; 6676 case CP0_REG25__PERFCNT0: 6677 /* gen_helper_mtc0_performance1(arg); */ 6678 register_name = "Performance1"; 6679 goto cp0_unimplemented; 6680 case CP0_REG25__PERFCTL1: 6681 /* gen_helper_mtc0_performance2(arg); */ 6682 register_name = "Performance2"; 6683 goto cp0_unimplemented; 6684 case CP0_REG25__PERFCNT1: 6685 /* gen_helper_mtc0_performance3(arg); */ 6686 register_name = "Performance3"; 6687 goto cp0_unimplemented; 6688 case CP0_REG25__PERFCTL2: 6689 /* gen_helper_mtc0_performance4(arg); */ 6690 register_name = "Performance4"; 6691 goto cp0_unimplemented; 6692 case CP0_REG25__PERFCNT2: 6693 /* gen_helper_mtc0_performance5(arg); */ 6694 register_name = "Performance5"; 6695 goto cp0_unimplemented; 6696 case CP0_REG25__PERFCTL3: 6697 /* gen_helper_mtc0_performance6(arg); */ 6698 register_name = "Performance6"; 6699 goto cp0_unimplemented; 6700 case CP0_REG25__PERFCNT3: 6701 /* gen_helper_mtc0_performance7(arg); */ 6702 register_name = "Performance7"; 6703 goto cp0_unimplemented; 6704 default: 6705 goto cp0_unimplemented; 6706 } 6707 break; 6708 case CP0_REGISTER_26: 6709 switch (sel) { 6710 case CP0_REG26__ERRCTL: 6711 gen_helper_mtc0_errctl(tcg_env, arg); 6712 ctx->base.is_jmp = DISAS_STOP; 6713 register_name = "ErrCtl"; 6714 break; 6715 default: 6716 goto cp0_unimplemented; 6717 } 6718 break; 6719 case CP0_REGISTER_27: 6720 switch (sel) { 6721 case CP0_REG27__CACHERR: 6722 /* ignored */ 6723 register_name = "CacheErr"; 6724 break; 6725 default: 6726 goto cp0_unimplemented; 6727 } 6728 break; 6729 case CP0_REGISTER_28: 6730 switch (sel) { 6731 case CP0_REG28__TAGLO: 6732 case CP0_REG28__TAGLO1: 6733 case CP0_REG28__TAGLO2: 6734 case CP0_REG28__TAGLO3: 6735 gen_helper_mtc0_taglo(tcg_env, arg); 6736 register_name = "TagLo"; 6737 break; 6738 case CP0_REG28__DATALO: 6739 case CP0_REG28__DATALO1: 6740 case CP0_REG28__DATALO2: 6741 case CP0_REG28__DATALO3: 6742 gen_helper_mtc0_datalo(tcg_env, arg); 6743 register_name = "DataLo"; 6744 break; 6745 default: 6746 goto cp0_unimplemented; 6747 } 6748 break; 6749 case CP0_REGISTER_29: 6750 switch (sel) { 6751 case CP0_REG29__TAGHI: 6752 case CP0_REG29__TAGHI1: 6753 case CP0_REG29__TAGHI2: 6754 case CP0_REG29__TAGHI3: 6755 gen_helper_mtc0_taghi(tcg_env, arg); 6756 register_name = "TagHi"; 6757 break; 6758 case CP0_REG29__DATAHI: 6759 case CP0_REG29__DATAHI1: 6760 case CP0_REG29__DATAHI2: 6761 case CP0_REG29__DATAHI3: 6762 gen_helper_mtc0_datahi(tcg_env, arg); 6763 register_name = "DataHi"; 6764 break; 6765 default: 6766 register_name = "invalid sel"; 6767 goto cp0_unimplemented; 6768 } 6769 break; 6770 case CP0_REGISTER_30: 6771 switch (sel) { 6772 case CP0_REG30__ERROREPC: 6773 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 6774 register_name = "ErrorEPC"; 6775 break; 6776 default: 6777 goto cp0_unimplemented; 6778 } 6779 break; 6780 case CP0_REGISTER_31: 6781 switch (sel) { 6782 case CP0_REG31__DESAVE: 6783 /* EJTAG support */ 6784 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 6785 register_name = "DESAVE"; 6786 break; 6787 case CP0_REG31__KSCRATCH1: 6788 case CP0_REG31__KSCRATCH2: 6789 case CP0_REG31__KSCRATCH3: 6790 case CP0_REG31__KSCRATCH4: 6791 case CP0_REG31__KSCRATCH5: 6792 case CP0_REG31__KSCRATCH6: 6793 CP0_CHECK(ctx->kscrexist & (1 << sel)); 6794 tcg_gen_st_tl(arg, tcg_env, 6795 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 6796 register_name = "KScratch"; 6797 break; 6798 default: 6799 goto cp0_unimplemented; 6800 } 6801 break; 6802 default: 6803 goto cp0_unimplemented; 6804 } 6805 trace_mips_translate_c0("mtc0", register_name, reg, sel); 6806 6807 /* For simplicity assume that all writes can cause interrupts. */ 6808 if (icount) { 6809 /* 6810 * DISAS_STOP isn't sufficient, we need to ensure we break out of 6811 * translated code to check for pending interrupts. 6812 */ 6813 gen_save_pc(ctx->base.pc_next + 4); 6814 ctx->base.is_jmp = DISAS_EXIT; 6815 } 6816 return; 6817 6818 cp0_unimplemented: 6819 qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n", 6820 register_name, reg, sel); 6821 } 6822 6823 #if defined(TARGET_MIPS64) 6824 static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 6825 { 6826 const char *register_name = "invalid"; 6827 6828 if (sel != 0) { 6829 check_insn(ctx, ISA_MIPS_R1); 6830 } 6831 6832 switch (reg) { 6833 case CP0_REGISTER_00: 6834 switch (sel) { 6835 case CP0_REG00__INDEX: 6836 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index)); 6837 register_name = "Index"; 6838 break; 6839 case CP0_REG00__MVPCONTROL: 6840 CP0_CHECK(ctx->insn_flags & ASE_MT); 6841 gen_helper_mfc0_mvpcontrol(arg, tcg_env); 6842 register_name = "MVPControl"; 6843 break; 6844 case CP0_REG00__MVPCONF0: 6845 CP0_CHECK(ctx->insn_flags & ASE_MT); 6846 gen_helper_mfc0_mvpconf0(arg, tcg_env); 6847 register_name = "MVPConf0"; 6848 break; 6849 case CP0_REG00__MVPCONF1: 6850 CP0_CHECK(ctx->insn_flags & ASE_MT); 6851 gen_helper_mfc0_mvpconf1(arg, tcg_env); 6852 register_name = "MVPConf1"; 6853 break; 6854 case CP0_REG00__VPCONTROL: 6855 CP0_CHECK(ctx->vp); 6856 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl)); 6857 register_name = "VPControl"; 6858 break; 6859 default: 6860 goto cp0_unimplemented; 6861 } 6862 break; 6863 case CP0_REGISTER_01: 6864 switch (sel) { 6865 case CP0_REG01__RANDOM: 6866 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 6867 gen_helper_mfc0_random(arg, tcg_env); 6868 register_name = "Random"; 6869 break; 6870 case CP0_REG01__VPECONTROL: 6871 CP0_CHECK(ctx->insn_flags & ASE_MT); 6872 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl)); 6873 register_name = "VPEControl"; 6874 break; 6875 case CP0_REG01__VPECONF0: 6876 CP0_CHECK(ctx->insn_flags & ASE_MT); 6877 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0)); 6878 register_name = "VPEConf0"; 6879 break; 6880 case CP0_REG01__VPECONF1: 6881 CP0_CHECK(ctx->insn_flags & ASE_MT); 6882 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1)); 6883 register_name = "VPEConf1"; 6884 break; 6885 case CP0_REG01__YQMASK: 6886 CP0_CHECK(ctx->insn_flags & ASE_MT); 6887 tcg_gen_ld_tl(arg, tcg_env, 6888 offsetof(CPUMIPSState, CP0_YQMask)); 6889 register_name = "YQMask"; 6890 break; 6891 case CP0_REG01__VPESCHEDULE: 6892 CP0_CHECK(ctx->insn_flags & ASE_MT); 6893 tcg_gen_ld_tl(arg, tcg_env, 6894 offsetof(CPUMIPSState, CP0_VPESchedule)); 6895 register_name = "VPESchedule"; 6896 break; 6897 case CP0_REG01__VPESCHEFBACK: 6898 CP0_CHECK(ctx->insn_flags & ASE_MT); 6899 tcg_gen_ld_tl(arg, tcg_env, 6900 offsetof(CPUMIPSState, CP0_VPEScheFBack)); 6901 register_name = "VPEScheFBack"; 6902 break; 6903 case CP0_REG01__VPEOPT: 6904 CP0_CHECK(ctx->insn_flags & ASE_MT); 6905 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt)); 6906 register_name = "VPEOpt"; 6907 break; 6908 default: 6909 goto cp0_unimplemented; 6910 } 6911 break; 6912 case CP0_REGISTER_02: 6913 switch (sel) { 6914 case CP0_REG02__ENTRYLO0: 6915 tcg_gen_ld_tl(arg, tcg_env, 6916 offsetof(CPUMIPSState, CP0_EntryLo0)); 6917 register_name = "EntryLo0"; 6918 break; 6919 case CP0_REG02__TCSTATUS: 6920 CP0_CHECK(ctx->insn_flags & ASE_MT); 6921 gen_helper_mfc0_tcstatus(arg, tcg_env); 6922 register_name = "TCStatus"; 6923 break; 6924 case CP0_REG02__TCBIND: 6925 CP0_CHECK(ctx->insn_flags & ASE_MT); 6926 gen_helper_mfc0_tcbind(arg, tcg_env); 6927 register_name = "TCBind"; 6928 break; 6929 case CP0_REG02__TCRESTART: 6930 CP0_CHECK(ctx->insn_flags & ASE_MT); 6931 gen_helper_dmfc0_tcrestart(arg, tcg_env); 6932 register_name = "TCRestart"; 6933 break; 6934 case CP0_REG02__TCHALT: 6935 CP0_CHECK(ctx->insn_flags & ASE_MT); 6936 gen_helper_dmfc0_tchalt(arg, tcg_env); 6937 register_name = "TCHalt"; 6938 break; 6939 case CP0_REG02__TCCONTEXT: 6940 CP0_CHECK(ctx->insn_flags & ASE_MT); 6941 gen_helper_dmfc0_tccontext(arg, tcg_env); 6942 register_name = "TCContext"; 6943 break; 6944 case CP0_REG02__TCSCHEDULE: 6945 CP0_CHECK(ctx->insn_flags & ASE_MT); 6946 gen_helper_dmfc0_tcschedule(arg, tcg_env); 6947 register_name = "TCSchedule"; 6948 break; 6949 case CP0_REG02__TCSCHEFBACK: 6950 CP0_CHECK(ctx->insn_flags & ASE_MT); 6951 gen_helper_dmfc0_tcschefback(arg, tcg_env); 6952 register_name = "TCScheFBack"; 6953 break; 6954 default: 6955 goto cp0_unimplemented; 6956 } 6957 break; 6958 case CP0_REGISTER_03: 6959 switch (sel) { 6960 case CP0_REG03__ENTRYLO1: 6961 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryLo1)); 6962 register_name = "EntryLo1"; 6963 break; 6964 case CP0_REG03__GLOBALNUM: 6965 CP0_CHECK(ctx->vp); 6966 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber)); 6967 register_name = "GlobalNumber"; 6968 break; 6969 default: 6970 goto cp0_unimplemented; 6971 } 6972 break; 6973 case CP0_REGISTER_04: 6974 switch (sel) { 6975 case CP0_REG04__CONTEXT: 6976 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_Context)); 6977 register_name = "Context"; 6978 break; 6979 case CP0_REG04__CONTEXTCONFIG: 6980 /* SmartMIPS ASE */ 6981 /* gen_helper_dmfc0_contextconfig(arg); */ 6982 register_name = "ContextConfig"; 6983 goto cp0_unimplemented; 6984 case CP0_REG04__USERLOCAL: 6985 CP0_CHECK(ctx->ulri); 6986 tcg_gen_ld_tl(arg, tcg_env, 6987 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 6988 register_name = "UserLocal"; 6989 break; 6990 case CP0_REG04__MMID: 6991 CP0_CHECK(ctx->mi); 6992 gen_helper_mtc0_memorymapid(tcg_env, arg); 6993 register_name = "MMID"; 6994 break; 6995 default: 6996 goto cp0_unimplemented; 6997 } 6998 break; 6999 case CP0_REGISTER_05: 7000 switch (sel) { 7001 case CP0_REG05__PAGEMASK: 7002 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask)); 7003 register_name = "PageMask"; 7004 break; 7005 case CP0_REG05__PAGEGRAIN: 7006 check_insn(ctx, ISA_MIPS_R2); 7007 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); 7008 register_name = "PageGrain"; 7009 break; 7010 case CP0_REG05__SEGCTL0: 7011 CP0_CHECK(ctx->sc); 7012 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl0)); 7013 register_name = "SegCtl0"; 7014 break; 7015 case CP0_REG05__SEGCTL1: 7016 CP0_CHECK(ctx->sc); 7017 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl1)); 7018 register_name = "SegCtl1"; 7019 break; 7020 case CP0_REG05__SEGCTL2: 7021 CP0_CHECK(ctx->sc); 7022 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl2)); 7023 register_name = "SegCtl2"; 7024 break; 7025 case CP0_REG05__PWBASE: 7026 check_pw(ctx); 7027 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWBase)); 7028 register_name = "PWBase"; 7029 break; 7030 case CP0_REG05__PWFIELD: 7031 check_pw(ctx); 7032 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWField)); 7033 register_name = "PWField"; 7034 break; 7035 case CP0_REG05__PWSIZE: 7036 check_pw(ctx); 7037 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWSize)); 7038 register_name = "PWSize"; 7039 break; 7040 default: 7041 goto cp0_unimplemented; 7042 } 7043 break; 7044 case CP0_REGISTER_06: 7045 switch (sel) { 7046 case CP0_REG06__WIRED: 7047 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired)); 7048 register_name = "Wired"; 7049 break; 7050 case CP0_REG06__SRSCONF0: 7051 check_insn(ctx, ISA_MIPS_R2); 7052 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); 7053 register_name = "SRSConf0"; 7054 break; 7055 case CP0_REG06__SRSCONF1: 7056 check_insn(ctx, ISA_MIPS_R2); 7057 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); 7058 register_name = "SRSConf1"; 7059 break; 7060 case CP0_REG06__SRSCONF2: 7061 check_insn(ctx, ISA_MIPS_R2); 7062 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); 7063 register_name = "SRSConf2"; 7064 break; 7065 case CP0_REG06__SRSCONF3: 7066 check_insn(ctx, ISA_MIPS_R2); 7067 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); 7068 register_name = "SRSConf3"; 7069 break; 7070 case CP0_REG06__SRSCONF4: 7071 check_insn(ctx, ISA_MIPS_R2); 7072 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); 7073 register_name = "SRSConf4"; 7074 break; 7075 case CP0_REG06__PWCTL: 7076 check_pw(ctx); 7077 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl)); 7078 register_name = "PWCtl"; 7079 break; 7080 default: 7081 goto cp0_unimplemented; 7082 } 7083 break; 7084 case CP0_REGISTER_07: 7085 switch (sel) { 7086 case CP0_REG07__HWRENA: 7087 check_insn(ctx, ISA_MIPS_R2); 7088 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); 7089 register_name = "HWREna"; 7090 break; 7091 default: 7092 goto cp0_unimplemented; 7093 } 7094 break; 7095 case CP0_REGISTER_08: 7096 switch (sel) { 7097 case CP0_REG08__BADVADDR: 7098 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr)); 7099 register_name = "BadVAddr"; 7100 break; 7101 case CP0_REG08__BADINSTR: 7102 CP0_CHECK(ctx->bi); 7103 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr)); 7104 register_name = "BadInstr"; 7105 break; 7106 case CP0_REG08__BADINSTRP: 7107 CP0_CHECK(ctx->bp); 7108 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP)); 7109 register_name = "BadInstrP"; 7110 break; 7111 case CP0_REG08__BADINSTRX: 7112 CP0_CHECK(ctx->bi); 7113 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX)); 7114 tcg_gen_andi_tl(arg, arg, ~0xffff); 7115 register_name = "BadInstrX"; 7116 break; 7117 default: 7118 goto cp0_unimplemented; 7119 } 7120 break; 7121 case CP0_REGISTER_09: 7122 switch (sel) { 7123 case CP0_REG09__COUNT: 7124 /* Mark as an IO operation because we read the time. */ 7125 translator_io_start(&ctx->base); 7126 gen_helper_mfc0_count(arg, tcg_env); 7127 /* 7128 * Break the TB to be able to take timer interrupts immediately 7129 * after reading count. DISAS_STOP isn't sufficient, we need to 7130 * ensure we break completely out of translated code. 7131 */ 7132 gen_save_pc(ctx->base.pc_next + 4); 7133 ctx->base.is_jmp = DISAS_EXIT; 7134 register_name = "Count"; 7135 break; 7136 default: 7137 goto cp0_unimplemented; 7138 } 7139 break; 7140 case CP0_REGISTER_10: 7141 switch (sel) { 7142 case CP0_REG10__ENTRYHI: 7143 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryHi)); 7144 register_name = "EntryHi"; 7145 break; 7146 default: 7147 goto cp0_unimplemented; 7148 } 7149 break; 7150 case CP0_REGISTER_11: 7151 switch (sel) { 7152 case CP0_REG11__COMPARE: 7153 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare)); 7154 register_name = "Compare"; 7155 break; 7156 /* 6,7 are implementation dependent */ 7157 default: 7158 goto cp0_unimplemented; 7159 } 7160 break; 7161 case CP0_REGISTER_12: 7162 switch (sel) { 7163 case CP0_REG12__STATUS: 7164 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status)); 7165 register_name = "Status"; 7166 break; 7167 case CP0_REG12__INTCTL: 7168 check_insn(ctx, ISA_MIPS_R2); 7169 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); 7170 register_name = "IntCtl"; 7171 break; 7172 case CP0_REG12__SRSCTL: 7173 check_insn(ctx, ISA_MIPS_R2); 7174 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); 7175 register_name = "SRSCtl"; 7176 break; 7177 case CP0_REG12__SRSMAP: 7178 check_insn(ctx, ISA_MIPS_R2); 7179 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 7180 register_name = "SRSMap"; 7181 break; 7182 default: 7183 goto cp0_unimplemented; 7184 } 7185 break; 7186 case CP0_REGISTER_13: 7187 switch (sel) { 7188 case CP0_REG13__CAUSE: 7189 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause)); 7190 register_name = "Cause"; 7191 break; 7192 default: 7193 goto cp0_unimplemented; 7194 } 7195 break; 7196 case CP0_REGISTER_14: 7197 switch (sel) { 7198 case CP0_REG14__EPC: 7199 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC)); 7200 register_name = "EPC"; 7201 break; 7202 default: 7203 goto cp0_unimplemented; 7204 } 7205 break; 7206 case CP0_REGISTER_15: 7207 switch (sel) { 7208 case CP0_REG15__PRID: 7209 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); 7210 register_name = "PRid"; 7211 break; 7212 case CP0_REG15__EBASE: 7213 check_insn(ctx, ISA_MIPS_R2); 7214 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EBase)); 7215 register_name = "EBase"; 7216 break; 7217 case CP0_REG15__CMGCRBASE: 7218 check_insn(ctx, ISA_MIPS_R2); 7219 CP0_CHECK(ctx->cmgcr); 7220 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); 7221 register_name = "CMGCRBase"; 7222 break; 7223 default: 7224 goto cp0_unimplemented; 7225 } 7226 break; 7227 case CP0_REGISTER_16: 7228 switch (sel) { 7229 case CP0_REG16__CONFIG: 7230 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0)); 7231 register_name = "Config"; 7232 break; 7233 case CP0_REG16__CONFIG1: 7234 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1)); 7235 register_name = "Config1"; 7236 break; 7237 case CP0_REG16__CONFIG2: 7238 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2)); 7239 register_name = "Config2"; 7240 break; 7241 case CP0_REG16__CONFIG3: 7242 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3)); 7243 register_name = "Config3"; 7244 break; 7245 case CP0_REG16__CONFIG4: 7246 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4)); 7247 register_name = "Config4"; 7248 break; 7249 case CP0_REG16__CONFIG5: 7250 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); 7251 register_name = "Config5"; 7252 break; 7253 /* 6,7 are implementation dependent */ 7254 case CP0_REG16__CONFIG6: 7255 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); 7256 register_name = "Config6"; 7257 break; 7258 case CP0_REG16__CONFIG7: 7259 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7)); 7260 register_name = "Config7"; 7261 break; 7262 default: 7263 goto cp0_unimplemented; 7264 } 7265 break; 7266 case CP0_REGISTER_17: 7267 switch (sel) { 7268 case CP0_REG17__LLADDR: 7269 gen_helper_dmfc0_lladdr(arg, tcg_env); 7270 register_name = "LLAddr"; 7271 break; 7272 case CP0_REG17__MAAR: 7273 CP0_CHECK(ctx->mrp); 7274 gen_helper_dmfc0_maar(arg, tcg_env); 7275 register_name = "MAAR"; 7276 break; 7277 case CP0_REG17__MAARI: 7278 CP0_CHECK(ctx->mrp); 7279 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI)); 7280 register_name = "MAARI"; 7281 break; 7282 default: 7283 goto cp0_unimplemented; 7284 } 7285 break; 7286 case CP0_REGISTER_18: 7287 switch (sel) { 7288 case CP0_REG18__WATCHLO0: 7289 case CP0_REG18__WATCHLO1: 7290 case CP0_REG18__WATCHLO2: 7291 case CP0_REG18__WATCHLO3: 7292 case CP0_REG18__WATCHLO4: 7293 case CP0_REG18__WATCHLO5: 7294 case CP0_REG18__WATCHLO6: 7295 case CP0_REG18__WATCHLO7: 7296 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 7297 gen_helper_1e0i(dmfc0_watchlo, arg, sel); 7298 register_name = "WatchLo"; 7299 break; 7300 default: 7301 goto cp0_unimplemented; 7302 } 7303 break; 7304 case CP0_REGISTER_19: 7305 switch (sel) { 7306 case CP0_REG19__WATCHHI0: 7307 case CP0_REG19__WATCHHI1: 7308 case CP0_REG19__WATCHHI2: 7309 case CP0_REG19__WATCHHI3: 7310 case CP0_REG19__WATCHHI4: 7311 case CP0_REG19__WATCHHI5: 7312 case CP0_REG19__WATCHHI6: 7313 case CP0_REG19__WATCHHI7: 7314 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 7315 gen_helper_1e0i(dmfc0_watchhi, arg, sel); 7316 register_name = "WatchHi"; 7317 break; 7318 default: 7319 goto cp0_unimplemented; 7320 } 7321 break; 7322 case CP0_REGISTER_20: 7323 switch (sel) { 7324 case CP0_REG20__XCONTEXT: 7325 check_insn(ctx, ISA_MIPS3); 7326 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_XContext)); 7327 register_name = "XContext"; 7328 break; 7329 default: 7330 goto cp0_unimplemented; 7331 } 7332 break; 7333 case CP0_REGISTER_21: 7334 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 7335 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 7336 switch (sel) { 7337 case 0: 7338 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); 7339 register_name = "Framemask"; 7340 break; 7341 default: 7342 goto cp0_unimplemented; 7343 } 7344 break; 7345 case CP0_REGISTER_22: 7346 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 7347 register_name = "'Diagnostic"; /* implementation dependent */ 7348 break; 7349 case CP0_REGISTER_23: 7350 switch (sel) { 7351 case CP0_REG23__DEBUG: 7352 gen_helper_mfc0_debug(arg, tcg_env); /* EJTAG support */ 7353 register_name = "Debug"; 7354 break; 7355 case CP0_REG23__TRACECONTROL: 7356 /* PDtrace support */ 7357 /* gen_helper_dmfc0_tracecontrol(arg, tcg_env); */ 7358 register_name = "TraceControl"; 7359 goto cp0_unimplemented; 7360 case CP0_REG23__TRACECONTROL2: 7361 /* PDtrace support */ 7362 /* gen_helper_dmfc0_tracecontrol2(arg, tcg_env); */ 7363 register_name = "TraceControl2"; 7364 goto cp0_unimplemented; 7365 case CP0_REG23__USERTRACEDATA1: 7366 /* PDtrace support */ 7367 /* gen_helper_dmfc0_usertracedata1(arg, tcg_env);*/ 7368 register_name = "UserTraceData1"; 7369 goto cp0_unimplemented; 7370 case CP0_REG23__TRACEIBPC: 7371 /* PDtrace support */ 7372 /* gen_helper_dmfc0_traceibpc(arg, tcg_env); */ 7373 register_name = "TraceIBPC"; 7374 goto cp0_unimplemented; 7375 case CP0_REG23__TRACEDBPC: 7376 /* PDtrace support */ 7377 /* gen_helper_dmfc0_tracedbpc(arg, tcg_env); */ 7378 register_name = "TraceDBPC"; 7379 goto cp0_unimplemented; 7380 default: 7381 goto cp0_unimplemented; 7382 } 7383 break; 7384 case CP0_REGISTER_24: 7385 switch (sel) { 7386 case CP0_REG24__DEPC: 7387 /* EJTAG support */ 7388 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC)); 7389 register_name = "DEPC"; 7390 break; 7391 default: 7392 goto cp0_unimplemented; 7393 } 7394 break; 7395 case CP0_REGISTER_25: 7396 switch (sel) { 7397 case CP0_REG25__PERFCTL0: 7398 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0)); 7399 register_name = "Performance0"; 7400 break; 7401 case CP0_REG25__PERFCNT0: 7402 /* gen_helper_dmfc0_performance1(arg); */ 7403 register_name = "Performance1"; 7404 goto cp0_unimplemented; 7405 case CP0_REG25__PERFCTL1: 7406 /* gen_helper_dmfc0_performance2(arg); */ 7407 register_name = "Performance2"; 7408 goto cp0_unimplemented; 7409 case CP0_REG25__PERFCNT1: 7410 /* gen_helper_dmfc0_performance3(arg); */ 7411 register_name = "Performance3"; 7412 goto cp0_unimplemented; 7413 case CP0_REG25__PERFCTL2: 7414 /* gen_helper_dmfc0_performance4(arg); */ 7415 register_name = "Performance4"; 7416 goto cp0_unimplemented; 7417 case CP0_REG25__PERFCNT2: 7418 /* gen_helper_dmfc0_performance5(arg); */ 7419 register_name = "Performance5"; 7420 goto cp0_unimplemented; 7421 case CP0_REG25__PERFCTL3: 7422 /* gen_helper_dmfc0_performance6(arg); */ 7423 register_name = "Performance6"; 7424 goto cp0_unimplemented; 7425 case CP0_REG25__PERFCNT3: 7426 /* gen_helper_dmfc0_performance7(arg); */ 7427 register_name = "Performance7"; 7428 goto cp0_unimplemented; 7429 default: 7430 goto cp0_unimplemented; 7431 } 7432 break; 7433 case CP0_REGISTER_26: 7434 switch (sel) { 7435 case CP0_REG26__ERRCTL: 7436 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl)); 7437 register_name = "ErrCtl"; 7438 break; 7439 default: 7440 goto cp0_unimplemented; 7441 } 7442 break; 7443 case CP0_REGISTER_27: 7444 switch (sel) { 7445 /* ignored */ 7446 case CP0_REG27__CACHERR: 7447 tcg_gen_movi_tl(arg, 0); /* unimplemented */ 7448 register_name = "CacheErr"; 7449 break; 7450 default: 7451 goto cp0_unimplemented; 7452 } 7453 break; 7454 case CP0_REGISTER_28: 7455 switch (sel) { 7456 case CP0_REG28__TAGLO: 7457 case CP0_REG28__TAGLO1: 7458 case CP0_REG28__TAGLO2: 7459 case CP0_REG28__TAGLO3: 7460 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo)); 7461 register_name = "TagLo"; 7462 break; 7463 case CP0_REG28__DATALO: 7464 case CP0_REG28__DATALO1: 7465 case CP0_REG28__DATALO2: 7466 case CP0_REG28__DATALO3: 7467 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo)); 7468 register_name = "DataLo"; 7469 break; 7470 default: 7471 goto cp0_unimplemented; 7472 } 7473 break; 7474 case CP0_REGISTER_29: 7475 switch (sel) { 7476 case CP0_REG29__TAGHI: 7477 case CP0_REG29__TAGHI1: 7478 case CP0_REG29__TAGHI2: 7479 case CP0_REG29__TAGHI3: 7480 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi)); 7481 register_name = "TagHi"; 7482 break; 7483 case CP0_REG29__DATAHI: 7484 case CP0_REG29__DATAHI1: 7485 case CP0_REG29__DATAHI2: 7486 case CP0_REG29__DATAHI3: 7487 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi)); 7488 register_name = "DataHi"; 7489 break; 7490 default: 7491 goto cp0_unimplemented; 7492 } 7493 break; 7494 case CP0_REGISTER_30: 7495 switch (sel) { 7496 case CP0_REG30__ERROREPC: 7497 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 7498 register_name = "ErrorEPC"; 7499 break; 7500 default: 7501 goto cp0_unimplemented; 7502 } 7503 break; 7504 case CP0_REGISTER_31: 7505 switch (sel) { 7506 case CP0_REG31__DESAVE: 7507 /* EJTAG support */ 7508 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 7509 register_name = "DESAVE"; 7510 break; 7511 case CP0_REG31__KSCRATCH1: 7512 case CP0_REG31__KSCRATCH2: 7513 case CP0_REG31__KSCRATCH3: 7514 case CP0_REG31__KSCRATCH4: 7515 case CP0_REG31__KSCRATCH5: 7516 case CP0_REG31__KSCRATCH6: 7517 CP0_CHECK(ctx->kscrexist & (1 << sel)); 7518 tcg_gen_ld_tl(arg, tcg_env, 7519 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 7520 register_name = "KScratch"; 7521 break; 7522 default: 7523 goto cp0_unimplemented; 7524 } 7525 break; 7526 default: 7527 goto cp0_unimplemented; 7528 } 7529 trace_mips_translate_c0("dmfc0", register_name, reg, sel); 7530 return; 7531 7532 cp0_unimplemented: 7533 qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n", 7534 register_name, reg, sel); 7535 gen_mfc0_unimplemented(ctx, arg); 7536 } 7537 7538 static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 7539 { 7540 const char *register_name = "invalid"; 7541 bool icount; 7542 7543 if (sel != 0) { 7544 check_insn(ctx, ISA_MIPS_R1); 7545 } 7546 7547 icount = translator_io_start(&ctx->base); 7548 7549 switch (reg) { 7550 case CP0_REGISTER_00: 7551 switch (sel) { 7552 case CP0_REG00__INDEX: 7553 gen_helper_mtc0_index(tcg_env, arg); 7554 register_name = "Index"; 7555 break; 7556 case CP0_REG00__MVPCONTROL: 7557 CP0_CHECK(ctx->insn_flags & ASE_MT); 7558 gen_helper_mtc0_mvpcontrol(tcg_env, arg); 7559 register_name = "MVPControl"; 7560 break; 7561 case CP0_REG00__MVPCONF0: 7562 CP0_CHECK(ctx->insn_flags & ASE_MT); 7563 /* ignored */ 7564 register_name = "MVPConf0"; 7565 break; 7566 case CP0_REG00__MVPCONF1: 7567 CP0_CHECK(ctx->insn_flags & ASE_MT); 7568 /* ignored */ 7569 register_name = "MVPConf1"; 7570 break; 7571 case CP0_REG00__VPCONTROL: 7572 CP0_CHECK(ctx->vp); 7573 /* ignored */ 7574 register_name = "VPControl"; 7575 break; 7576 default: 7577 goto cp0_unimplemented; 7578 } 7579 break; 7580 case CP0_REGISTER_01: 7581 switch (sel) { 7582 case CP0_REG01__RANDOM: 7583 /* ignored */ 7584 register_name = "Random"; 7585 break; 7586 case CP0_REG01__VPECONTROL: 7587 CP0_CHECK(ctx->insn_flags & ASE_MT); 7588 gen_helper_mtc0_vpecontrol(tcg_env, arg); 7589 register_name = "VPEControl"; 7590 break; 7591 case CP0_REG01__VPECONF0: 7592 CP0_CHECK(ctx->insn_flags & ASE_MT); 7593 gen_helper_mtc0_vpeconf0(tcg_env, arg); 7594 register_name = "VPEConf0"; 7595 break; 7596 case CP0_REG01__VPECONF1: 7597 CP0_CHECK(ctx->insn_flags & ASE_MT); 7598 gen_helper_mtc0_vpeconf1(tcg_env, arg); 7599 register_name = "VPEConf1"; 7600 break; 7601 case CP0_REG01__YQMASK: 7602 CP0_CHECK(ctx->insn_flags & ASE_MT); 7603 gen_helper_mtc0_yqmask(tcg_env, arg); 7604 register_name = "YQMask"; 7605 break; 7606 case CP0_REG01__VPESCHEDULE: 7607 CP0_CHECK(ctx->insn_flags & ASE_MT); 7608 tcg_gen_st_tl(arg, tcg_env, 7609 offsetof(CPUMIPSState, CP0_VPESchedule)); 7610 register_name = "VPESchedule"; 7611 break; 7612 case CP0_REG01__VPESCHEFBACK: 7613 CP0_CHECK(ctx->insn_flags & ASE_MT); 7614 tcg_gen_st_tl(arg, tcg_env, 7615 offsetof(CPUMIPSState, CP0_VPEScheFBack)); 7616 register_name = "VPEScheFBack"; 7617 break; 7618 case CP0_REG01__VPEOPT: 7619 CP0_CHECK(ctx->insn_flags & ASE_MT); 7620 gen_helper_mtc0_vpeopt(tcg_env, arg); 7621 register_name = "VPEOpt"; 7622 break; 7623 default: 7624 goto cp0_unimplemented; 7625 } 7626 break; 7627 case CP0_REGISTER_02: 7628 switch (sel) { 7629 case CP0_REG02__ENTRYLO0: 7630 gen_helper_dmtc0_entrylo0(tcg_env, arg); 7631 register_name = "EntryLo0"; 7632 break; 7633 case CP0_REG02__TCSTATUS: 7634 CP0_CHECK(ctx->insn_flags & ASE_MT); 7635 gen_helper_mtc0_tcstatus(tcg_env, arg); 7636 register_name = "TCStatus"; 7637 break; 7638 case CP0_REG02__TCBIND: 7639 CP0_CHECK(ctx->insn_flags & ASE_MT); 7640 gen_helper_mtc0_tcbind(tcg_env, arg); 7641 register_name = "TCBind"; 7642 break; 7643 case CP0_REG02__TCRESTART: 7644 CP0_CHECK(ctx->insn_flags & ASE_MT); 7645 gen_helper_mtc0_tcrestart(tcg_env, arg); 7646 register_name = "TCRestart"; 7647 break; 7648 case CP0_REG02__TCHALT: 7649 CP0_CHECK(ctx->insn_flags & ASE_MT); 7650 gen_helper_mtc0_tchalt(tcg_env, arg); 7651 register_name = "TCHalt"; 7652 break; 7653 case CP0_REG02__TCCONTEXT: 7654 CP0_CHECK(ctx->insn_flags & ASE_MT); 7655 gen_helper_mtc0_tccontext(tcg_env, arg); 7656 register_name = "TCContext"; 7657 break; 7658 case CP0_REG02__TCSCHEDULE: 7659 CP0_CHECK(ctx->insn_flags & ASE_MT); 7660 gen_helper_mtc0_tcschedule(tcg_env, arg); 7661 register_name = "TCSchedule"; 7662 break; 7663 case CP0_REG02__TCSCHEFBACK: 7664 CP0_CHECK(ctx->insn_flags & ASE_MT); 7665 gen_helper_mtc0_tcschefback(tcg_env, arg); 7666 register_name = "TCScheFBack"; 7667 break; 7668 default: 7669 goto cp0_unimplemented; 7670 } 7671 break; 7672 case CP0_REGISTER_03: 7673 switch (sel) { 7674 case CP0_REG03__ENTRYLO1: 7675 gen_helper_dmtc0_entrylo1(tcg_env, arg); 7676 register_name = "EntryLo1"; 7677 break; 7678 case CP0_REG03__GLOBALNUM: 7679 CP0_CHECK(ctx->vp); 7680 /* ignored */ 7681 register_name = "GlobalNumber"; 7682 break; 7683 default: 7684 goto cp0_unimplemented; 7685 } 7686 break; 7687 case CP0_REGISTER_04: 7688 switch (sel) { 7689 case CP0_REG04__CONTEXT: 7690 gen_helper_mtc0_context(tcg_env, arg); 7691 register_name = "Context"; 7692 break; 7693 case CP0_REG04__CONTEXTCONFIG: 7694 /* SmartMIPS ASE */ 7695 /* gen_helper_dmtc0_contextconfig(arg); */ 7696 register_name = "ContextConfig"; 7697 goto cp0_unimplemented; 7698 case CP0_REG04__USERLOCAL: 7699 CP0_CHECK(ctx->ulri); 7700 tcg_gen_st_tl(arg, tcg_env, 7701 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 7702 register_name = "UserLocal"; 7703 break; 7704 case CP0_REG04__MMID: 7705 CP0_CHECK(ctx->mi); 7706 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID)); 7707 register_name = "MMID"; 7708 break; 7709 default: 7710 goto cp0_unimplemented; 7711 } 7712 break; 7713 case CP0_REGISTER_05: 7714 switch (sel) { 7715 case CP0_REG05__PAGEMASK: 7716 gen_helper_mtc0_pagemask(tcg_env, arg); 7717 register_name = "PageMask"; 7718 break; 7719 case CP0_REG05__PAGEGRAIN: 7720 check_insn(ctx, ISA_MIPS_R2); 7721 gen_helper_mtc0_pagegrain(tcg_env, arg); 7722 register_name = "PageGrain"; 7723 break; 7724 case CP0_REG05__SEGCTL0: 7725 CP0_CHECK(ctx->sc); 7726 gen_helper_mtc0_segctl0(tcg_env, arg); 7727 register_name = "SegCtl0"; 7728 break; 7729 case CP0_REG05__SEGCTL1: 7730 CP0_CHECK(ctx->sc); 7731 gen_helper_mtc0_segctl1(tcg_env, arg); 7732 register_name = "SegCtl1"; 7733 break; 7734 case CP0_REG05__SEGCTL2: 7735 CP0_CHECK(ctx->sc); 7736 gen_helper_mtc0_segctl2(tcg_env, arg); 7737 register_name = "SegCtl2"; 7738 break; 7739 case CP0_REG05__PWBASE: 7740 check_pw(ctx); 7741 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWBase)); 7742 register_name = "PWBase"; 7743 break; 7744 case CP0_REG05__PWFIELD: 7745 check_pw(ctx); 7746 gen_helper_mtc0_pwfield(tcg_env, arg); 7747 register_name = "PWField"; 7748 break; 7749 case CP0_REG05__PWSIZE: 7750 check_pw(ctx); 7751 gen_helper_mtc0_pwsize(tcg_env, arg); 7752 register_name = "PWSize"; 7753 break; 7754 default: 7755 goto cp0_unimplemented; 7756 } 7757 break; 7758 case CP0_REGISTER_06: 7759 switch (sel) { 7760 case CP0_REG06__WIRED: 7761 gen_helper_mtc0_wired(tcg_env, arg); 7762 register_name = "Wired"; 7763 break; 7764 case CP0_REG06__SRSCONF0: 7765 check_insn(ctx, ISA_MIPS_R2); 7766 gen_helper_mtc0_srsconf0(tcg_env, arg); 7767 register_name = "SRSConf0"; 7768 break; 7769 case CP0_REG06__SRSCONF1: 7770 check_insn(ctx, ISA_MIPS_R2); 7771 gen_helper_mtc0_srsconf1(tcg_env, arg); 7772 register_name = "SRSConf1"; 7773 break; 7774 case CP0_REG06__SRSCONF2: 7775 check_insn(ctx, ISA_MIPS_R2); 7776 gen_helper_mtc0_srsconf2(tcg_env, arg); 7777 register_name = "SRSConf2"; 7778 break; 7779 case CP0_REG06__SRSCONF3: 7780 check_insn(ctx, ISA_MIPS_R2); 7781 gen_helper_mtc0_srsconf3(tcg_env, arg); 7782 register_name = "SRSConf3"; 7783 break; 7784 case CP0_REG06__SRSCONF4: 7785 check_insn(ctx, ISA_MIPS_R2); 7786 gen_helper_mtc0_srsconf4(tcg_env, arg); 7787 register_name = "SRSConf4"; 7788 break; 7789 case CP0_REG06__PWCTL: 7790 check_pw(ctx); 7791 gen_helper_mtc0_pwctl(tcg_env, arg); 7792 register_name = "PWCtl"; 7793 break; 7794 default: 7795 goto cp0_unimplemented; 7796 } 7797 break; 7798 case CP0_REGISTER_07: 7799 switch (sel) { 7800 case CP0_REG07__HWRENA: 7801 check_insn(ctx, ISA_MIPS_R2); 7802 gen_helper_mtc0_hwrena(tcg_env, arg); 7803 ctx->base.is_jmp = DISAS_STOP; 7804 register_name = "HWREna"; 7805 break; 7806 default: 7807 goto cp0_unimplemented; 7808 } 7809 break; 7810 case CP0_REGISTER_08: 7811 switch (sel) { 7812 case CP0_REG08__BADVADDR: 7813 /* ignored */ 7814 register_name = "BadVAddr"; 7815 break; 7816 case CP0_REG08__BADINSTR: 7817 /* ignored */ 7818 register_name = "BadInstr"; 7819 break; 7820 case CP0_REG08__BADINSTRP: 7821 /* ignored */ 7822 register_name = "BadInstrP"; 7823 break; 7824 case CP0_REG08__BADINSTRX: 7825 /* ignored */ 7826 register_name = "BadInstrX"; 7827 break; 7828 default: 7829 goto cp0_unimplemented; 7830 } 7831 break; 7832 case CP0_REGISTER_09: 7833 switch (sel) { 7834 case CP0_REG09__COUNT: 7835 gen_helper_mtc0_count(tcg_env, arg); 7836 register_name = "Count"; 7837 break; 7838 default: 7839 goto cp0_unimplemented; 7840 } 7841 /* Stop translation as we may have switched the execution mode */ 7842 ctx->base.is_jmp = DISAS_STOP; 7843 break; 7844 case CP0_REGISTER_10: 7845 switch (sel) { 7846 case CP0_REG10__ENTRYHI: 7847 gen_helper_mtc0_entryhi(tcg_env, arg); 7848 register_name = "EntryHi"; 7849 break; 7850 default: 7851 goto cp0_unimplemented; 7852 } 7853 break; 7854 case CP0_REGISTER_11: 7855 switch (sel) { 7856 case CP0_REG11__COMPARE: 7857 gen_helper_mtc0_compare(tcg_env, arg); 7858 register_name = "Compare"; 7859 break; 7860 /* 6,7 are implementation dependent */ 7861 default: 7862 goto cp0_unimplemented; 7863 } 7864 /* Stop translation as we may have switched the execution mode */ 7865 ctx->base.is_jmp = DISAS_STOP; 7866 break; 7867 case CP0_REGISTER_12: 7868 switch (sel) { 7869 case CP0_REG12__STATUS: 7870 save_cpu_state(ctx, 1); 7871 gen_helper_mtc0_status(tcg_env, arg); 7872 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 7873 gen_save_pc(ctx->base.pc_next + 4); 7874 ctx->base.is_jmp = DISAS_EXIT; 7875 register_name = "Status"; 7876 break; 7877 case CP0_REG12__INTCTL: 7878 check_insn(ctx, ISA_MIPS_R2); 7879 gen_helper_mtc0_intctl(tcg_env, arg); 7880 /* Stop translation as we may have switched the execution mode */ 7881 ctx->base.is_jmp = DISAS_STOP; 7882 register_name = "IntCtl"; 7883 break; 7884 case CP0_REG12__SRSCTL: 7885 check_insn(ctx, ISA_MIPS_R2); 7886 gen_helper_mtc0_srsctl(tcg_env, arg); 7887 /* Stop translation as we may have switched the execution mode */ 7888 ctx->base.is_jmp = DISAS_STOP; 7889 register_name = "SRSCtl"; 7890 break; 7891 case CP0_REG12__SRSMAP: 7892 check_insn(ctx, ISA_MIPS_R2); 7893 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); 7894 /* Stop translation as we may have switched the execution mode */ 7895 ctx->base.is_jmp = DISAS_STOP; 7896 register_name = "SRSMap"; 7897 break; 7898 default: 7899 goto cp0_unimplemented; 7900 } 7901 break; 7902 case CP0_REGISTER_13: 7903 switch (sel) { 7904 case CP0_REG13__CAUSE: 7905 save_cpu_state(ctx, 1); 7906 gen_helper_mtc0_cause(tcg_env, arg); 7907 /* 7908 * Stop translation as we may have triggered an interrupt. 7909 * DISAS_STOP isn't sufficient, we need to ensure we break out of 7910 * translated code to check for pending interrupts. 7911 */ 7912 gen_save_pc(ctx->base.pc_next + 4); 7913 ctx->base.is_jmp = DISAS_EXIT; 7914 register_name = "Cause"; 7915 break; 7916 default: 7917 goto cp0_unimplemented; 7918 } 7919 break; 7920 case CP0_REGISTER_14: 7921 switch (sel) { 7922 case CP0_REG14__EPC: 7923 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC)); 7924 register_name = "EPC"; 7925 break; 7926 default: 7927 goto cp0_unimplemented; 7928 } 7929 break; 7930 case CP0_REGISTER_15: 7931 switch (sel) { 7932 case CP0_REG15__PRID: 7933 /* ignored */ 7934 register_name = "PRid"; 7935 break; 7936 case CP0_REG15__EBASE: 7937 check_insn(ctx, ISA_MIPS_R2); 7938 gen_helper_mtc0_ebase(tcg_env, arg); 7939 register_name = "EBase"; 7940 break; 7941 default: 7942 goto cp0_unimplemented; 7943 } 7944 break; 7945 case CP0_REGISTER_16: 7946 switch (sel) { 7947 case CP0_REG16__CONFIG: 7948 gen_helper_mtc0_config0(tcg_env, arg); 7949 register_name = "Config"; 7950 /* Stop translation as we may have switched the execution mode */ 7951 ctx->base.is_jmp = DISAS_STOP; 7952 break; 7953 case CP0_REG16__CONFIG1: 7954 /* ignored, read only */ 7955 register_name = "Config1"; 7956 break; 7957 case CP0_REG16__CONFIG2: 7958 gen_helper_mtc0_config2(tcg_env, arg); 7959 register_name = "Config2"; 7960 /* Stop translation as we may have switched the execution mode */ 7961 ctx->base.is_jmp = DISAS_STOP; 7962 break; 7963 case CP0_REG16__CONFIG3: 7964 gen_helper_mtc0_config3(tcg_env, arg); 7965 register_name = "Config3"; 7966 /* Stop translation as we may have switched the execution mode */ 7967 ctx->base.is_jmp = DISAS_STOP; 7968 break; 7969 case CP0_REG16__CONFIG4: 7970 /* currently ignored */ 7971 register_name = "Config4"; 7972 break; 7973 case CP0_REG16__CONFIG5: 7974 gen_helper_mtc0_config5(tcg_env, arg); 7975 register_name = "Config5"; 7976 /* Stop translation as we may have switched the execution mode */ 7977 ctx->base.is_jmp = DISAS_STOP; 7978 break; 7979 /* 6,7 are implementation dependent */ 7980 default: 7981 register_name = "Invalid config selector"; 7982 goto cp0_unimplemented; 7983 } 7984 break; 7985 case CP0_REGISTER_17: 7986 switch (sel) { 7987 case CP0_REG17__LLADDR: 7988 gen_helper_mtc0_lladdr(tcg_env, arg); 7989 register_name = "LLAddr"; 7990 break; 7991 case CP0_REG17__MAAR: 7992 CP0_CHECK(ctx->mrp); 7993 gen_helper_mtc0_maar(tcg_env, arg); 7994 register_name = "MAAR"; 7995 break; 7996 case CP0_REG17__MAARI: 7997 CP0_CHECK(ctx->mrp); 7998 gen_helper_mtc0_maari(tcg_env, arg); 7999 register_name = "MAARI"; 8000 break; 8001 default: 8002 goto cp0_unimplemented; 8003 } 8004 break; 8005 case CP0_REGISTER_18: 8006 switch (sel) { 8007 case CP0_REG18__WATCHLO0: 8008 case CP0_REG18__WATCHLO1: 8009 case CP0_REG18__WATCHLO2: 8010 case CP0_REG18__WATCHLO3: 8011 case CP0_REG18__WATCHLO4: 8012 case CP0_REG18__WATCHLO5: 8013 case CP0_REG18__WATCHLO6: 8014 case CP0_REG18__WATCHLO7: 8015 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 8016 gen_helper_0e1i(mtc0_watchlo, arg, sel); 8017 register_name = "WatchLo"; 8018 break; 8019 default: 8020 goto cp0_unimplemented; 8021 } 8022 break; 8023 case CP0_REGISTER_19: 8024 switch (sel) { 8025 case CP0_REG19__WATCHHI0: 8026 case CP0_REG19__WATCHHI1: 8027 case CP0_REG19__WATCHHI2: 8028 case CP0_REG19__WATCHHI3: 8029 case CP0_REG19__WATCHHI4: 8030 case CP0_REG19__WATCHHI5: 8031 case CP0_REG19__WATCHHI6: 8032 case CP0_REG19__WATCHHI7: 8033 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); 8034 gen_helper_0e1i(mtc0_watchhi, arg, sel); 8035 register_name = "WatchHi"; 8036 break; 8037 default: 8038 goto cp0_unimplemented; 8039 } 8040 break; 8041 case CP0_REGISTER_20: 8042 switch (sel) { 8043 case CP0_REG20__XCONTEXT: 8044 check_insn(ctx, ISA_MIPS3); 8045 gen_helper_mtc0_xcontext(tcg_env, arg); 8046 register_name = "XContext"; 8047 break; 8048 default: 8049 goto cp0_unimplemented; 8050 } 8051 break; 8052 case CP0_REGISTER_21: 8053 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 8054 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); 8055 switch (sel) { 8056 case 0: 8057 gen_helper_mtc0_framemask(tcg_env, arg); 8058 register_name = "Framemask"; 8059 break; 8060 default: 8061 goto cp0_unimplemented; 8062 } 8063 break; 8064 case CP0_REGISTER_22: 8065 /* ignored */ 8066 register_name = "Diagnostic"; /* implementation dependent */ 8067 break; 8068 case CP0_REGISTER_23: 8069 switch (sel) { 8070 case CP0_REG23__DEBUG: 8071 gen_helper_mtc0_debug(tcg_env, arg); /* EJTAG support */ 8072 /* DISAS_STOP isn't good enough here, hflags may have changed. */ 8073 gen_save_pc(ctx->base.pc_next + 4); 8074 ctx->base.is_jmp = DISAS_EXIT; 8075 register_name = "Debug"; 8076 break; 8077 case CP0_REG23__TRACECONTROL: 8078 /* PDtrace support */ 8079 /* gen_helper_mtc0_tracecontrol(tcg_env, arg); */ 8080 /* Stop translation as we may have switched the execution mode */ 8081 ctx->base.is_jmp = DISAS_STOP; 8082 register_name = "TraceControl"; 8083 goto cp0_unimplemented; 8084 case CP0_REG23__TRACECONTROL2: 8085 /* PDtrace support */ 8086 /* gen_helper_mtc0_tracecontrol2(tcg_env, arg); */ 8087 /* Stop translation as we may have switched the execution mode */ 8088 ctx->base.is_jmp = DISAS_STOP; 8089 register_name = "TraceControl2"; 8090 goto cp0_unimplemented; 8091 case CP0_REG23__USERTRACEDATA1: 8092 /* PDtrace support */ 8093 /* gen_helper_mtc0_usertracedata1(tcg_env, arg);*/ 8094 /* Stop translation as we may have switched the execution mode */ 8095 ctx->base.is_jmp = DISAS_STOP; 8096 register_name = "UserTraceData1"; 8097 goto cp0_unimplemented; 8098 case CP0_REG23__TRACEIBPC: 8099 /* PDtrace support */ 8100 /* gen_helper_mtc0_traceibpc(tcg_env, arg); */ 8101 /* Stop translation as we may have switched the execution mode */ 8102 ctx->base.is_jmp = DISAS_STOP; 8103 register_name = "TraceIBPC"; 8104 goto cp0_unimplemented; 8105 case CP0_REG23__TRACEDBPC: 8106 /* PDtrace support */ 8107 /* gen_helper_mtc0_tracedbpc(tcg_env, arg); */ 8108 /* Stop translation as we may have switched the execution mode */ 8109 ctx->base.is_jmp = DISAS_STOP; 8110 register_name = "TraceDBPC"; 8111 goto cp0_unimplemented; 8112 default: 8113 goto cp0_unimplemented; 8114 } 8115 break; 8116 case CP0_REGISTER_24: 8117 switch (sel) { 8118 case CP0_REG24__DEPC: 8119 /* EJTAG support */ 8120 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC)); 8121 register_name = "DEPC"; 8122 break; 8123 default: 8124 goto cp0_unimplemented; 8125 } 8126 break; 8127 case CP0_REGISTER_25: 8128 switch (sel) { 8129 case CP0_REG25__PERFCTL0: 8130 gen_helper_mtc0_performance0(tcg_env, arg); 8131 register_name = "Performance0"; 8132 break; 8133 case CP0_REG25__PERFCNT0: 8134 /* gen_helper_mtc0_performance1(tcg_env, arg); */ 8135 register_name = "Performance1"; 8136 goto cp0_unimplemented; 8137 case CP0_REG25__PERFCTL1: 8138 /* gen_helper_mtc0_performance2(tcg_env, arg); */ 8139 register_name = "Performance2"; 8140 goto cp0_unimplemented; 8141 case CP0_REG25__PERFCNT1: 8142 /* gen_helper_mtc0_performance3(tcg_env, arg); */ 8143 register_name = "Performance3"; 8144 goto cp0_unimplemented; 8145 case CP0_REG25__PERFCTL2: 8146 /* gen_helper_mtc0_performance4(tcg_env, arg); */ 8147 register_name = "Performance4"; 8148 goto cp0_unimplemented; 8149 case CP0_REG25__PERFCNT2: 8150 /* gen_helper_mtc0_performance5(tcg_env, arg); */ 8151 register_name = "Performance5"; 8152 goto cp0_unimplemented; 8153 case CP0_REG25__PERFCTL3: 8154 /* gen_helper_mtc0_performance6(tcg_env, arg); */ 8155 register_name = "Performance6"; 8156 goto cp0_unimplemented; 8157 case CP0_REG25__PERFCNT3: 8158 /* gen_helper_mtc0_performance7(tcg_env, arg); */ 8159 register_name = "Performance7"; 8160 goto cp0_unimplemented; 8161 default: 8162 goto cp0_unimplemented; 8163 } 8164 break; 8165 case CP0_REGISTER_26: 8166 switch (sel) { 8167 case CP0_REG26__ERRCTL: 8168 gen_helper_mtc0_errctl(tcg_env, arg); 8169 ctx->base.is_jmp = DISAS_STOP; 8170 register_name = "ErrCtl"; 8171 break; 8172 default: 8173 goto cp0_unimplemented; 8174 } 8175 break; 8176 case CP0_REGISTER_27: 8177 switch (sel) { 8178 case CP0_REG27__CACHERR: 8179 /* ignored */ 8180 register_name = "CacheErr"; 8181 break; 8182 default: 8183 goto cp0_unimplemented; 8184 } 8185 break; 8186 case CP0_REGISTER_28: 8187 switch (sel) { 8188 case CP0_REG28__TAGLO: 8189 case CP0_REG28__TAGLO1: 8190 case CP0_REG28__TAGLO2: 8191 case CP0_REG28__TAGLO3: 8192 gen_helper_mtc0_taglo(tcg_env, arg); 8193 register_name = "TagLo"; 8194 break; 8195 case CP0_REG28__DATALO: 8196 case CP0_REG28__DATALO1: 8197 case CP0_REG28__DATALO2: 8198 case CP0_REG28__DATALO3: 8199 gen_helper_mtc0_datalo(tcg_env, arg); 8200 register_name = "DataLo"; 8201 break; 8202 default: 8203 goto cp0_unimplemented; 8204 } 8205 break; 8206 case CP0_REGISTER_29: 8207 switch (sel) { 8208 case CP0_REG29__TAGHI: 8209 case CP0_REG29__TAGHI1: 8210 case CP0_REG29__TAGHI2: 8211 case CP0_REG29__TAGHI3: 8212 gen_helper_mtc0_taghi(tcg_env, arg); 8213 register_name = "TagHi"; 8214 break; 8215 case CP0_REG29__DATAHI: 8216 case CP0_REG29__DATAHI1: 8217 case CP0_REG29__DATAHI2: 8218 case CP0_REG29__DATAHI3: 8219 gen_helper_mtc0_datahi(tcg_env, arg); 8220 register_name = "DataHi"; 8221 break; 8222 default: 8223 register_name = "invalid sel"; 8224 goto cp0_unimplemented; 8225 } 8226 break; 8227 case CP0_REGISTER_30: 8228 switch (sel) { 8229 case CP0_REG30__ERROREPC: 8230 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); 8231 register_name = "ErrorEPC"; 8232 break; 8233 default: 8234 goto cp0_unimplemented; 8235 } 8236 break; 8237 case CP0_REGISTER_31: 8238 switch (sel) { 8239 case CP0_REG31__DESAVE: 8240 /* EJTAG support */ 8241 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE)); 8242 register_name = "DESAVE"; 8243 break; 8244 case CP0_REG31__KSCRATCH1: 8245 case CP0_REG31__KSCRATCH2: 8246 case CP0_REG31__KSCRATCH3: 8247 case CP0_REG31__KSCRATCH4: 8248 case CP0_REG31__KSCRATCH5: 8249 case CP0_REG31__KSCRATCH6: 8250 CP0_CHECK(ctx->kscrexist & (1 << sel)); 8251 tcg_gen_st_tl(arg, tcg_env, 8252 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); 8253 register_name = "KScratch"; 8254 break; 8255 default: 8256 goto cp0_unimplemented; 8257 } 8258 break; 8259 default: 8260 goto cp0_unimplemented; 8261 } 8262 trace_mips_translate_c0("dmtc0", register_name, reg, sel); 8263 8264 /* For simplicity assume that all writes can cause interrupts. */ 8265 if (icount) { 8266 /* 8267 * DISAS_STOP isn't sufficient, we need to ensure we break out of 8268 * translated code to check for pending interrupts. 8269 */ 8270 gen_save_pc(ctx->base.pc_next + 4); 8271 ctx->base.is_jmp = DISAS_EXIT; 8272 } 8273 return; 8274 8275 cp0_unimplemented: 8276 qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n", 8277 register_name, reg, sel); 8278 } 8279 #endif /* TARGET_MIPS64 */ 8280 8281 static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, 8282 int u, int sel, int h) 8283 { 8284 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 8285 TCGv t0 = tcg_temp_new(); 8286 8287 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && 8288 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != 8289 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { 8290 tcg_gen_movi_tl(t0, -1); 8291 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > 8292 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { 8293 tcg_gen_movi_tl(t0, -1); 8294 } else if (u == 0) { 8295 switch (rt) { 8296 case 1: 8297 switch (sel) { 8298 case 1: 8299 gen_helper_mftc0_vpecontrol(t0, tcg_env); 8300 break; 8301 case 2: 8302 gen_helper_mftc0_vpeconf0(t0, tcg_env); 8303 break; 8304 default: 8305 goto die; 8306 break; 8307 } 8308 break; 8309 case 2: 8310 switch (sel) { 8311 case 1: 8312 gen_helper_mftc0_tcstatus(t0, tcg_env); 8313 break; 8314 case 2: 8315 gen_helper_mftc0_tcbind(t0, tcg_env); 8316 break; 8317 case 3: 8318 gen_helper_mftc0_tcrestart(t0, tcg_env); 8319 break; 8320 case 4: 8321 gen_helper_mftc0_tchalt(t0, tcg_env); 8322 break; 8323 case 5: 8324 gen_helper_mftc0_tccontext(t0, tcg_env); 8325 break; 8326 case 6: 8327 gen_helper_mftc0_tcschedule(t0, tcg_env); 8328 break; 8329 case 7: 8330 gen_helper_mftc0_tcschefback(t0, tcg_env); 8331 break; 8332 default: 8333 gen_mfc0(ctx, t0, rt, sel); 8334 break; 8335 } 8336 break; 8337 case 10: 8338 switch (sel) { 8339 case 0: 8340 gen_helper_mftc0_entryhi(t0, tcg_env); 8341 break; 8342 default: 8343 gen_mfc0(ctx, t0, rt, sel); 8344 break; 8345 } 8346 break; 8347 case 12: 8348 switch (sel) { 8349 case 0: 8350 gen_helper_mftc0_status(t0, tcg_env); 8351 break; 8352 default: 8353 gen_mfc0(ctx, t0, rt, sel); 8354 break; 8355 } 8356 break; 8357 case 13: 8358 switch (sel) { 8359 case 0: 8360 gen_helper_mftc0_cause(t0, tcg_env); 8361 break; 8362 default: 8363 goto die; 8364 break; 8365 } 8366 break; 8367 case 14: 8368 switch (sel) { 8369 case 0: 8370 gen_helper_mftc0_epc(t0, tcg_env); 8371 break; 8372 default: 8373 goto die; 8374 break; 8375 } 8376 break; 8377 case 15: 8378 switch (sel) { 8379 case 1: 8380 gen_helper_mftc0_ebase(t0, tcg_env); 8381 break; 8382 default: 8383 goto die; 8384 break; 8385 } 8386 break; 8387 case 16: 8388 switch (sel) { 8389 case 0: 8390 case 1: 8391 case 2: 8392 case 3: 8393 case 4: 8394 case 5: 8395 case 6: 8396 case 7: 8397 gen_helper_mftc0_configx(t0, tcg_env, tcg_constant_tl(sel)); 8398 break; 8399 default: 8400 goto die; 8401 break; 8402 } 8403 break; 8404 case 23: 8405 switch (sel) { 8406 case 0: 8407 gen_helper_mftc0_debug(t0, tcg_env); 8408 break; 8409 default: 8410 gen_mfc0(ctx, t0, rt, sel); 8411 break; 8412 } 8413 break; 8414 default: 8415 gen_mfc0(ctx, t0, rt, sel); 8416 } 8417 } else { 8418 switch (sel) { 8419 /* GPR registers. */ 8420 case 0: 8421 gen_helper_1e0i(mftgpr, t0, rt); 8422 break; 8423 /* Auxiliary CPU registers */ 8424 case 1: 8425 switch (rt) { 8426 case 0: 8427 gen_helper_1e0i(mftlo, t0, 0); 8428 break; 8429 case 1: 8430 gen_helper_1e0i(mfthi, t0, 0); 8431 break; 8432 case 2: 8433 gen_helper_1e0i(mftacx, t0, 0); 8434 break; 8435 case 4: 8436 gen_helper_1e0i(mftlo, t0, 1); 8437 break; 8438 case 5: 8439 gen_helper_1e0i(mfthi, t0, 1); 8440 break; 8441 case 6: 8442 gen_helper_1e0i(mftacx, t0, 1); 8443 break; 8444 case 8: 8445 gen_helper_1e0i(mftlo, t0, 2); 8446 break; 8447 case 9: 8448 gen_helper_1e0i(mfthi, t0, 2); 8449 break; 8450 case 10: 8451 gen_helper_1e0i(mftacx, t0, 2); 8452 break; 8453 case 12: 8454 gen_helper_1e0i(mftlo, t0, 3); 8455 break; 8456 case 13: 8457 gen_helper_1e0i(mfthi, t0, 3); 8458 break; 8459 case 14: 8460 gen_helper_1e0i(mftacx, t0, 3); 8461 break; 8462 case 16: 8463 gen_helper_mftdsp(t0, tcg_env); 8464 break; 8465 default: 8466 goto die; 8467 } 8468 break; 8469 /* Floating point (COP1). */ 8470 case 2: 8471 /* XXX: For now we support only a single FPU context. */ 8472 if (h == 0) { 8473 TCGv_i32 fp0 = tcg_temp_new_i32(); 8474 8475 gen_load_fpr32(ctx, fp0, rt); 8476 tcg_gen_ext_i32_tl(t0, fp0); 8477 } else { 8478 TCGv_i32 fp0 = tcg_temp_new_i32(); 8479 8480 gen_load_fpr32h(ctx, fp0, rt); 8481 tcg_gen_ext_i32_tl(t0, fp0); 8482 } 8483 break; 8484 case 3: 8485 /* XXX: For now we support only a single FPU context. */ 8486 gen_helper_1e0i(cfc1, t0, rt); 8487 break; 8488 /* COP2: Not implemented. */ 8489 case 4: 8490 case 5: 8491 /* fall through */ 8492 default: 8493 goto die; 8494 } 8495 } 8496 trace_mips_translate_tr("mftr", rt, u, sel, h); 8497 gen_store_gpr(t0, rd); 8498 return; 8499 8500 die: 8501 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); 8502 gen_reserved_instruction(ctx); 8503 } 8504 8505 static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, 8506 int u, int sel, int h) 8507 { 8508 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); 8509 TCGv t0 = tcg_temp_new(); 8510 8511 gen_load_gpr(t0, rt); 8512 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && 8513 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != 8514 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { 8515 /* NOP */ 8516 ; 8517 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > 8518 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { 8519 /* NOP */ 8520 ; 8521 } else if (u == 0) { 8522 switch (rd) { 8523 case 1: 8524 switch (sel) { 8525 case 1: 8526 gen_helper_mttc0_vpecontrol(tcg_env, t0); 8527 break; 8528 case 2: 8529 gen_helper_mttc0_vpeconf0(tcg_env, t0); 8530 break; 8531 default: 8532 goto die; 8533 break; 8534 } 8535 break; 8536 case 2: 8537 switch (sel) { 8538 case 1: 8539 gen_helper_mttc0_tcstatus(tcg_env, t0); 8540 break; 8541 case 2: 8542 gen_helper_mttc0_tcbind(tcg_env, t0); 8543 break; 8544 case 3: 8545 gen_helper_mttc0_tcrestart(tcg_env, t0); 8546 break; 8547 case 4: 8548 gen_helper_mttc0_tchalt(tcg_env, t0); 8549 break; 8550 case 5: 8551 gen_helper_mttc0_tccontext(tcg_env, t0); 8552 break; 8553 case 6: 8554 gen_helper_mttc0_tcschedule(tcg_env, t0); 8555 break; 8556 case 7: 8557 gen_helper_mttc0_tcschefback(tcg_env, t0); 8558 break; 8559 default: 8560 gen_mtc0(ctx, t0, rd, sel); 8561 break; 8562 } 8563 break; 8564 case 10: 8565 switch (sel) { 8566 case 0: 8567 gen_helper_mttc0_entryhi(tcg_env, t0); 8568 break; 8569 default: 8570 gen_mtc0(ctx, t0, rd, sel); 8571 break; 8572 } 8573 break; 8574 case 12: 8575 switch (sel) { 8576 case 0: 8577 gen_helper_mttc0_status(tcg_env, t0); 8578 break; 8579 default: 8580 gen_mtc0(ctx, t0, rd, sel); 8581 break; 8582 } 8583 break; 8584 case 13: 8585 switch (sel) { 8586 case 0: 8587 gen_helper_mttc0_cause(tcg_env, t0); 8588 break; 8589 default: 8590 goto die; 8591 break; 8592 } 8593 break; 8594 case 15: 8595 switch (sel) { 8596 case 1: 8597 gen_helper_mttc0_ebase(tcg_env, t0); 8598 break; 8599 default: 8600 goto die; 8601 break; 8602 } 8603 break; 8604 case 23: 8605 switch (sel) { 8606 case 0: 8607 gen_helper_mttc0_debug(tcg_env, t0); 8608 break; 8609 default: 8610 gen_mtc0(ctx, t0, rd, sel); 8611 break; 8612 } 8613 break; 8614 default: 8615 gen_mtc0(ctx, t0, rd, sel); 8616 } 8617 } else { 8618 switch (sel) { 8619 /* GPR registers. */ 8620 case 0: 8621 gen_helper_0e1i(mttgpr, t0, rd); 8622 break; 8623 /* Auxiliary CPU registers */ 8624 case 1: 8625 switch (rd) { 8626 case 0: 8627 gen_helper_0e1i(mttlo, t0, 0); 8628 break; 8629 case 1: 8630 gen_helper_0e1i(mtthi, t0, 0); 8631 break; 8632 case 2: 8633 gen_helper_0e1i(mttacx, t0, 0); 8634 break; 8635 case 4: 8636 gen_helper_0e1i(mttlo, t0, 1); 8637 break; 8638 case 5: 8639 gen_helper_0e1i(mtthi, t0, 1); 8640 break; 8641 case 6: 8642 gen_helper_0e1i(mttacx, t0, 1); 8643 break; 8644 case 8: 8645 gen_helper_0e1i(mttlo, t0, 2); 8646 break; 8647 case 9: 8648 gen_helper_0e1i(mtthi, t0, 2); 8649 break; 8650 case 10: 8651 gen_helper_0e1i(mttacx, t0, 2); 8652 break; 8653 case 12: 8654 gen_helper_0e1i(mttlo, t0, 3); 8655 break; 8656 case 13: 8657 gen_helper_0e1i(mtthi, t0, 3); 8658 break; 8659 case 14: 8660 gen_helper_0e1i(mttacx, t0, 3); 8661 break; 8662 case 16: 8663 gen_helper_mttdsp(tcg_env, t0); 8664 break; 8665 default: 8666 goto die; 8667 } 8668 break; 8669 /* Floating point (COP1). */ 8670 case 2: 8671 /* XXX: For now we support only a single FPU context. */ 8672 if (h == 0) { 8673 TCGv_i32 fp0 = tcg_temp_new_i32(); 8674 8675 tcg_gen_trunc_tl_i32(fp0, t0); 8676 gen_store_fpr32(ctx, fp0, rd); 8677 } else { 8678 TCGv_i32 fp0 = tcg_temp_new_i32(); 8679 8680 tcg_gen_trunc_tl_i32(fp0, t0); 8681 gen_store_fpr32h(ctx, fp0, rd); 8682 } 8683 break; 8684 case 3: 8685 /* XXX: For now we support only a single FPU context. */ 8686 gen_helper_0e2i(ctc1, t0, tcg_constant_i32(rd), rt); 8687 /* Stop translation as we may have changed hflags */ 8688 ctx->base.is_jmp = DISAS_STOP; 8689 break; 8690 /* COP2: Not implemented. */ 8691 case 4: 8692 case 5: 8693 /* fall through */ 8694 default: 8695 goto die; 8696 } 8697 } 8698 trace_mips_translate_tr("mttr", rd, u, sel, h); 8699 return; 8700 8701 die: 8702 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); 8703 gen_reserved_instruction(ctx); 8704 } 8705 8706 static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, 8707 int rt, int rd) 8708 { 8709 const char *opn = "ldst"; 8710 8711 check_cp0_enabled(ctx); 8712 switch (opc) { 8713 case OPC_MFC0: 8714 if (rt == 0) { 8715 /* Treat as NOP. */ 8716 return; 8717 } 8718 gen_mfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); 8719 opn = "mfc0"; 8720 break; 8721 case OPC_MTC0: 8722 { 8723 TCGv t0 = tcg_temp_new(); 8724 8725 gen_load_gpr(t0, rt); 8726 gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7); 8727 } 8728 opn = "mtc0"; 8729 break; 8730 #if defined(TARGET_MIPS64) 8731 case OPC_DMFC0: 8732 check_insn(ctx, ISA_MIPS3); 8733 if (rt == 0) { 8734 /* Treat as NOP. */ 8735 return; 8736 } 8737 gen_dmfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); 8738 opn = "dmfc0"; 8739 break; 8740 case OPC_DMTC0: 8741 check_insn(ctx, ISA_MIPS3); 8742 { 8743 TCGv t0 = tcg_temp_new(); 8744 8745 gen_load_gpr(t0, rt); 8746 gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7); 8747 } 8748 opn = "dmtc0"; 8749 break; 8750 #endif 8751 case OPC_MFHC0: 8752 check_mvh(ctx); 8753 if (rt == 0) { 8754 /* Treat as NOP. */ 8755 return; 8756 } 8757 gen_mfhc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); 8758 opn = "mfhc0"; 8759 break; 8760 case OPC_MTHC0: 8761 check_mvh(ctx); 8762 { 8763 TCGv t0 = tcg_temp_new(); 8764 gen_load_gpr(t0, rt); 8765 gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7); 8766 } 8767 opn = "mthc0"; 8768 break; 8769 case OPC_MFTR: 8770 check_cp0_enabled(ctx); 8771 if (rd == 0) { 8772 /* Treat as NOP. */ 8773 return; 8774 } 8775 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1, 8776 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); 8777 opn = "mftr"; 8778 break; 8779 case OPC_MTTR: 8780 check_cp0_enabled(ctx); 8781 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1, 8782 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); 8783 opn = "mttr"; 8784 break; 8785 case OPC_TLBWI: 8786 opn = "tlbwi"; 8787 if (!env->tlb->helper_tlbwi) { 8788 goto die; 8789 } 8790 gen_helper_tlbwi(tcg_env); 8791 break; 8792 case OPC_TLBINV: 8793 opn = "tlbinv"; 8794 if (ctx->ie >= 2) { 8795 if (!env->tlb->helper_tlbinv) { 8796 goto die; 8797 } 8798 gen_helper_tlbinv(tcg_env); 8799 } /* treat as nop if TLBINV not supported */ 8800 break; 8801 case OPC_TLBINVF: 8802 opn = "tlbinvf"; 8803 if (ctx->ie >= 2) { 8804 if (!env->tlb->helper_tlbinvf) { 8805 goto die; 8806 } 8807 gen_helper_tlbinvf(tcg_env); 8808 } /* treat as nop if TLBINV not supported */ 8809 break; 8810 case OPC_TLBWR: 8811 opn = "tlbwr"; 8812 if (!env->tlb->helper_tlbwr) { 8813 goto die; 8814 } 8815 gen_helper_tlbwr(tcg_env); 8816 break; 8817 case OPC_TLBP: 8818 opn = "tlbp"; 8819 if (!env->tlb->helper_tlbp) { 8820 goto die; 8821 } 8822 gen_helper_tlbp(tcg_env); 8823 break; 8824 case OPC_TLBR: 8825 opn = "tlbr"; 8826 if (!env->tlb->helper_tlbr) { 8827 goto die; 8828 } 8829 gen_helper_tlbr(tcg_env); 8830 break; 8831 case OPC_ERET: /* OPC_ERETNC */ 8832 if ((ctx->insn_flags & ISA_MIPS_R6) && 8833 (ctx->hflags & MIPS_HFLAG_BMASK)) { 8834 goto die; 8835 } else { 8836 int bit_shift = (ctx->hflags & MIPS_HFLAG_M16) ? 16 : 6; 8837 if (ctx->opcode & (1 << bit_shift)) { 8838 /* OPC_ERETNC */ 8839 opn = "eretnc"; 8840 check_insn(ctx, ISA_MIPS_R5); 8841 gen_helper_eretnc(tcg_env); 8842 } else { 8843 /* OPC_ERET */ 8844 opn = "eret"; 8845 check_insn(ctx, ISA_MIPS2); 8846 gen_helper_eret(tcg_env); 8847 } 8848 ctx->base.is_jmp = DISAS_EXIT; 8849 } 8850 break; 8851 case OPC_DERET: 8852 opn = "deret"; 8853 check_insn(ctx, ISA_MIPS_R1); 8854 if ((ctx->insn_flags & ISA_MIPS_R6) && 8855 (ctx->hflags & MIPS_HFLAG_BMASK)) { 8856 goto die; 8857 } 8858 if (!(ctx->hflags & MIPS_HFLAG_DM)) { 8859 MIPS_INVAL(opn); 8860 gen_reserved_instruction(ctx); 8861 } else { 8862 gen_helper_deret(tcg_env); 8863 ctx->base.is_jmp = DISAS_EXIT; 8864 } 8865 break; 8866 case OPC_WAIT: 8867 opn = "wait"; 8868 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); 8869 if ((ctx->insn_flags & ISA_MIPS_R6) && 8870 (ctx->hflags & MIPS_HFLAG_BMASK)) { 8871 goto die; 8872 } 8873 /* If we get an exception, we want to restart at next instruction */ 8874 ctx->base.pc_next += 4; 8875 save_cpu_state(ctx, 1); 8876 ctx->base.pc_next -= 4; 8877 gen_helper_wait(tcg_env); 8878 ctx->base.is_jmp = DISAS_NORETURN; 8879 break; 8880 default: 8881 die: 8882 MIPS_INVAL(opn); 8883 gen_reserved_instruction(ctx); 8884 return; 8885 } 8886 (void)opn; /* avoid a compiler warning */ 8887 } 8888 #endif /* !CONFIG_USER_ONLY */ 8889 8890 /* CP1 Branches (before delay slot) */ 8891 static void gen_compute_branch1(DisasContext *ctx, uint32_t op, 8892 int32_t cc, int32_t offset) 8893 { 8894 target_ulong btarget; 8895 TCGv_i32 t0 = tcg_temp_new_i32(); 8896 8897 if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { 8898 gen_reserved_instruction(ctx); 8899 return; 8900 } 8901 8902 if (cc != 0) { 8903 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); 8904 } 8905 8906 btarget = ctx->base.pc_next + 4 + offset; 8907 8908 switch (op) { 8909 case OPC_BC1F: 8910 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8911 tcg_gen_not_i32(t0, t0); 8912 tcg_gen_andi_i32(t0, t0, 1); 8913 tcg_gen_extu_i32_tl(bcond, t0); 8914 goto not_likely; 8915 case OPC_BC1FL: 8916 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8917 tcg_gen_not_i32(t0, t0); 8918 tcg_gen_andi_i32(t0, t0, 1); 8919 tcg_gen_extu_i32_tl(bcond, t0); 8920 goto likely; 8921 case OPC_BC1T: 8922 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8923 tcg_gen_andi_i32(t0, t0, 1); 8924 tcg_gen_extu_i32_tl(bcond, t0); 8925 goto not_likely; 8926 case OPC_BC1TL: 8927 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8928 tcg_gen_andi_i32(t0, t0, 1); 8929 tcg_gen_extu_i32_tl(bcond, t0); 8930 likely: 8931 ctx->hflags |= MIPS_HFLAG_BL; 8932 break; 8933 case OPC_BC1FANY2: 8934 { 8935 TCGv_i32 t1 = tcg_temp_new_i32(); 8936 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8937 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 8938 tcg_gen_nand_i32(t0, t0, t1); 8939 tcg_gen_andi_i32(t0, t0, 1); 8940 tcg_gen_extu_i32_tl(bcond, t0); 8941 } 8942 goto not_likely; 8943 case OPC_BC1TANY2: 8944 { 8945 TCGv_i32 t1 = tcg_temp_new_i32(); 8946 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8947 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 8948 tcg_gen_or_i32(t0, t0, t1); 8949 tcg_gen_andi_i32(t0, t0, 1); 8950 tcg_gen_extu_i32_tl(bcond, t0); 8951 } 8952 goto not_likely; 8953 case OPC_BC1FANY4: 8954 { 8955 TCGv_i32 t1 = tcg_temp_new_i32(); 8956 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8957 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 8958 tcg_gen_and_i32(t0, t0, t1); 8959 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2)); 8960 tcg_gen_and_i32(t0, t0, t1); 8961 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3)); 8962 tcg_gen_nand_i32(t0, t0, t1); 8963 tcg_gen_andi_i32(t0, t0, 1); 8964 tcg_gen_extu_i32_tl(bcond, t0); 8965 } 8966 goto not_likely; 8967 case OPC_BC1TANY4: 8968 { 8969 TCGv_i32 t1 = tcg_temp_new_i32(); 8970 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); 8971 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); 8972 tcg_gen_or_i32(t0, t0, t1); 8973 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2)); 8974 tcg_gen_or_i32(t0, t0, t1); 8975 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3)); 8976 tcg_gen_or_i32(t0, t0, t1); 8977 tcg_gen_andi_i32(t0, t0, 1); 8978 tcg_gen_extu_i32_tl(bcond, t0); 8979 } 8980 not_likely: 8981 ctx->hflags |= MIPS_HFLAG_BC; 8982 break; 8983 default: 8984 MIPS_INVAL("cp1 cond branch"); 8985 gen_reserved_instruction(ctx); 8986 return; 8987 } 8988 ctx->btarget = btarget; 8989 ctx->hflags |= MIPS_HFLAG_BDS32; 8990 } 8991 8992 /* R6 CP1 Branches */ 8993 static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op, 8994 int32_t ft, int32_t offset, 8995 int delayslot_size) 8996 { 8997 target_ulong btarget; 8998 TCGv_i64 t0 = tcg_temp_new_i64(); 8999 9000 if (ctx->hflags & MIPS_HFLAG_BMASK) { 9001 #ifdef MIPS_DEBUG_DISAS 9002 LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" 9003 VADDR_PRIx "\n", ctx->base.pc_next); 9004 #endif 9005 gen_reserved_instruction(ctx); 9006 return; 9007 } 9008 9009 gen_load_fpr64(ctx, t0, ft); 9010 tcg_gen_andi_i64(t0, t0, 1); 9011 9012 btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 9013 9014 switch (op) { 9015 case OPC_BC1EQZ: 9016 tcg_gen_xori_i64(t0, t0, 1); 9017 ctx->hflags |= MIPS_HFLAG_BC; 9018 break; 9019 case OPC_BC1NEZ: 9020 /* t0 already set */ 9021 ctx->hflags |= MIPS_HFLAG_BC; 9022 break; 9023 default: 9024 MIPS_INVAL("cp1 cond branch"); 9025 gen_reserved_instruction(ctx); 9026 return; 9027 } 9028 9029 tcg_gen_trunc_i64_tl(bcond, t0); 9030 9031 ctx->btarget = btarget; 9032 9033 switch (delayslot_size) { 9034 case 2: 9035 ctx->hflags |= MIPS_HFLAG_BDS16; 9036 break; 9037 case 4: 9038 ctx->hflags |= MIPS_HFLAG_BDS32; 9039 break; 9040 } 9041 } 9042 9043 /* Coprocessor 1 (FPU) */ 9044 9045 #define FOP(func, fmt) (((fmt) << 21) | (func)) 9046 9047 enum fopcode { 9048 OPC_ADD_S = FOP(0, FMT_S), 9049 OPC_SUB_S = FOP(1, FMT_S), 9050 OPC_MUL_S = FOP(2, FMT_S), 9051 OPC_DIV_S = FOP(3, FMT_S), 9052 OPC_SQRT_S = FOP(4, FMT_S), 9053 OPC_ABS_S = FOP(5, FMT_S), 9054 OPC_MOV_S = FOP(6, FMT_S), 9055 OPC_NEG_S = FOP(7, FMT_S), 9056 OPC_ROUND_L_S = FOP(8, FMT_S), 9057 OPC_TRUNC_L_S = FOP(9, FMT_S), 9058 OPC_CEIL_L_S = FOP(10, FMT_S), 9059 OPC_FLOOR_L_S = FOP(11, FMT_S), 9060 OPC_ROUND_W_S = FOP(12, FMT_S), 9061 OPC_TRUNC_W_S = FOP(13, FMT_S), 9062 OPC_CEIL_W_S = FOP(14, FMT_S), 9063 OPC_FLOOR_W_S = FOP(15, FMT_S), 9064 OPC_SEL_S = FOP(16, FMT_S), 9065 OPC_MOVCF_S = FOP(17, FMT_S), 9066 OPC_MOVZ_S = FOP(18, FMT_S), 9067 OPC_MOVN_S = FOP(19, FMT_S), 9068 OPC_SELEQZ_S = FOP(20, FMT_S), 9069 OPC_RECIP_S = FOP(21, FMT_S), 9070 OPC_RSQRT_S = FOP(22, FMT_S), 9071 OPC_SELNEZ_S = FOP(23, FMT_S), 9072 OPC_MADDF_S = FOP(24, FMT_S), 9073 OPC_MSUBF_S = FOP(25, FMT_S), 9074 OPC_RINT_S = FOP(26, FMT_S), 9075 OPC_CLASS_S = FOP(27, FMT_S), 9076 OPC_MIN_S = FOP(28, FMT_S), 9077 OPC_RECIP2_S = FOP(28, FMT_S), 9078 OPC_MINA_S = FOP(29, FMT_S), 9079 OPC_RECIP1_S = FOP(29, FMT_S), 9080 OPC_MAX_S = FOP(30, FMT_S), 9081 OPC_RSQRT1_S = FOP(30, FMT_S), 9082 OPC_MAXA_S = FOP(31, FMT_S), 9083 OPC_RSQRT2_S = FOP(31, FMT_S), 9084 OPC_CVT_D_S = FOP(33, FMT_S), 9085 OPC_CVT_W_S = FOP(36, FMT_S), 9086 OPC_CVT_L_S = FOP(37, FMT_S), 9087 OPC_CVT_PS_S = FOP(38, FMT_S), 9088 OPC_CMP_F_S = FOP(48, FMT_S), 9089 OPC_CMP_UN_S = FOP(49, FMT_S), 9090 OPC_CMP_EQ_S = FOP(50, FMT_S), 9091 OPC_CMP_UEQ_S = FOP(51, FMT_S), 9092 OPC_CMP_OLT_S = FOP(52, FMT_S), 9093 OPC_CMP_ULT_S = FOP(53, FMT_S), 9094 OPC_CMP_OLE_S = FOP(54, FMT_S), 9095 OPC_CMP_ULE_S = FOP(55, FMT_S), 9096 OPC_CMP_SF_S = FOP(56, FMT_S), 9097 OPC_CMP_NGLE_S = FOP(57, FMT_S), 9098 OPC_CMP_SEQ_S = FOP(58, FMT_S), 9099 OPC_CMP_NGL_S = FOP(59, FMT_S), 9100 OPC_CMP_LT_S = FOP(60, FMT_S), 9101 OPC_CMP_NGE_S = FOP(61, FMT_S), 9102 OPC_CMP_LE_S = FOP(62, FMT_S), 9103 OPC_CMP_NGT_S = FOP(63, FMT_S), 9104 9105 OPC_ADD_D = FOP(0, FMT_D), 9106 OPC_SUB_D = FOP(1, FMT_D), 9107 OPC_MUL_D = FOP(2, FMT_D), 9108 OPC_DIV_D = FOP(3, FMT_D), 9109 OPC_SQRT_D = FOP(4, FMT_D), 9110 OPC_ABS_D = FOP(5, FMT_D), 9111 OPC_MOV_D = FOP(6, FMT_D), 9112 OPC_NEG_D = FOP(7, FMT_D), 9113 OPC_ROUND_L_D = FOP(8, FMT_D), 9114 OPC_TRUNC_L_D = FOP(9, FMT_D), 9115 OPC_CEIL_L_D = FOP(10, FMT_D), 9116 OPC_FLOOR_L_D = FOP(11, FMT_D), 9117 OPC_ROUND_W_D = FOP(12, FMT_D), 9118 OPC_TRUNC_W_D = FOP(13, FMT_D), 9119 OPC_CEIL_W_D = FOP(14, FMT_D), 9120 OPC_FLOOR_W_D = FOP(15, FMT_D), 9121 OPC_SEL_D = FOP(16, FMT_D), 9122 OPC_MOVCF_D = FOP(17, FMT_D), 9123 OPC_MOVZ_D = FOP(18, FMT_D), 9124 OPC_MOVN_D = FOP(19, FMT_D), 9125 OPC_SELEQZ_D = FOP(20, FMT_D), 9126 OPC_RECIP_D = FOP(21, FMT_D), 9127 OPC_RSQRT_D = FOP(22, FMT_D), 9128 OPC_SELNEZ_D = FOP(23, FMT_D), 9129 OPC_MADDF_D = FOP(24, FMT_D), 9130 OPC_MSUBF_D = FOP(25, FMT_D), 9131 OPC_RINT_D = FOP(26, FMT_D), 9132 OPC_CLASS_D = FOP(27, FMT_D), 9133 OPC_MIN_D = FOP(28, FMT_D), 9134 OPC_RECIP2_D = FOP(28, FMT_D), 9135 OPC_MINA_D = FOP(29, FMT_D), 9136 OPC_RECIP1_D = FOP(29, FMT_D), 9137 OPC_MAX_D = FOP(30, FMT_D), 9138 OPC_RSQRT1_D = FOP(30, FMT_D), 9139 OPC_MAXA_D = FOP(31, FMT_D), 9140 OPC_RSQRT2_D = FOP(31, FMT_D), 9141 OPC_CVT_S_D = FOP(32, FMT_D), 9142 OPC_CVT_W_D = FOP(36, FMT_D), 9143 OPC_CVT_L_D = FOP(37, FMT_D), 9144 OPC_CMP_F_D = FOP(48, FMT_D), 9145 OPC_CMP_UN_D = FOP(49, FMT_D), 9146 OPC_CMP_EQ_D = FOP(50, FMT_D), 9147 OPC_CMP_UEQ_D = FOP(51, FMT_D), 9148 OPC_CMP_OLT_D = FOP(52, FMT_D), 9149 OPC_CMP_ULT_D = FOP(53, FMT_D), 9150 OPC_CMP_OLE_D = FOP(54, FMT_D), 9151 OPC_CMP_ULE_D = FOP(55, FMT_D), 9152 OPC_CMP_SF_D = FOP(56, FMT_D), 9153 OPC_CMP_NGLE_D = FOP(57, FMT_D), 9154 OPC_CMP_SEQ_D = FOP(58, FMT_D), 9155 OPC_CMP_NGL_D = FOP(59, FMT_D), 9156 OPC_CMP_LT_D = FOP(60, FMT_D), 9157 OPC_CMP_NGE_D = FOP(61, FMT_D), 9158 OPC_CMP_LE_D = FOP(62, FMT_D), 9159 OPC_CMP_NGT_D = FOP(63, FMT_D), 9160 9161 OPC_CVT_S_W = FOP(32, FMT_W), 9162 OPC_CVT_D_W = FOP(33, FMT_W), 9163 OPC_CVT_S_L = FOP(32, FMT_L), 9164 OPC_CVT_D_L = FOP(33, FMT_L), 9165 OPC_CVT_PS_PW = FOP(38, FMT_W), 9166 9167 OPC_ADD_PS = FOP(0, FMT_PS), 9168 OPC_SUB_PS = FOP(1, FMT_PS), 9169 OPC_MUL_PS = FOP(2, FMT_PS), 9170 OPC_DIV_PS = FOP(3, FMT_PS), 9171 OPC_ABS_PS = FOP(5, FMT_PS), 9172 OPC_MOV_PS = FOP(6, FMT_PS), 9173 OPC_NEG_PS = FOP(7, FMT_PS), 9174 OPC_MOVCF_PS = FOP(17, FMT_PS), 9175 OPC_MOVZ_PS = FOP(18, FMT_PS), 9176 OPC_MOVN_PS = FOP(19, FMT_PS), 9177 OPC_ADDR_PS = FOP(24, FMT_PS), 9178 OPC_MULR_PS = FOP(26, FMT_PS), 9179 OPC_RECIP2_PS = FOP(28, FMT_PS), 9180 OPC_RECIP1_PS = FOP(29, FMT_PS), 9181 OPC_RSQRT1_PS = FOP(30, FMT_PS), 9182 OPC_RSQRT2_PS = FOP(31, FMT_PS), 9183 9184 OPC_CVT_S_PU = FOP(32, FMT_PS), 9185 OPC_CVT_PW_PS = FOP(36, FMT_PS), 9186 OPC_CVT_S_PL = FOP(40, FMT_PS), 9187 OPC_PLL_PS = FOP(44, FMT_PS), 9188 OPC_PLU_PS = FOP(45, FMT_PS), 9189 OPC_PUL_PS = FOP(46, FMT_PS), 9190 OPC_PUU_PS = FOP(47, FMT_PS), 9191 OPC_CMP_F_PS = FOP(48, FMT_PS), 9192 OPC_CMP_UN_PS = FOP(49, FMT_PS), 9193 OPC_CMP_EQ_PS = FOP(50, FMT_PS), 9194 OPC_CMP_UEQ_PS = FOP(51, FMT_PS), 9195 OPC_CMP_OLT_PS = FOP(52, FMT_PS), 9196 OPC_CMP_ULT_PS = FOP(53, FMT_PS), 9197 OPC_CMP_OLE_PS = FOP(54, FMT_PS), 9198 OPC_CMP_ULE_PS = FOP(55, FMT_PS), 9199 OPC_CMP_SF_PS = FOP(56, FMT_PS), 9200 OPC_CMP_NGLE_PS = FOP(57, FMT_PS), 9201 OPC_CMP_SEQ_PS = FOP(58, FMT_PS), 9202 OPC_CMP_NGL_PS = FOP(59, FMT_PS), 9203 OPC_CMP_LT_PS = FOP(60, FMT_PS), 9204 OPC_CMP_NGE_PS = FOP(61, FMT_PS), 9205 OPC_CMP_LE_PS = FOP(62, FMT_PS), 9206 OPC_CMP_NGT_PS = FOP(63, FMT_PS), 9207 }; 9208 9209 enum r6_f_cmp_op { 9210 R6_OPC_CMP_AF_S = FOP(0, FMT_W), 9211 R6_OPC_CMP_UN_S = FOP(1, FMT_W), 9212 R6_OPC_CMP_EQ_S = FOP(2, FMT_W), 9213 R6_OPC_CMP_UEQ_S = FOP(3, FMT_W), 9214 R6_OPC_CMP_LT_S = FOP(4, FMT_W), 9215 R6_OPC_CMP_ULT_S = FOP(5, FMT_W), 9216 R6_OPC_CMP_LE_S = FOP(6, FMT_W), 9217 R6_OPC_CMP_ULE_S = FOP(7, FMT_W), 9218 R6_OPC_CMP_SAF_S = FOP(8, FMT_W), 9219 R6_OPC_CMP_SUN_S = FOP(9, FMT_W), 9220 R6_OPC_CMP_SEQ_S = FOP(10, FMT_W), 9221 R6_OPC_CMP_SEUQ_S = FOP(11, FMT_W), 9222 R6_OPC_CMP_SLT_S = FOP(12, FMT_W), 9223 R6_OPC_CMP_SULT_S = FOP(13, FMT_W), 9224 R6_OPC_CMP_SLE_S = FOP(14, FMT_W), 9225 R6_OPC_CMP_SULE_S = FOP(15, FMT_W), 9226 R6_OPC_CMP_OR_S = FOP(17, FMT_W), 9227 R6_OPC_CMP_UNE_S = FOP(18, FMT_W), 9228 R6_OPC_CMP_NE_S = FOP(19, FMT_W), 9229 R6_OPC_CMP_SOR_S = FOP(25, FMT_W), 9230 R6_OPC_CMP_SUNE_S = FOP(26, FMT_W), 9231 R6_OPC_CMP_SNE_S = FOP(27, FMT_W), 9232 9233 R6_OPC_CMP_AF_D = FOP(0, FMT_L), 9234 R6_OPC_CMP_UN_D = FOP(1, FMT_L), 9235 R6_OPC_CMP_EQ_D = FOP(2, FMT_L), 9236 R6_OPC_CMP_UEQ_D = FOP(3, FMT_L), 9237 R6_OPC_CMP_LT_D = FOP(4, FMT_L), 9238 R6_OPC_CMP_ULT_D = FOP(5, FMT_L), 9239 R6_OPC_CMP_LE_D = FOP(6, FMT_L), 9240 R6_OPC_CMP_ULE_D = FOP(7, FMT_L), 9241 R6_OPC_CMP_SAF_D = FOP(8, FMT_L), 9242 R6_OPC_CMP_SUN_D = FOP(9, FMT_L), 9243 R6_OPC_CMP_SEQ_D = FOP(10, FMT_L), 9244 R6_OPC_CMP_SEUQ_D = FOP(11, FMT_L), 9245 R6_OPC_CMP_SLT_D = FOP(12, FMT_L), 9246 R6_OPC_CMP_SULT_D = FOP(13, FMT_L), 9247 R6_OPC_CMP_SLE_D = FOP(14, FMT_L), 9248 R6_OPC_CMP_SULE_D = FOP(15, FMT_L), 9249 R6_OPC_CMP_OR_D = FOP(17, FMT_L), 9250 R6_OPC_CMP_UNE_D = FOP(18, FMT_L), 9251 R6_OPC_CMP_NE_D = FOP(19, FMT_L), 9252 R6_OPC_CMP_SOR_D = FOP(25, FMT_L), 9253 R6_OPC_CMP_SUNE_D = FOP(26, FMT_L), 9254 R6_OPC_CMP_SNE_D = FOP(27, FMT_L), 9255 }; 9256 9257 static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs) 9258 { 9259 TCGv t0 = tcg_temp_new(); 9260 9261 switch (opc) { 9262 case OPC_MFC1: 9263 { 9264 TCGv_i32 fp0 = tcg_temp_new_i32(); 9265 9266 gen_load_fpr32(ctx, fp0, fs); 9267 tcg_gen_ext_i32_tl(t0, fp0); 9268 } 9269 gen_store_gpr(t0, rt); 9270 break; 9271 case OPC_MTC1: 9272 gen_load_gpr(t0, rt); 9273 { 9274 TCGv_i32 fp0 = tcg_temp_new_i32(); 9275 9276 tcg_gen_trunc_tl_i32(fp0, t0); 9277 gen_store_fpr32(ctx, fp0, fs); 9278 } 9279 break; 9280 case OPC_CFC1: 9281 gen_helper_1e0i(cfc1, t0, fs); 9282 gen_store_gpr(t0, rt); 9283 break; 9284 case OPC_CTC1: 9285 gen_load_gpr(t0, rt); 9286 save_cpu_state(ctx, 0); 9287 gen_helper_0e2i(ctc1, t0, tcg_constant_i32(fs), rt); 9288 /* Stop translation as we may have changed hflags */ 9289 ctx->base.is_jmp = DISAS_STOP; 9290 break; 9291 #if defined(TARGET_MIPS64) 9292 case OPC_DMFC1: 9293 gen_load_fpr64(ctx, t0, fs); 9294 gen_store_gpr(t0, rt); 9295 break; 9296 case OPC_DMTC1: 9297 gen_load_gpr(t0, rt); 9298 gen_store_fpr64(ctx, t0, fs); 9299 break; 9300 #endif 9301 case OPC_MFHC1: 9302 { 9303 TCGv_i32 fp0 = tcg_temp_new_i32(); 9304 9305 gen_load_fpr32h(ctx, fp0, fs); 9306 tcg_gen_ext_i32_tl(t0, fp0); 9307 } 9308 gen_store_gpr(t0, rt); 9309 break; 9310 case OPC_MTHC1: 9311 gen_load_gpr(t0, rt); 9312 { 9313 TCGv_i32 fp0 = tcg_temp_new_i32(); 9314 9315 tcg_gen_trunc_tl_i32(fp0, t0); 9316 gen_store_fpr32h(ctx, fp0, fs); 9317 } 9318 break; 9319 default: 9320 MIPS_INVAL("cp1 move"); 9321 gen_reserved_instruction(ctx); 9322 return; 9323 } 9324 } 9325 9326 static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf) 9327 { 9328 TCGLabel *l1; 9329 TCGCond cond; 9330 TCGv_i32 t0; 9331 9332 if (rd == 0) { 9333 /* Treat as NOP. */ 9334 return; 9335 } 9336 9337 if (tf) { 9338 cond = TCG_COND_EQ; 9339 } else { 9340 cond = TCG_COND_NE; 9341 } 9342 9343 l1 = gen_new_label(); 9344 t0 = tcg_temp_new_i32(); 9345 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9346 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9347 gen_load_gpr(cpu_gpr[rd], rs); 9348 gen_set_label(l1); 9349 } 9350 9351 static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc, 9352 int tf) 9353 { 9354 int cond; 9355 TCGv_i32 t0 = tcg_temp_new_i32(); 9356 TCGLabel *l1 = gen_new_label(); 9357 9358 if (tf) { 9359 cond = TCG_COND_EQ; 9360 } else { 9361 cond = TCG_COND_NE; 9362 } 9363 9364 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9365 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9366 gen_load_fpr32(ctx, t0, fs); 9367 gen_store_fpr32(ctx, t0, fd); 9368 gen_set_label(l1); 9369 } 9370 9371 static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc, 9372 int tf) 9373 { 9374 int cond; 9375 TCGv_i32 t0 = tcg_temp_new_i32(); 9376 TCGv_i64 fp0; 9377 TCGLabel *l1 = gen_new_label(); 9378 9379 if (tf) { 9380 cond = TCG_COND_EQ; 9381 } else { 9382 cond = TCG_COND_NE; 9383 } 9384 9385 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9386 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9387 fp0 = tcg_temp_new_i64(); 9388 gen_load_fpr64(ctx, fp0, fs); 9389 gen_store_fpr64(ctx, fp0, fd); 9390 gen_set_label(l1); 9391 } 9392 9393 static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd, 9394 int cc, int tf) 9395 { 9396 int cond; 9397 TCGv_i32 t0 = tcg_temp_new_i32(); 9398 TCGLabel *l1 = gen_new_label(); 9399 TCGLabel *l2 = gen_new_label(); 9400 9401 if (tf) { 9402 cond = TCG_COND_EQ; 9403 } else { 9404 cond = TCG_COND_NE; 9405 } 9406 9407 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); 9408 tcg_gen_brcondi_i32(cond, t0, 0, l1); 9409 gen_load_fpr32(ctx, t0, fs); 9410 gen_store_fpr32(ctx, t0, fd); 9411 gen_set_label(l1); 9412 9413 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc + 1)); 9414 tcg_gen_brcondi_i32(cond, t0, 0, l2); 9415 gen_load_fpr32h(ctx, t0, fs); 9416 gen_store_fpr32h(ctx, t0, fd); 9417 gen_set_label(l2); 9418 } 9419 9420 static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft, 9421 int fs) 9422 { 9423 TCGv_i32 t1 = tcg_constant_i32(0); 9424 TCGv_i32 fp0 = tcg_temp_new_i32(); 9425 TCGv_i32 fp1 = tcg_temp_new_i32(); 9426 TCGv_i32 fp2 = tcg_temp_new_i32(); 9427 gen_load_fpr32(ctx, fp0, fd); 9428 gen_load_fpr32(ctx, fp1, ft); 9429 gen_load_fpr32(ctx, fp2, fs); 9430 9431 switch (op1) { 9432 case OPC_SEL_S: 9433 tcg_gen_andi_i32(fp0, fp0, 1); 9434 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp0, t1, fp1, fp2); 9435 break; 9436 case OPC_SELEQZ_S: 9437 tcg_gen_andi_i32(fp1, fp1, 1); 9438 tcg_gen_movcond_i32(TCG_COND_EQ, fp0, fp1, t1, fp2, t1); 9439 break; 9440 case OPC_SELNEZ_S: 9441 tcg_gen_andi_i32(fp1, fp1, 1); 9442 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp1, t1, fp2, t1); 9443 break; 9444 default: 9445 MIPS_INVAL("gen_sel_s"); 9446 gen_reserved_instruction(ctx); 9447 break; 9448 } 9449 9450 gen_store_fpr32(ctx, fp0, fd); 9451 } 9452 9453 static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft, 9454 int fs) 9455 { 9456 TCGv_i64 t1 = tcg_constant_i64(0); 9457 TCGv_i64 fp0 = tcg_temp_new_i64(); 9458 TCGv_i64 fp1 = tcg_temp_new_i64(); 9459 TCGv_i64 fp2 = tcg_temp_new_i64(); 9460 gen_load_fpr64(ctx, fp0, fd); 9461 gen_load_fpr64(ctx, fp1, ft); 9462 gen_load_fpr64(ctx, fp2, fs); 9463 9464 switch (op1) { 9465 case OPC_SEL_D: 9466 tcg_gen_andi_i64(fp0, fp0, 1); 9467 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp0, t1, fp1, fp2); 9468 break; 9469 case OPC_SELEQZ_D: 9470 tcg_gen_andi_i64(fp1, fp1, 1); 9471 tcg_gen_movcond_i64(TCG_COND_EQ, fp0, fp1, t1, fp2, t1); 9472 break; 9473 case OPC_SELNEZ_D: 9474 tcg_gen_andi_i64(fp1, fp1, 1); 9475 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp1, t1, fp2, t1); 9476 break; 9477 default: 9478 MIPS_INVAL("gen_sel_d"); 9479 gen_reserved_instruction(ctx); 9480 break; 9481 } 9482 9483 gen_store_fpr64(ctx, fp0, fd); 9484 } 9485 9486 static void gen_farith(DisasContext *ctx, enum fopcode op1, 9487 int ft, int fs, int fd, int cc) 9488 { 9489 uint32_t func = ctx->opcode & 0x3f; 9490 switch (op1) { 9491 case OPC_ADD_S: 9492 { 9493 TCGv_i32 fp0 = tcg_temp_new_i32(); 9494 TCGv_i32 fp1 = tcg_temp_new_i32(); 9495 9496 gen_load_fpr32(ctx, fp0, fs); 9497 gen_load_fpr32(ctx, fp1, ft); 9498 gen_helper_float_add_s(fp0, tcg_env, fp0, fp1); 9499 gen_store_fpr32(ctx, fp0, fd); 9500 } 9501 break; 9502 case OPC_SUB_S: 9503 { 9504 TCGv_i32 fp0 = tcg_temp_new_i32(); 9505 TCGv_i32 fp1 = tcg_temp_new_i32(); 9506 9507 gen_load_fpr32(ctx, fp0, fs); 9508 gen_load_fpr32(ctx, fp1, ft); 9509 gen_helper_float_sub_s(fp0, tcg_env, fp0, fp1); 9510 gen_store_fpr32(ctx, fp0, fd); 9511 } 9512 break; 9513 case OPC_MUL_S: 9514 { 9515 TCGv_i32 fp0 = tcg_temp_new_i32(); 9516 TCGv_i32 fp1 = tcg_temp_new_i32(); 9517 9518 gen_load_fpr32(ctx, fp0, fs); 9519 gen_load_fpr32(ctx, fp1, ft); 9520 gen_helper_float_mul_s(fp0, tcg_env, fp0, fp1); 9521 gen_store_fpr32(ctx, fp0, fd); 9522 } 9523 break; 9524 case OPC_DIV_S: 9525 { 9526 TCGv_i32 fp0 = tcg_temp_new_i32(); 9527 TCGv_i32 fp1 = tcg_temp_new_i32(); 9528 9529 gen_load_fpr32(ctx, fp0, fs); 9530 gen_load_fpr32(ctx, fp1, ft); 9531 gen_helper_float_div_s(fp0, tcg_env, fp0, fp1); 9532 gen_store_fpr32(ctx, fp0, fd); 9533 } 9534 break; 9535 case OPC_SQRT_S: 9536 { 9537 TCGv_i32 fp0 = tcg_temp_new_i32(); 9538 9539 gen_load_fpr32(ctx, fp0, fs); 9540 gen_helper_float_sqrt_s(fp0, tcg_env, fp0); 9541 gen_store_fpr32(ctx, fp0, fd); 9542 } 9543 break; 9544 case OPC_ABS_S: 9545 { 9546 TCGv_i32 fp0 = tcg_temp_new_i32(); 9547 9548 gen_load_fpr32(ctx, fp0, fs); 9549 if (ctx->abs2008) { 9550 tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL); 9551 } else { 9552 gen_helper_float_abs_s(fp0, fp0); 9553 } 9554 gen_store_fpr32(ctx, fp0, fd); 9555 } 9556 break; 9557 case OPC_MOV_S: 9558 { 9559 TCGv_i32 fp0 = tcg_temp_new_i32(); 9560 9561 gen_load_fpr32(ctx, fp0, fs); 9562 gen_store_fpr32(ctx, fp0, fd); 9563 } 9564 break; 9565 case OPC_NEG_S: 9566 { 9567 TCGv_i32 fp0 = tcg_temp_new_i32(); 9568 9569 gen_load_fpr32(ctx, fp0, fs); 9570 if (ctx->abs2008) { 9571 tcg_gen_xori_i32(fp0, fp0, 1UL << 31); 9572 } else { 9573 gen_helper_float_chs_s(fp0, fp0); 9574 } 9575 gen_store_fpr32(ctx, fp0, fd); 9576 } 9577 break; 9578 case OPC_ROUND_L_S: 9579 check_cp1_64bitmode(ctx); 9580 { 9581 TCGv_i32 fp32 = tcg_temp_new_i32(); 9582 TCGv_i64 fp64 = tcg_temp_new_i64(); 9583 9584 gen_load_fpr32(ctx, fp32, fs); 9585 if (ctx->nan2008) { 9586 gen_helper_float_round_2008_l_s(fp64, tcg_env, fp32); 9587 } else { 9588 gen_helper_float_round_l_s(fp64, tcg_env, fp32); 9589 } 9590 gen_store_fpr64(ctx, fp64, fd); 9591 } 9592 break; 9593 case OPC_TRUNC_L_S: 9594 check_cp1_64bitmode(ctx); 9595 { 9596 TCGv_i32 fp32 = tcg_temp_new_i32(); 9597 TCGv_i64 fp64 = tcg_temp_new_i64(); 9598 9599 gen_load_fpr32(ctx, fp32, fs); 9600 if (ctx->nan2008) { 9601 gen_helper_float_trunc_2008_l_s(fp64, tcg_env, fp32); 9602 } else { 9603 gen_helper_float_trunc_l_s(fp64, tcg_env, fp32); 9604 } 9605 gen_store_fpr64(ctx, fp64, fd); 9606 } 9607 break; 9608 case OPC_CEIL_L_S: 9609 check_cp1_64bitmode(ctx); 9610 { 9611 TCGv_i32 fp32 = tcg_temp_new_i32(); 9612 TCGv_i64 fp64 = tcg_temp_new_i64(); 9613 9614 gen_load_fpr32(ctx, fp32, fs); 9615 if (ctx->nan2008) { 9616 gen_helper_float_ceil_2008_l_s(fp64, tcg_env, fp32); 9617 } else { 9618 gen_helper_float_ceil_l_s(fp64, tcg_env, fp32); 9619 } 9620 gen_store_fpr64(ctx, fp64, fd); 9621 } 9622 break; 9623 case OPC_FLOOR_L_S: 9624 check_cp1_64bitmode(ctx); 9625 { 9626 TCGv_i32 fp32 = tcg_temp_new_i32(); 9627 TCGv_i64 fp64 = tcg_temp_new_i64(); 9628 9629 gen_load_fpr32(ctx, fp32, fs); 9630 if (ctx->nan2008) { 9631 gen_helper_float_floor_2008_l_s(fp64, tcg_env, fp32); 9632 } else { 9633 gen_helper_float_floor_l_s(fp64, tcg_env, fp32); 9634 } 9635 gen_store_fpr64(ctx, fp64, fd); 9636 } 9637 break; 9638 case OPC_ROUND_W_S: 9639 { 9640 TCGv_i32 fp0 = tcg_temp_new_i32(); 9641 9642 gen_load_fpr32(ctx, fp0, fs); 9643 if (ctx->nan2008) { 9644 gen_helper_float_round_2008_w_s(fp0, tcg_env, fp0); 9645 } else { 9646 gen_helper_float_round_w_s(fp0, tcg_env, fp0); 9647 } 9648 gen_store_fpr32(ctx, fp0, fd); 9649 } 9650 break; 9651 case OPC_TRUNC_W_S: 9652 { 9653 TCGv_i32 fp0 = tcg_temp_new_i32(); 9654 9655 gen_load_fpr32(ctx, fp0, fs); 9656 if (ctx->nan2008) { 9657 gen_helper_float_trunc_2008_w_s(fp0, tcg_env, fp0); 9658 } else { 9659 gen_helper_float_trunc_w_s(fp0, tcg_env, fp0); 9660 } 9661 gen_store_fpr32(ctx, fp0, fd); 9662 } 9663 break; 9664 case OPC_CEIL_W_S: 9665 { 9666 TCGv_i32 fp0 = tcg_temp_new_i32(); 9667 9668 gen_load_fpr32(ctx, fp0, fs); 9669 if (ctx->nan2008) { 9670 gen_helper_float_ceil_2008_w_s(fp0, tcg_env, fp0); 9671 } else { 9672 gen_helper_float_ceil_w_s(fp0, tcg_env, fp0); 9673 } 9674 gen_store_fpr32(ctx, fp0, fd); 9675 } 9676 break; 9677 case OPC_FLOOR_W_S: 9678 { 9679 TCGv_i32 fp0 = tcg_temp_new_i32(); 9680 9681 gen_load_fpr32(ctx, fp0, fs); 9682 if (ctx->nan2008) { 9683 gen_helper_float_floor_2008_w_s(fp0, tcg_env, fp0); 9684 } else { 9685 gen_helper_float_floor_w_s(fp0, tcg_env, fp0); 9686 } 9687 gen_store_fpr32(ctx, fp0, fd); 9688 } 9689 break; 9690 case OPC_SEL_S: 9691 check_insn(ctx, ISA_MIPS_R6); 9692 gen_sel_s(ctx, op1, fd, ft, fs); 9693 break; 9694 case OPC_SELEQZ_S: 9695 check_insn(ctx, ISA_MIPS_R6); 9696 gen_sel_s(ctx, op1, fd, ft, fs); 9697 break; 9698 case OPC_SELNEZ_S: 9699 check_insn(ctx, ISA_MIPS_R6); 9700 gen_sel_s(ctx, op1, fd, ft, fs); 9701 break; 9702 case OPC_MOVCF_S: 9703 check_insn_opc_removed(ctx, ISA_MIPS_R6); 9704 gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); 9705 break; 9706 case OPC_MOVZ_S: 9707 check_insn_opc_removed(ctx, ISA_MIPS_R6); 9708 { 9709 TCGLabel *l1 = gen_new_label(); 9710 TCGv_i32 fp0; 9711 9712 if (ft != 0) { 9713 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); 9714 } 9715 fp0 = tcg_temp_new_i32(); 9716 gen_load_fpr32(ctx, fp0, fs); 9717 gen_store_fpr32(ctx, fp0, fd); 9718 gen_set_label(l1); 9719 } 9720 break; 9721 case OPC_MOVN_S: 9722 check_insn_opc_removed(ctx, ISA_MIPS_R6); 9723 { 9724 TCGLabel *l1 = gen_new_label(); 9725 TCGv_i32 fp0; 9726 9727 if (ft != 0) { 9728 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); 9729 fp0 = tcg_temp_new_i32(); 9730 gen_load_fpr32(ctx, fp0, fs); 9731 gen_store_fpr32(ctx, fp0, fd); 9732 gen_set_label(l1); 9733 } 9734 } 9735 break; 9736 case OPC_RECIP_S: 9737 { 9738 TCGv_i32 fp0 = tcg_temp_new_i32(); 9739 9740 gen_load_fpr32(ctx, fp0, fs); 9741 gen_helper_float_recip_s(fp0, tcg_env, fp0); 9742 gen_store_fpr32(ctx, fp0, fd); 9743 } 9744 break; 9745 case OPC_RSQRT_S: 9746 { 9747 TCGv_i32 fp0 = tcg_temp_new_i32(); 9748 9749 gen_load_fpr32(ctx, fp0, fs); 9750 gen_helper_float_rsqrt_s(fp0, tcg_env, fp0); 9751 gen_store_fpr32(ctx, fp0, fd); 9752 } 9753 break; 9754 case OPC_MADDF_S: 9755 check_insn(ctx, ISA_MIPS_R6); 9756 { 9757 TCGv_i32 fp0 = tcg_temp_new_i32(); 9758 TCGv_i32 fp1 = tcg_temp_new_i32(); 9759 TCGv_i32 fp2 = tcg_temp_new_i32(); 9760 gen_load_fpr32(ctx, fp0, fs); 9761 gen_load_fpr32(ctx, fp1, ft); 9762 gen_load_fpr32(ctx, fp2, fd); 9763 gen_helper_float_maddf_s(fp2, tcg_env, fp0, fp1, fp2); 9764 gen_store_fpr32(ctx, fp2, fd); 9765 } 9766 break; 9767 case OPC_MSUBF_S: 9768 check_insn(ctx, ISA_MIPS_R6); 9769 { 9770 TCGv_i32 fp0 = tcg_temp_new_i32(); 9771 TCGv_i32 fp1 = tcg_temp_new_i32(); 9772 TCGv_i32 fp2 = tcg_temp_new_i32(); 9773 gen_load_fpr32(ctx, fp0, fs); 9774 gen_load_fpr32(ctx, fp1, ft); 9775 gen_load_fpr32(ctx, fp2, fd); 9776 gen_helper_float_msubf_s(fp2, tcg_env, fp0, fp1, fp2); 9777 gen_store_fpr32(ctx, fp2, fd); 9778 } 9779 break; 9780 case OPC_RINT_S: 9781 check_insn(ctx, ISA_MIPS_R6); 9782 { 9783 TCGv_i32 fp0 = tcg_temp_new_i32(); 9784 gen_load_fpr32(ctx, fp0, fs); 9785 gen_helper_float_rint_s(fp0, tcg_env, fp0); 9786 gen_store_fpr32(ctx, fp0, fd); 9787 } 9788 break; 9789 case OPC_CLASS_S: 9790 check_insn(ctx, ISA_MIPS_R6); 9791 { 9792 TCGv_i32 fp0 = tcg_temp_new_i32(); 9793 gen_load_fpr32(ctx, fp0, fs); 9794 gen_helper_float_class_s(fp0, tcg_env, fp0); 9795 gen_store_fpr32(ctx, fp0, fd); 9796 } 9797 break; 9798 case OPC_MIN_S: /* OPC_RECIP2_S */ 9799 if (ctx->insn_flags & ISA_MIPS_R6) { 9800 /* OPC_MIN_S */ 9801 TCGv_i32 fp0 = tcg_temp_new_i32(); 9802 TCGv_i32 fp1 = tcg_temp_new_i32(); 9803 TCGv_i32 fp2 = tcg_temp_new_i32(); 9804 gen_load_fpr32(ctx, fp0, fs); 9805 gen_load_fpr32(ctx, fp1, ft); 9806 gen_helper_float_min_s(fp2, tcg_env, fp0, fp1); 9807 gen_store_fpr32(ctx, fp2, fd); 9808 } else { 9809 /* OPC_RECIP2_S */ 9810 check_cp1_64bitmode(ctx); 9811 { 9812 TCGv_i32 fp0 = tcg_temp_new_i32(); 9813 TCGv_i32 fp1 = tcg_temp_new_i32(); 9814 9815 gen_load_fpr32(ctx, fp0, fs); 9816 gen_load_fpr32(ctx, fp1, ft); 9817 gen_helper_float_recip2_s(fp0, tcg_env, fp0, fp1); 9818 gen_store_fpr32(ctx, fp0, fd); 9819 } 9820 } 9821 break; 9822 case OPC_MINA_S: /* OPC_RECIP1_S */ 9823 if (ctx->insn_flags & ISA_MIPS_R6) { 9824 /* OPC_MINA_S */ 9825 TCGv_i32 fp0 = tcg_temp_new_i32(); 9826 TCGv_i32 fp1 = tcg_temp_new_i32(); 9827 TCGv_i32 fp2 = tcg_temp_new_i32(); 9828 gen_load_fpr32(ctx, fp0, fs); 9829 gen_load_fpr32(ctx, fp1, ft); 9830 gen_helper_float_mina_s(fp2, tcg_env, fp0, fp1); 9831 gen_store_fpr32(ctx, fp2, fd); 9832 } else { 9833 /* OPC_RECIP1_S */ 9834 check_cp1_64bitmode(ctx); 9835 { 9836 TCGv_i32 fp0 = tcg_temp_new_i32(); 9837 9838 gen_load_fpr32(ctx, fp0, fs); 9839 gen_helper_float_recip1_s(fp0, tcg_env, fp0); 9840 gen_store_fpr32(ctx, fp0, fd); 9841 } 9842 } 9843 break; 9844 case OPC_MAX_S: /* OPC_RSQRT1_S */ 9845 if (ctx->insn_flags & ISA_MIPS_R6) { 9846 /* OPC_MAX_S */ 9847 TCGv_i32 fp0 = tcg_temp_new_i32(); 9848 TCGv_i32 fp1 = tcg_temp_new_i32(); 9849 gen_load_fpr32(ctx, fp0, fs); 9850 gen_load_fpr32(ctx, fp1, ft); 9851 gen_helper_float_max_s(fp1, tcg_env, fp0, fp1); 9852 gen_store_fpr32(ctx, fp1, fd); 9853 } else { 9854 /* OPC_RSQRT1_S */ 9855 check_cp1_64bitmode(ctx); 9856 { 9857 TCGv_i32 fp0 = tcg_temp_new_i32(); 9858 9859 gen_load_fpr32(ctx, fp0, fs); 9860 gen_helper_float_rsqrt1_s(fp0, tcg_env, fp0); 9861 gen_store_fpr32(ctx, fp0, fd); 9862 } 9863 } 9864 break; 9865 case OPC_MAXA_S: /* OPC_RSQRT2_S */ 9866 if (ctx->insn_flags & ISA_MIPS_R6) { 9867 /* OPC_MAXA_S */ 9868 TCGv_i32 fp0 = tcg_temp_new_i32(); 9869 TCGv_i32 fp1 = tcg_temp_new_i32(); 9870 gen_load_fpr32(ctx, fp0, fs); 9871 gen_load_fpr32(ctx, fp1, ft); 9872 gen_helper_float_maxa_s(fp1, tcg_env, fp0, fp1); 9873 gen_store_fpr32(ctx, fp1, fd); 9874 } else { 9875 /* OPC_RSQRT2_S */ 9876 check_cp1_64bitmode(ctx); 9877 { 9878 TCGv_i32 fp0 = tcg_temp_new_i32(); 9879 TCGv_i32 fp1 = tcg_temp_new_i32(); 9880 9881 gen_load_fpr32(ctx, fp0, fs); 9882 gen_load_fpr32(ctx, fp1, ft); 9883 gen_helper_float_rsqrt2_s(fp0, tcg_env, fp0, fp1); 9884 gen_store_fpr32(ctx, fp0, fd); 9885 } 9886 } 9887 break; 9888 case OPC_CVT_D_S: 9889 check_cp1_registers(ctx, fd); 9890 { 9891 TCGv_i32 fp32 = tcg_temp_new_i32(); 9892 TCGv_i64 fp64 = tcg_temp_new_i64(); 9893 9894 gen_load_fpr32(ctx, fp32, fs); 9895 gen_helper_float_cvtd_s(fp64, tcg_env, fp32); 9896 gen_store_fpr64(ctx, fp64, fd); 9897 } 9898 break; 9899 case OPC_CVT_W_S: 9900 { 9901 TCGv_i32 fp0 = tcg_temp_new_i32(); 9902 9903 gen_load_fpr32(ctx, fp0, fs); 9904 if (ctx->nan2008) { 9905 gen_helper_float_cvt_2008_w_s(fp0, tcg_env, fp0); 9906 } else { 9907 gen_helper_float_cvt_w_s(fp0, tcg_env, fp0); 9908 } 9909 gen_store_fpr32(ctx, fp0, fd); 9910 } 9911 break; 9912 case OPC_CVT_L_S: 9913 check_cp1_64bitmode(ctx); 9914 { 9915 TCGv_i32 fp32 = tcg_temp_new_i32(); 9916 TCGv_i64 fp64 = tcg_temp_new_i64(); 9917 9918 gen_load_fpr32(ctx, fp32, fs); 9919 if (ctx->nan2008) { 9920 gen_helper_float_cvt_2008_l_s(fp64, tcg_env, fp32); 9921 } else { 9922 gen_helper_float_cvt_l_s(fp64, tcg_env, fp32); 9923 } 9924 gen_store_fpr64(ctx, fp64, fd); 9925 } 9926 break; 9927 case OPC_CVT_PS_S: 9928 check_ps(ctx); 9929 { 9930 TCGv_i64 fp64 = tcg_temp_new_i64(); 9931 TCGv_i32 fp32_0 = tcg_temp_new_i32(); 9932 TCGv_i32 fp32_1 = tcg_temp_new_i32(); 9933 9934 gen_load_fpr32(ctx, fp32_0, fs); 9935 gen_load_fpr32(ctx, fp32_1, ft); 9936 tcg_gen_concat_i32_i64(fp64, fp32_1, fp32_0); 9937 gen_store_fpr64(ctx, fp64, fd); 9938 } 9939 break; 9940 case OPC_CMP_F_S: 9941 case OPC_CMP_UN_S: 9942 case OPC_CMP_EQ_S: 9943 case OPC_CMP_UEQ_S: 9944 case OPC_CMP_OLT_S: 9945 case OPC_CMP_ULT_S: 9946 case OPC_CMP_OLE_S: 9947 case OPC_CMP_ULE_S: 9948 case OPC_CMP_SF_S: 9949 case OPC_CMP_NGLE_S: 9950 case OPC_CMP_SEQ_S: 9951 case OPC_CMP_NGL_S: 9952 case OPC_CMP_LT_S: 9953 case OPC_CMP_NGE_S: 9954 case OPC_CMP_LE_S: 9955 case OPC_CMP_NGT_S: 9956 check_insn_opc_removed(ctx, ISA_MIPS_R6); 9957 if (ctx->opcode & (1 << 6)) { 9958 gen_cmpabs_s(ctx, func - 48, ft, fs, cc); 9959 } else { 9960 gen_cmp_s(ctx, func - 48, ft, fs, cc); 9961 } 9962 break; 9963 case OPC_ADD_D: 9964 check_cp1_registers(ctx, fs | ft | fd); 9965 { 9966 TCGv_i64 fp0 = tcg_temp_new_i64(); 9967 TCGv_i64 fp1 = tcg_temp_new_i64(); 9968 9969 gen_load_fpr64(ctx, fp0, fs); 9970 gen_load_fpr64(ctx, fp1, ft); 9971 gen_helper_float_add_d(fp0, tcg_env, fp0, fp1); 9972 gen_store_fpr64(ctx, fp0, fd); 9973 } 9974 break; 9975 case OPC_SUB_D: 9976 check_cp1_registers(ctx, fs | ft | fd); 9977 { 9978 TCGv_i64 fp0 = tcg_temp_new_i64(); 9979 TCGv_i64 fp1 = tcg_temp_new_i64(); 9980 9981 gen_load_fpr64(ctx, fp0, fs); 9982 gen_load_fpr64(ctx, fp1, ft); 9983 gen_helper_float_sub_d(fp0, tcg_env, fp0, fp1); 9984 gen_store_fpr64(ctx, fp0, fd); 9985 } 9986 break; 9987 case OPC_MUL_D: 9988 check_cp1_registers(ctx, fs | ft | fd); 9989 { 9990 TCGv_i64 fp0 = tcg_temp_new_i64(); 9991 TCGv_i64 fp1 = tcg_temp_new_i64(); 9992 9993 gen_load_fpr64(ctx, fp0, fs); 9994 gen_load_fpr64(ctx, fp1, ft); 9995 gen_helper_float_mul_d(fp0, tcg_env, fp0, fp1); 9996 gen_store_fpr64(ctx, fp0, fd); 9997 } 9998 break; 9999 case OPC_DIV_D: 10000 check_cp1_registers(ctx, fs | ft | fd); 10001 { 10002 TCGv_i64 fp0 = tcg_temp_new_i64(); 10003 TCGv_i64 fp1 = tcg_temp_new_i64(); 10004 10005 gen_load_fpr64(ctx, fp0, fs); 10006 gen_load_fpr64(ctx, fp1, ft); 10007 gen_helper_float_div_d(fp0, tcg_env, fp0, fp1); 10008 gen_store_fpr64(ctx, fp0, fd); 10009 } 10010 break; 10011 case OPC_SQRT_D: 10012 check_cp1_registers(ctx, fs | fd); 10013 { 10014 TCGv_i64 fp0 = tcg_temp_new_i64(); 10015 10016 gen_load_fpr64(ctx, fp0, fs); 10017 gen_helper_float_sqrt_d(fp0, tcg_env, fp0); 10018 gen_store_fpr64(ctx, fp0, fd); 10019 } 10020 break; 10021 case OPC_ABS_D: 10022 check_cp1_registers(ctx, fs | fd); 10023 { 10024 TCGv_i64 fp0 = tcg_temp_new_i64(); 10025 10026 gen_load_fpr64(ctx, fp0, fs); 10027 if (ctx->abs2008) { 10028 tcg_gen_andi_i64(fp0, fp0, 0x7fffffffffffffffULL); 10029 } else { 10030 gen_helper_float_abs_d(fp0, fp0); 10031 } 10032 gen_store_fpr64(ctx, fp0, fd); 10033 } 10034 break; 10035 case OPC_MOV_D: 10036 check_cp1_registers(ctx, fs | fd); 10037 { 10038 TCGv_i64 fp0 = tcg_temp_new_i64(); 10039 10040 gen_load_fpr64(ctx, fp0, fs); 10041 gen_store_fpr64(ctx, fp0, fd); 10042 } 10043 break; 10044 case OPC_NEG_D: 10045 check_cp1_registers(ctx, fs | fd); 10046 { 10047 TCGv_i64 fp0 = tcg_temp_new_i64(); 10048 10049 gen_load_fpr64(ctx, fp0, fs); 10050 if (ctx->abs2008) { 10051 tcg_gen_xori_i64(fp0, fp0, 1ULL << 63); 10052 } else { 10053 gen_helper_float_chs_d(fp0, fp0); 10054 } 10055 gen_store_fpr64(ctx, fp0, fd); 10056 } 10057 break; 10058 case OPC_ROUND_L_D: 10059 check_cp1_64bitmode(ctx); 10060 { 10061 TCGv_i64 fp0 = tcg_temp_new_i64(); 10062 10063 gen_load_fpr64(ctx, fp0, fs); 10064 if (ctx->nan2008) { 10065 gen_helper_float_round_2008_l_d(fp0, tcg_env, fp0); 10066 } else { 10067 gen_helper_float_round_l_d(fp0, tcg_env, fp0); 10068 } 10069 gen_store_fpr64(ctx, fp0, fd); 10070 } 10071 break; 10072 case OPC_TRUNC_L_D: 10073 check_cp1_64bitmode(ctx); 10074 { 10075 TCGv_i64 fp0 = tcg_temp_new_i64(); 10076 10077 gen_load_fpr64(ctx, fp0, fs); 10078 if (ctx->nan2008) { 10079 gen_helper_float_trunc_2008_l_d(fp0, tcg_env, fp0); 10080 } else { 10081 gen_helper_float_trunc_l_d(fp0, tcg_env, fp0); 10082 } 10083 gen_store_fpr64(ctx, fp0, fd); 10084 } 10085 break; 10086 case OPC_CEIL_L_D: 10087 check_cp1_64bitmode(ctx); 10088 { 10089 TCGv_i64 fp0 = tcg_temp_new_i64(); 10090 10091 gen_load_fpr64(ctx, fp0, fs); 10092 if (ctx->nan2008) { 10093 gen_helper_float_ceil_2008_l_d(fp0, tcg_env, fp0); 10094 } else { 10095 gen_helper_float_ceil_l_d(fp0, tcg_env, fp0); 10096 } 10097 gen_store_fpr64(ctx, fp0, fd); 10098 } 10099 break; 10100 case OPC_FLOOR_L_D: 10101 check_cp1_64bitmode(ctx); 10102 { 10103 TCGv_i64 fp0 = tcg_temp_new_i64(); 10104 10105 gen_load_fpr64(ctx, fp0, fs); 10106 if (ctx->nan2008) { 10107 gen_helper_float_floor_2008_l_d(fp0, tcg_env, fp0); 10108 } else { 10109 gen_helper_float_floor_l_d(fp0, tcg_env, fp0); 10110 } 10111 gen_store_fpr64(ctx, fp0, fd); 10112 } 10113 break; 10114 case OPC_ROUND_W_D: 10115 check_cp1_registers(ctx, fs); 10116 { 10117 TCGv_i32 fp32 = tcg_temp_new_i32(); 10118 TCGv_i64 fp64 = tcg_temp_new_i64(); 10119 10120 gen_load_fpr64(ctx, fp64, fs); 10121 if (ctx->nan2008) { 10122 gen_helper_float_round_2008_w_d(fp32, tcg_env, fp64); 10123 } else { 10124 gen_helper_float_round_w_d(fp32, tcg_env, fp64); 10125 } 10126 gen_store_fpr32(ctx, fp32, fd); 10127 } 10128 break; 10129 case OPC_TRUNC_W_D: 10130 check_cp1_registers(ctx, fs); 10131 { 10132 TCGv_i32 fp32 = tcg_temp_new_i32(); 10133 TCGv_i64 fp64 = tcg_temp_new_i64(); 10134 10135 gen_load_fpr64(ctx, fp64, fs); 10136 if (ctx->nan2008) { 10137 gen_helper_float_trunc_2008_w_d(fp32, tcg_env, fp64); 10138 } else { 10139 gen_helper_float_trunc_w_d(fp32, tcg_env, fp64); 10140 } 10141 gen_store_fpr32(ctx, fp32, fd); 10142 } 10143 break; 10144 case OPC_CEIL_W_D: 10145 check_cp1_registers(ctx, fs); 10146 { 10147 TCGv_i32 fp32 = tcg_temp_new_i32(); 10148 TCGv_i64 fp64 = tcg_temp_new_i64(); 10149 10150 gen_load_fpr64(ctx, fp64, fs); 10151 if (ctx->nan2008) { 10152 gen_helper_float_ceil_2008_w_d(fp32, tcg_env, fp64); 10153 } else { 10154 gen_helper_float_ceil_w_d(fp32, tcg_env, fp64); 10155 } 10156 gen_store_fpr32(ctx, fp32, fd); 10157 } 10158 break; 10159 case OPC_FLOOR_W_D: 10160 check_cp1_registers(ctx, fs); 10161 { 10162 TCGv_i32 fp32 = tcg_temp_new_i32(); 10163 TCGv_i64 fp64 = tcg_temp_new_i64(); 10164 10165 gen_load_fpr64(ctx, fp64, fs); 10166 if (ctx->nan2008) { 10167 gen_helper_float_floor_2008_w_d(fp32, tcg_env, fp64); 10168 } else { 10169 gen_helper_float_floor_w_d(fp32, tcg_env, fp64); 10170 } 10171 gen_store_fpr32(ctx, fp32, fd); 10172 } 10173 break; 10174 case OPC_SEL_D: 10175 check_insn(ctx, ISA_MIPS_R6); 10176 gen_sel_d(ctx, op1, fd, ft, fs); 10177 break; 10178 case OPC_SELEQZ_D: 10179 check_insn(ctx, ISA_MIPS_R6); 10180 gen_sel_d(ctx, op1, fd, ft, fs); 10181 break; 10182 case OPC_SELNEZ_D: 10183 check_insn(ctx, ISA_MIPS_R6); 10184 gen_sel_d(ctx, op1, fd, ft, fs); 10185 break; 10186 case OPC_MOVCF_D: 10187 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10188 gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); 10189 break; 10190 case OPC_MOVZ_D: 10191 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10192 { 10193 TCGLabel *l1 = gen_new_label(); 10194 TCGv_i64 fp0; 10195 10196 if (ft != 0) { 10197 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); 10198 } 10199 fp0 = tcg_temp_new_i64(); 10200 gen_load_fpr64(ctx, fp0, fs); 10201 gen_store_fpr64(ctx, fp0, fd); 10202 gen_set_label(l1); 10203 } 10204 break; 10205 case OPC_MOVN_D: 10206 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10207 { 10208 TCGLabel *l1 = gen_new_label(); 10209 TCGv_i64 fp0; 10210 10211 if (ft != 0) { 10212 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); 10213 fp0 = tcg_temp_new_i64(); 10214 gen_load_fpr64(ctx, fp0, fs); 10215 gen_store_fpr64(ctx, fp0, fd); 10216 gen_set_label(l1); 10217 } 10218 } 10219 break; 10220 case OPC_RECIP_D: 10221 check_cp1_registers(ctx, fs | fd); 10222 { 10223 TCGv_i64 fp0 = tcg_temp_new_i64(); 10224 10225 gen_load_fpr64(ctx, fp0, fs); 10226 gen_helper_float_recip_d(fp0, tcg_env, fp0); 10227 gen_store_fpr64(ctx, fp0, fd); 10228 } 10229 break; 10230 case OPC_RSQRT_D: 10231 check_cp1_registers(ctx, fs | fd); 10232 { 10233 TCGv_i64 fp0 = tcg_temp_new_i64(); 10234 10235 gen_load_fpr64(ctx, fp0, fs); 10236 gen_helper_float_rsqrt_d(fp0, tcg_env, fp0); 10237 gen_store_fpr64(ctx, fp0, fd); 10238 } 10239 break; 10240 case OPC_MADDF_D: 10241 check_insn(ctx, ISA_MIPS_R6); 10242 { 10243 TCGv_i64 fp0 = tcg_temp_new_i64(); 10244 TCGv_i64 fp1 = tcg_temp_new_i64(); 10245 TCGv_i64 fp2 = tcg_temp_new_i64(); 10246 gen_load_fpr64(ctx, fp0, fs); 10247 gen_load_fpr64(ctx, fp1, ft); 10248 gen_load_fpr64(ctx, fp2, fd); 10249 gen_helper_float_maddf_d(fp2, tcg_env, fp0, fp1, fp2); 10250 gen_store_fpr64(ctx, fp2, fd); 10251 } 10252 break; 10253 case OPC_MSUBF_D: 10254 check_insn(ctx, ISA_MIPS_R6); 10255 { 10256 TCGv_i64 fp0 = tcg_temp_new_i64(); 10257 TCGv_i64 fp1 = tcg_temp_new_i64(); 10258 TCGv_i64 fp2 = tcg_temp_new_i64(); 10259 gen_load_fpr64(ctx, fp0, fs); 10260 gen_load_fpr64(ctx, fp1, ft); 10261 gen_load_fpr64(ctx, fp2, fd); 10262 gen_helper_float_msubf_d(fp2, tcg_env, fp0, fp1, fp2); 10263 gen_store_fpr64(ctx, fp2, fd); 10264 } 10265 break; 10266 case OPC_RINT_D: 10267 check_insn(ctx, ISA_MIPS_R6); 10268 { 10269 TCGv_i64 fp0 = tcg_temp_new_i64(); 10270 gen_load_fpr64(ctx, fp0, fs); 10271 gen_helper_float_rint_d(fp0, tcg_env, fp0); 10272 gen_store_fpr64(ctx, fp0, fd); 10273 } 10274 break; 10275 case OPC_CLASS_D: 10276 check_insn(ctx, ISA_MIPS_R6); 10277 { 10278 TCGv_i64 fp0 = tcg_temp_new_i64(); 10279 gen_load_fpr64(ctx, fp0, fs); 10280 gen_helper_float_class_d(fp0, tcg_env, fp0); 10281 gen_store_fpr64(ctx, fp0, fd); 10282 } 10283 break; 10284 case OPC_MIN_D: /* OPC_RECIP2_D */ 10285 if (ctx->insn_flags & ISA_MIPS_R6) { 10286 /* OPC_MIN_D */ 10287 TCGv_i64 fp0 = tcg_temp_new_i64(); 10288 TCGv_i64 fp1 = tcg_temp_new_i64(); 10289 gen_load_fpr64(ctx, fp0, fs); 10290 gen_load_fpr64(ctx, fp1, ft); 10291 gen_helper_float_min_d(fp1, tcg_env, fp0, fp1); 10292 gen_store_fpr64(ctx, fp1, fd); 10293 } else { 10294 /* OPC_RECIP2_D */ 10295 check_cp1_64bitmode(ctx); 10296 { 10297 TCGv_i64 fp0 = tcg_temp_new_i64(); 10298 TCGv_i64 fp1 = tcg_temp_new_i64(); 10299 10300 gen_load_fpr64(ctx, fp0, fs); 10301 gen_load_fpr64(ctx, fp1, ft); 10302 gen_helper_float_recip2_d(fp0, tcg_env, fp0, fp1); 10303 gen_store_fpr64(ctx, fp0, fd); 10304 } 10305 } 10306 break; 10307 case OPC_MINA_D: /* OPC_RECIP1_D */ 10308 if (ctx->insn_flags & ISA_MIPS_R6) { 10309 /* OPC_MINA_D */ 10310 TCGv_i64 fp0 = tcg_temp_new_i64(); 10311 TCGv_i64 fp1 = tcg_temp_new_i64(); 10312 gen_load_fpr64(ctx, fp0, fs); 10313 gen_load_fpr64(ctx, fp1, ft); 10314 gen_helper_float_mina_d(fp1, tcg_env, fp0, fp1); 10315 gen_store_fpr64(ctx, fp1, fd); 10316 } else { 10317 /* OPC_RECIP1_D */ 10318 check_cp1_64bitmode(ctx); 10319 { 10320 TCGv_i64 fp0 = tcg_temp_new_i64(); 10321 10322 gen_load_fpr64(ctx, fp0, fs); 10323 gen_helper_float_recip1_d(fp0, tcg_env, fp0); 10324 gen_store_fpr64(ctx, fp0, fd); 10325 } 10326 } 10327 break; 10328 case OPC_MAX_D: /* OPC_RSQRT1_D */ 10329 if (ctx->insn_flags & ISA_MIPS_R6) { 10330 /* OPC_MAX_D */ 10331 TCGv_i64 fp0 = tcg_temp_new_i64(); 10332 TCGv_i64 fp1 = tcg_temp_new_i64(); 10333 gen_load_fpr64(ctx, fp0, fs); 10334 gen_load_fpr64(ctx, fp1, ft); 10335 gen_helper_float_max_d(fp1, tcg_env, fp0, fp1); 10336 gen_store_fpr64(ctx, fp1, fd); 10337 } else { 10338 /* OPC_RSQRT1_D */ 10339 check_cp1_64bitmode(ctx); 10340 { 10341 TCGv_i64 fp0 = tcg_temp_new_i64(); 10342 10343 gen_load_fpr64(ctx, fp0, fs); 10344 gen_helper_float_rsqrt1_d(fp0, tcg_env, fp0); 10345 gen_store_fpr64(ctx, fp0, fd); 10346 } 10347 } 10348 break; 10349 case OPC_MAXA_D: /* OPC_RSQRT2_D */ 10350 if (ctx->insn_flags & ISA_MIPS_R6) { 10351 /* OPC_MAXA_D */ 10352 TCGv_i64 fp0 = tcg_temp_new_i64(); 10353 TCGv_i64 fp1 = tcg_temp_new_i64(); 10354 gen_load_fpr64(ctx, fp0, fs); 10355 gen_load_fpr64(ctx, fp1, ft); 10356 gen_helper_float_maxa_d(fp1, tcg_env, fp0, fp1); 10357 gen_store_fpr64(ctx, fp1, fd); 10358 } else { 10359 /* OPC_RSQRT2_D */ 10360 check_cp1_64bitmode(ctx); 10361 { 10362 TCGv_i64 fp0 = tcg_temp_new_i64(); 10363 TCGv_i64 fp1 = tcg_temp_new_i64(); 10364 10365 gen_load_fpr64(ctx, fp0, fs); 10366 gen_load_fpr64(ctx, fp1, ft); 10367 gen_helper_float_rsqrt2_d(fp0, tcg_env, fp0, fp1); 10368 gen_store_fpr64(ctx, fp0, fd); 10369 } 10370 } 10371 break; 10372 case OPC_CMP_F_D: 10373 case OPC_CMP_UN_D: 10374 case OPC_CMP_EQ_D: 10375 case OPC_CMP_UEQ_D: 10376 case OPC_CMP_OLT_D: 10377 case OPC_CMP_ULT_D: 10378 case OPC_CMP_OLE_D: 10379 case OPC_CMP_ULE_D: 10380 case OPC_CMP_SF_D: 10381 case OPC_CMP_NGLE_D: 10382 case OPC_CMP_SEQ_D: 10383 case OPC_CMP_NGL_D: 10384 case OPC_CMP_LT_D: 10385 case OPC_CMP_NGE_D: 10386 case OPC_CMP_LE_D: 10387 case OPC_CMP_NGT_D: 10388 check_insn_opc_removed(ctx, ISA_MIPS_R6); 10389 if (ctx->opcode & (1 << 6)) { 10390 gen_cmpabs_d(ctx, func - 48, ft, fs, cc); 10391 } else { 10392 gen_cmp_d(ctx, func - 48, ft, fs, cc); 10393 } 10394 break; 10395 case OPC_CVT_S_D: 10396 check_cp1_registers(ctx, fs); 10397 { 10398 TCGv_i32 fp32 = tcg_temp_new_i32(); 10399 TCGv_i64 fp64 = tcg_temp_new_i64(); 10400 10401 gen_load_fpr64(ctx, fp64, fs); 10402 gen_helper_float_cvts_d(fp32, tcg_env, fp64); 10403 gen_store_fpr32(ctx, fp32, fd); 10404 } 10405 break; 10406 case OPC_CVT_W_D: 10407 check_cp1_registers(ctx, fs); 10408 { 10409 TCGv_i32 fp32 = tcg_temp_new_i32(); 10410 TCGv_i64 fp64 = tcg_temp_new_i64(); 10411 10412 gen_load_fpr64(ctx, fp64, fs); 10413 if (ctx->nan2008) { 10414 gen_helper_float_cvt_2008_w_d(fp32, tcg_env, fp64); 10415 } else { 10416 gen_helper_float_cvt_w_d(fp32, tcg_env, fp64); 10417 } 10418 gen_store_fpr32(ctx, fp32, fd); 10419 } 10420 break; 10421 case OPC_CVT_L_D: 10422 check_cp1_64bitmode(ctx); 10423 { 10424 TCGv_i64 fp0 = tcg_temp_new_i64(); 10425 10426 gen_load_fpr64(ctx, fp0, fs); 10427 if (ctx->nan2008) { 10428 gen_helper_float_cvt_2008_l_d(fp0, tcg_env, fp0); 10429 } else { 10430 gen_helper_float_cvt_l_d(fp0, tcg_env, fp0); 10431 } 10432 gen_store_fpr64(ctx, fp0, fd); 10433 } 10434 break; 10435 case OPC_CVT_S_W: 10436 { 10437 TCGv_i32 fp0 = tcg_temp_new_i32(); 10438 10439 gen_load_fpr32(ctx, fp0, fs); 10440 gen_helper_float_cvts_w(fp0, tcg_env, fp0); 10441 gen_store_fpr32(ctx, fp0, fd); 10442 } 10443 break; 10444 case OPC_CVT_D_W: 10445 check_cp1_registers(ctx, fd); 10446 { 10447 TCGv_i32 fp32 = tcg_temp_new_i32(); 10448 TCGv_i64 fp64 = tcg_temp_new_i64(); 10449 10450 gen_load_fpr32(ctx, fp32, fs); 10451 gen_helper_float_cvtd_w(fp64, tcg_env, fp32); 10452 gen_store_fpr64(ctx, fp64, fd); 10453 } 10454 break; 10455 case OPC_CVT_S_L: 10456 check_cp1_64bitmode(ctx); 10457 { 10458 TCGv_i32 fp32 = tcg_temp_new_i32(); 10459 TCGv_i64 fp64 = tcg_temp_new_i64(); 10460 10461 gen_load_fpr64(ctx, fp64, fs); 10462 gen_helper_float_cvts_l(fp32, tcg_env, fp64); 10463 gen_store_fpr32(ctx, fp32, fd); 10464 } 10465 break; 10466 case OPC_CVT_D_L: 10467 check_cp1_64bitmode(ctx); 10468 { 10469 TCGv_i64 fp0 = tcg_temp_new_i64(); 10470 10471 gen_load_fpr64(ctx, fp0, fs); 10472 gen_helper_float_cvtd_l(fp0, tcg_env, fp0); 10473 gen_store_fpr64(ctx, fp0, fd); 10474 } 10475 break; 10476 case OPC_CVT_PS_PW: 10477 check_ps(ctx); 10478 { 10479 TCGv_i64 fp0 = tcg_temp_new_i64(); 10480 10481 gen_load_fpr64(ctx, fp0, fs); 10482 gen_helper_float_cvtps_pw(fp0, tcg_env, fp0); 10483 gen_store_fpr64(ctx, fp0, fd); 10484 } 10485 break; 10486 case OPC_ADD_PS: 10487 check_ps(ctx); 10488 { 10489 TCGv_i64 fp0 = tcg_temp_new_i64(); 10490 TCGv_i64 fp1 = tcg_temp_new_i64(); 10491 10492 gen_load_fpr64(ctx, fp0, fs); 10493 gen_load_fpr64(ctx, fp1, ft); 10494 gen_helper_float_add_ps(fp0, tcg_env, fp0, fp1); 10495 gen_store_fpr64(ctx, fp0, fd); 10496 } 10497 break; 10498 case OPC_SUB_PS: 10499 check_ps(ctx); 10500 { 10501 TCGv_i64 fp0 = tcg_temp_new_i64(); 10502 TCGv_i64 fp1 = tcg_temp_new_i64(); 10503 10504 gen_load_fpr64(ctx, fp0, fs); 10505 gen_load_fpr64(ctx, fp1, ft); 10506 gen_helper_float_sub_ps(fp0, tcg_env, fp0, fp1); 10507 gen_store_fpr64(ctx, fp0, fd); 10508 } 10509 break; 10510 case OPC_MUL_PS: 10511 check_ps(ctx); 10512 { 10513 TCGv_i64 fp0 = tcg_temp_new_i64(); 10514 TCGv_i64 fp1 = tcg_temp_new_i64(); 10515 10516 gen_load_fpr64(ctx, fp0, fs); 10517 gen_load_fpr64(ctx, fp1, ft); 10518 gen_helper_float_mul_ps(fp0, tcg_env, fp0, fp1); 10519 gen_store_fpr64(ctx, fp0, fd); 10520 } 10521 break; 10522 case OPC_ABS_PS: 10523 check_ps(ctx); 10524 { 10525 TCGv_i64 fp0 = tcg_temp_new_i64(); 10526 10527 gen_load_fpr64(ctx, fp0, fs); 10528 gen_helper_float_abs_ps(fp0, fp0); 10529 gen_store_fpr64(ctx, fp0, fd); 10530 } 10531 break; 10532 case OPC_MOV_PS: 10533 check_ps(ctx); 10534 { 10535 TCGv_i64 fp0 = tcg_temp_new_i64(); 10536 10537 gen_load_fpr64(ctx, fp0, fs); 10538 gen_store_fpr64(ctx, fp0, fd); 10539 } 10540 break; 10541 case OPC_NEG_PS: 10542 check_ps(ctx); 10543 { 10544 TCGv_i64 fp0 = tcg_temp_new_i64(); 10545 10546 gen_load_fpr64(ctx, fp0, fs); 10547 gen_helper_float_chs_ps(fp0, fp0); 10548 gen_store_fpr64(ctx, fp0, fd); 10549 } 10550 break; 10551 case OPC_MOVCF_PS: 10552 check_ps(ctx); 10553 gen_movcf_ps(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); 10554 break; 10555 case OPC_MOVZ_PS: 10556 check_ps(ctx); 10557 { 10558 TCGLabel *l1 = gen_new_label(); 10559 TCGv_i64 fp0; 10560 10561 if (ft != 0) { 10562 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); 10563 } 10564 fp0 = tcg_temp_new_i64(); 10565 gen_load_fpr64(ctx, fp0, fs); 10566 gen_store_fpr64(ctx, fp0, fd); 10567 gen_set_label(l1); 10568 } 10569 break; 10570 case OPC_MOVN_PS: 10571 check_ps(ctx); 10572 { 10573 TCGLabel *l1 = gen_new_label(); 10574 TCGv_i64 fp0; 10575 10576 if (ft != 0) { 10577 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); 10578 fp0 = tcg_temp_new_i64(); 10579 gen_load_fpr64(ctx, fp0, fs); 10580 gen_store_fpr64(ctx, fp0, fd); 10581 gen_set_label(l1); 10582 } 10583 } 10584 break; 10585 case OPC_ADDR_PS: 10586 check_ps(ctx); 10587 { 10588 TCGv_i64 fp0 = tcg_temp_new_i64(); 10589 TCGv_i64 fp1 = tcg_temp_new_i64(); 10590 10591 gen_load_fpr64(ctx, fp0, ft); 10592 gen_load_fpr64(ctx, fp1, fs); 10593 gen_helper_float_addr_ps(fp0, tcg_env, fp0, fp1); 10594 gen_store_fpr64(ctx, fp0, fd); 10595 } 10596 break; 10597 case OPC_MULR_PS: 10598 check_ps(ctx); 10599 { 10600 TCGv_i64 fp0 = tcg_temp_new_i64(); 10601 TCGv_i64 fp1 = tcg_temp_new_i64(); 10602 10603 gen_load_fpr64(ctx, fp0, ft); 10604 gen_load_fpr64(ctx, fp1, fs); 10605 gen_helper_float_mulr_ps(fp0, tcg_env, fp0, fp1); 10606 gen_store_fpr64(ctx, fp0, fd); 10607 } 10608 break; 10609 case OPC_RECIP2_PS: 10610 check_ps(ctx); 10611 { 10612 TCGv_i64 fp0 = tcg_temp_new_i64(); 10613 TCGv_i64 fp1 = tcg_temp_new_i64(); 10614 10615 gen_load_fpr64(ctx, fp0, fs); 10616 gen_load_fpr64(ctx, fp1, ft); 10617 gen_helper_float_recip2_ps(fp0, tcg_env, fp0, fp1); 10618 gen_store_fpr64(ctx, fp0, fd); 10619 } 10620 break; 10621 case OPC_RECIP1_PS: 10622 check_ps(ctx); 10623 { 10624 TCGv_i64 fp0 = tcg_temp_new_i64(); 10625 10626 gen_load_fpr64(ctx, fp0, fs); 10627 gen_helper_float_recip1_ps(fp0, tcg_env, fp0); 10628 gen_store_fpr64(ctx, fp0, fd); 10629 } 10630 break; 10631 case OPC_RSQRT1_PS: 10632 check_ps(ctx); 10633 { 10634 TCGv_i64 fp0 = tcg_temp_new_i64(); 10635 10636 gen_load_fpr64(ctx, fp0, fs); 10637 gen_helper_float_rsqrt1_ps(fp0, tcg_env, fp0); 10638 gen_store_fpr64(ctx, fp0, fd); 10639 } 10640 break; 10641 case OPC_RSQRT2_PS: 10642 check_ps(ctx); 10643 { 10644 TCGv_i64 fp0 = tcg_temp_new_i64(); 10645 TCGv_i64 fp1 = tcg_temp_new_i64(); 10646 10647 gen_load_fpr64(ctx, fp0, fs); 10648 gen_load_fpr64(ctx, fp1, ft); 10649 gen_helper_float_rsqrt2_ps(fp0, tcg_env, fp0, fp1); 10650 gen_store_fpr64(ctx, fp0, fd); 10651 } 10652 break; 10653 case OPC_CVT_S_PU: 10654 check_cp1_64bitmode(ctx); 10655 { 10656 TCGv_i32 fp0 = tcg_temp_new_i32(); 10657 10658 gen_load_fpr32h(ctx, fp0, fs); 10659 gen_helper_float_cvts_pu(fp0, tcg_env, fp0); 10660 gen_store_fpr32(ctx, fp0, fd); 10661 } 10662 break; 10663 case OPC_CVT_PW_PS: 10664 check_ps(ctx); 10665 { 10666 TCGv_i64 fp0 = tcg_temp_new_i64(); 10667 10668 gen_load_fpr64(ctx, fp0, fs); 10669 gen_helper_float_cvtpw_ps(fp0, tcg_env, fp0); 10670 gen_store_fpr64(ctx, fp0, fd); 10671 } 10672 break; 10673 case OPC_CVT_S_PL: 10674 check_cp1_64bitmode(ctx); 10675 { 10676 TCGv_i32 fp0 = tcg_temp_new_i32(); 10677 10678 gen_load_fpr32(ctx, fp0, fs); 10679 gen_helper_float_cvts_pl(fp0, tcg_env, fp0); 10680 gen_store_fpr32(ctx, fp0, fd); 10681 } 10682 break; 10683 case OPC_PLL_PS: 10684 check_ps(ctx); 10685 { 10686 TCGv_i32 fp0 = tcg_temp_new_i32(); 10687 TCGv_i32 fp1 = tcg_temp_new_i32(); 10688 10689 gen_load_fpr32(ctx, fp0, fs); 10690 gen_load_fpr32(ctx, fp1, ft); 10691 gen_store_fpr32h(ctx, fp0, fd); 10692 gen_store_fpr32(ctx, fp1, fd); 10693 } 10694 break; 10695 case OPC_PLU_PS: 10696 check_ps(ctx); 10697 { 10698 TCGv_i32 fp0 = tcg_temp_new_i32(); 10699 TCGv_i32 fp1 = tcg_temp_new_i32(); 10700 10701 gen_load_fpr32(ctx, fp0, fs); 10702 gen_load_fpr32h(ctx, fp1, ft); 10703 gen_store_fpr32(ctx, fp1, fd); 10704 gen_store_fpr32h(ctx, fp0, fd); 10705 } 10706 break; 10707 case OPC_PUL_PS: 10708 check_ps(ctx); 10709 { 10710 TCGv_i32 fp0 = tcg_temp_new_i32(); 10711 TCGv_i32 fp1 = tcg_temp_new_i32(); 10712 10713 gen_load_fpr32h(ctx, fp0, fs); 10714 gen_load_fpr32(ctx, fp1, ft); 10715 gen_store_fpr32(ctx, fp1, fd); 10716 gen_store_fpr32h(ctx, fp0, fd); 10717 } 10718 break; 10719 case OPC_PUU_PS: 10720 check_ps(ctx); 10721 { 10722 TCGv_i32 fp0 = tcg_temp_new_i32(); 10723 TCGv_i32 fp1 = tcg_temp_new_i32(); 10724 10725 gen_load_fpr32h(ctx, fp0, fs); 10726 gen_load_fpr32h(ctx, fp1, ft); 10727 gen_store_fpr32(ctx, fp1, fd); 10728 gen_store_fpr32h(ctx, fp0, fd); 10729 } 10730 break; 10731 case OPC_CMP_F_PS: 10732 case OPC_CMP_UN_PS: 10733 case OPC_CMP_EQ_PS: 10734 case OPC_CMP_UEQ_PS: 10735 case OPC_CMP_OLT_PS: 10736 case OPC_CMP_ULT_PS: 10737 case OPC_CMP_OLE_PS: 10738 case OPC_CMP_ULE_PS: 10739 case OPC_CMP_SF_PS: 10740 case OPC_CMP_NGLE_PS: 10741 case OPC_CMP_SEQ_PS: 10742 case OPC_CMP_NGL_PS: 10743 case OPC_CMP_LT_PS: 10744 case OPC_CMP_NGE_PS: 10745 case OPC_CMP_LE_PS: 10746 case OPC_CMP_NGT_PS: 10747 if (ctx->opcode & (1 << 6)) { 10748 gen_cmpabs_ps(ctx, func - 48, ft, fs, cc); 10749 } else { 10750 gen_cmp_ps(ctx, func - 48, ft, fs, cc); 10751 } 10752 break; 10753 default: 10754 MIPS_INVAL("farith"); 10755 gen_reserved_instruction(ctx); 10756 return; 10757 } 10758 } 10759 10760 /* Coprocessor 3 (FPU) */ 10761 static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, 10762 int fd, int fs, int base, int index) 10763 { 10764 TCGv t0 = tcg_temp_new(); 10765 10766 if (base == 0) { 10767 gen_load_gpr(t0, index); 10768 } else if (index == 0) { 10769 gen_load_gpr(t0, base); 10770 } else { 10771 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]); 10772 } 10773 /* 10774 * Don't do NOP if destination is zero: we must perform the actual 10775 * memory access. 10776 */ 10777 switch (opc) { 10778 case OPC_LWXC1: 10779 check_cop1x(ctx); 10780 { 10781 TCGv_i32 fp0 = tcg_temp_new_i32(); 10782 10783 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); 10784 tcg_gen_trunc_tl_i32(fp0, t0); 10785 gen_store_fpr32(ctx, fp0, fd); 10786 } 10787 break; 10788 case OPC_LDXC1: 10789 check_cop1x(ctx); 10790 check_cp1_registers(ctx, fd); 10791 { 10792 TCGv_i64 fp0 = tcg_temp_new_i64(); 10793 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); 10794 gen_store_fpr64(ctx, fp0, fd); 10795 } 10796 break; 10797 case OPC_LUXC1: 10798 check_cp1_64bitmode(ctx); 10799 tcg_gen_andi_tl(t0, t0, ~0x7); 10800 { 10801 TCGv_i64 fp0 = tcg_temp_new_i64(); 10802 10803 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); 10804 gen_store_fpr64(ctx, fp0, fd); 10805 } 10806 break; 10807 case OPC_SWXC1: 10808 check_cop1x(ctx); 10809 { 10810 TCGv_i32 fp0 = tcg_temp_new_i32(); 10811 gen_load_fpr32(ctx, fp0, fs); 10812 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL); 10813 } 10814 break; 10815 case OPC_SDXC1: 10816 check_cop1x(ctx); 10817 check_cp1_registers(ctx, fs); 10818 { 10819 TCGv_i64 fp0 = tcg_temp_new_i64(); 10820 gen_load_fpr64(ctx, fp0, fs); 10821 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); 10822 } 10823 break; 10824 case OPC_SUXC1: 10825 check_cp1_64bitmode(ctx); 10826 tcg_gen_andi_tl(t0, t0, ~0x7); 10827 { 10828 TCGv_i64 fp0 = tcg_temp_new_i64(); 10829 gen_load_fpr64(ctx, fp0, fs); 10830 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); 10831 } 10832 break; 10833 } 10834 } 10835 10836 static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, 10837 int fd, int fr, int fs, int ft) 10838 { 10839 switch (opc) { 10840 case OPC_ALNV_PS: 10841 check_ps(ctx); 10842 { 10843 TCGv t0 = tcg_temp_new(); 10844 TCGv_i32 fp = tcg_temp_new_i32(); 10845 TCGv_i32 fph = tcg_temp_new_i32(); 10846 TCGLabel *l1 = gen_new_label(); 10847 TCGLabel *l2 = gen_new_label(); 10848 10849 gen_load_gpr(t0, fr); 10850 tcg_gen_andi_tl(t0, t0, 0x7); 10851 10852 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1); 10853 gen_load_fpr32(ctx, fp, fs); 10854 gen_load_fpr32h(ctx, fph, fs); 10855 gen_store_fpr32(ctx, fp, fd); 10856 gen_store_fpr32h(ctx, fph, fd); 10857 tcg_gen_br(l2); 10858 gen_set_label(l1); 10859 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); 10860 if (cpu_is_bigendian(ctx)) { 10861 gen_load_fpr32(ctx, fp, fs); 10862 gen_load_fpr32h(ctx, fph, ft); 10863 gen_store_fpr32h(ctx, fp, fd); 10864 gen_store_fpr32(ctx, fph, fd); 10865 } else { 10866 gen_load_fpr32h(ctx, fph, fs); 10867 gen_load_fpr32(ctx, fp, ft); 10868 gen_store_fpr32(ctx, fph, fd); 10869 gen_store_fpr32h(ctx, fp, fd); 10870 } 10871 gen_set_label(l2); 10872 } 10873 break; 10874 case OPC_MADD_S: 10875 check_cop1x(ctx); 10876 { 10877 TCGv_i32 fp0 = tcg_temp_new_i32(); 10878 TCGv_i32 fp1 = tcg_temp_new_i32(); 10879 TCGv_i32 fp2 = tcg_temp_new_i32(); 10880 10881 gen_load_fpr32(ctx, fp0, fs); 10882 gen_load_fpr32(ctx, fp1, ft); 10883 gen_load_fpr32(ctx, fp2, fr); 10884 gen_helper_float_madd_s(fp2, tcg_env, fp0, fp1, fp2); 10885 gen_store_fpr32(ctx, fp2, fd); 10886 } 10887 break; 10888 case OPC_MADD_D: 10889 check_cop1x(ctx); 10890 check_cp1_registers(ctx, fd | fs | ft | fr); 10891 { 10892 TCGv_i64 fp0 = tcg_temp_new_i64(); 10893 TCGv_i64 fp1 = tcg_temp_new_i64(); 10894 TCGv_i64 fp2 = tcg_temp_new_i64(); 10895 10896 gen_load_fpr64(ctx, fp0, fs); 10897 gen_load_fpr64(ctx, fp1, ft); 10898 gen_load_fpr64(ctx, fp2, fr); 10899 gen_helper_float_madd_d(fp2, tcg_env, fp0, fp1, fp2); 10900 gen_store_fpr64(ctx, fp2, fd); 10901 } 10902 break; 10903 case OPC_MADD_PS: 10904 check_ps(ctx); 10905 { 10906 TCGv_i64 fp0 = tcg_temp_new_i64(); 10907 TCGv_i64 fp1 = tcg_temp_new_i64(); 10908 TCGv_i64 fp2 = tcg_temp_new_i64(); 10909 10910 gen_load_fpr64(ctx, fp0, fs); 10911 gen_load_fpr64(ctx, fp1, ft); 10912 gen_load_fpr64(ctx, fp2, fr); 10913 gen_helper_float_madd_ps(fp2, tcg_env, fp0, fp1, fp2); 10914 gen_store_fpr64(ctx, fp2, fd); 10915 } 10916 break; 10917 case OPC_MSUB_S: 10918 check_cop1x(ctx); 10919 { 10920 TCGv_i32 fp0 = tcg_temp_new_i32(); 10921 TCGv_i32 fp1 = tcg_temp_new_i32(); 10922 TCGv_i32 fp2 = tcg_temp_new_i32(); 10923 10924 gen_load_fpr32(ctx, fp0, fs); 10925 gen_load_fpr32(ctx, fp1, ft); 10926 gen_load_fpr32(ctx, fp2, fr); 10927 gen_helper_float_msub_s(fp2, tcg_env, fp0, fp1, fp2); 10928 gen_store_fpr32(ctx, fp2, fd); 10929 } 10930 break; 10931 case OPC_MSUB_D: 10932 check_cop1x(ctx); 10933 check_cp1_registers(ctx, fd | fs | ft | fr); 10934 { 10935 TCGv_i64 fp0 = tcg_temp_new_i64(); 10936 TCGv_i64 fp1 = tcg_temp_new_i64(); 10937 TCGv_i64 fp2 = tcg_temp_new_i64(); 10938 10939 gen_load_fpr64(ctx, fp0, fs); 10940 gen_load_fpr64(ctx, fp1, ft); 10941 gen_load_fpr64(ctx, fp2, fr); 10942 gen_helper_float_msub_d(fp2, tcg_env, fp0, fp1, fp2); 10943 gen_store_fpr64(ctx, fp2, fd); 10944 } 10945 break; 10946 case OPC_MSUB_PS: 10947 check_ps(ctx); 10948 { 10949 TCGv_i64 fp0 = tcg_temp_new_i64(); 10950 TCGv_i64 fp1 = tcg_temp_new_i64(); 10951 TCGv_i64 fp2 = tcg_temp_new_i64(); 10952 10953 gen_load_fpr64(ctx, fp0, fs); 10954 gen_load_fpr64(ctx, fp1, ft); 10955 gen_load_fpr64(ctx, fp2, fr); 10956 gen_helper_float_msub_ps(fp2, tcg_env, fp0, fp1, fp2); 10957 gen_store_fpr64(ctx, fp2, fd); 10958 } 10959 break; 10960 case OPC_NMADD_S: 10961 check_cop1x(ctx); 10962 { 10963 TCGv_i32 fp0 = tcg_temp_new_i32(); 10964 TCGv_i32 fp1 = tcg_temp_new_i32(); 10965 TCGv_i32 fp2 = tcg_temp_new_i32(); 10966 10967 gen_load_fpr32(ctx, fp0, fs); 10968 gen_load_fpr32(ctx, fp1, ft); 10969 gen_load_fpr32(ctx, fp2, fr); 10970 gen_helper_float_nmadd_s(fp2, tcg_env, fp0, fp1, fp2); 10971 gen_store_fpr32(ctx, fp2, fd); 10972 } 10973 break; 10974 case OPC_NMADD_D: 10975 check_cop1x(ctx); 10976 check_cp1_registers(ctx, fd | fs | ft | fr); 10977 { 10978 TCGv_i64 fp0 = tcg_temp_new_i64(); 10979 TCGv_i64 fp1 = tcg_temp_new_i64(); 10980 TCGv_i64 fp2 = tcg_temp_new_i64(); 10981 10982 gen_load_fpr64(ctx, fp0, fs); 10983 gen_load_fpr64(ctx, fp1, ft); 10984 gen_load_fpr64(ctx, fp2, fr); 10985 gen_helper_float_nmadd_d(fp2, tcg_env, fp0, fp1, fp2); 10986 gen_store_fpr64(ctx, fp2, fd); 10987 } 10988 break; 10989 case OPC_NMADD_PS: 10990 check_ps(ctx); 10991 { 10992 TCGv_i64 fp0 = tcg_temp_new_i64(); 10993 TCGv_i64 fp1 = tcg_temp_new_i64(); 10994 TCGv_i64 fp2 = tcg_temp_new_i64(); 10995 10996 gen_load_fpr64(ctx, fp0, fs); 10997 gen_load_fpr64(ctx, fp1, ft); 10998 gen_load_fpr64(ctx, fp2, fr); 10999 gen_helper_float_nmadd_ps(fp2, tcg_env, fp0, fp1, fp2); 11000 gen_store_fpr64(ctx, fp2, fd); 11001 } 11002 break; 11003 case OPC_NMSUB_S: 11004 check_cop1x(ctx); 11005 { 11006 TCGv_i32 fp0 = tcg_temp_new_i32(); 11007 TCGv_i32 fp1 = tcg_temp_new_i32(); 11008 TCGv_i32 fp2 = tcg_temp_new_i32(); 11009 11010 gen_load_fpr32(ctx, fp0, fs); 11011 gen_load_fpr32(ctx, fp1, ft); 11012 gen_load_fpr32(ctx, fp2, fr); 11013 gen_helper_float_nmsub_s(fp2, tcg_env, fp0, fp1, fp2); 11014 gen_store_fpr32(ctx, fp2, fd); 11015 } 11016 break; 11017 case OPC_NMSUB_D: 11018 check_cop1x(ctx); 11019 check_cp1_registers(ctx, fd | fs | ft | fr); 11020 { 11021 TCGv_i64 fp0 = tcg_temp_new_i64(); 11022 TCGv_i64 fp1 = tcg_temp_new_i64(); 11023 TCGv_i64 fp2 = tcg_temp_new_i64(); 11024 11025 gen_load_fpr64(ctx, fp0, fs); 11026 gen_load_fpr64(ctx, fp1, ft); 11027 gen_load_fpr64(ctx, fp2, fr); 11028 gen_helper_float_nmsub_d(fp2, tcg_env, fp0, fp1, fp2); 11029 gen_store_fpr64(ctx, fp2, fd); 11030 } 11031 break; 11032 case OPC_NMSUB_PS: 11033 check_ps(ctx); 11034 { 11035 TCGv_i64 fp0 = tcg_temp_new_i64(); 11036 TCGv_i64 fp1 = tcg_temp_new_i64(); 11037 TCGv_i64 fp2 = tcg_temp_new_i64(); 11038 11039 gen_load_fpr64(ctx, fp0, fs); 11040 gen_load_fpr64(ctx, fp1, ft); 11041 gen_load_fpr64(ctx, fp2, fr); 11042 gen_helper_float_nmsub_ps(fp2, tcg_env, fp0, fp1, fp2); 11043 gen_store_fpr64(ctx, fp2, fd); 11044 } 11045 break; 11046 default: 11047 MIPS_INVAL("flt3_arith"); 11048 gen_reserved_instruction(ctx); 11049 return; 11050 } 11051 } 11052 11053 void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) 11054 { 11055 TCGv t0; 11056 11057 #if !defined(CONFIG_USER_ONLY) 11058 /* 11059 * The Linux kernel will emulate rdhwr if it's not supported natively. 11060 * Therefore only check the ISA in system mode. 11061 */ 11062 check_insn(ctx, ISA_MIPS_R2); 11063 #endif 11064 t0 = tcg_temp_new(); 11065 11066 switch (rd) { 11067 case 0: 11068 gen_helper_rdhwr_cpunum(t0, tcg_env); 11069 gen_store_gpr(t0, rt); 11070 break; 11071 case 1: 11072 gen_helper_rdhwr_synci_step(t0, tcg_env); 11073 gen_store_gpr(t0, rt); 11074 break; 11075 case 2: 11076 translator_io_start(&ctx->base); 11077 gen_helper_rdhwr_cc(t0, tcg_env); 11078 gen_store_gpr(t0, rt); 11079 /* 11080 * Break the TB to be able to take timer interrupts immediately 11081 * after reading count. DISAS_STOP isn't sufficient, we need to ensure 11082 * we break completely out of translated code. 11083 */ 11084 gen_save_pc(ctx->base.pc_next + 4); 11085 ctx->base.is_jmp = DISAS_EXIT; 11086 break; 11087 case 3: 11088 gen_helper_rdhwr_ccres(t0, tcg_env); 11089 gen_store_gpr(t0, rt); 11090 break; 11091 case 4: 11092 check_insn(ctx, ISA_MIPS_R6); 11093 if (sel != 0) { 11094 /* 11095 * Performance counter registers are not implemented other than 11096 * control register 0. 11097 */ 11098 generate_exception(ctx, EXCP_RI); 11099 } 11100 gen_helper_rdhwr_performance(t0, tcg_env); 11101 gen_store_gpr(t0, rt); 11102 break; 11103 case 5: 11104 check_insn(ctx, ISA_MIPS_R6); 11105 gen_helper_rdhwr_xnp(t0, tcg_env); 11106 gen_store_gpr(t0, rt); 11107 break; 11108 case 29: 11109 #if defined(CONFIG_USER_ONLY) 11110 tcg_gen_ld_tl(t0, tcg_env, 11111 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 11112 gen_store_gpr(t0, rt); 11113 break; 11114 #else 11115 if ((ctx->hflags & MIPS_HFLAG_CP0) || 11116 (ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) { 11117 tcg_gen_ld_tl(t0, tcg_env, 11118 offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); 11119 gen_store_gpr(t0, rt); 11120 } else { 11121 gen_reserved_instruction(ctx); 11122 } 11123 break; 11124 #endif 11125 default: /* Invalid */ 11126 MIPS_INVAL("rdhwr"); 11127 gen_reserved_instruction(ctx); 11128 break; 11129 } 11130 } 11131 11132 static inline void clear_branch_hflags(DisasContext *ctx) 11133 { 11134 ctx->hflags &= ~MIPS_HFLAG_BMASK; 11135 if (ctx->base.is_jmp == DISAS_NEXT) { 11136 save_cpu_state(ctx, 0); 11137 } else { 11138 /* 11139 * It is not safe to save ctx->hflags as hflags may be changed 11140 * in execution time by the instruction in delay / forbidden slot. 11141 */ 11142 tcg_gen_andi_i32(hflags, hflags, ~MIPS_HFLAG_BMASK); 11143 } 11144 } 11145 11146 static void gen_branch(DisasContext *ctx, int insn_bytes) 11147 { 11148 if (ctx->hflags & MIPS_HFLAG_BMASK) { 11149 int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK; 11150 /* Branches completion */ 11151 clear_branch_hflags(ctx); 11152 ctx->base.is_jmp = DISAS_NORETURN; 11153 switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) { 11154 case MIPS_HFLAG_FBNSLOT: 11155 gen_goto_tb(ctx, 0, ctx->base.pc_next + insn_bytes); 11156 break; 11157 case MIPS_HFLAG_B: 11158 /* unconditional branch */ 11159 if (proc_hflags & MIPS_HFLAG_BX) { 11160 tcg_gen_xori_i32(hflags, hflags, MIPS_HFLAG_M16); 11161 } 11162 gen_goto_tb(ctx, 0, ctx->btarget); 11163 break; 11164 case MIPS_HFLAG_BL: 11165 /* blikely taken case */ 11166 gen_goto_tb(ctx, 0, ctx->btarget); 11167 break; 11168 case MIPS_HFLAG_BC: 11169 /* Conditional branch */ 11170 { 11171 TCGLabel *l1 = gen_new_label(); 11172 11173 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); 11174 gen_goto_tb(ctx, 1, ctx->base.pc_next + insn_bytes); 11175 gen_set_label(l1); 11176 gen_goto_tb(ctx, 0, ctx->btarget); 11177 } 11178 break; 11179 case MIPS_HFLAG_BR: 11180 /* unconditional branch to register */ 11181 if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) { 11182 TCGv t0 = tcg_temp_new(); 11183 TCGv_i32 t1 = tcg_temp_new_i32(); 11184 11185 tcg_gen_andi_tl(t0, btarget, 0x1); 11186 tcg_gen_trunc_tl_i32(t1, t0); 11187 tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16); 11188 tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT); 11189 tcg_gen_or_i32(hflags, hflags, t1); 11190 11191 tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1); 11192 } else { 11193 tcg_gen_mov_tl(cpu_PC, btarget); 11194 } 11195 tcg_gen_lookup_and_goto_ptr(); 11196 break; 11197 default: 11198 LOG_DISAS("unknown branch 0x%x\n", proc_hflags); 11199 gen_reserved_instruction(ctx); 11200 } 11201 } 11202 } 11203 11204 /* Compact Branches */ 11205 static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, 11206 int rs, int rt, int32_t offset) 11207 { 11208 int bcond_compute = 0; 11209 TCGv t0 = tcg_temp_new(); 11210 TCGv t1 = tcg_temp_new(); 11211 int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0; 11212 11213 if (ctx->hflags & MIPS_HFLAG_BMASK) { 11214 #ifdef MIPS_DEBUG_DISAS 11215 LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" 11216 VADDR_PRIx "\n", ctx->base.pc_next); 11217 #endif 11218 gen_reserved_instruction(ctx); 11219 return; 11220 } 11221 11222 /* Load needed operands and calculate btarget */ 11223 switch (opc) { 11224 /* compact branch */ 11225 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */ 11226 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ 11227 gen_load_gpr(t0, rs); 11228 gen_load_gpr(t1, rt); 11229 bcond_compute = 1; 11230 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11231 if (rs <= rt && rs == 0) { 11232 /* OPC_BEQZALC, OPC_BNEZALC */ 11233 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11234 } 11235 break; 11236 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */ 11237 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */ 11238 gen_load_gpr(t0, rs); 11239 gen_load_gpr(t1, rt); 11240 bcond_compute = 1; 11241 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11242 break; 11243 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */ 11244 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */ 11245 if (rs == 0 || rs == rt) { 11246 /* OPC_BLEZALC, OPC_BGEZALC */ 11247 /* OPC_BGTZALC, OPC_BLTZALC */ 11248 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11249 } 11250 gen_load_gpr(t0, rs); 11251 gen_load_gpr(t1, rt); 11252 bcond_compute = 1; 11253 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11254 break; 11255 case OPC_BC: 11256 case OPC_BALC: 11257 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11258 break; 11259 case OPC_BEQZC: 11260 case OPC_BNEZC: 11261 if (rs != 0) { 11262 /* OPC_BEQZC, OPC_BNEZC */ 11263 gen_load_gpr(t0, rs); 11264 bcond_compute = 1; 11265 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); 11266 } else { 11267 /* OPC_JIC, OPC_JIALC */ 11268 TCGv tbase = tcg_temp_new(); 11269 TCGv toffset = tcg_constant_tl(offset); 11270 11271 gen_load_gpr(tbase, rt); 11272 gen_op_addr_add(ctx, btarget, tbase, toffset); 11273 } 11274 break; 11275 default: 11276 MIPS_INVAL("Compact branch/jump"); 11277 gen_reserved_instruction(ctx); 11278 return; 11279 } 11280 11281 if (bcond_compute == 0) { 11282 /* Unconditional compact branch */ 11283 switch (opc) { 11284 case OPC_JIALC: 11285 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11286 /* Fallthrough */ 11287 case OPC_JIC: 11288 ctx->hflags |= MIPS_HFLAG_BR; 11289 break; 11290 case OPC_BALC: 11291 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); 11292 /* Fallthrough */ 11293 case OPC_BC: 11294 ctx->hflags |= MIPS_HFLAG_B; 11295 break; 11296 default: 11297 MIPS_INVAL("Compact branch/jump"); 11298 gen_reserved_instruction(ctx); 11299 return; 11300 } 11301 11302 /* Generating branch here as compact branches don't have delay slot */ 11303 gen_branch(ctx, 4); 11304 } else { 11305 /* Conditional compact branch */ 11306 TCGLabel *fs = gen_new_label(); 11307 save_cpu_state(ctx, 0); 11308 11309 switch (opc) { 11310 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */ 11311 if (rs == 0 && rt != 0) { 11312 /* OPC_BLEZALC */ 11313 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs); 11314 } else if (rs != 0 && rt != 0 && rs == rt) { 11315 /* OPC_BGEZALC */ 11316 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs); 11317 } else { 11318 /* OPC_BGEUC */ 11319 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs); 11320 } 11321 break; 11322 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */ 11323 if (rs == 0 && rt != 0) { 11324 /* OPC_BGTZALC */ 11325 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs); 11326 } else if (rs != 0 && rt != 0 && rs == rt) { 11327 /* OPC_BLTZALC */ 11328 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs); 11329 } else { 11330 /* OPC_BLTUC */ 11331 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs); 11332 } 11333 break; 11334 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */ 11335 if (rs == 0 && rt != 0) { 11336 /* OPC_BLEZC */ 11337 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs); 11338 } else if (rs != 0 && rt != 0 && rs == rt) { 11339 /* OPC_BGEZC */ 11340 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs); 11341 } else { 11342 /* OPC_BGEC */ 11343 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs); 11344 } 11345 break; 11346 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */ 11347 if (rs == 0 && rt != 0) { 11348 /* OPC_BGTZC */ 11349 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs); 11350 } else if (rs != 0 && rt != 0 && rs == rt) { 11351 /* OPC_BLTZC */ 11352 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs); 11353 } else { 11354 /* OPC_BLTC */ 11355 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs); 11356 } 11357 break; 11358 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */ 11359 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ 11360 if (rs >= rt) { 11361 /* OPC_BOVC, OPC_BNVC */ 11362 TCGv t2 = tcg_temp_new(); 11363 TCGv t3 = tcg_temp_new(); 11364 TCGv t4 = tcg_temp_new(); 11365 TCGv input_overflow = tcg_temp_new(); 11366 11367 gen_load_gpr(t0, rs); 11368 gen_load_gpr(t1, rt); 11369 tcg_gen_ext32s_tl(t2, t0); 11370 tcg_gen_setcond_tl(TCG_COND_NE, input_overflow, t2, t0); 11371 tcg_gen_ext32s_tl(t3, t1); 11372 tcg_gen_setcond_tl(TCG_COND_NE, t4, t3, t1); 11373 tcg_gen_or_tl(input_overflow, input_overflow, t4); 11374 11375 tcg_gen_add_tl(t4, t2, t3); 11376 tcg_gen_ext32s_tl(t4, t4); 11377 tcg_gen_xor_tl(t2, t2, t3); 11378 tcg_gen_xor_tl(t3, t4, t3); 11379 tcg_gen_andc_tl(t2, t3, t2); 11380 tcg_gen_setcondi_tl(TCG_COND_LT, t4, t2, 0); 11381 tcg_gen_or_tl(t4, t4, input_overflow); 11382 if (opc == OPC_BOVC) { 11383 /* OPC_BOVC */ 11384 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t4, 0, fs); 11385 } else { 11386 /* OPC_BNVC */ 11387 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0, fs); 11388 } 11389 } else if (rs < rt && rs == 0) { 11390 /* OPC_BEQZALC, OPC_BNEZALC */ 11391 if (opc == OPC_BEQZALC) { 11392 /* OPC_BEQZALC */ 11393 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t1, 0, fs); 11394 } else { 11395 /* OPC_BNEZALC */ 11396 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t1, 0, fs); 11397 } 11398 } else { 11399 /* OPC_BEQC, OPC_BNEC */ 11400 if (opc == OPC_BEQC) { 11401 /* OPC_BEQC */ 11402 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs); 11403 } else { 11404 /* OPC_BNEC */ 11405 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs); 11406 } 11407 } 11408 break; 11409 case OPC_BEQZC: 11410 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t0, 0, fs); 11411 break; 11412 case OPC_BNEZC: 11413 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t0, 0, fs); 11414 break; 11415 default: 11416 MIPS_INVAL("Compact conditional branch/jump"); 11417 gen_reserved_instruction(ctx); 11418 return; 11419 } 11420 11421 /* Generating branch here as compact branches don't have delay slot */ 11422 gen_goto_tb(ctx, 1, ctx->btarget); 11423 gen_set_label(fs); 11424 11425 ctx->hflags |= MIPS_HFLAG_FBNSLOT; 11426 } 11427 } 11428 11429 void gen_addiupc(DisasContext *ctx, int rx, int imm, 11430 int is_64_bit, int extended) 11431 { 11432 TCGv t0; 11433 11434 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { 11435 gen_reserved_instruction(ctx); 11436 return; 11437 } 11438 11439 t0 = tcg_temp_new(); 11440 11441 tcg_gen_movi_tl(t0, pc_relative_pc(ctx)); 11442 tcg_gen_addi_tl(cpu_gpr[rx], t0, imm); 11443 if (!is_64_bit) { 11444 tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); 11445 } 11446 } 11447 11448 static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base, 11449 int16_t offset) 11450 { 11451 TCGv_i32 t0 = tcg_constant_i32(op); 11452 TCGv t1 = tcg_temp_new(); 11453 gen_base_offset_addr(ctx, t1, base, offset); 11454 gen_helper_cache(tcg_env, t1, t0); 11455 } 11456 11457 static inline bool is_uhi(DisasContext *ctx, int sdbbp_code) 11458 { 11459 #ifdef CONFIG_USER_ONLY 11460 return false; 11461 #else 11462 bool is_user = (ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM; 11463 return semihosting_enabled(is_user) && sdbbp_code == 1; 11464 #endif 11465 } 11466 11467 void gen_ldxs(DisasContext *ctx, int base, int index, int rd) 11468 { 11469 TCGv t0 = tcg_temp_new(); 11470 TCGv t1 = tcg_temp_new(); 11471 11472 gen_load_gpr(t0, base); 11473 11474 if (index != 0) { 11475 gen_load_gpr(t1, index); 11476 tcg_gen_shli_tl(t1, t1, 2); 11477 gen_op_addr_add(ctx, t0, t1, t0); 11478 } 11479 11480 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); 11481 gen_store_gpr(t1, rd); 11482 } 11483 11484 static void gen_sync(int stype) 11485 { 11486 TCGBar tcg_mo = TCG_BAR_SC; 11487 11488 switch (stype) { 11489 case 0x4: /* SYNC_WMB */ 11490 tcg_mo |= TCG_MO_ST_ST; 11491 break; 11492 case 0x10: /* SYNC_MB */ 11493 tcg_mo |= TCG_MO_ALL; 11494 break; 11495 case 0x11: /* SYNC_ACQUIRE */ 11496 tcg_mo |= TCG_MO_LD_LD | TCG_MO_LD_ST; 11497 break; 11498 case 0x12: /* SYNC_RELEASE */ 11499 tcg_mo |= TCG_MO_ST_ST | TCG_MO_LD_ST; 11500 break; 11501 case 0x13: /* SYNC_RMB */ 11502 tcg_mo |= TCG_MO_LD_LD; 11503 break; 11504 default: 11505 tcg_mo |= TCG_MO_ALL; 11506 break; 11507 } 11508 11509 tcg_gen_mb(tcg_mo); 11510 } 11511 11512 /* ISA extensions (ASEs) */ 11513 11514 /* MIPS16 extension to MIPS32 */ 11515 #include "mips16e_translate.c.inc" 11516 11517 /* microMIPS extension to MIPS32/MIPS64 */ 11518 11519 /* 11520 * Values for microMIPS fmt field. Variable-width, depending on which 11521 * formats the instruction supports. 11522 */ 11523 enum { 11524 FMT_SD_S = 0, 11525 FMT_SD_D = 1, 11526 11527 FMT_SDPS_S = 0, 11528 FMT_SDPS_D = 1, 11529 FMT_SDPS_PS = 2, 11530 11531 FMT_SWL_S = 0, 11532 FMT_SWL_W = 1, 11533 FMT_SWL_L = 2, 11534 11535 FMT_DWL_D = 0, 11536 FMT_DWL_W = 1, 11537 FMT_DWL_L = 2 11538 }; 11539 11540 #include "micromips_translate.c.inc" 11541 11542 #include "nanomips_translate.c.inc" 11543 11544 /* MIPSDSP functions. */ 11545 11546 /* Indexed load is not for DSP only */ 11547 static void gen_mips_lx(DisasContext *ctx, uint32_t opc, 11548 int rd, int base, int offset) 11549 { 11550 TCGv t0; 11551 11552 if (!(ctx->insn_flags & INSN_OCTEON)) { 11553 check_dsp(ctx); 11554 } 11555 t0 = tcg_temp_new(); 11556 11557 if (base == 0) { 11558 gen_load_gpr(t0, offset); 11559 } else if (offset == 0) { 11560 gen_load_gpr(t0, base); 11561 } else { 11562 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]); 11563 } 11564 11565 switch (opc) { 11566 case OPC_LBUX: 11567 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB); 11568 gen_store_gpr(t0, rd); 11569 break; 11570 case OPC_LHX: 11571 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW); 11572 gen_store_gpr(t0, rd); 11573 break; 11574 case OPC_LWX: 11575 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); 11576 gen_store_gpr(t0, rd); 11577 break; 11578 #if defined(TARGET_MIPS64) 11579 case OPC_LDX: 11580 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ); 11581 gen_store_gpr(t0, rd); 11582 break; 11583 #endif 11584 } 11585 } 11586 11587 static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2, 11588 int ret, int v1, int v2) 11589 { 11590 TCGv v1_t; 11591 TCGv v2_t; 11592 11593 if (ret == 0) { 11594 /* Treat as NOP. */ 11595 return; 11596 } 11597 11598 v1_t = tcg_temp_new(); 11599 v2_t = tcg_temp_new(); 11600 11601 gen_load_gpr(v1_t, v1); 11602 gen_load_gpr(v2_t, v2); 11603 11604 switch (op1) { 11605 /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */ 11606 case OPC_MULT_G_2E: 11607 check_dsp_r2(ctx); 11608 switch (op2) { 11609 case OPC_ADDUH_QB: 11610 gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t); 11611 break; 11612 case OPC_ADDUH_R_QB: 11613 gen_helper_adduh_r_qb(cpu_gpr[ret], v1_t, v2_t); 11614 break; 11615 case OPC_ADDQH_PH: 11616 gen_helper_addqh_ph(cpu_gpr[ret], v1_t, v2_t); 11617 break; 11618 case OPC_ADDQH_R_PH: 11619 gen_helper_addqh_r_ph(cpu_gpr[ret], v1_t, v2_t); 11620 break; 11621 case OPC_ADDQH_W: 11622 gen_helper_addqh_w(cpu_gpr[ret], v1_t, v2_t); 11623 break; 11624 case OPC_ADDQH_R_W: 11625 gen_helper_addqh_r_w(cpu_gpr[ret], v1_t, v2_t); 11626 break; 11627 case OPC_SUBUH_QB: 11628 gen_helper_subuh_qb(cpu_gpr[ret], v1_t, v2_t); 11629 break; 11630 case OPC_SUBUH_R_QB: 11631 gen_helper_subuh_r_qb(cpu_gpr[ret], v1_t, v2_t); 11632 break; 11633 case OPC_SUBQH_PH: 11634 gen_helper_subqh_ph(cpu_gpr[ret], v1_t, v2_t); 11635 break; 11636 case OPC_SUBQH_R_PH: 11637 gen_helper_subqh_r_ph(cpu_gpr[ret], v1_t, v2_t); 11638 break; 11639 case OPC_SUBQH_W: 11640 gen_helper_subqh_w(cpu_gpr[ret], v1_t, v2_t); 11641 break; 11642 case OPC_SUBQH_R_W: 11643 gen_helper_subqh_r_w(cpu_gpr[ret], v1_t, v2_t); 11644 break; 11645 } 11646 break; 11647 case OPC_ABSQ_S_PH_DSP: 11648 switch (op2) { 11649 case OPC_ABSQ_S_QB: 11650 check_dsp_r2(ctx); 11651 gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, tcg_env); 11652 break; 11653 case OPC_ABSQ_S_PH: 11654 check_dsp(ctx); 11655 gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, tcg_env); 11656 break; 11657 case OPC_ABSQ_S_W: 11658 check_dsp(ctx); 11659 gen_helper_absq_s_w(cpu_gpr[ret], v2_t, tcg_env); 11660 break; 11661 case OPC_PRECEQ_W_PHL: 11662 check_dsp(ctx); 11663 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFF0000); 11664 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 11665 break; 11666 case OPC_PRECEQ_W_PHR: 11667 check_dsp(ctx); 11668 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0x0000FFFF); 11669 tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 16); 11670 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 11671 break; 11672 case OPC_PRECEQU_PH_QBL: 11673 check_dsp(ctx); 11674 gen_helper_precequ_ph_qbl(cpu_gpr[ret], v2_t); 11675 break; 11676 case OPC_PRECEQU_PH_QBR: 11677 check_dsp(ctx); 11678 gen_helper_precequ_ph_qbr(cpu_gpr[ret], v2_t); 11679 break; 11680 case OPC_PRECEQU_PH_QBLA: 11681 check_dsp(ctx); 11682 gen_helper_precequ_ph_qbla(cpu_gpr[ret], v2_t); 11683 break; 11684 case OPC_PRECEQU_PH_QBRA: 11685 check_dsp(ctx); 11686 gen_helper_precequ_ph_qbra(cpu_gpr[ret], v2_t); 11687 break; 11688 case OPC_PRECEU_PH_QBL: 11689 check_dsp(ctx); 11690 gen_helper_preceu_ph_qbl(cpu_gpr[ret], v2_t); 11691 break; 11692 case OPC_PRECEU_PH_QBR: 11693 check_dsp(ctx); 11694 gen_helper_preceu_ph_qbr(cpu_gpr[ret], v2_t); 11695 break; 11696 case OPC_PRECEU_PH_QBLA: 11697 check_dsp(ctx); 11698 gen_helper_preceu_ph_qbla(cpu_gpr[ret], v2_t); 11699 break; 11700 case OPC_PRECEU_PH_QBRA: 11701 check_dsp(ctx); 11702 gen_helper_preceu_ph_qbra(cpu_gpr[ret], v2_t); 11703 break; 11704 } 11705 break; 11706 case OPC_ADDU_QB_DSP: 11707 switch (op2) { 11708 case OPC_ADDQ_PH: 11709 check_dsp(ctx); 11710 gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11711 break; 11712 case OPC_ADDQ_S_PH: 11713 check_dsp(ctx); 11714 gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11715 break; 11716 case OPC_ADDQ_S_W: 11717 check_dsp(ctx); 11718 gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11719 break; 11720 case OPC_ADDU_QB: 11721 check_dsp(ctx); 11722 gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11723 break; 11724 case OPC_ADDU_S_QB: 11725 check_dsp(ctx); 11726 gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11727 break; 11728 case OPC_ADDU_PH: 11729 check_dsp_r2(ctx); 11730 gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11731 break; 11732 case OPC_ADDU_S_PH: 11733 check_dsp_r2(ctx); 11734 gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11735 break; 11736 case OPC_SUBQ_PH: 11737 check_dsp(ctx); 11738 gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11739 break; 11740 case OPC_SUBQ_S_PH: 11741 check_dsp(ctx); 11742 gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11743 break; 11744 case OPC_SUBQ_S_W: 11745 check_dsp(ctx); 11746 gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11747 break; 11748 case OPC_SUBU_QB: 11749 check_dsp(ctx); 11750 gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11751 break; 11752 case OPC_SUBU_S_QB: 11753 check_dsp(ctx); 11754 gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11755 break; 11756 case OPC_SUBU_PH: 11757 check_dsp_r2(ctx); 11758 gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11759 break; 11760 case OPC_SUBU_S_PH: 11761 check_dsp_r2(ctx); 11762 gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11763 break; 11764 case OPC_ADDSC: 11765 check_dsp(ctx); 11766 gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11767 break; 11768 case OPC_ADDWC: 11769 check_dsp(ctx); 11770 gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11771 break; 11772 case OPC_MODSUB: 11773 check_dsp(ctx); 11774 gen_helper_modsub(cpu_gpr[ret], v1_t, v2_t); 11775 break; 11776 case OPC_RADDU_W_QB: 11777 check_dsp(ctx); 11778 gen_helper_raddu_w_qb(cpu_gpr[ret], v1_t); 11779 break; 11780 } 11781 break; 11782 case OPC_CMPU_EQ_QB_DSP: 11783 switch (op2) { 11784 case OPC_PRECR_QB_PH: 11785 check_dsp_r2(ctx); 11786 gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t); 11787 break; 11788 case OPC_PRECRQ_QB_PH: 11789 check_dsp(ctx); 11790 gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t); 11791 break; 11792 case OPC_PRECR_SRA_PH_W: 11793 check_dsp_r2(ctx); 11794 { 11795 TCGv_i32 sa_t = tcg_constant_i32(v2); 11796 gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t, 11797 cpu_gpr[ret]); 11798 break; 11799 } 11800 case OPC_PRECR_SRA_R_PH_W: 11801 check_dsp_r2(ctx); 11802 { 11803 TCGv_i32 sa_t = tcg_constant_i32(v2); 11804 gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t, 11805 cpu_gpr[ret]); 11806 break; 11807 } 11808 case OPC_PRECRQ_PH_W: 11809 check_dsp(ctx); 11810 gen_helper_precrq_ph_w(cpu_gpr[ret], v1_t, v2_t); 11811 break; 11812 case OPC_PRECRQ_RS_PH_W: 11813 check_dsp(ctx); 11814 gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11815 break; 11816 case OPC_PRECRQU_S_QB_PH: 11817 check_dsp(ctx); 11818 gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11819 break; 11820 } 11821 break; 11822 #ifdef TARGET_MIPS64 11823 case OPC_ABSQ_S_QH_DSP: 11824 switch (op2) { 11825 case OPC_PRECEQ_L_PWL: 11826 check_dsp(ctx); 11827 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFFFFFF00000000ull); 11828 break; 11829 case OPC_PRECEQ_L_PWR: 11830 check_dsp(ctx); 11831 tcg_gen_shli_tl(cpu_gpr[ret], v2_t, 32); 11832 break; 11833 case OPC_PRECEQ_PW_QHL: 11834 check_dsp(ctx); 11835 gen_helper_preceq_pw_qhl(cpu_gpr[ret], v2_t); 11836 break; 11837 case OPC_PRECEQ_PW_QHR: 11838 check_dsp(ctx); 11839 gen_helper_preceq_pw_qhr(cpu_gpr[ret], v2_t); 11840 break; 11841 case OPC_PRECEQ_PW_QHLA: 11842 check_dsp(ctx); 11843 gen_helper_preceq_pw_qhla(cpu_gpr[ret], v2_t); 11844 break; 11845 case OPC_PRECEQ_PW_QHRA: 11846 check_dsp(ctx); 11847 gen_helper_preceq_pw_qhra(cpu_gpr[ret], v2_t); 11848 break; 11849 case OPC_PRECEQU_QH_OBL: 11850 check_dsp(ctx); 11851 gen_helper_precequ_qh_obl(cpu_gpr[ret], v2_t); 11852 break; 11853 case OPC_PRECEQU_QH_OBR: 11854 check_dsp(ctx); 11855 gen_helper_precequ_qh_obr(cpu_gpr[ret], v2_t); 11856 break; 11857 case OPC_PRECEQU_QH_OBLA: 11858 check_dsp(ctx); 11859 gen_helper_precequ_qh_obla(cpu_gpr[ret], v2_t); 11860 break; 11861 case OPC_PRECEQU_QH_OBRA: 11862 check_dsp(ctx); 11863 gen_helper_precequ_qh_obra(cpu_gpr[ret], v2_t); 11864 break; 11865 case OPC_PRECEU_QH_OBL: 11866 check_dsp(ctx); 11867 gen_helper_preceu_qh_obl(cpu_gpr[ret], v2_t); 11868 break; 11869 case OPC_PRECEU_QH_OBR: 11870 check_dsp(ctx); 11871 gen_helper_preceu_qh_obr(cpu_gpr[ret], v2_t); 11872 break; 11873 case OPC_PRECEU_QH_OBLA: 11874 check_dsp(ctx); 11875 gen_helper_preceu_qh_obla(cpu_gpr[ret], v2_t); 11876 break; 11877 case OPC_PRECEU_QH_OBRA: 11878 check_dsp(ctx); 11879 gen_helper_preceu_qh_obra(cpu_gpr[ret], v2_t); 11880 break; 11881 case OPC_ABSQ_S_OB: 11882 check_dsp_r2(ctx); 11883 gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, tcg_env); 11884 break; 11885 case OPC_ABSQ_S_PW: 11886 check_dsp(ctx); 11887 gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, tcg_env); 11888 break; 11889 case OPC_ABSQ_S_QH: 11890 check_dsp(ctx); 11891 gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, tcg_env); 11892 break; 11893 } 11894 break; 11895 case OPC_ADDU_OB_DSP: 11896 switch (op2) { 11897 case OPC_RADDU_L_OB: 11898 check_dsp(ctx); 11899 gen_helper_raddu_l_ob(cpu_gpr[ret], v1_t); 11900 break; 11901 case OPC_SUBQ_PW: 11902 check_dsp(ctx); 11903 gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11904 break; 11905 case OPC_SUBQ_S_PW: 11906 check_dsp(ctx); 11907 gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11908 break; 11909 case OPC_SUBQ_QH: 11910 check_dsp(ctx); 11911 gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11912 break; 11913 case OPC_SUBQ_S_QH: 11914 check_dsp(ctx); 11915 gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11916 break; 11917 case OPC_SUBU_OB: 11918 check_dsp(ctx); 11919 gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11920 break; 11921 case OPC_SUBU_S_OB: 11922 check_dsp(ctx); 11923 gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11924 break; 11925 case OPC_SUBU_QH: 11926 check_dsp_r2(ctx); 11927 gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11928 break; 11929 case OPC_SUBU_S_QH: 11930 check_dsp_r2(ctx); 11931 gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11932 break; 11933 case OPC_SUBUH_OB: 11934 check_dsp_r2(ctx); 11935 gen_helper_subuh_ob(cpu_gpr[ret], v1_t, v2_t); 11936 break; 11937 case OPC_SUBUH_R_OB: 11938 check_dsp_r2(ctx); 11939 gen_helper_subuh_r_ob(cpu_gpr[ret], v1_t, v2_t); 11940 break; 11941 case OPC_ADDQ_PW: 11942 check_dsp(ctx); 11943 gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11944 break; 11945 case OPC_ADDQ_S_PW: 11946 check_dsp(ctx); 11947 gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11948 break; 11949 case OPC_ADDQ_QH: 11950 check_dsp(ctx); 11951 gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11952 break; 11953 case OPC_ADDQ_S_QH: 11954 check_dsp(ctx); 11955 gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11956 break; 11957 case OPC_ADDU_OB: 11958 check_dsp(ctx); 11959 gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11960 break; 11961 case OPC_ADDU_S_OB: 11962 check_dsp(ctx); 11963 gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11964 break; 11965 case OPC_ADDU_QH: 11966 check_dsp_r2(ctx); 11967 gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11968 break; 11969 case OPC_ADDU_S_QH: 11970 check_dsp_r2(ctx); 11971 gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 11972 break; 11973 case OPC_ADDUH_OB: 11974 check_dsp_r2(ctx); 11975 gen_helper_adduh_ob(cpu_gpr[ret], v1_t, v2_t); 11976 break; 11977 case OPC_ADDUH_R_OB: 11978 check_dsp_r2(ctx); 11979 gen_helper_adduh_r_ob(cpu_gpr[ret], v1_t, v2_t); 11980 break; 11981 } 11982 break; 11983 case OPC_CMPU_EQ_OB_DSP: 11984 switch (op2) { 11985 case OPC_PRECR_OB_QH: 11986 check_dsp_r2(ctx); 11987 gen_helper_precr_ob_qh(cpu_gpr[ret], v1_t, v2_t); 11988 break; 11989 case OPC_PRECR_SRA_QH_PW: 11990 check_dsp_r2(ctx); 11991 { 11992 TCGv_i32 ret_t = tcg_constant_i32(ret); 11993 gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t); 11994 break; 11995 } 11996 case OPC_PRECR_SRA_R_QH_PW: 11997 check_dsp_r2(ctx); 11998 { 11999 TCGv_i32 sa_v = tcg_constant_i32(ret); 12000 gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v); 12001 break; 12002 } 12003 case OPC_PRECRQ_OB_QH: 12004 check_dsp(ctx); 12005 gen_helper_precrq_ob_qh(cpu_gpr[ret], v1_t, v2_t); 12006 break; 12007 case OPC_PRECRQ_PW_L: 12008 check_dsp(ctx); 12009 gen_helper_precrq_pw_l(cpu_gpr[ret], v1_t, v2_t); 12010 break; 12011 case OPC_PRECRQ_QH_PW: 12012 check_dsp(ctx); 12013 gen_helper_precrq_qh_pw(cpu_gpr[ret], v1_t, v2_t); 12014 break; 12015 case OPC_PRECRQ_RS_QH_PW: 12016 check_dsp(ctx); 12017 gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12018 break; 12019 case OPC_PRECRQU_S_OB_QH: 12020 check_dsp(ctx); 12021 gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12022 break; 12023 } 12024 break; 12025 #endif 12026 } 12027 } 12028 12029 static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, 12030 int ret, int v1, int v2) 12031 { 12032 uint32_t op2; 12033 TCGv t0; 12034 TCGv v1_t; 12035 TCGv v2_t; 12036 12037 if (ret == 0) { 12038 /* Treat as NOP. */ 12039 return; 12040 } 12041 12042 t0 = tcg_temp_new(); 12043 v1_t = tcg_temp_new(); 12044 v2_t = tcg_temp_new(); 12045 12046 tcg_gen_movi_tl(t0, v1); 12047 gen_load_gpr(v1_t, v1); 12048 gen_load_gpr(v2_t, v2); 12049 12050 switch (opc) { 12051 case OPC_SHLL_QB_DSP: 12052 { 12053 op2 = MASK_SHLL_QB(ctx->opcode); 12054 switch (op2) { 12055 case OPC_SHLL_QB: 12056 check_dsp(ctx); 12057 gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, tcg_env); 12058 break; 12059 case OPC_SHLLV_QB: 12060 check_dsp(ctx); 12061 gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12062 break; 12063 case OPC_SHLL_PH: 12064 check_dsp(ctx); 12065 gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, tcg_env); 12066 break; 12067 case OPC_SHLLV_PH: 12068 check_dsp(ctx); 12069 gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12070 break; 12071 case OPC_SHLL_S_PH: 12072 check_dsp(ctx); 12073 gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, tcg_env); 12074 break; 12075 case OPC_SHLLV_S_PH: 12076 check_dsp(ctx); 12077 gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12078 break; 12079 case OPC_SHLL_S_W: 12080 check_dsp(ctx); 12081 gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, tcg_env); 12082 break; 12083 case OPC_SHLLV_S_W: 12084 check_dsp(ctx); 12085 gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12086 break; 12087 case OPC_SHRL_QB: 12088 check_dsp(ctx); 12089 gen_helper_shrl_qb(cpu_gpr[ret], t0, v2_t); 12090 break; 12091 case OPC_SHRLV_QB: 12092 check_dsp(ctx); 12093 gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t); 12094 break; 12095 case OPC_SHRL_PH: 12096 check_dsp_r2(ctx); 12097 gen_helper_shrl_ph(cpu_gpr[ret], t0, v2_t); 12098 break; 12099 case OPC_SHRLV_PH: 12100 check_dsp_r2(ctx); 12101 gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t); 12102 break; 12103 case OPC_SHRA_QB: 12104 check_dsp_r2(ctx); 12105 gen_helper_shra_qb(cpu_gpr[ret], t0, v2_t); 12106 break; 12107 case OPC_SHRA_R_QB: 12108 check_dsp_r2(ctx); 12109 gen_helper_shra_r_qb(cpu_gpr[ret], t0, v2_t); 12110 break; 12111 case OPC_SHRAV_QB: 12112 check_dsp_r2(ctx); 12113 gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t); 12114 break; 12115 case OPC_SHRAV_R_QB: 12116 check_dsp_r2(ctx); 12117 gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t); 12118 break; 12119 case OPC_SHRA_PH: 12120 check_dsp(ctx); 12121 gen_helper_shra_ph(cpu_gpr[ret], t0, v2_t); 12122 break; 12123 case OPC_SHRA_R_PH: 12124 check_dsp(ctx); 12125 gen_helper_shra_r_ph(cpu_gpr[ret], t0, v2_t); 12126 break; 12127 case OPC_SHRAV_PH: 12128 check_dsp(ctx); 12129 gen_helper_shra_ph(cpu_gpr[ret], v1_t, v2_t); 12130 break; 12131 case OPC_SHRAV_R_PH: 12132 check_dsp(ctx); 12133 gen_helper_shra_r_ph(cpu_gpr[ret], v1_t, v2_t); 12134 break; 12135 case OPC_SHRA_R_W: 12136 check_dsp(ctx); 12137 gen_helper_shra_r_w(cpu_gpr[ret], t0, v2_t); 12138 break; 12139 case OPC_SHRAV_R_W: 12140 check_dsp(ctx); 12141 gen_helper_shra_r_w(cpu_gpr[ret], v1_t, v2_t); 12142 break; 12143 default: /* Invalid */ 12144 MIPS_INVAL("MASK SHLL.QB"); 12145 gen_reserved_instruction(ctx); 12146 break; 12147 } 12148 break; 12149 } 12150 #ifdef TARGET_MIPS64 12151 case OPC_SHLL_OB_DSP: 12152 op2 = MASK_SHLL_OB(ctx->opcode); 12153 switch (op2) { 12154 case OPC_SHLL_PW: 12155 check_dsp(ctx); 12156 gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, tcg_env); 12157 break; 12158 case OPC_SHLLV_PW: 12159 check_dsp(ctx); 12160 gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, tcg_env); 12161 break; 12162 case OPC_SHLL_S_PW: 12163 check_dsp(ctx); 12164 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, tcg_env); 12165 break; 12166 case OPC_SHLLV_S_PW: 12167 check_dsp(ctx); 12168 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, tcg_env); 12169 break; 12170 case OPC_SHLL_OB: 12171 check_dsp(ctx); 12172 gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, tcg_env); 12173 break; 12174 case OPC_SHLLV_OB: 12175 check_dsp(ctx); 12176 gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, tcg_env); 12177 break; 12178 case OPC_SHLL_QH: 12179 check_dsp(ctx); 12180 gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, tcg_env); 12181 break; 12182 case OPC_SHLLV_QH: 12183 check_dsp(ctx); 12184 gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, tcg_env); 12185 break; 12186 case OPC_SHLL_S_QH: 12187 check_dsp(ctx); 12188 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, tcg_env); 12189 break; 12190 case OPC_SHLLV_S_QH: 12191 check_dsp(ctx); 12192 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, tcg_env); 12193 break; 12194 case OPC_SHRA_OB: 12195 check_dsp_r2(ctx); 12196 gen_helper_shra_ob(cpu_gpr[ret], v2_t, t0); 12197 break; 12198 case OPC_SHRAV_OB: 12199 check_dsp_r2(ctx); 12200 gen_helper_shra_ob(cpu_gpr[ret], v2_t, v1_t); 12201 break; 12202 case OPC_SHRA_R_OB: 12203 check_dsp_r2(ctx); 12204 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, t0); 12205 break; 12206 case OPC_SHRAV_R_OB: 12207 check_dsp_r2(ctx); 12208 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, v1_t); 12209 break; 12210 case OPC_SHRA_PW: 12211 check_dsp(ctx); 12212 gen_helper_shra_pw(cpu_gpr[ret], v2_t, t0); 12213 break; 12214 case OPC_SHRAV_PW: 12215 check_dsp(ctx); 12216 gen_helper_shra_pw(cpu_gpr[ret], v2_t, v1_t); 12217 break; 12218 case OPC_SHRA_R_PW: 12219 check_dsp(ctx); 12220 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, t0); 12221 break; 12222 case OPC_SHRAV_R_PW: 12223 check_dsp(ctx); 12224 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, v1_t); 12225 break; 12226 case OPC_SHRA_QH: 12227 check_dsp(ctx); 12228 gen_helper_shra_qh(cpu_gpr[ret], v2_t, t0); 12229 break; 12230 case OPC_SHRAV_QH: 12231 check_dsp(ctx); 12232 gen_helper_shra_qh(cpu_gpr[ret], v2_t, v1_t); 12233 break; 12234 case OPC_SHRA_R_QH: 12235 check_dsp(ctx); 12236 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, t0); 12237 break; 12238 case OPC_SHRAV_R_QH: 12239 check_dsp(ctx); 12240 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, v1_t); 12241 break; 12242 case OPC_SHRL_OB: 12243 check_dsp(ctx); 12244 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, t0); 12245 break; 12246 case OPC_SHRLV_OB: 12247 check_dsp(ctx); 12248 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, v1_t); 12249 break; 12250 case OPC_SHRL_QH: 12251 check_dsp_r2(ctx); 12252 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, t0); 12253 break; 12254 case OPC_SHRLV_QH: 12255 check_dsp_r2(ctx); 12256 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, v1_t); 12257 break; 12258 default: /* Invalid */ 12259 MIPS_INVAL("MASK SHLL.OB"); 12260 gen_reserved_instruction(ctx); 12261 break; 12262 } 12263 break; 12264 #endif 12265 } 12266 } 12267 12268 static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2, 12269 int ret, int v1, int v2, int check_ret) 12270 { 12271 TCGv_i32 t0; 12272 TCGv v1_t; 12273 TCGv v2_t; 12274 12275 if ((ret == 0) && (check_ret == 1)) { 12276 /* Treat as NOP. */ 12277 return; 12278 } 12279 12280 t0 = tcg_temp_new_i32(); 12281 v1_t = tcg_temp_new(); 12282 v2_t = tcg_temp_new(); 12283 12284 tcg_gen_movi_i32(t0, ret); 12285 gen_load_gpr(v1_t, v1); 12286 gen_load_gpr(v2_t, v2); 12287 12288 switch (op1) { 12289 /* 12290 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have 12291 * the same mask and op1. 12292 */ 12293 case OPC_MULT_G_2E: 12294 check_dsp_r2(ctx); 12295 switch (op2) { 12296 case OPC_MUL_PH: 12297 gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12298 break; 12299 case OPC_MUL_S_PH: 12300 gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12301 break; 12302 case OPC_MULQ_S_W: 12303 gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12304 break; 12305 case OPC_MULQ_RS_W: 12306 gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12307 break; 12308 } 12309 break; 12310 case OPC_DPA_W_PH_DSP: 12311 switch (op2) { 12312 case OPC_DPAU_H_QBL: 12313 check_dsp(ctx); 12314 gen_helper_dpau_h_qbl(t0, v1_t, v2_t, tcg_env); 12315 break; 12316 case OPC_DPAU_H_QBR: 12317 check_dsp(ctx); 12318 gen_helper_dpau_h_qbr(t0, v1_t, v2_t, tcg_env); 12319 break; 12320 case OPC_DPSU_H_QBL: 12321 check_dsp(ctx); 12322 gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, tcg_env); 12323 break; 12324 case OPC_DPSU_H_QBR: 12325 check_dsp(ctx); 12326 gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, tcg_env); 12327 break; 12328 case OPC_DPA_W_PH: 12329 check_dsp_r2(ctx); 12330 gen_helper_dpa_w_ph(t0, v1_t, v2_t, tcg_env); 12331 break; 12332 case OPC_DPAX_W_PH: 12333 check_dsp_r2(ctx); 12334 gen_helper_dpax_w_ph(t0, v1_t, v2_t, tcg_env); 12335 break; 12336 case OPC_DPAQ_S_W_PH: 12337 check_dsp(ctx); 12338 gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, tcg_env); 12339 break; 12340 case OPC_DPAQX_S_W_PH: 12341 check_dsp_r2(ctx); 12342 gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, tcg_env); 12343 break; 12344 case OPC_DPAQX_SA_W_PH: 12345 check_dsp_r2(ctx); 12346 gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, tcg_env); 12347 break; 12348 case OPC_DPS_W_PH: 12349 check_dsp_r2(ctx); 12350 gen_helper_dps_w_ph(t0, v1_t, v2_t, tcg_env); 12351 break; 12352 case OPC_DPSX_W_PH: 12353 check_dsp_r2(ctx); 12354 gen_helper_dpsx_w_ph(t0, v1_t, v2_t, tcg_env); 12355 break; 12356 case OPC_DPSQ_S_W_PH: 12357 check_dsp(ctx); 12358 gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, tcg_env); 12359 break; 12360 case OPC_DPSQX_S_W_PH: 12361 check_dsp_r2(ctx); 12362 gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, tcg_env); 12363 break; 12364 case OPC_DPSQX_SA_W_PH: 12365 check_dsp_r2(ctx); 12366 gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, tcg_env); 12367 break; 12368 case OPC_MULSAQ_S_W_PH: 12369 check_dsp(ctx); 12370 gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, tcg_env); 12371 break; 12372 case OPC_DPAQ_SA_L_W: 12373 check_dsp(ctx); 12374 gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, tcg_env); 12375 break; 12376 case OPC_DPSQ_SA_L_W: 12377 check_dsp(ctx); 12378 gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, tcg_env); 12379 break; 12380 case OPC_MAQ_S_W_PHL: 12381 check_dsp(ctx); 12382 gen_helper_maq_s_w_phl(t0, v1_t, v2_t, tcg_env); 12383 break; 12384 case OPC_MAQ_S_W_PHR: 12385 check_dsp(ctx); 12386 gen_helper_maq_s_w_phr(t0, v1_t, v2_t, tcg_env); 12387 break; 12388 case OPC_MAQ_SA_W_PHL: 12389 check_dsp(ctx); 12390 gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, tcg_env); 12391 break; 12392 case OPC_MAQ_SA_W_PHR: 12393 check_dsp(ctx); 12394 gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, tcg_env); 12395 break; 12396 case OPC_MULSA_W_PH: 12397 check_dsp_r2(ctx); 12398 gen_helper_mulsa_w_ph(t0, v1_t, v2_t, tcg_env); 12399 break; 12400 } 12401 break; 12402 #ifdef TARGET_MIPS64 12403 case OPC_DPAQ_W_QH_DSP: 12404 { 12405 int ac = ret & 0x03; 12406 tcg_gen_movi_i32(t0, ac); 12407 12408 switch (op2) { 12409 case OPC_DMADD: 12410 check_dsp(ctx); 12411 gen_helper_dmadd(v1_t, v2_t, t0, tcg_env); 12412 break; 12413 case OPC_DMADDU: 12414 check_dsp(ctx); 12415 gen_helper_dmaddu(v1_t, v2_t, t0, tcg_env); 12416 break; 12417 case OPC_DMSUB: 12418 check_dsp(ctx); 12419 gen_helper_dmsub(v1_t, v2_t, t0, tcg_env); 12420 break; 12421 case OPC_DMSUBU: 12422 check_dsp(ctx); 12423 gen_helper_dmsubu(v1_t, v2_t, t0, tcg_env); 12424 break; 12425 case OPC_DPA_W_QH: 12426 check_dsp_r2(ctx); 12427 gen_helper_dpa_w_qh(v1_t, v2_t, t0, tcg_env); 12428 break; 12429 case OPC_DPAQ_S_W_QH: 12430 check_dsp(ctx); 12431 gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, tcg_env); 12432 break; 12433 case OPC_DPAQ_SA_L_PW: 12434 check_dsp(ctx); 12435 gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, tcg_env); 12436 break; 12437 case OPC_DPAU_H_OBL: 12438 check_dsp(ctx); 12439 gen_helper_dpau_h_obl(v1_t, v2_t, t0, tcg_env); 12440 break; 12441 case OPC_DPAU_H_OBR: 12442 check_dsp(ctx); 12443 gen_helper_dpau_h_obr(v1_t, v2_t, t0, tcg_env); 12444 break; 12445 case OPC_DPS_W_QH: 12446 check_dsp_r2(ctx); 12447 gen_helper_dps_w_qh(v1_t, v2_t, t0, tcg_env); 12448 break; 12449 case OPC_DPSQ_S_W_QH: 12450 check_dsp(ctx); 12451 gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, tcg_env); 12452 break; 12453 case OPC_DPSQ_SA_L_PW: 12454 check_dsp(ctx); 12455 gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, tcg_env); 12456 break; 12457 case OPC_DPSU_H_OBL: 12458 check_dsp(ctx); 12459 gen_helper_dpsu_h_obl(v1_t, v2_t, t0, tcg_env); 12460 break; 12461 case OPC_DPSU_H_OBR: 12462 check_dsp(ctx); 12463 gen_helper_dpsu_h_obr(v1_t, v2_t, t0, tcg_env); 12464 break; 12465 case OPC_MAQ_S_L_PWL: 12466 check_dsp(ctx); 12467 gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, tcg_env); 12468 break; 12469 case OPC_MAQ_S_L_PWR: 12470 check_dsp(ctx); 12471 gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, tcg_env); 12472 break; 12473 case OPC_MAQ_S_W_QHLL: 12474 check_dsp(ctx); 12475 gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, tcg_env); 12476 break; 12477 case OPC_MAQ_SA_W_QHLL: 12478 check_dsp(ctx); 12479 gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, tcg_env); 12480 break; 12481 case OPC_MAQ_S_W_QHLR: 12482 check_dsp(ctx); 12483 gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, tcg_env); 12484 break; 12485 case OPC_MAQ_SA_W_QHLR: 12486 check_dsp(ctx); 12487 gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, tcg_env); 12488 break; 12489 case OPC_MAQ_S_W_QHRL: 12490 check_dsp(ctx); 12491 gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, tcg_env); 12492 break; 12493 case OPC_MAQ_SA_W_QHRL: 12494 check_dsp(ctx); 12495 gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, tcg_env); 12496 break; 12497 case OPC_MAQ_S_W_QHRR: 12498 check_dsp(ctx); 12499 gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, tcg_env); 12500 break; 12501 case OPC_MAQ_SA_W_QHRR: 12502 check_dsp(ctx); 12503 gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, tcg_env); 12504 break; 12505 case OPC_MULSAQ_S_L_PW: 12506 check_dsp(ctx); 12507 gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, tcg_env); 12508 break; 12509 case OPC_MULSAQ_S_W_QH: 12510 check_dsp(ctx); 12511 gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, tcg_env); 12512 break; 12513 } 12514 } 12515 break; 12516 #endif 12517 case OPC_ADDU_QB_DSP: 12518 switch (op2) { 12519 case OPC_MULEU_S_PH_QBL: 12520 check_dsp(ctx); 12521 gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12522 break; 12523 case OPC_MULEU_S_PH_QBR: 12524 check_dsp(ctx); 12525 gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12526 break; 12527 case OPC_MULQ_RS_PH: 12528 check_dsp(ctx); 12529 gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12530 break; 12531 case OPC_MULEQ_S_W_PHL: 12532 check_dsp(ctx); 12533 gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12534 break; 12535 case OPC_MULEQ_S_W_PHR: 12536 check_dsp(ctx); 12537 gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12538 break; 12539 case OPC_MULQ_S_PH: 12540 check_dsp_r2(ctx); 12541 gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12542 break; 12543 } 12544 break; 12545 #ifdef TARGET_MIPS64 12546 case OPC_ADDU_OB_DSP: 12547 switch (op2) { 12548 case OPC_MULEQ_S_PW_QHL: 12549 check_dsp(ctx); 12550 gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12551 break; 12552 case OPC_MULEQ_S_PW_QHR: 12553 check_dsp(ctx); 12554 gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12555 break; 12556 case OPC_MULEU_S_QH_OBL: 12557 check_dsp(ctx); 12558 gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12559 break; 12560 case OPC_MULEU_S_QH_OBR: 12561 check_dsp(ctx); 12562 gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12563 break; 12564 case OPC_MULQ_RS_QH: 12565 check_dsp(ctx); 12566 gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12567 break; 12568 } 12569 break; 12570 #endif 12571 } 12572 } 12573 12574 static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, 12575 int ret, int val) 12576 { 12577 int16_t imm; 12578 TCGv t0; 12579 TCGv val_t; 12580 12581 if (ret == 0) { 12582 /* Treat as NOP. */ 12583 return; 12584 } 12585 12586 t0 = tcg_temp_new(); 12587 val_t = tcg_temp_new(); 12588 gen_load_gpr(val_t, val); 12589 12590 switch (op1) { 12591 case OPC_ABSQ_S_PH_DSP: 12592 switch (op2) { 12593 case OPC_BITREV: 12594 check_dsp(ctx); 12595 gen_helper_bitrev(cpu_gpr[ret], val_t); 12596 break; 12597 case OPC_REPL_QB: 12598 check_dsp(ctx); 12599 { 12600 target_long result; 12601 imm = (ctx->opcode >> 16) & 0xFF; 12602 result = (uint32_t)imm << 24 | 12603 (uint32_t)imm << 16 | 12604 (uint32_t)imm << 8 | 12605 (uint32_t)imm; 12606 result = (int32_t)result; 12607 tcg_gen_movi_tl(cpu_gpr[ret], result); 12608 } 12609 break; 12610 case OPC_REPLV_QB: 12611 check_dsp(ctx); 12612 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t); 12613 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8); 12614 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12615 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12616 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12617 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 12618 break; 12619 case OPC_REPL_PH: 12620 check_dsp(ctx); 12621 { 12622 imm = (ctx->opcode >> 16) & 0x03FF; 12623 imm = (int16_t)(imm << 6) >> 6; 12624 tcg_gen_movi_tl(cpu_gpr[ret], \ 12625 (target_long)((int32_t)imm << 16 | \ 12626 (uint16_t)imm)); 12627 } 12628 break; 12629 case OPC_REPLV_PH: 12630 check_dsp(ctx); 12631 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t); 12632 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12633 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12634 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); 12635 break; 12636 } 12637 break; 12638 #ifdef TARGET_MIPS64 12639 case OPC_ABSQ_S_QH_DSP: 12640 switch (op2) { 12641 case OPC_REPL_OB: 12642 check_dsp(ctx); 12643 { 12644 target_long temp; 12645 12646 imm = (ctx->opcode >> 16) & 0xFF; 12647 temp = ((uint64_t)imm << 8) | (uint64_t)imm; 12648 temp = (temp << 16) | temp; 12649 temp = (temp << 32) | temp; 12650 tcg_gen_movi_tl(cpu_gpr[ret], temp); 12651 break; 12652 } 12653 case OPC_REPL_PW: 12654 check_dsp(ctx); 12655 { 12656 target_long temp; 12657 12658 imm = (ctx->opcode >> 16) & 0x03FF; 12659 imm = (int16_t)(imm << 6) >> 6; 12660 temp = ((target_long)imm << 32) \ 12661 | ((target_long)imm & 0xFFFFFFFF); 12662 tcg_gen_movi_tl(cpu_gpr[ret], temp); 12663 break; 12664 } 12665 case OPC_REPL_QH: 12666 check_dsp(ctx); 12667 { 12668 target_long temp; 12669 12670 imm = (ctx->opcode >> 16) & 0x03FF; 12671 imm = (int16_t)(imm << 6) >> 6; 12672 12673 temp = ((uint64_t)(uint16_t)imm << 48) | 12674 ((uint64_t)(uint16_t)imm << 32) | 12675 ((uint64_t)(uint16_t)imm << 16) | 12676 (uint64_t)(uint16_t)imm; 12677 tcg_gen_movi_tl(cpu_gpr[ret], temp); 12678 break; 12679 } 12680 case OPC_REPLV_OB: 12681 check_dsp(ctx); 12682 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t); 12683 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8); 12684 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12685 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12686 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12687 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); 12688 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12689 break; 12690 case OPC_REPLV_PW: 12691 check_dsp(ctx); 12692 tcg_gen_ext32u_i64(cpu_gpr[ret], val_t); 12693 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); 12694 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12695 break; 12696 case OPC_REPLV_QH: 12697 check_dsp(ctx); 12698 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t); 12699 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); 12700 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12701 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); 12702 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); 12703 break; 12704 } 12705 break; 12706 #endif 12707 } 12708 } 12709 12710 static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, 12711 uint32_t op1, uint32_t op2, 12712 int ret, int v1, int v2, int check_ret) 12713 { 12714 TCGv t1; 12715 TCGv v1_t; 12716 TCGv v2_t; 12717 12718 if ((ret == 0) && (check_ret == 1)) { 12719 /* Treat as NOP. */ 12720 return; 12721 } 12722 12723 t1 = tcg_temp_new(); 12724 v1_t = tcg_temp_new(); 12725 v2_t = tcg_temp_new(); 12726 12727 gen_load_gpr(v1_t, v1); 12728 gen_load_gpr(v2_t, v2); 12729 12730 switch (op1) { 12731 case OPC_CMPU_EQ_QB_DSP: 12732 switch (op2) { 12733 case OPC_CMPU_EQ_QB: 12734 check_dsp(ctx); 12735 gen_helper_cmpu_eq_qb(v1_t, v2_t, tcg_env); 12736 break; 12737 case OPC_CMPU_LT_QB: 12738 check_dsp(ctx); 12739 gen_helper_cmpu_lt_qb(v1_t, v2_t, tcg_env); 12740 break; 12741 case OPC_CMPU_LE_QB: 12742 check_dsp(ctx); 12743 gen_helper_cmpu_le_qb(v1_t, v2_t, tcg_env); 12744 break; 12745 case OPC_CMPGU_EQ_QB: 12746 check_dsp(ctx); 12747 gen_helper_cmpgu_eq_qb(cpu_gpr[ret], v1_t, v2_t); 12748 break; 12749 case OPC_CMPGU_LT_QB: 12750 check_dsp(ctx); 12751 gen_helper_cmpgu_lt_qb(cpu_gpr[ret], v1_t, v2_t); 12752 break; 12753 case OPC_CMPGU_LE_QB: 12754 check_dsp(ctx); 12755 gen_helper_cmpgu_le_qb(cpu_gpr[ret], v1_t, v2_t); 12756 break; 12757 case OPC_CMPGDU_EQ_QB: 12758 check_dsp_r2(ctx); 12759 gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t); 12760 tcg_gen_mov_tl(cpu_gpr[ret], t1); 12761 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); 12762 tcg_gen_shli_tl(t1, t1, 24); 12763 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); 12764 break; 12765 case OPC_CMPGDU_LT_QB: 12766 check_dsp_r2(ctx); 12767 gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t); 12768 tcg_gen_mov_tl(cpu_gpr[ret], t1); 12769 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); 12770 tcg_gen_shli_tl(t1, t1, 24); 12771 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); 12772 break; 12773 case OPC_CMPGDU_LE_QB: 12774 check_dsp_r2(ctx); 12775 gen_helper_cmpgu_le_qb(t1, v1_t, v2_t); 12776 tcg_gen_mov_tl(cpu_gpr[ret], t1); 12777 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); 12778 tcg_gen_shli_tl(t1, t1, 24); 12779 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); 12780 break; 12781 case OPC_CMP_EQ_PH: 12782 check_dsp(ctx); 12783 gen_helper_cmp_eq_ph(v1_t, v2_t, tcg_env); 12784 break; 12785 case OPC_CMP_LT_PH: 12786 check_dsp(ctx); 12787 gen_helper_cmp_lt_ph(v1_t, v2_t, tcg_env); 12788 break; 12789 case OPC_CMP_LE_PH: 12790 check_dsp(ctx); 12791 gen_helper_cmp_le_ph(v1_t, v2_t, tcg_env); 12792 break; 12793 case OPC_PICK_QB: 12794 check_dsp(ctx); 12795 gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12796 break; 12797 case OPC_PICK_PH: 12798 check_dsp(ctx); 12799 gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12800 break; 12801 case OPC_PACKRL_PH: 12802 check_dsp(ctx); 12803 gen_helper_packrl_ph(cpu_gpr[ret], v1_t, v2_t); 12804 break; 12805 } 12806 break; 12807 #ifdef TARGET_MIPS64 12808 case OPC_CMPU_EQ_OB_DSP: 12809 switch (op2) { 12810 case OPC_CMP_EQ_PW: 12811 check_dsp(ctx); 12812 gen_helper_cmp_eq_pw(v1_t, v2_t, tcg_env); 12813 break; 12814 case OPC_CMP_LT_PW: 12815 check_dsp(ctx); 12816 gen_helper_cmp_lt_pw(v1_t, v2_t, tcg_env); 12817 break; 12818 case OPC_CMP_LE_PW: 12819 check_dsp(ctx); 12820 gen_helper_cmp_le_pw(v1_t, v2_t, tcg_env); 12821 break; 12822 case OPC_CMP_EQ_QH: 12823 check_dsp(ctx); 12824 gen_helper_cmp_eq_qh(v1_t, v2_t, tcg_env); 12825 break; 12826 case OPC_CMP_LT_QH: 12827 check_dsp(ctx); 12828 gen_helper_cmp_lt_qh(v1_t, v2_t, tcg_env); 12829 break; 12830 case OPC_CMP_LE_QH: 12831 check_dsp(ctx); 12832 gen_helper_cmp_le_qh(v1_t, v2_t, tcg_env); 12833 break; 12834 case OPC_CMPGDU_EQ_OB: 12835 check_dsp_r2(ctx); 12836 gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12837 break; 12838 case OPC_CMPGDU_LT_OB: 12839 check_dsp_r2(ctx); 12840 gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12841 break; 12842 case OPC_CMPGDU_LE_OB: 12843 check_dsp_r2(ctx); 12844 gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12845 break; 12846 case OPC_CMPGU_EQ_OB: 12847 check_dsp(ctx); 12848 gen_helper_cmpgu_eq_ob(cpu_gpr[ret], v1_t, v2_t); 12849 break; 12850 case OPC_CMPGU_LT_OB: 12851 check_dsp(ctx); 12852 gen_helper_cmpgu_lt_ob(cpu_gpr[ret], v1_t, v2_t); 12853 break; 12854 case OPC_CMPGU_LE_OB: 12855 check_dsp(ctx); 12856 gen_helper_cmpgu_le_ob(cpu_gpr[ret], v1_t, v2_t); 12857 break; 12858 case OPC_CMPU_EQ_OB: 12859 check_dsp(ctx); 12860 gen_helper_cmpu_eq_ob(v1_t, v2_t, tcg_env); 12861 break; 12862 case OPC_CMPU_LT_OB: 12863 check_dsp(ctx); 12864 gen_helper_cmpu_lt_ob(v1_t, v2_t, tcg_env); 12865 break; 12866 case OPC_CMPU_LE_OB: 12867 check_dsp(ctx); 12868 gen_helper_cmpu_le_ob(v1_t, v2_t, tcg_env); 12869 break; 12870 case OPC_PACKRL_PW: 12871 check_dsp(ctx); 12872 gen_helper_packrl_pw(cpu_gpr[ret], v1_t, v2_t); 12873 break; 12874 case OPC_PICK_OB: 12875 check_dsp(ctx); 12876 gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12877 break; 12878 case OPC_PICK_PW: 12879 check_dsp(ctx); 12880 gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12881 break; 12882 case OPC_PICK_QH: 12883 check_dsp(ctx); 12884 gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); 12885 break; 12886 } 12887 break; 12888 #endif 12889 } 12890 } 12891 12892 static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, 12893 uint32_t op1, int rt, int rs, int sa) 12894 { 12895 TCGv t0; 12896 12897 check_dsp_r2(ctx); 12898 12899 if (rt == 0) { 12900 /* Treat as NOP. */ 12901 return; 12902 } 12903 12904 t0 = tcg_temp_new(); 12905 gen_load_gpr(t0, rs); 12906 12907 switch (op1) { 12908 case OPC_APPEND_DSP: 12909 switch (MASK_APPEND(ctx->opcode)) { 12910 case OPC_APPEND: 12911 if (sa != 0) { 12912 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 32 - sa); 12913 } 12914 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 12915 break; 12916 case OPC_PREPEND: 12917 if (sa != 0) { 12918 tcg_gen_ext32u_tl(cpu_gpr[rt], cpu_gpr[rt]); 12919 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa); 12920 tcg_gen_shli_tl(t0, t0, 32 - sa); 12921 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 12922 } 12923 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 12924 break; 12925 case OPC_BALIGN: 12926 sa &= 3; 12927 if (sa != 0 && sa != 2) { 12928 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa); 12929 tcg_gen_ext32u_tl(t0, t0); 12930 tcg_gen_shri_tl(t0, t0, 8 * (4 - sa)); 12931 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 12932 } 12933 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); 12934 break; 12935 default: /* Invalid */ 12936 MIPS_INVAL("MASK APPEND"); 12937 gen_reserved_instruction(ctx); 12938 break; 12939 } 12940 break; 12941 #ifdef TARGET_MIPS64 12942 case OPC_DAPPEND_DSP: 12943 switch (MASK_DAPPEND(ctx->opcode)) { 12944 case OPC_DAPPEND: 12945 if (sa != 0) { 12946 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 64 - sa); 12947 } 12948 break; 12949 case OPC_PREPENDD: 12950 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], 0x20 | sa); 12951 tcg_gen_shli_tl(t0, t0, 64 - (0x20 | sa)); 12952 tcg_gen_or_tl(cpu_gpr[rt], t0, t0); 12953 break; 12954 case OPC_PREPENDW: 12955 if (sa != 0) { 12956 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa); 12957 tcg_gen_shli_tl(t0, t0, 64 - sa); 12958 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 12959 } 12960 break; 12961 case OPC_DBALIGN: 12962 sa &= 7; 12963 if (sa != 0 && sa != 2 && sa != 4) { 12964 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa); 12965 tcg_gen_shri_tl(t0, t0, 8 * (8 - sa)); 12966 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0); 12967 } 12968 break; 12969 default: /* Invalid */ 12970 MIPS_INVAL("MASK DAPPEND"); 12971 gen_reserved_instruction(ctx); 12972 break; 12973 } 12974 break; 12975 #endif 12976 } 12977 } 12978 12979 static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, 12980 int ret, int v1, int v2, int check_ret) 12981 12982 { 12983 TCGv t0; 12984 TCGv t1; 12985 TCGv v1_t; 12986 int16_t imm; 12987 12988 if ((ret == 0) && (check_ret == 1)) { 12989 /* Treat as NOP. */ 12990 return; 12991 } 12992 12993 t0 = tcg_temp_new(); 12994 t1 = tcg_temp_new(); 12995 v1_t = tcg_temp_new(); 12996 12997 gen_load_gpr(v1_t, v1); 12998 12999 switch (op1) { 13000 case OPC_EXTR_W_DSP: 13001 check_dsp(ctx); 13002 switch (op2) { 13003 case OPC_EXTR_W: 13004 tcg_gen_movi_tl(t0, v2); 13005 tcg_gen_movi_tl(t1, v1); 13006 gen_helper_extr_w(cpu_gpr[ret], t0, t1, tcg_env); 13007 break; 13008 case OPC_EXTR_R_W: 13009 tcg_gen_movi_tl(t0, v2); 13010 tcg_gen_movi_tl(t1, v1); 13011 gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, tcg_env); 13012 break; 13013 case OPC_EXTR_RS_W: 13014 tcg_gen_movi_tl(t0, v2); 13015 tcg_gen_movi_tl(t1, v1); 13016 gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, tcg_env); 13017 break; 13018 case OPC_EXTR_S_H: 13019 tcg_gen_movi_tl(t0, v2); 13020 tcg_gen_movi_tl(t1, v1); 13021 gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, tcg_env); 13022 break; 13023 case OPC_EXTRV_S_H: 13024 tcg_gen_movi_tl(t0, v2); 13025 gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, tcg_env); 13026 break; 13027 case OPC_EXTRV_W: 13028 tcg_gen_movi_tl(t0, v2); 13029 gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, tcg_env); 13030 break; 13031 case OPC_EXTRV_R_W: 13032 tcg_gen_movi_tl(t0, v2); 13033 gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, tcg_env); 13034 break; 13035 case OPC_EXTRV_RS_W: 13036 tcg_gen_movi_tl(t0, v2); 13037 gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, tcg_env); 13038 break; 13039 case OPC_EXTP: 13040 tcg_gen_movi_tl(t0, v2); 13041 tcg_gen_movi_tl(t1, v1); 13042 gen_helper_extp(cpu_gpr[ret], t0, t1, tcg_env); 13043 break; 13044 case OPC_EXTPV: 13045 tcg_gen_movi_tl(t0, v2); 13046 gen_helper_extp(cpu_gpr[ret], t0, v1_t, tcg_env); 13047 break; 13048 case OPC_EXTPDP: 13049 tcg_gen_movi_tl(t0, v2); 13050 tcg_gen_movi_tl(t1, v1); 13051 gen_helper_extpdp(cpu_gpr[ret], t0, t1, tcg_env); 13052 break; 13053 case OPC_EXTPDPV: 13054 tcg_gen_movi_tl(t0, v2); 13055 gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, tcg_env); 13056 break; 13057 case OPC_SHILO: 13058 imm = (ctx->opcode >> 20) & 0x3F; 13059 tcg_gen_movi_tl(t0, ret); 13060 tcg_gen_movi_tl(t1, imm); 13061 gen_helper_shilo(t0, t1, tcg_env); 13062 break; 13063 case OPC_SHILOV: 13064 tcg_gen_movi_tl(t0, ret); 13065 gen_helper_shilo(t0, v1_t, tcg_env); 13066 break; 13067 case OPC_MTHLIP: 13068 tcg_gen_movi_tl(t0, ret); 13069 gen_helper_mthlip(t0, v1_t, tcg_env); 13070 break; 13071 case OPC_WRDSP: 13072 imm = (ctx->opcode >> 11) & 0x3FF; 13073 tcg_gen_movi_tl(t0, imm); 13074 gen_helper_wrdsp(v1_t, t0, tcg_env); 13075 break; 13076 case OPC_RDDSP: 13077 imm = (ctx->opcode >> 16) & 0x03FF; 13078 tcg_gen_movi_tl(t0, imm); 13079 gen_helper_rddsp(cpu_gpr[ret], t0, tcg_env); 13080 break; 13081 } 13082 break; 13083 #ifdef TARGET_MIPS64 13084 case OPC_DEXTR_W_DSP: 13085 check_dsp(ctx); 13086 switch (op2) { 13087 case OPC_DMTHLIP: 13088 tcg_gen_movi_tl(t0, ret); 13089 gen_helper_dmthlip(v1_t, t0, tcg_env); 13090 break; 13091 case OPC_DSHILO: 13092 { 13093 int shift = (ctx->opcode >> 19) & 0x7F; 13094 int ac = (ctx->opcode >> 11) & 0x03; 13095 tcg_gen_movi_tl(t0, shift); 13096 tcg_gen_movi_tl(t1, ac); 13097 gen_helper_dshilo(t0, t1, tcg_env); 13098 break; 13099 } 13100 case OPC_DSHILOV: 13101 { 13102 int ac = (ctx->opcode >> 11) & 0x03; 13103 tcg_gen_movi_tl(t0, ac); 13104 gen_helper_dshilo(v1_t, t0, tcg_env); 13105 break; 13106 } 13107 case OPC_DEXTP: 13108 tcg_gen_movi_tl(t0, v2); 13109 tcg_gen_movi_tl(t1, v1); 13110 13111 gen_helper_dextp(cpu_gpr[ret], t0, t1, tcg_env); 13112 break; 13113 case OPC_DEXTPV: 13114 tcg_gen_movi_tl(t0, v2); 13115 gen_helper_dextp(cpu_gpr[ret], t0, v1_t, tcg_env); 13116 break; 13117 case OPC_DEXTPDP: 13118 tcg_gen_movi_tl(t0, v2); 13119 tcg_gen_movi_tl(t1, v1); 13120 gen_helper_dextpdp(cpu_gpr[ret], t0, t1, tcg_env); 13121 break; 13122 case OPC_DEXTPDPV: 13123 tcg_gen_movi_tl(t0, v2); 13124 gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, tcg_env); 13125 break; 13126 case OPC_DEXTR_L: 13127 tcg_gen_movi_tl(t0, v2); 13128 tcg_gen_movi_tl(t1, v1); 13129 gen_helper_dextr_l(cpu_gpr[ret], t0, t1, tcg_env); 13130 break; 13131 case OPC_DEXTR_R_L: 13132 tcg_gen_movi_tl(t0, v2); 13133 tcg_gen_movi_tl(t1, v1); 13134 gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, tcg_env); 13135 break; 13136 case OPC_DEXTR_RS_L: 13137 tcg_gen_movi_tl(t0, v2); 13138 tcg_gen_movi_tl(t1, v1); 13139 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, tcg_env); 13140 break; 13141 case OPC_DEXTR_W: 13142 tcg_gen_movi_tl(t0, v2); 13143 tcg_gen_movi_tl(t1, v1); 13144 gen_helper_dextr_w(cpu_gpr[ret], t0, t1, tcg_env); 13145 break; 13146 case OPC_DEXTR_R_W: 13147 tcg_gen_movi_tl(t0, v2); 13148 tcg_gen_movi_tl(t1, v1); 13149 gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, tcg_env); 13150 break; 13151 case OPC_DEXTR_RS_W: 13152 tcg_gen_movi_tl(t0, v2); 13153 tcg_gen_movi_tl(t1, v1); 13154 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, tcg_env); 13155 break; 13156 case OPC_DEXTR_S_H: 13157 tcg_gen_movi_tl(t0, v2); 13158 tcg_gen_movi_tl(t1, v1); 13159 gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, tcg_env); 13160 break; 13161 case OPC_DEXTRV_S_H: 13162 tcg_gen_movi_tl(t0, v2); 13163 gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, tcg_env); 13164 break; 13165 case OPC_DEXTRV_L: 13166 tcg_gen_movi_tl(t0, v2); 13167 gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, tcg_env); 13168 break; 13169 case OPC_DEXTRV_R_L: 13170 tcg_gen_movi_tl(t0, v2); 13171 gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, tcg_env); 13172 break; 13173 case OPC_DEXTRV_RS_L: 13174 tcg_gen_movi_tl(t0, v2); 13175 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, tcg_env); 13176 break; 13177 case OPC_DEXTRV_W: 13178 tcg_gen_movi_tl(t0, v2); 13179 gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, tcg_env); 13180 break; 13181 case OPC_DEXTRV_R_W: 13182 tcg_gen_movi_tl(t0, v2); 13183 gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, tcg_env); 13184 break; 13185 case OPC_DEXTRV_RS_W: 13186 tcg_gen_movi_tl(t0, v2); 13187 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, tcg_env); 13188 break; 13189 } 13190 break; 13191 #endif 13192 } 13193 } 13194 13195 /* End MIPSDSP functions. */ 13196 13197 static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) 13198 { 13199 int rs, rt, rd, sa; 13200 uint32_t op1, op2; 13201 13202 rs = (ctx->opcode >> 21) & 0x1f; 13203 rt = (ctx->opcode >> 16) & 0x1f; 13204 rd = (ctx->opcode >> 11) & 0x1f; 13205 sa = (ctx->opcode >> 6) & 0x1f; 13206 13207 op1 = MASK_SPECIAL(ctx->opcode); 13208 switch (op1) { 13209 case OPC_MULT: 13210 case OPC_MULTU: 13211 case OPC_DIV: 13212 case OPC_DIVU: 13213 op2 = MASK_R6_MULDIV(ctx->opcode); 13214 switch (op2) { 13215 case R6_OPC_MUL: 13216 case R6_OPC_MUH: 13217 case R6_OPC_MULU: 13218 case R6_OPC_MUHU: 13219 case R6_OPC_DIV: 13220 case R6_OPC_MOD: 13221 case R6_OPC_DIVU: 13222 case R6_OPC_MODU: 13223 gen_r6_muldiv(ctx, op2, rd, rs, rt); 13224 break; 13225 default: 13226 MIPS_INVAL("special_r6 muldiv"); 13227 gen_reserved_instruction(ctx); 13228 break; 13229 } 13230 break; 13231 case OPC_SELEQZ: 13232 case OPC_SELNEZ: 13233 gen_cond_move(ctx, op1, rd, rs, rt); 13234 break; 13235 case R6_OPC_CLO: 13236 case R6_OPC_CLZ: 13237 if (rt == 0 && sa == 1) { 13238 /* 13239 * Major opcode and function field is shared with preR6 MFHI/MTHI. 13240 * We need additionally to check other fields. 13241 */ 13242 gen_cl(ctx, op1, rd, rs); 13243 } else { 13244 gen_reserved_instruction(ctx); 13245 } 13246 break; 13247 case R6_OPC_SDBBP: 13248 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) { 13249 ctx->base.is_jmp = DISAS_SEMIHOST; 13250 } else { 13251 if (ctx->hflags & MIPS_HFLAG_SBRI) { 13252 gen_reserved_instruction(ctx); 13253 } else { 13254 generate_exception_end(ctx, EXCP_DBp); 13255 } 13256 } 13257 break; 13258 #if defined(TARGET_MIPS64) 13259 case R6_OPC_DCLO: 13260 case R6_OPC_DCLZ: 13261 if (rt == 0 && sa == 1) { 13262 /* 13263 * Major opcode and function field is shared with preR6 MFHI/MTHI. 13264 * We need additionally to check other fields. 13265 */ 13266 check_mips_64(ctx); 13267 gen_cl(ctx, op1, rd, rs); 13268 } else { 13269 gen_reserved_instruction(ctx); 13270 } 13271 break; 13272 case OPC_DMULT: 13273 case OPC_DMULTU: 13274 case OPC_DDIV: 13275 case OPC_DDIVU: 13276 13277 op2 = MASK_R6_MULDIV(ctx->opcode); 13278 switch (op2) { 13279 case R6_OPC_DMUL: 13280 case R6_OPC_DMUH: 13281 case R6_OPC_DMULU: 13282 case R6_OPC_DMUHU: 13283 case R6_OPC_DDIV: 13284 case R6_OPC_DMOD: 13285 case R6_OPC_DDIVU: 13286 case R6_OPC_DMODU: 13287 check_mips_64(ctx); 13288 gen_r6_muldiv(ctx, op2, rd, rs, rt); 13289 break; 13290 default: 13291 MIPS_INVAL("special_r6 muldiv"); 13292 gen_reserved_instruction(ctx); 13293 break; 13294 } 13295 break; 13296 #endif 13297 default: /* Invalid */ 13298 MIPS_INVAL("special_r6"); 13299 gen_reserved_instruction(ctx); 13300 break; 13301 } 13302 } 13303 13304 static void decode_opc_special_tx79(CPUMIPSState *env, DisasContext *ctx) 13305 { 13306 int rs = extract32(ctx->opcode, 21, 5); 13307 int rt = extract32(ctx->opcode, 16, 5); 13308 int rd = extract32(ctx->opcode, 11, 5); 13309 uint32_t op1 = MASK_SPECIAL(ctx->opcode); 13310 13311 switch (op1) { 13312 case OPC_MOVN: /* Conditional move */ 13313 case OPC_MOVZ: 13314 gen_cond_move(ctx, op1, rd, rs, rt); 13315 break; 13316 case OPC_MFHI: /* Move from HI/LO */ 13317 case OPC_MFLO: 13318 gen_HILO(ctx, op1, 0, rd); 13319 break; 13320 case OPC_MTHI: 13321 case OPC_MTLO: /* Move to HI/LO */ 13322 gen_HILO(ctx, op1, 0, rs); 13323 break; 13324 case OPC_MULT: 13325 case OPC_MULTU: 13326 gen_mul_txx9(ctx, op1, rd, rs, rt); 13327 break; 13328 case OPC_DIV: 13329 case OPC_DIVU: 13330 gen_muldiv(ctx, op1, 0, rs, rt); 13331 break; 13332 #if defined(TARGET_MIPS64) 13333 case OPC_DMULT: 13334 case OPC_DMULTU: 13335 case OPC_DDIV: 13336 case OPC_DDIVU: 13337 check_insn_opc_user_only(ctx, INSN_R5900); 13338 gen_muldiv(ctx, op1, 0, rs, rt); 13339 break; 13340 #endif 13341 case OPC_JR: 13342 gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4); 13343 break; 13344 default: /* Invalid */ 13345 MIPS_INVAL("special_tx79"); 13346 gen_reserved_instruction(ctx); 13347 break; 13348 } 13349 } 13350 13351 static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) 13352 { 13353 int rs, rt, rd; 13354 uint32_t op1; 13355 13356 rs = (ctx->opcode >> 21) & 0x1f; 13357 rt = (ctx->opcode >> 16) & 0x1f; 13358 rd = (ctx->opcode >> 11) & 0x1f; 13359 13360 op1 = MASK_SPECIAL(ctx->opcode); 13361 switch (op1) { 13362 case OPC_MOVN: /* Conditional move */ 13363 case OPC_MOVZ: 13364 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | 13365 INSN_LOONGSON2E | INSN_LOONGSON2F); 13366 gen_cond_move(ctx, op1, rd, rs, rt); 13367 break; 13368 case OPC_MFHI: /* Move from HI/LO */ 13369 case OPC_MFLO: 13370 gen_HILO(ctx, op1, rs & 3, rd); 13371 break; 13372 case OPC_MTHI: 13373 case OPC_MTLO: /* Move to HI/LO */ 13374 gen_HILO(ctx, op1, rd & 3, rs); 13375 break; 13376 case OPC_MOVCI: 13377 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); 13378 if (env->CP0_Config1 & (1 << CP0C1_FP)) { 13379 check_cp1_enabled(ctx); 13380 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, 13381 (ctx->opcode >> 16) & 1); 13382 } else { 13383 generate_exception_err(ctx, EXCP_CpU, 1); 13384 } 13385 break; 13386 case OPC_MULT: 13387 case OPC_MULTU: 13388 gen_muldiv(ctx, op1, rd & 3, rs, rt); 13389 break; 13390 case OPC_DIV: 13391 case OPC_DIVU: 13392 gen_muldiv(ctx, op1, 0, rs, rt); 13393 break; 13394 #if defined(TARGET_MIPS64) 13395 case OPC_DMULT: 13396 case OPC_DMULTU: 13397 case OPC_DDIV: 13398 case OPC_DDIVU: 13399 check_insn(ctx, ISA_MIPS3); 13400 check_mips_64(ctx); 13401 gen_muldiv(ctx, op1, 0, rs, rt); 13402 break; 13403 #endif 13404 case OPC_JR: 13405 gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4); 13406 break; 13407 case OPC_SPIM: 13408 #ifdef MIPS_STRICT_STANDARD 13409 MIPS_INVAL("SPIM"); 13410 gen_reserved_instruction(ctx); 13411 #else 13412 /* Implemented as RI exception for now. */ 13413 MIPS_INVAL("spim (unofficial)"); 13414 gen_reserved_instruction(ctx); 13415 #endif 13416 break; 13417 default: /* Invalid */ 13418 MIPS_INVAL("special_legacy"); 13419 gen_reserved_instruction(ctx); 13420 break; 13421 } 13422 } 13423 13424 static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) 13425 { 13426 int rs, rt, rd, sa; 13427 uint32_t op1; 13428 13429 rs = (ctx->opcode >> 21) & 0x1f; 13430 rt = (ctx->opcode >> 16) & 0x1f; 13431 rd = (ctx->opcode >> 11) & 0x1f; 13432 sa = (ctx->opcode >> 6) & 0x1f; 13433 13434 op1 = MASK_SPECIAL(ctx->opcode); 13435 switch (op1) { 13436 case OPC_SLL: /* Shift with immediate */ 13437 if (sa == 5 && rd == 0 && 13438 rs == 0 && rt == 0) { /* PAUSE */ 13439 if ((ctx->insn_flags & ISA_MIPS_R6) && 13440 (ctx->hflags & MIPS_HFLAG_BMASK)) { 13441 gen_reserved_instruction(ctx); 13442 break; 13443 } 13444 } 13445 /* Fallthrough */ 13446 case OPC_SRA: 13447 gen_shift_imm(ctx, op1, rd, rt, sa); 13448 break; 13449 case OPC_SRL: 13450 switch ((ctx->opcode >> 21) & 0x1f) { 13451 case 1: 13452 /* rotr is decoded as srl on non-R2 CPUs */ 13453 if (ctx->insn_flags & ISA_MIPS_R2) { 13454 op1 = OPC_ROTR; 13455 } 13456 /* Fallthrough */ 13457 case 0: 13458 gen_shift_imm(ctx, op1, rd, rt, sa); 13459 break; 13460 default: 13461 gen_reserved_instruction(ctx); 13462 break; 13463 } 13464 break; 13465 case OPC_ADD: 13466 case OPC_ADDU: 13467 case OPC_SUB: 13468 case OPC_SUBU: 13469 gen_arith(ctx, op1, rd, rs, rt); 13470 break; 13471 case OPC_SLLV: /* Shifts */ 13472 case OPC_SRAV: 13473 gen_shift(ctx, op1, rd, rs, rt); 13474 break; 13475 case OPC_SRLV: 13476 switch ((ctx->opcode >> 6) & 0x1f) { 13477 case 1: 13478 /* rotrv is decoded as srlv on non-R2 CPUs */ 13479 if (ctx->insn_flags & ISA_MIPS_R2) { 13480 op1 = OPC_ROTRV; 13481 } 13482 /* Fallthrough */ 13483 case 0: 13484 gen_shift(ctx, op1, rd, rs, rt); 13485 break; 13486 default: 13487 gen_reserved_instruction(ctx); 13488 break; 13489 } 13490 break; 13491 case OPC_SLT: /* Set on less than */ 13492 case OPC_SLTU: 13493 gen_slt(ctx, op1, rd, rs, rt); 13494 break; 13495 case OPC_AND: /* Logic*/ 13496 case OPC_OR: 13497 case OPC_NOR: 13498 case OPC_XOR: 13499 gen_logic(ctx, op1, rd, rs, rt); 13500 break; 13501 case OPC_JALR: 13502 gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4); 13503 break; 13504 case OPC_TGE: /* Traps */ 13505 case OPC_TGEU: 13506 case OPC_TLT: 13507 case OPC_TLTU: 13508 case OPC_TEQ: 13509 case OPC_TNE: 13510 check_insn(ctx, ISA_MIPS2); 13511 gen_trap(ctx, op1, rs, rt, -1, extract32(ctx->opcode, 6, 10)); 13512 break; 13513 case OPC_PMON: 13514 /* Pmon entry point, also R4010 selsl */ 13515 #ifdef MIPS_STRICT_STANDARD 13516 MIPS_INVAL("PMON / selsl"); 13517 gen_reserved_instruction(ctx); 13518 #else 13519 gen_helper_pmon(tcg_env, tcg_constant_i32(sa)); 13520 #endif 13521 break; 13522 case OPC_SYSCALL: 13523 generate_exception_end(ctx, EXCP_SYSCALL); 13524 break; 13525 case OPC_BREAK: 13526 generate_exception_break(ctx, extract32(ctx->opcode, 6, 20)); 13527 break; 13528 case OPC_SYNC: 13529 check_insn(ctx, ISA_MIPS2); 13530 gen_sync(extract32(ctx->opcode, 6, 5)); 13531 break; 13532 13533 #if defined(TARGET_MIPS64) 13534 /* MIPS64 specific opcodes */ 13535 case OPC_DSLL: 13536 case OPC_DSRA: 13537 case OPC_DSLL32: 13538 case OPC_DSRA32: 13539 check_insn(ctx, ISA_MIPS3); 13540 check_mips_64(ctx); 13541 gen_shift_imm(ctx, op1, rd, rt, sa); 13542 break; 13543 case OPC_DSRL: 13544 switch ((ctx->opcode >> 21) & 0x1f) { 13545 case 1: 13546 /* drotr is decoded as dsrl on non-R2 CPUs */ 13547 if (ctx->insn_flags & ISA_MIPS_R2) { 13548 op1 = OPC_DROTR; 13549 } 13550 /* Fallthrough */ 13551 case 0: 13552 check_insn(ctx, ISA_MIPS3); 13553 check_mips_64(ctx); 13554 gen_shift_imm(ctx, op1, rd, rt, sa); 13555 break; 13556 default: 13557 gen_reserved_instruction(ctx); 13558 break; 13559 } 13560 break; 13561 case OPC_DSRL32: 13562 switch ((ctx->opcode >> 21) & 0x1f) { 13563 case 1: 13564 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ 13565 if (ctx->insn_flags & ISA_MIPS_R2) { 13566 op1 = OPC_DROTR32; 13567 } 13568 /* Fallthrough */ 13569 case 0: 13570 check_insn(ctx, ISA_MIPS3); 13571 check_mips_64(ctx); 13572 gen_shift_imm(ctx, op1, rd, rt, sa); 13573 break; 13574 default: 13575 gen_reserved_instruction(ctx); 13576 break; 13577 } 13578 break; 13579 case OPC_DADD: 13580 case OPC_DADDU: 13581 case OPC_DSUB: 13582 case OPC_DSUBU: 13583 check_insn(ctx, ISA_MIPS3); 13584 check_mips_64(ctx); 13585 gen_arith(ctx, op1, rd, rs, rt); 13586 break; 13587 case OPC_DSLLV: 13588 case OPC_DSRAV: 13589 check_insn(ctx, ISA_MIPS3); 13590 check_mips_64(ctx); 13591 gen_shift(ctx, op1, rd, rs, rt); 13592 break; 13593 case OPC_DSRLV: 13594 switch ((ctx->opcode >> 6) & 0x1f) { 13595 case 1: 13596 /* drotrv is decoded as dsrlv on non-R2 CPUs */ 13597 if (ctx->insn_flags & ISA_MIPS_R2) { 13598 op1 = OPC_DROTRV; 13599 } 13600 /* Fallthrough */ 13601 case 0: 13602 check_insn(ctx, ISA_MIPS3); 13603 check_mips_64(ctx); 13604 gen_shift(ctx, op1, rd, rs, rt); 13605 break; 13606 default: 13607 gen_reserved_instruction(ctx); 13608 break; 13609 } 13610 break; 13611 #endif 13612 default: 13613 if (ctx->insn_flags & ISA_MIPS_R6) { 13614 decode_opc_special_r6(env, ctx); 13615 } else if (ctx->insn_flags & INSN_R5900) { 13616 decode_opc_special_tx79(env, ctx); 13617 } else { 13618 decode_opc_special_legacy(env, ctx); 13619 } 13620 } 13621 } 13622 13623 13624 static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) 13625 { 13626 int rs, rt, rd; 13627 uint32_t op1; 13628 13629 rs = (ctx->opcode >> 21) & 0x1f; 13630 rt = (ctx->opcode >> 16) & 0x1f; 13631 rd = (ctx->opcode >> 11) & 0x1f; 13632 13633 op1 = MASK_SPECIAL2(ctx->opcode); 13634 switch (op1) { 13635 case OPC_MADD: /* Multiply and add/sub */ 13636 case OPC_MADDU: 13637 case OPC_MSUB: 13638 case OPC_MSUBU: 13639 check_insn(ctx, ISA_MIPS_R1); 13640 gen_muldiv(ctx, op1, rd & 3, rs, rt); 13641 break; 13642 case OPC_MUL: 13643 gen_arith(ctx, op1, rd, rs, rt); 13644 break; 13645 case OPC_DIV_G_2F: 13646 case OPC_DIVU_G_2F: 13647 case OPC_MULT_G_2F: 13648 case OPC_MULTU_G_2F: 13649 case OPC_MOD_G_2F: 13650 case OPC_MODU_G_2F: 13651 check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); 13652 gen_loongson_integer(ctx, op1, rd, rs, rt); 13653 break; 13654 case OPC_CLO: 13655 case OPC_CLZ: 13656 check_insn(ctx, ISA_MIPS_R1); 13657 gen_cl(ctx, op1, rd, rs); 13658 break; 13659 case OPC_SDBBP: 13660 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) { 13661 ctx->base.is_jmp = DISAS_SEMIHOST; 13662 } else { 13663 /* 13664 * XXX: not clear which exception should be raised 13665 * when in debug mode... 13666 */ 13667 check_insn(ctx, ISA_MIPS_R1); 13668 generate_exception_end(ctx, EXCP_DBp); 13669 } 13670 break; 13671 #if defined(TARGET_MIPS64) 13672 case OPC_DCLO: 13673 case OPC_DCLZ: 13674 check_insn(ctx, ISA_MIPS_R1); 13675 check_mips_64(ctx); 13676 gen_cl(ctx, op1, rd, rs); 13677 break; 13678 case OPC_DMULT_G_2F: 13679 case OPC_DMULTU_G_2F: 13680 case OPC_DDIV_G_2F: 13681 case OPC_DDIVU_G_2F: 13682 case OPC_DMOD_G_2F: 13683 case OPC_DMODU_G_2F: 13684 check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT); 13685 gen_loongson_integer(ctx, op1, rd, rs, rt); 13686 break; 13687 #endif 13688 default: /* Invalid */ 13689 MIPS_INVAL("special2_legacy"); 13690 gen_reserved_instruction(ctx); 13691 break; 13692 } 13693 } 13694 13695 static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) 13696 { 13697 int rs, rt, rd, sa; 13698 uint32_t op1, op2; 13699 int16_t imm; 13700 13701 rs = (ctx->opcode >> 21) & 0x1f; 13702 rt = (ctx->opcode >> 16) & 0x1f; 13703 rd = (ctx->opcode >> 11) & 0x1f; 13704 sa = (ctx->opcode >> 6) & 0x1f; 13705 imm = (int16_t)ctx->opcode >> 7; 13706 13707 op1 = MASK_SPECIAL3(ctx->opcode); 13708 switch (op1) { 13709 case R6_OPC_PREF: 13710 if (rt >= 24) { 13711 /* hint codes 24-31 are reserved and signal RI */ 13712 gen_reserved_instruction(ctx); 13713 } 13714 /* Treat as NOP. */ 13715 break; 13716 case R6_OPC_CACHE: 13717 check_cp0_enabled(ctx); 13718 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 13719 gen_cache_operation(ctx, rt, rs, imm); 13720 } 13721 break; 13722 case R6_OPC_SC: 13723 gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); 13724 break; 13725 case R6_OPC_LL: 13726 gen_ld(ctx, op1, rt, rs, imm); 13727 break; 13728 case OPC_BSHFL: 13729 { 13730 if (rd == 0) { 13731 /* Treat as NOP. */ 13732 break; 13733 } 13734 op2 = MASK_BSHFL(ctx->opcode); 13735 switch (op2) { 13736 case OPC_ALIGN: 13737 case OPC_ALIGN_1: 13738 case OPC_ALIGN_2: 13739 case OPC_ALIGN_3: 13740 gen_align(ctx, 32, rd, rs, rt, sa & 3); 13741 break; 13742 case OPC_BITSWAP: 13743 gen_bitswap(ctx, op2, rd, rt); 13744 break; 13745 } 13746 } 13747 break; 13748 #ifndef CONFIG_USER_ONLY 13749 case OPC_GINV: 13750 if (unlikely(ctx->gi <= 1)) { 13751 gen_reserved_instruction(ctx); 13752 } 13753 check_cp0_enabled(ctx); 13754 switch ((ctx->opcode >> 6) & 3) { 13755 case 0: /* GINVI */ 13756 /* Treat as NOP. */ 13757 break; 13758 case 2: /* GINVT */ 13759 gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, 2)); 13760 break; 13761 default: 13762 gen_reserved_instruction(ctx); 13763 break; 13764 } 13765 break; 13766 #endif 13767 #if defined(TARGET_MIPS64) 13768 case R6_OPC_SCD: 13769 gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false); 13770 break; 13771 case R6_OPC_LLD: 13772 gen_ld(ctx, op1, rt, rs, imm); 13773 break; 13774 case OPC_DBSHFL: 13775 check_mips_64(ctx); 13776 { 13777 if (rd == 0) { 13778 /* Treat as NOP. */ 13779 break; 13780 } 13781 op2 = MASK_DBSHFL(ctx->opcode); 13782 switch (op2) { 13783 case OPC_DALIGN: 13784 case OPC_DALIGN_1: 13785 case OPC_DALIGN_2: 13786 case OPC_DALIGN_3: 13787 case OPC_DALIGN_4: 13788 case OPC_DALIGN_5: 13789 case OPC_DALIGN_6: 13790 case OPC_DALIGN_7: 13791 gen_align(ctx, 64, rd, rs, rt, sa & 7); 13792 break; 13793 case OPC_DBITSWAP: 13794 gen_bitswap(ctx, op2, rd, rt); 13795 break; 13796 } 13797 13798 } 13799 break; 13800 #endif 13801 default: /* Invalid */ 13802 MIPS_INVAL("special3_r6"); 13803 gen_reserved_instruction(ctx); 13804 break; 13805 } 13806 } 13807 13808 static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) 13809 { 13810 int rs, rt, rd; 13811 uint32_t op1, op2; 13812 13813 rs = (ctx->opcode >> 21) & 0x1f; 13814 rt = (ctx->opcode >> 16) & 0x1f; 13815 rd = (ctx->opcode >> 11) & 0x1f; 13816 13817 op1 = MASK_SPECIAL3(ctx->opcode); 13818 switch (op1) { 13819 case OPC_DIV_G_2E: 13820 case OPC_DIVU_G_2E: 13821 case OPC_MOD_G_2E: 13822 case OPC_MODU_G_2E: 13823 case OPC_MULT_G_2E: 13824 case OPC_MULTU_G_2E: 13825 /* 13826 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have 13827 * the same mask and op1. 13828 */ 13829 if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) { 13830 op2 = MASK_ADDUH_QB(ctx->opcode); 13831 switch (op2) { 13832 case OPC_ADDUH_QB: 13833 case OPC_ADDUH_R_QB: 13834 case OPC_ADDQH_PH: 13835 case OPC_ADDQH_R_PH: 13836 case OPC_ADDQH_W: 13837 case OPC_ADDQH_R_W: 13838 case OPC_SUBUH_QB: 13839 case OPC_SUBUH_R_QB: 13840 case OPC_SUBQH_PH: 13841 case OPC_SUBQH_R_PH: 13842 case OPC_SUBQH_W: 13843 case OPC_SUBQH_R_W: 13844 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 13845 break; 13846 case OPC_MUL_PH: 13847 case OPC_MUL_S_PH: 13848 case OPC_MULQ_S_W: 13849 case OPC_MULQ_RS_W: 13850 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); 13851 break; 13852 default: 13853 MIPS_INVAL("MASK ADDUH.QB"); 13854 gen_reserved_instruction(ctx); 13855 break; 13856 } 13857 } else if (ctx->insn_flags & INSN_LOONGSON2E) { 13858 gen_loongson_integer(ctx, op1, rd, rs, rt); 13859 } else { 13860 gen_reserved_instruction(ctx); 13861 } 13862 break; 13863 case OPC_LX_DSP: 13864 op2 = MASK_LX(ctx->opcode); 13865 switch (op2) { 13866 #if defined(TARGET_MIPS64) 13867 case OPC_LDX: 13868 #endif 13869 case OPC_LBUX: 13870 case OPC_LHX: 13871 case OPC_LWX: 13872 gen_mips_lx(ctx, op2, rd, rs, rt); 13873 break; 13874 default: /* Invalid */ 13875 MIPS_INVAL("MASK LX"); 13876 gen_reserved_instruction(ctx); 13877 break; 13878 } 13879 break; 13880 case OPC_ABSQ_S_PH_DSP: 13881 op2 = MASK_ABSQ_S_PH(ctx->opcode); 13882 switch (op2) { 13883 case OPC_ABSQ_S_QB: 13884 case OPC_ABSQ_S_PH: 13885 case OPC_ABSQ_S_W: 13886 case OPC_PRECEQ_W_PHL: 13887 case OPC_PRECEQ_W_PHR: 13888 case OPC_PRECEQU_PH_QBL: 13889 case OPC_PRECEQU_PH_QBR: 13890 case OPC_PRECEQU_PH_QBLA: 13891 case OPC_PRECEQU_PH_QBRA: 13892 case OPC_PRECEU_PH_QBL: 13893 case OPC_PRECEU_PH_QBR: 13894 case OPC_PRECEU_PH_QBLA: 13895 case OPC_PRECEU_PH_QBRA: 13896 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 13897 break; 13898 case OPC_BITREV: 13899 case OPC_REPL_QB: 13900 case OPC_REPLV_QB: 13901 case OPC_REPL_PH: 13902 case OPC_REPLV_PH: 13903 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt); 13904 break; 13905 default: 13906 MIPS_INVAL("MASK ABSQ_S.PH"); 13907 gen_reserved_instruction(ctx); 13908 break; 13909 } 13910 break; 13911 case OPC_ADDU_QB_DSP: 13912 op2 = MASK_ADDU_QB(ctx->opcode); 13913 switch (op2) { 13914 case OPC_ADDQ_PH: 13915 case OPC_ADDQ_S_PH: 13916 case OPC_ADDQ_S_W: 13917 case OPC_ADDU_QB: 13918 case OPC_ADDU_S_QB: 13919 case OPC_ADDU_PH: 13920 case OPC_ADDU_S_PH: 13921 case OPC_SUBQ_PH: 13922 case OPC_SUBQ_S_PH: 13923 case OPC_SUBQ_S_W: 13924 case OPC_SUBU_QB: 13925 case OPC_SUBU_S_QB: 13926 case OPC_SUBU_PH: 13927 case OPC_SUBU_S_PH: 13928 case OPC_ADDSC: 13929 case OPC_ADDWC: 13930 case OPC_MODSUB: 13931 case OPC_RADDU_W_QB: 13932 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 13933 break; 13934 case OPC_MULEU_S_PH_QBL: 13935 case OPC_MULEU_S_PH_QBR: 13936 case OPC_MULQ_RS_PH: 13937 case OPC_MULEQ_S_W_PHL: 13938 case OPC_MULEQ_S_W_PHR: 13939 case OPC_MULQ_S_PH: 13940 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); 13941 break; 13942 default: /* Invalid */ 13943 MIPS_INVAL("MASK ADDU.QB"); 13944 gen_reserved_instruction(ctx); 13945 break; 13946 13947 } 13948 break; 13949 case OPC_CMPU_EQ_QB_DSP: 13950 op2 = MASK_CMPU_EQ_QB(ctx->opcode); 13951 switch (op2) { 13952 case OPC_PRECR_SRA_PH_W: 13953 case OPC_PRECR_SRA_R_PH_W: 13954 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd); 13955 break; 13956 case OPC_PRECR_QB_PH: 13957 case OPC_PRECRQ_QB_PH: 13958 case OPC_PRECRQ_PH_W: 13959 case OPC_PRECRQ_RS_PH_W: 13960 case OPC_PRECRQU_S_QB_PH: 13961 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 13962 break; 13963 case OPC_CMPU_EQ_QB: 13964 case OPC_CMPU_LT_QB: 13965 case OPC_CMPU_LE_QB: 13966 case OPC_CMP_EQ_PH: 13967 case OPC_CMP_LT_PH: 13968 case OPC_CMP_LE_PH: 13969 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0); 13970 break; 13971 case OPC_CMPGU_EQ_QB: 13972 case OPC_CMPGU_LT_QB: 13973 case OPC_CMPGU_LE_QB: 13974 case OPC_CMPGDU_EQ_QB: 13975 case OPC_CMPGDU_LT_QB: 13976 case OPC_CMPGDU_LE_QB: 13977 case OPC_PICK_QB: 13978 case OPC_PICK_PH: 13979 case OPC_PACKRL_PH: 13980 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1); 13981 break; 13982 default: /* Invalid */ 13983 MIPS_INVAL("MASK CMPU.EQ.QB"); 13984 gen_reserved_instruction(ctx); 13985 break; 13986 } 13987 break; 13988 case OPC_SHLL_QB_DSP: 13989 gen_mipsdsp_shift(ctx, op1, rd, rs, rt); 13990 break; 13991 case OPC_DPA_W_PH_DSP: 13992 op2 = MASK_DPA_W_PH(ctx->opcode); 13993 switch (op2) { 13994 case OPC_DPAU_H_QBL: 13995 case OPC_DPAU_H_QBR: 13996 case OPC_DPSU_H_QBL: 13997 case OPC_DPSU_H_QBR: 13998 case OPC_DPA_W_PH: 13999 case OPC_DPAX_W_PH: 14000 case OPC_DPAQ_S_W_PH: 14001 case OPC_DPAQX_S_W_PH: 14002 case OPC_DPAQX_SA_W_PH: 14003 case OPC_DPS_W_PH: 14004 case OPC_DPSX_W_PH: 14005 case OPC_DPSQ_S_W_PH: 14006 case OPC_DPSQX_S_W_PH: 14007 case OPC_DPSQX_SA_W_PH: 14008 case OPC_MULSAQ_S_W_PH: 14009 case OPC_DPAQ_SA_L_W: 14010 case OPC_DPSQ_SA_L_W: 14011 case OPC_MAQ_S_W_PHL: 14012 case OPC_MAQ_S_W_PHR: 14013 case OPC_MAQ_SA_W_PHL: 14014 case OPC_MAQ_SA_W_PHR: 14015 case OPC_MULSA_W_PH: 14016 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); 14017 break; 14018 default: /* Invalid */ 14019 MIPS_INVAL("MASK DPAW.PH"); 14020 gen_reserved_instruction(ctx); 14021 break; 14022 } 14023 break; 14024 case OPC_INSV_DSP: 14025 op2 = MASK_INSV(ctx->opcode); 14026 switch (op2) { 14027 case OPC_INSV: 14028 check_dsp(ctx); 14029 { 14030 TCGv t0, t1; 14031 14032 if (rt == 0) { 14033 break; 14034 } 14035 14036 t0 = tcg_temp_new(); 14037 t1 = tcg_temp_new(); 14038 14039 gen_load_gpr(t0, rt); 14040 gen_load_gpr(t1, rs); 14041 14042 gen_helper_insv(cpu_gpr[rt], tcg_env, t1, t0); 14043 break; 14044 } 14045 default: /* Invalid */ 14046 MIPS_INVAL("MASK INSV"); 14047 gen_reserved_instruction(ctx); 14048 break; 14049 } 14050 break; 14051 case OPC_APPEND_DSP: 14052 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd); 14053 break; 14054 case OPC_EXTR_W_DSP: 14055 op2 = MASK_EXTR_W(ctx->opcode); 14056 switch (op2) { 14057 case OPC_EXTR_W: 14058 case OPC_EXTR_R_W: 14059 case OPC_EXTR_RS_W: 14060 case OPC_EXTR_S_H: 14061 case OPC_EXTRV_S_H: 14062 case OPC_EXTRV_W: 14063 case OPC_EXTRV_R_W: 14064 case OPC_EXTRV_RS_W: 14065 case OPC_EXTP: 14066 case OPC_EXTPV: 14067 case OPC_EXTPDP: 14068 case OPC_EXTPDPV: 14069 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1); 14070 break; 14071 case OPC_RDDSP: 14072 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 1); 14073 break; 14074 case OPC_SHILO: 14075 case OPC_SHILOV: 14076 case OPC_MTHLIP: 14077 case OPC_WRDSP: 14078 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0); 14079 break; 14080 default: /* Invalid */ 14081 MIPS_INVAL("MASK EXTR.W"); 14082 gen_reserved_instruction(ctx); 14083 break; 14084 } 14085 break; 14086 #if defined(TARGET_MIPS64) 14087 case OPC_DDIV_G_2E: 14088 case OPC_DDIVU_G_2E: 14089 case OPC_DMULT_G_2E: 14090 case OPC_DMULTU_G_2E: 14091 case OPC_DMOD_G_2E: 14092 case OPC_DMODU_G_2E: 14093 check_insn(ctx, INSN_LOONGSON2E); 14094 gen_loongson_integer(ctx, op1, rd, rs, rt); 14095 break; 14096 case OPC_ABSQ_S_QH_DSP: 14097 op2 = MASK_ABSQ_S_QH(ctx->opcode); 14098 switch (op2) { 14099 case OPC_PRECEQ_L_PWL: 14100 case OPC_PRECEQ_L_PWR: 14101 case OPC_PRECEQ_PW_QHL: 14102 case OPC_PRECEQ_PW_QHR: 14103 case OPC_PRECEQ_PW_QHLA: 14104 case OPC_PRECEQ_PW_QHRA: 14105 case OPC_PRECEQU_QH_OBL: 14106 case OPC_PRECEQU_QH_OBR: 14107 case OPC_PRECEQU_QH_OBLA: 14108 case OPC_PRECEQU_QH_OBRA: 14109 case OPC_PRECEU_QH_OBL: 14110 case OPC_PRECEU_QH_OBR: 14111 case OPC_PRECEU_QH_OBLA: 14112 case OPC_PRECEU_QH_OBRA: 14113 case OPC_ABSQ_S_OB: 14114 case OPC_ABSQ_S_PW: 14115 case OPC_ABSQ_S_QH: 14116 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14117 break; 14118 case OPC_REPL_OB: 14119 case OPC_REPL_PW: 14120 case OPC_REPL_QH: 14121 case OPC_REPLV_OB: 14122 case OPC_REPLV_PW: 14123 case OPC_REPLV_QH: 14124 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt); 14125 break; 14126 default: /* Invalid */ 14127 MIPS_INVAL("MASK ABSQ_S.QH"); 14128 gen_reserved_instruction(ctx); 14129 break; 14130 } 14131 break; 14132 case OPC_ADDU_OB_DSP: 14133 op2 = MASK_ADDU_OB(ctx->opcode); 14134 switch (op2) { 14135 case OPC_RADDU_L_OB: 14136 case OPC_SUBQ_PW: 14137 case OPC_SUBQ_S_PW: 14138 case OPC_SUBQ_QH: 14139 case OPC_SUBQ_S_QH: 14140 case OPC_SUBU_OB: 14141 case OPC_SUBU_S_OB: 14142 case OPC_SUBU_QH: 14143 case OPC_SUBU_S_QH: 14144 case OPC_SUBUH_OB: 14145 case OPC_SUBUH_R_OB: 14146 case OPC_ADDQ_PW: 14147 case OPC_ADDQ_S_PW: 14148 case OPC_ADDQ_QH: 14149 case OPC_ADDQ_S_QH: 14150 case OPC_ADDU_OB: 14151 case OPC_ADDU_S_OB: 14152 case OPC_ADDU_QH: 14153 case OPC_ADDU_S_QH: 14154 case OPC_ADDUH_OB: 14155 case OPC_ADDUH_R_OB: 14156 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14157 break; 14158 case OPC_MULEQ_S_PW_QHL: 14159 case OPC_MULEQ_S_PW_QHR: 14160 case OPC_MULEU_S_QH_OBL: 14161 case OPC_MULEU_S_QH_OBR: 14162 case OPC_MULQ_RS_QH: 14163 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); 14164 break; 14165 default: /* Invalid */ 14166 MIPS_INVAL("MASK ADDU.OB"); 14167 gen_reserved_instruction(ctx); 14168 break; 14169 } 14170 break; 14171 case OPC_CMPU_EQ_OB_DSP: 14172 op2 = MASK_CMPU_EQ_OB(ctx->opcode); 14173 switch (op2) { 14174 case OPC_PRECR_SRA_QH_PW: 14175 case OPC_PRECR_SRA_R_QH_PW: 14176 /* Return value is rt. */ 14177 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd); 14178 break; 14179 case OPC_PRECR_OB_QH: 14180 case OPC_PRECRQ_OB_QH: 14181 case OPC_PRECRQ_PW_L: 14182 case OPC_PRECRQ_QH_PW: 14183 case OPC_PRECRQ_RS_QH_PW: 14184 case OPC_PRECRQU_S_OB_QH: 14185 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); 14186 break; 14187 case OPC_CMPU_EQ_OB: 14188 case OPC_CMPU_LT_OB: 14189 case OPC_CMPU_LE_OB: 14190 case OPC_CMP_EQ_QH: 14191 case OPC_CMP_LT_QH: 14192 case OPC_CMP_LE_QH: 14193 case OPC_CMP_EQ_PW: 14194 case OPC_CMP_LT_PW: 14195 case OPC_CMP_LE_PW: 14196 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0); 14197 break; 14198 case OPC_CMPGDU_EQ_OB: 14199 case OPC_CMPGDU_LT_OB: 14200 case OPC_CMPGDU_LE_OB: 14201 case OPC_CMPGU_EQ_OB: 14202 case OPC_CMPGU_LT_OB: 14203 case OPC_CMPGU_LE_OB: 14204 case OPC_PACKRL_PW: 14205 case OPC_PICK_OB: 14206 case OPC_PICK_PW: 14207 case OPC_PICK_QH: 14208 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1); 14209 break; 14210 default: /* Invalid */ 14211 MIPS_INVAL("MASK CMPU_EQ.OB"); 14212 gen_reserved_instruction(ctx); 14213 break; 14214 } 14215 break; 14216 case OPC_DAPPEND_DSP: 14217 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd); 14218 break; 14219 case OPC_DEXTR_W_DSP: 14220 op2 = MASK_DEXTR_W(ctx->opcode); 14221 switch (op2) { 14222 case OPC_DEXTP: 14223 case OPC_DEXTPDP: 14224 case OPC_DEXTPDPV: 14225 case OPC_DEXTPV: 14226 case OPC_DEXTR_L: 14227 case OPC_DEXTR_R_L: 14228 case OPC_DEXTR_RS_L: 14229 case OPC_DEXTR_W: 14230 case OPC_DEXTR_R_W: 14231 case OPC_DEXTR_RS_W: 14232 case OPC_DEXTR_S_H: 14233 case OPC_DEXTRV_L: 14234 case OPC_DEXTRV_R_L: 14235 case OPC_DEXTRV_RS_L: 14236 case OPC_DEXTRV_S_H: 14237 case OPC_DEXTRV_W: 14238 case OPC_DEXTRV_R_W: 14239 case OPC_DEXTRV_RS_W: 14240 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1); 14241 break; 14242 case OPC_DMTHLIP: 14243 case OPC_DSHILO: 14244 case OPC_DSHILOV: 14245 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0); 14246 break; 14247 default: /* Invalid */ 14248 MIPS_INVAL("MASK EXTR.W"); 14249 gen_reserved_instruction(ctx); 14250 break; 14251 } 14252 break; 14253 case OPC_DPAQ_W_QH_DSP: 14254 op2 = MASK_DPAQ_W_QH(ctx->opcode); 14255 switch (op2) { 14256 case OPC_DPAU_H_OBL: 14257 case OPC_DPAU_H_OBR: 14258 case OPC_DPSU_H_OBL: 14259 case OPC_DPSU_H_OBR: 14260 case OPC_DPA_W_QH: 14261 case OPC_DPAQ_S_W_QH: 14262 case OPC_DPS_W_QH: 14263 case OPC_DPSQ_S_W_QH: 14264 case OPC_MULSAQ_S_W_QH: 14265 case OPC_DPAQ_SA_L_PW: 14266 case OPC_DPSQ_SA_L_PW: 14267 case OPC_MULSAQ_S_L_PW: 14268 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); 14269 break; 14270 case OPC_MAQ_S_W_QHLL: 14271 case OPC_MAQ_S_W_QHLR: 14272 case OPC_MAQ_S_W_QHRL: 14273 case OPC_MAQ_S_W_QHRR: 14274 case OPC_MAQ_SA_W_QHLL: 14275 case OPC_MAQ_SA_W_QHLR: 14276 case OPC_MAQ_SA_W_QHRL: 14277 case OPC_MAQ_SA_W_QHRR: 14278 case OPC_MAQ_S_L_PWL: 14279 case OPC_MAQ_S_L_PWR: 14280 case OPC_DMADD: 14281 case OPC_DMADDU: 14282 case OPC_DMSUB: 14283 case OPC_DMSUBU: 14284 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); 14285 break; 14286 default: /* Invalid */ 14287 MIPS_INVAL("MASK DPAQ.W.QH"); 14288 gen_reserved_instruction(ctx); 14289 break; 14290 } 14291 break; 14292 case OPC_DINSV_DSP: 14293 op2 = MASK_INSV(ctx->opcode); 14294 switch (op2) { 14295 case OPC_DINSV: 14296 { 14297 TCGv t0, t1; 14298 14299 check_dsp(ctx); 14300 14301 if (rt == 0) { 14302 break; 14303 } 14304 14305 t0 = tcg_temp_new(); 14306 t1 = tcg_temp_new(); 14307 14308 gen_load_gpr(t0, rt); 14309 gen_load_gpr(t1, rs); 14310 14311 gen_helper_dinsv(cpu_gpr[rt], tcg_env, t1, t0); 14312 break; 14313 } 14314 default: /* Invalid */ 14315 MIPS_INVAL("MASK DINSV"); 14316 gen_reserved_instruction(ctx); 14317 break; 14318 } 14319 break; 14320 case OPC_SHLL_OB_DSP: 14321 gen_mipsdsp_shift(ctx, op1, rd, rs, rt); 14322 break; 14323 #endif 14324 default: /* Invalid */ 14325 MIPS_INVAL("special3_legacy"); 14326 gen_reserved_instruction(ctx); 14327 break; 14328 } 14329 } 14330 14331 14332 #if defined(TARGET_MIPS64) 14333 14334 static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) 14335 { 14336 uint32_t opc = MASK_MMI(ctx->opcode); 14337 int rs = extract32(ctx->opcode, 21, 5); 14338 int rt = extract32(ctx->opcode, 16, 5); 14339 int rd = extract32(ctx->opcode, 11, 5); 14340 14341 switch (opc) { 14342 case MMI_OPC_MULT1: 14343 case MMI_OPC_MULTU1: 14344 case MMI_OPC_MADD: 14345 case MMI_OPC_MADDU: 14346 case MMI_OPC_MADD1: 14347 case MMI_OPC_MADDU1: 14348 gen_mul_txx9(ctx, opc, rd, rs, rt); 14349 break; 14350 case MMI_OPC_DIV1: 14351 case MMI_OPC_DIVU1: 14352 gen_div1_tx79(ctx, opc, rs, rt); 14353 break; 14354 default: 14355 MIPS_INVAL("TX79 MMI class"); 14356 gen_reserved_instruction(ctx); 14357 break; 14358 } 14359 } 14360 14361 static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) 14362 { 14363 gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */ 14364 } 14365 14366 /* 14367 * The TX79-specific instruction Store Quadword 14368 * 14369 * +--------+-------+-------+------------------------+ 14370 * | 011111 | base | rt | offset | SQ 14371 * +--------+-------+-------+------------------------+ 14372 * 6 5 5 16 14373 * 14374 * has the same opcode as the Read Hardware Register instruction 14375 * 14376 * +--------+-------+-------+-------+-------+--------+ 14377 * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR 14378 * +--------+-------+-------+-------+-------+--------+ 14379 * 6 5 5 5 5 6 14380 * 14381 * that is required, trapped and emulated by the Linux kernel. However, all 14382 * RDHWR encodings yield address error exceptions on the TX79 since the SQ 14383 * offset is odd. Therefore all valid SQ instructions can execute normally. 14384 * In user mode, QEMU must verify the upper and lower 11 bits to distinguish 14385 * between SQ and RDHWR, as the Linux kernel does. 14386 */ 14387 static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx) 14388 { 14389 int base = extract32(ctx->opcode, 21, 5); 14390 int rt = extract32(ctx->opcode, 16, 5); 14391 int offset = extract32(ctx->opcode, 0, 16); 14392 14393 #ifdef CONFIG_USER_ONLY 14394 uint32_t op1 = MASK_SPECIAL3(ctx->opcode); 14395 uint32_t op2 = extract32(ctx->opcode, 6, 5); 14396 14397 if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) { 14398 int rd = extract32(ctx->opcode, 11, 5); 14399 14400 gen_rdhwr(ctx, rt, rd, 0); 14401 return; 14402 } 14403 #endif 14404 14405 gen_mmi_sq(ctx, base, rt, offset); 14406 } 14407 14408 #endif 14409 14410 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) 14411 { 14412 int rs, rt, rd, sa; 14413 uint32_t op1, op2; 14414 int16_t imm; 14415 14416 rs = (ctx->opcode >> 21) & 0x1f; 14417 rt = (ctx->opcode >> 16) & 0x1f; 14418 rd = (ctx->opcode >> 11) & 0x1f; 14419 sa = (ctx->opcode >> 6) & 0x1f; 14420 imm = sextract32(ctx->opcode, 7, 9); 14421 14422 op1 = MASK_SPECIAL3(ctx->opcode); 14423 14424 /* 14425 * EVA loads and stores overlap Loongson 2E instructions decoded by 14426 * decode_opc_special3_legacy(), so be careful to allow their decoding when 14427 * EVA is absent. 14428 */ 14429 if (ctx->eva) { 14430 switch (op1) { 14431 case OPC_LWLE: 14432 case OPC_LWRE: 14433 case OPC_LBUE: 14434 case OPC_LHUE: 14435 case OPC_LBE: 14436 case OPC_LHE: 14437 case OPC_LLE: 14438 case OPC_LWE: 14439 check_cp0_enabled(ctx); 14440 gen_ld(ctx, op1, rt, rs, imm); 14441 return; 14442 case OPC_SWLE: 14443 case OPC_SWRE: 14444 case OPC_SBE: 14445 case OPC_SHE: 14446 case OPC_SWE: 14447 check_cp0_enabled(ctx); 14448 gen_st(ctx, op1, rt, rs, imm); 14449 return; 14450 case OPC_SCE: 14451 check_cp0_enabled(ctx); 14452 gen_st_cond(ctx, rt, rs, imm, MO_TESL, true); 14453 return; 14454 case OPC_CACHEE: 14455 check_eva(ctx); 14456 check_cp0_enabled(ctx); 14457 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 14458 gen_cache_operation(ctx, rt, rs, imm); 14459 } 14460 return; 14461 case OPC_PREFE: 14462 check_cp0_enabled(ctx); 14463 /* Treat as NOP. */ 14464 return; 14465 } 14466 } 14467 14468 switch (op1) { 14469 case OPC_EXT: 14470 case OPC_INS: 14471 check_insn(ctx, ISA_MIPS_R2); 14472 gen_bitops(ctx, op1, rt, rs, sa, rd); 14473 break; 14474 case OPC_BSHFL: 14475 op2 = MASK_BSHFL(ctx->opcode); 14476 switch (op2) { 14477 case OPC_ALIGN: 14478 case OPC_ALIGN_1: 14479 case OPC_ALIGN_2: 14480 case OPC_ALIGN_3: 14481 case OPC_BITSWAP: 14482 check_insn(ctx, ISA_MIPS_R6); 14483 decode_opc_special3_r6(env, ctx); 14484 break; 14485 default: 14486 check_insn(ctx, ISA_MIPS_R2); 14487 gen_bshfl(ctx, op2, rt, rd); 14488 break; 14489 } 14490 break; 14491 #if defined(TARGET_MIPS64) 14492 case OPC_DEXTM: 14493 case OPC_DEXTU: 14494 case OPC_DEXT: 14495 case OPC_DINSM: 14496 case OPC_DINSU: 14497 case OPC_DINS: 14498 check_insn(ctx, ISA_MIPS_R2); 14499 check_mips_64(ctx); 14500 gen_bitops(ctx, op1, rt, rs, sa, rd); 14501 break; 14502 case OPC_DBSHFL: 14503 op2 = MASK_DBSHFL(ctx->opcode); 14504 switch (op2) { 14505 case OPC_DALIGN: 14506 case OPC_DALIGN_1: 14507 case OPC_DALIGN_2: 14508 case OPC_DALIGN_3: 14509 case OPC_DALIGN_4: 14510 case OPC_DALIGN_5: 14511 case OPC_DALIGN_6: 14512 case OPC_DALIGN_7: 14513 case OPC_DBITSWAP: 14514 check_insn(ctx, ISA_MIPS_R6); 14515 decode_opc_special3_r6(env, ctx); 14516 break; 14517 default: 14518 check_insn(ctx, ISA_MIPS_R2); 14519 check_mips_64(ctx); 14520 op2 = MASK_DBSHFL(ctx->opcode); 14521 gen_bshfl(ctx, op2, rt, rd); 14522 break; 14523 } 14524 break; 14525 #endif 14526 case OPC_RDHWR: 14527 gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3)); 14528 break; 14529 case OPC_FORK: 14530 check_mt(ctx); 14531 { 14532 TCGv t0 = tcg_temp_new(); 14533 TCGv t1 = tcg_temp_new(); 14534 14535 gen_load_gpr(t0, rt); 14536 gen_load_gpr(t1, rs); 14537 gen_helper_fork(t0, t1); 14538 } 14539 break; 14540 case OPC_YIELD: 14541 check_mt(ctx); 14542 { 14543 TCGv t0 = tcg_temp_new(); 14544 14545 gen_load_gpr(t0, rs); 14546 gen_helper_yield(t0, tcg_env, t0); 14547 gen_store_gpr(t0, rd); 14548 } 14549 break; 14550 default: 14551 if (ctx->insn_flags & ISA_MIPS_R6) { 14552 decode_opc_special3_r6(env, ctx); 14553 } else { 14554 decode_opc_special3_legacy(env, ctx); 14555 } 14556 } 14557 } 14558 14559 static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) 14560 { 14561 int32_t offset; 14562 int rs, rt, rd, sa; 14563 uint32_t op, op1; 14564 int16_t imm; 14565 14566 op = MASK_OP_MAJOR(ctx->opcode); 14567 rs = (ctx->opcode >> 21) & 0x1f; 14568 rt = (ctx->opcode >> 16) & 0x1f; 14569 rd = (ctx->opcode >> 11) & 0x1f; 14570 sa = (ctx->opcode >> 6) & 0x1f; 14571 imm = (int16_t)ctx->opcode; 14572 switch (op) { 14573 case OPC_SPECIAL: 14574 decode_opc_special(env, ctx); 14575 break; 14576 case OPC_SPECIAL2: 14577 #if defined(TARGET_MIPS64) 14578 if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) { 14579 decode_mmi(env, ctx); 14580 break; 14581 } 14582 #endif 14583 if (TARGET_LONG_BITS == 32 && (ctx->insn_flags & ASE_MXU)) { 14584 if (decode_ase_mxu(ctx, ctx->opcode)) { 14585 break; 14586 } 14587 } 14588 decode_opc_special2_legacy(env, ctx); 14589 break; 14590 case OPC_SPECIAL3: 14591 #if defined(TARGET_MIPS64) 14592 if (ctx->insn_flags & INSN_R5900) { 14593 decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */ 14594 } else { 14595 decode_opc_special3(env, ctx); 14596 } 14597 #else 14598 decode_opc_special3(env, ctx); 14599 #endif 14600 break; 14601 case OPC_REGIMM: 14602 op1 = MASK_REGIMM(ctx->opcode); 14603 switch (op1) { 14604 case OPC_BLTZL: /* REGIMM branches */ 14605 case OPC_BGEZL: 14606 case OPC_BLTZALL: 14607 case OPC_BGEZALL: 14608 check_insn(ctx, ISA_MIPS2); 14609 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14610 /* Fallthrough */ 14611 case OPC_BLTZ: 14612 case OPC_BGEZ: 14613 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); 14614 break; 14615 case OPC_BLTZAL: 14616 case OPC_BGEZAL: 14617 if (ctx->insn_flags & ISA_MIPS_R6) { 14618 if (rs == 0) { 14619 /* OPC_NAL, OPC_BAL */ 14620 gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); 14621 } else { 14622 gen_reserved_instruction(ctx); 14623 } 14624 } else { 14625 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); 14626 } 14627 break; 14628 case OPC_TGEI: /* REGIMM traps */ 14629 case OPC_TGEIU: 14630 case OPC_TLTI: 14631 case OPC_TLTIU: 14632 case OPC_TEQI: 14633 case OPC_TNEI: 14634 check_insn(ctx, ISA_MIPS2); 14635 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14636 gen_trap(ctx, op1, rs, -1, imm, 0); 14637 break; 14638 case OPC_SIGRIE: 14639 check_insn(ctx, ISA_MIPS_R6); 14640 gen_reserved_instruction(ctx); 14641 break; 14642 case OPC_SYNCI: 14643 check_insn(ctx, ISA_MIPS_R2); 14644 /* 14645 * Break the TB to be able to sync copied instructions 14646 * immediately. 14647 */ 14648 ctx->base.is_jmp = DISAS_STOP; 14649 break; 14650 case OPC_BPOSGE32: /* MIPS DSP branch */ 14651 #if defined(TARGET_MIPS64) 14652 case OPC_BPOSGE64: 14653 #endif 14654 check_dsp(ctx); 14655 gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2, 4); 14656 break; 14657 #if defined(TARGET_MIPS64) 14658 case OPC_DAHI: 14659 check_insn(ctx, ISA_MIPS_R6); 14660 check_mips_64(ctx); 14661 if (rs != 0) { 14662 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32); 14663 } 14664 break; 14665 case OPC_DATI: 14666 check_insn(ctx, ISA_MIPS_R6); 14667 check_mips_64(ctx); 14668 if (rs != 0) { 14669 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48); 14670 } 14671 break; 14672 #endif 14673 default: /* Invalid */ 14674 MIPS_INVAL("regimm"); 14675 gen_reserved_instruction(ctx); 14676 break; 14677 } 14678 break; 14679 case OPC_CP0: 14680 check_cp0_enabled(ctx); 14681 op1 = MASK_CP0(ctx->opcode); 14682 switch (op1) { 14683 case OPC_MFC0: 14684 case OPC_MTC0: 14685 case OPC_MFTR: 14686 case OPC_MTTR: 14687 case OPC_MFHC0: 14688 case OPC_MTHC0: 14689 #if defined(TARGET_MIPS64) 14690 case OPC_DMFC0: 14691 case OPC_DMTC0: 14692 #endif 14693 #ifndef CONFIG_USER_ONLY 14694 gen_cp0(env, ctx, op1, rt, rd); 14695 #endif /* !CONFIG_USER_ONLY */ 14696 break; 14697 case OPC_C0: 14698 case OPC_C0_1: 14699 case OPC_C0_2: 14700 case OPC_C0_3: 14701 case OPC_C0_4: 14702 case OPC_C0_5: 14703 case OPC_C0_6: 14704 case OPC_C0_7: 14705 case OPC_C0_8: 14706 case OPC_C0_9: 14707 case OPC_C0_A: 14708 case OPC_C0_B: 14709 case OPC_C0_C: 14710 case OPC_C0_D: 14711 case OPC_C0_E: 14712 case OPC_C0_F: 14713 #ifndef CONFIG_USER_ONLY 14714 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); 14715 #endif /* !CONFIG_USER_ONLY */ 14716 break; 14717 case OPC_MFMC0: 14718 #ifndef CONFIG_USER_ONLY 14719 { 14720 uint32_t op2; 14721 TCGv t0 = tcg_temp_new(); 14722 14723 op2 = MASK_MFMC0(ctx->opcode); 14724 switch (op2) { 14725 case OPC_DMT: 14726 check_cp0_mt(ctx); 14727 gen_helper_dmt(t0); 14728 gen_store_gpr(t0, rt); 14729 break; 14730 case OPC_EMT: 14731 check_cp0_mt(ctx); 14732 gen_helper_emt(t0); 14733 gen_store_gpr(t0, rt); 14734 break; 14735 case OPC_DVPE: 14736 check_cp0_mt(ctx); 14737 gen_helper_dvpe(t0, tcg_env); 14738 gen_store_gpr(t0, rt); 14739 break; 14740 case OPC_EVPE: 14741 check_cp0_mt(ctx); 14742 gen_helper_evpe(t0, tcg_env); 14743 gen_store_gpr(t0, rt); 14744 break; 14745 case OPC_DVP: 14746 check_insn(ctx, ISA_MIPS_R6); 14747 if (ctx->vp) { 14748 gen_helper_dvp(t0, tcg_env); 14749 gen_store_gpr(t0, rt); 14750 } 14751 break; 14752 case OPC_EVP: 14753 check_insn(ctx, ISA_MIPS_R6); 14754 if (ctx->vp) { 14755 gen_helper_evp(t0, tcg_env); 14756 gen_store_gpr(t0, rt); 14757 } 14758 break; 14759 case OPC_DI: 14760 check_insn(ctx, ISA_MIPS_R2); 14761 save_cpu_state(ctx, 1); 14762 gen_helper_di(t0, tcg_env); 14763 gen_store_gpr(t0, rt); 14764 /* 14765 * Stop translation as we may have switched 14766 * the execution mode. 14767 */ 14768 ctx->base.is_jmp = DISAS_STOP; 14769 break; 14770 case OPC_EI: 14771 check_insn(ctx, ISA_MIPS_R2); 14772 save_cpu_state(ctx, 1); 14773 gen_helper_ei(t0, tcg_env); 14774 gen_store_gpr(t0, rt); 14775 /* 14776 * DISAS_STOP isn't sufficient, we need to ensure we break 14777 * out of translated code to check for pending interrupts. 14778 */ 14779 gen_save_pc(ctx->base.pc_next + 4); 14780 ctx->base.is_jmp = DISAS_EXIT; 14781 break; 14782 default: /* Invalid */ 14783 MIPS_INVAL("mfmc0"); 14784 gen_reserved_instruction(ctx); 14785 break; 14786 } 14787 } 14788 #endif /* !CONFIG_USER_ONLY */ 14789 break; 14790 case OPC_RDPGPR: 14791 check_insn(ctx, ISA_MIPS_R2); 14792 gen_load_srsgpr(rt, rd); 14793 break; 14794 case OPC_WRPGPR: 14795 check_insn(ctx, ISA_MIPS_R2); 14796 gen_store_srsgpr(rt, rd); 14797 break; 14798 default: 14799 MIPS_INVAL("cp0"); 14800 gen_reserved_instruction(ctx); 14801 break; 14802 } 14803 break; 14804 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */ 14805 if (ctx->insn_flags & ISA_MIPS_R6) { 14806 /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */ 14807 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14808 } else { 14809 /* OPC_ADDI */ 14810 /* Arithmetic with immediate opcode */ 14811 gen_arith_imm(ctx, op, rt, rs, imm); 14812 } 14813 break; 14814 case OPC_ADDIU: 14815 gen_arith_imm(ctx, op, rt, rs, imm); 14816 break; 14817 case OPC_SLTI: /* Set on less than with immediate opcode */ 14818 case OPC_SLTIU: 14819 gen_slt_imm(ctx, op, rt, rs, imm); 14820 break; 14821 case OPC_ANDI: /* Arithmetic with immediate opcode */ 14822 case OPC_LUI: /* OPC_AUI */ 14823 case OPC_ORI: 14824 case OPC_XORI: 14825 gen_logic_imm(ctx, op, rt, rs, imm); 14826 break; 14827 case OPC_J: /* Jump */ 14828 case OPC_JAL: 14829 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; 14830 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); 14831 break; 14832 /* Branch */ 14833 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */ 14834 if (ctx->insn_flags & ISA_MIPS_R6) { 14835 if (rt == 0) { 14836 gen_reserved_instruction(ctx); 14837 break; 14838 } 14839 /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */ 14840 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14841 } else { 14842 /* OPC_BLEZL */ 14843 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14844 } 14845 break; 14846 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */ 14847 if (ctx->insn_flags & ISA_MIPS_R6) { 14848 if (rt == 0) { 14849 gen_reserved_instruction(ctx); 14850 break; 14851 } 14852 /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */ 14853 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14854 } else { 14855 /* OPC_BGTZL */ 14856 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14857 } 14858 break; 14859 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC, OPC_BLEZ */ 14860 if (rt == 0) { 14861 /* OPC_BLEZ */ 14862 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14863 } else { 14864 check_insn(ctx, ISA_MIPS_R6); 14865 /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */ 14866 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14867 } 14868 break; 14869 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC, OPC_BGTZ */ 14870 if (rt == 0) { 14871 /* OPC_BGTZ */ 14872 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14873 } else { 14874 check_insn(ctx, ISA_MIPS_R6); 14875 /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */ 14876 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 14877 } 14878 break; 14879 case OPC_BEQL: 14880 case OPC_BNEL: 14881 check_insn(ctx, ISA_MIPS2); 14882 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14883 /* Fallthrough */ 14884 case OPC_BEQ: 14885 case OPC_BNE: 14886 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); 14887 break; 14888 case OPC_LL: /* Load and stores */ 14889 check_insn(ctx, ISA_MIPS2); 14890 if (ctx->insn_flags & INSN_R5900) { 14891 check_insn_opc_user_only(ctx, INSN_R5900); 14892 } 14893 /* Fallthrough */ 14894 case OPC_LWL: 14895 case OPC_LWR: 14896 case OPC_LB: 14897 case OPC_LH: 14898 case OPC_LW: 14899 case OPC_LWPC: 14900 case OPC_LBU: 14901 case OPC_LHU: 14902 gen_ld(ctx, op, rt, rs, imm); 14903 break; 14904 case OPC_SWL: 14905 case OPC_SWR: 14906 case OPC_SB: 14907 case OPC_SH: 14908 case OPC_SW: 14909 gen_st(ctx, op, rt, rs, imm); 14910 break; 14911 case OPC_SC: 14912 check_insn(ctx, ISA_MIPS2); 14913 if (ctx->insn_flags & INSN_R5900) { 14914 check_insn_opc_user_only(ctx, INSN_R5900); 14915 } 14916 gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); 14917 break; 14918 case OPC_CACHE: 14919 check_cp0_enabled(ctx); 14920 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); 14921 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { 14922 gen_cache_operation(ctx, rt, rs, imm); 14923 } 14924 /* Treat as NOP. */ 14925 break; 14926 case OPC_PREF: 14927 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_R5900); 14928 /* Treat as NOP. */ 14929 break; 14930 14931 /* Floating point (COP1). */ 14932 case OPC_LWC1: 14933 case OPC_LDC1: 14934 case OPC_SWC1: 14935 case OPC_SDC1: 14936 gen_cop1_ldst(ctx, op, rt, rs, imm); 14937 break; 14938 14939 case OPC_CP1: 14940 op1 = MASK_CP1(ctx->opcode); 14941 14942 switch (op1) { 14943 case OPC_MFHC1: 14944 case OPC_MTHC1: 14945 check_cp1_enabled(ctx); 14946 check_insn(ctx, ISA_MIPS_R2); 14947 /* fall through */ 14948 case OPC_MFC1: 14949 case OPC_CFC1: 14950 case OPC_MTC1: 14951 case OPC_CTC1: 14952 check_cp1_enabled(ctx); 14953 gen_cp1(ctx, op1, rt, rd); 14954 break; 14955 #if defined(TARGET_MIPS64) 14956 case OPC_DMFC1: 14957 case OPC_DMTC1: 14958 check_cp1_enabled(ctx); 14959 check_insn(ctx, ISA_MIPS3); 14960 check_mips_64(ctx); 14961 gen_cp1(ctx, op1, rt, rd); 14962 break; 14963 #endif 14964 case OPC_BC1EQZ: /* OPC_BC1ANY2 */ 14965 check_cp1_enabled(ctx); 14966 if (ctx->insn_flags & ISA_MIPS_R6) { 14967 /* OPC_BC1EQZ */ 14968 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), 14969 rt, imm << 2, 4); 14970 } else { 14971 /* OPC_BC1ANY2 */ 14972 check_cop1x(ctx); 14973 check_insn(ctx, ASE_MIPS3D); 14974 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), 14975 (rt >> 2) & 0x7, imm << 2); 14976 } 14977 break; 14978 case OPC_BC1NEZ: 14979 check_cp1_enabled(ctx); 14980 check_insn(ctx, ISA_MIPS_R6); 14981 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), 14982 rt, imm << 2, 4); 14983 break; 14984 case OPC_BC1ANY4: 14985 check_cp1_enabled(ctx); 14986 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14987 check_cop1x(ctx); 14988 check_insn(ctx, ASE_MIPS3D); 14989 /* fall through */ 14990 case OPC_BC1: 14991 check_cp1_enabled(ctx); 14992 check_insn_opc_removed(ctx, ISA_MIPS_R6); 14993 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), 14994 (rt >> 2) & 0x7, imm << 2); 14995 break; 14996 case OPC_PS_FMT: 14997 check_ps(ctx); 14998 /* fall through */ 14999 case OPC_S_FMT: 15000 case OPC_D_FMT: 15001 check_cp1_enabled(ctx); 15002 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, 15003 (imm >> 8) & 0x7); 15004 break; 15005 case OPC_W_FMT: 15006 case OPC_L_FMT: 15007 { 15008 int r6_op = ctx->opcode & FOP(0x3f, 0x1f); 15009 check_cp1_enabled(ctx); 15010 if (ctx->insn_flags & ISA_MIPS_R6) { 15011 switch (r6_op) { 15012 case R6_OPC_CMP_AF_S: 15013 case R6_OPC_CMP_UN_S: 15014 case R6_OPC_CMP_EQ_S: 15015 case R6_OPC_CMP_UEQ_S: 15016 case R6_OPC_CMP_LT_S: 15017 case R6_OPC_CMP_ULT_S: 15018 case R6_OPC_CMP_LE_S: 15019 case R6_OPC_CMP_ULE_S: 15020 case R6_OPC_CMP_SAF_S: 15021 case R6_OPC_CMP_SUN_S: 15022 case R6_OPC_CMP_SEQ_S: 15023 case R6_OPC_CMP_SEUQ_S: 15024 case R6_OPC_CMP_SLT_S: 15025 case R6_OPC_CMP_SULT_S: 15026 case R6_OPC_CMP_SLE_S: 15027 case R6_OPC_CMP_SULE_S: 15028 case R6_OPC_CMP_OR_S: 15029 case R6_OPC_CMP_UNE_S: 15030 case R6_OPC_CMP_NE_S: 15031 case R6_OPC_CMP_SOR_S: 15032 case R6_OPC_CMP_SUNE_S: 15033 case R6_OPC_CMP_SNE_S: 15034 gen_r6_cmp_s(ctx, ctx->opcode & 0x1f, rt, rd, sa); 15035 break; 15036 case R6_OPC_CMP_AF_D: 15037 case R6_OPC_CMP_UN_D: 15038 case R6_OPC_CMP_EQ_D: 15039 case R6_OPC_CMP_UEQ_D: 15040 case R6_OPC_CMP_LT_D: 15041 case R6_OPC_CMP_ULT_D: 15042 case R6_OPC_CMP_LE_D: 15043 case R6_OPC_CMP_ULE_D: 15044 case R6_OPC_CMP_SAF_D: 15045 case R6_OPC_CMP_SUN_D: 15046 case R6_OPC_CMP_SEQ_D: 15047 case R6_OPC_CMP_SEUQ_D: 15048 case R6_OPC_CMP_SLT_D: 15049 case R6_OPC_CMP_SULT_D: 15050 case R6_OPC_CMP_SLE_D: 15051 case R6_OPC_CMP_SULE_D: 15052 case R6_OPC_CMP_OR_D: 15053 case R6_OPC_CMP_UNE_D: 15054 case R6_OPC_CMP_NE_D: 15055 case R6_OPC_CMP_SOR_D: 15056 case R6_OPC_CMP_SUNE_D: 15057 case R6_OPC_CMP_SNE_D: 15058 gen_r6_cmp_d(ctx, ctx->opcode & 0x1f, rt, rd, sa); 15059 break; 15060 default: 15061 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), 15062 rt, rd, sa, (imm >> 8) & 0x7); 15063 15064 break; 15065 } 15066 } else { 15067 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, 15068 (imm >> 8) & 0x7); 15069 } 15070 break; 15071 } 15072 default: 15073 MIPS_INVAL("cp1"); 15074 gen_reserved_instruction(ctx); 15075 break; 15076 } 15077 break; 15078 15079 /* Compact branches [R6] and COP2 [non-R6] */ 15080 case OPC_BC: /* OPC_LWC2 */ 15081 case OPC_BALC: /* OPC_SWC2 */ 15082 if (ctx->insn_flags & ISA_MIPS_R6) { 15083 /* OPC_BC, OPC_BALC */ 15084 gen_compute_compact_branch(ctx, op, 0, 0, 15085 sextract32(ctx->opcode << 2, 0, 28)); 15086 } else if (ctx->insn_flags & ASE_LEXT) { 15087 gen_loongson_lswc2(ctx, rt, rs, rd); 15088 } else { 15089 /* OPC_LWC2, OPC_SWC2 */ 15090 /* COP2: Not implemented. */ 15091 generate_exception_err(ctx, EXCP_CpU, 2); 15092 } 15093 break; 15094 case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */ 15095 case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */ 15096 if (ctx->insn_flags & ISA_MIPS_R6) { 15097 if (rs != 0) { 15098 /* OPC_BEQZC, OPC_BNEZC */ 15099 gen_compute_compact_branch(ctx, op, rs, 0, 15100 sextract32(ctx->opcode << 2, 0, 23)); 15101 } else { 15102 /* OPC_JIC, OPC_JIALC */ 15103 gen_compute_compact_branch(ctx, op, 0, rt, imm); 15104 } 15105 } else if (ctx->insn_flags & ASE_LEXT) { 15106 gen_loongson_lsdc2(ctx, rt, rs, rd); 15107 } else { 15108 /* OPC_LWC2, OPC_SWC2 */ 15109 /* COP2: Not implemented. */ 15110 generate_exception_err(ctx, EXCP_CpU, 2); 15111 } 15112 break; 15113 case OPC_CP2: 15114 check_insn(ctx, ASE_LMMI); 15115 /* Note that these instructions use different fields. */ 15116 gen_loongson_multimedia(ctx, sa, rd, rt); 15117 break; 15118 15119 case OPC_CP3: 15120 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { 15121 check_cp1_enabled(ctx); 15122 op1 = MASK_CP3(ctx->opcode); 15123 switch (op1) { 15124 case OPC_LUXC1: 15125 case OPC_SUXC1: 15126 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); 15127 /* Fallthrough */ 15128 case OPC_LWXC1: 15129 case OPC_LDXC1: 15130 case OPC_SWXC1: 15131 case OPC_SDXC1: 15132 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); 15133 gen_flt3_ldst(ctx, op1, sa, rd, rs, rt); 15134 break; 15135 case OPC_PREFX: 15136 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); 15137 /* Treat as NOP. */ 15138 break; 15139 case OPC_ALNV_PS: 15140 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); 15141 /* Fallthrough */ 15142 case OPC_MADD_S: 15143 case OPC_MADD_D: 15144 case OPC_MADD_PS: 15145 case OPC_MSUB_S: 15146 case OPC_MSUB_D: 15147 case OPC_MSUB_PS: 15148 case OPC_NMADD_S: 15149 case OPC_NMADD_D: 15150 case OPC_NMADD_PS: 15151 case OPC_NMSUB_S: 15152 case OPC_NMSUB_D: 15153 case OPC_NMSUB_PS: 15154 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); 15155 gen_flt3_arith(ctx, op1, sa, rs, rd, rt); 15156 break; 15157 default: 15158 MIPS_INVAL("cp3"); 15159 gen_reserved_instruction(ctx); 15160 break; 15161 } 15162 } else { 15163 generate_exception_err(ctx, EXCP_CpU, 1); 15164 } 15165 break; 15166 15167 #if defined(TARGET_MIPS64) 15168 /* MIPS64 opcodes */ 15169 case OPC_LLD: 15170 if (ctx->insn_flags & INSN_R5900) { 15171 check_insn_opc_user_only(ctx, INSN_R5900); 15172 } 15173 /* fall through */ 15174 case OPC_LDL: 15175 case OPC_LDR: 15176 case OPC_LWU: 15177 case OPC_LD: 15178 check_insn(ctx, ISA_MIPS3); 15179 check_mips_64(ctx); 15180 gen_ld(ctx, op, rt, rs, imm); 15181 break; 15182 case OPC_SDL: 15183 case OPC_SDR: 15184 case OPC_SD: 15185 check_insn(ctx, ISA_MIPS3); 15186 check_mips_64(ctx); 15187 gen_st(ctx, op, rt, rs, imm); 15188 break; 15189 case OPC_SCD: 15190 check_insn(ctx, ISA_MIPS3); 15191 if (ctx->insn_flags & INSN_R5900) { 15192 check_insn_opc_user_only(ctx, INSN_R5900); 15193 } 15194 check_mips_64(ctx); 15195 gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false); 15196 break; 15197 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ 15198 if (ctx->insn_flags & ISA_MIPS_R6) { 15199 /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */ 15200 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 15201 } else { 15202 /* OPC_DADDI */ 15203 check_insn(ctx, ISA_MIPS3); 15204 check_mips_64(ctx); 15205 gen_arith_imm(ctx, op, rt, rs, imm); 15206 } 15207 break; 15208 case OPC_DADDIU: 15209 check_insn(ctx, ISA_MIPS3); 15210 check_mips_64(ctx); 15211 gen_arith_imm(ctx, op, rt, rs, imm); 15212 break; 15213 #else 15214 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ 15215 if (ctx->insn_flags & ISA_MIPS_R6) { 15216 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); 15217 } else { 15218 MIPS_INVAL("major opcode"); 15219 gen_reserved_instruction(ctx); 15220 } 15221 break; 15222 #endif 15223 case OPC_DAUI: /* OPC_JALX */ 15224 if (ctx->insn_flags & ISA_MIPS_R6) { 15225 #if defined(TARGET_MIPS64) 15226 /* OPC_DAUI */ 15227 check_mips_64(ctx); 15228 if (rs == 0) { 15229 generate_exception(ctx, EXCP_RI); 15230 } else if (rt != 0) { 15231 TCGv t0 = tcg_temp_new(); 15232 gen_load_gpr(t0, rs); 15233 tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16); 15234 } 15235 #else 15236 gen_reserved_instruction(ctx); 15237 MIPS_INVAL("major opcode"); 15238 #endif 15239 } else { 15240 /* OPC_JALX */ 15241 check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS); 15242 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; 15243 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); 15244 } 15245 break; 15246 case OPC_MDMX: 15247 /* MDMX: Not implemented. */ 15248 break; 15249 case OPC_PCREL: 15250 check_insn(ctx, ISA_MIPS_R6); 15251 gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs); 15252 break; 15253 default: /* Invalid */ 15254 MIPS_INVAL("major opcode"); 15255 return false; 15256 } 15257 return true; 15258 } 15259 15260 static void decode_opc(CPUMIPSState *env, DisasContext *ctx) 15261 { 15262 /* make sure instructions are on a word boundary */ 15263 if (ctx->base.pc_next & 0x3) { 15264 env->CP0_BadVAddr = ctx->base.pc_next; 15265 generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL); 15266 return; 15267 } 15268 15269 /* Handle blikely not taken case */ 15270 if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) { 15271 TCGLabel *l1 = gen_new_label(); 15272 15273 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); 15274 tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); 15275 gen_goto_tb(ctx, 1, ctx->base.pc_next + 4); 15276 gen_set_label(l1); 15277 } 15278 15279 /* Transition to the auto-generated decoder. */ 15280 15281 /* Vendor specific extensions */ 15282 if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) { 15283 return; 15284 } 15285 if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) { 15286 return; 15287 } 15288 #if defined(TARGET_MIPS64) 15289 if (ase_lcsr_available(env) && decode_ase_lcsr(ctx, ctx->opcode)) { 15290 return; 15291 } 15292 if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) { 15293 return; 15294 } 15295 #endif 15296 15297 /* ISA extensions */ 15298 if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { 15299 return; 15300 } 15301 15302 /* ISA (from latest to oldest) */ 15303 if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) { 15304 return; 15305 } 15306 15307 if (decode_opc_legacy(env, ctx)) { 15308 return; 15309 } 15310 15311 gen_reserved_instruction(ctx); 15312 } 15313 15314 static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 15315 { 15316 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15317 CPUMIPSState *env = cpu_env(cs); 15318 15319 ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 15320 ctx->saved_pc = -1; 15321 ctx->insn_flags = env->insn_flags; 15322 ctx->CP0_Config0 = env->CP0_Config0; 15323 ctx->CP0_Config1 = env->CP0_Config1; 15324 ctx->CP0_Config2 = env->CP0_Config2; 15325 ctx->CP0_Config3 = env->CP0_Config3; 15326 ctx->CP0_Config5 = env->CP0_Config5; 15327 ctx->btarget = 0; 15328 ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; 15329 ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1; 15330 ctx->ie = (env->CP0_Config4 >> CP0C4_IE) & 3; 15331 ctx->bi = (env->CP0_Config3 >> CP0C3_BI) & 1; 15332 ctx->bp = (env->CP0_Config3 >> CP0C3_BP) & 1; 15333 ctx->PAMask = env->PAMask; 15334 ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1; 15335 ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1; 15336 ctx->sc = (env->CP0_Config3 >> CP0C3_SC) & 1; 15337 ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift; 15338 ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1; 15339 /* Restore delay slot state from the tb context. */ 15340 ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? */ 15341 ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1; 15342 ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || 15343 (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)); 15344 ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1; 15345 ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1; 15346 ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; 15347 ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; 15348 ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1; 15349 ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3; 15350 restore_cpu_state(env, ctx); 15351 #ifdef CONFIG_USER_ONLY 15352 ctx->mem_idx = MIPS_HFLAG_UM; 15353 #else 15354 ctx->mem_idx = hflags_mmu_index(ctx->hflags); 15355 #endif 15356 ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) && 15357 (ctx->insn_flags & (ISA_MIPS_R6 | 15358 INSN_LOONGSON3A))) ? MO_UNALN : MO_ALIGN; 15359 15360 /* 15361 * Execute a branch and its delay slot as a single instruction. 15362 * This is what GDB expects and is consistent with what the 15363 * hardware does (e.g. if a delay slot instruction faults, the 15364 * reported PC is the PC of the branch). 15365 */ 15366 if (ctx->base.singlestep_enabled && (ctx->hflags & MIPS_HFLAG_BMASK)) { 15367 ctx->base.max_insns = 2; 15368 } 15369 15370 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, 15371 ctx->hflags); 15372 } 15373 15374 static void mips_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) 15375 { 15376 } 15377 15378 static void mips_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 15379 { 15380 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15381 15382 tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK, 15383 ctx->btarget); 15384 } 15385 15386 static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 15387 { 15388 CPUMIPSState *env = cpu_env(cs); 15389 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15390 int insn_bytes; 15391 int is_slot; 15392 15393 is_slot = ctx->hflags & MIPS_HFLAG_BMASK; 15394 if (ctx->insn_flags & ISA_NANOMIPS32) { 15395 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); 15396 insn_bytes = decode_isa_nanomips(env, ctx); 15397 } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { 15398 ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next); 15399 insn_bytes = 4; 15400 decode_opc(env, ctx); 15401 } else if (ctx->insn_flags & ASE_MICROMIPS) { 15402 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); 15403 insn_bytes = decode_isa_micromips(env, ctx); 15404 } else if (ctx->insn_flags & ASE_MIPS16) { 15405 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); 15406 insn_bytes = decode_ase_mips16e(env, ctx); 15407 } else { 15408 gen_reserved_instruction(ctx); 15409 g_assert(ctx->base.is_jmp == DISAS_NORETURN); 15410 return; 15411 } 15412 15413 if (ctx->hflags & MIPS_HFLAG_BMASK) { 15414 if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 | 15415 MIPS_HFLAG_FBNSLOT))) { 15416 /* 15417 * Force to generate branch as there is neither delay nor 15418 * forbidden slot. 15419 */ 15420 is_slot = 1; 15421 } 15422 if ((ctx->hflags & MIPS_HFLAG_M16) && 15423 (ctx->hflags & MIPS_HFLAG_FBNSLOT)) { 15424 /* 15425 * Force to generate branch as microMIPS R6 doesn't restrict 15426 * branches in the forbidden slot. 15427 */ 15428 is_slot = 1; 15429 } 15430 } 15431 if (is_slot) { 15432 gen_branch(ctx, insn_bytes); 15433 } 15434 if (ctx->base.is_jmp == DISAS_SEMIHOST) { 15435 generate_exception_err(ctx, EXCP_SEMIHOST, insn_bytes); 15436 } 15437 ctx->base.pc_next += insn_bytes; 15438 15439 if (ctx->base.is_jmp != DISAS_NEXT) { 15440 return; 15441 } 15442 15443 /* 15444 * End the TB on (most) page crossings. 15445 * See mips_tr_init_disas_context about single-stepping a branch 15446 * together with its delay slot. 15447 */ 15448 if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE 15449 && !ctx->base.singlestep_enabled) { 15450 ctx->base.is_jmp = DISAS_TOO_MANY; 15451 } 15452 } 15453 15454 static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 15455 { 15456 DisasContext *ctx = container_of(dcbase, DisasContext, base); 15457 15458 switch (ctx->base.is_jmp) { 15459 case DISAS_STOP: 15460 gen_save_pc(ctx->base.pc_next); 15461 tcg_gen_lookup_and_goto_ptr(); 15462 break; 15463 case DISAS_NEXT: 15464 case DISAS_TOO_MANY: 15465 save_cpu_state(ctx, 0); 15466 gen_goto_tb(ctx, 0, ctx->base.pc_next); 15467 break; 15468 case DISAS_EXIT: 15469 tcg_gen_exit_tb(NULL, 0); 15470 break; 15471 case DISAS_NORETURN: 15472 break; 15473 default: 15474 g_assert_not_reached(); 15475 } 15476 } 15477 15478 static void mips_tr_disas_log(const DisasContextBase *dcbase, 15479 CPUState *cs, FILE *logfile) 15480 { 15481 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 15482 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 15483 } 15484 15485 static const TranslatorOps mips_tr_ops = { 15486 .init_disas_context = mips_tr_init_disas_context, 15487 .tb_start = mips_tr_tb_start, 15488 .insn_start = mips_tr_insn_start, 15489 .translate_insn = mips_tr_translate_insn, 15490 .tb_stop = mips_tr_tb_stop, 15491 .disas_log = mips_tr_disas_log, 15492 }; 15493 15494 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 15495 vaddr pc, void *host_pc) 15496 { 15497 DisasContext ctx; 15498 15499 translator_loop(cs, tb, max_insns, pc, host_pc, &mips_tr_ops, &ctx.base); 15500 } 15501 15502 void mips_tcg_init(void) 15503 { 15504 cpu_gpr[0] = NULL; 15505 for (unsigned i = 1; i < 32; i++) 15506 cpu_gpr[i] = tcg_global_mem_new(tcg_env, 15507 offsetof(CPUMIPSState, 15508 active_tc.gpr[i]), 15509 regnames[i]); 15510 #if defined(TARGET_MIPS64) 15511 cpu_gpr_hi[0] = NULL; 15512 15513 for (unsigned i = 1; i < 32; i++) { 15514 g_autofree char *rname = g_strdup_printf("%s[hi]", regnames[i]); 15515 15516 cpu_gpr_hi[i] = tcg_global_mem_new_i64(tcg_env, 15517 offsetof(CPUMIPSState, 15518 active_tc.gpr_hi[i]), 15519 rname); 15520 } 15521 #endif /* !TARGET_MIPS64 */ 15522 for (unsigned i = 0; i < 32; i++) { 15523 int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); 15524 15525 fpu_f64[i] = tcg_global_mem_new_i64(tcg_env, off, fregnames[i]); 15526 } 15527 msa_translate_init(); 15528 cpu_PC = tcg_global_mem_new(tcg_env, 15529 offsetof(CPUMIPSState, active_tc.PC), "PC"); 15530 for (unsigned i = 0; i < MIPS_DSP_ACC; i++) { 15531 cpu_HI[i] = tcg_global_mem_new(tcg_env, 15532 offsetof(CPUMIPSState, active_tc.HI[i]), 15533 regnames_HI[i]); 15534 cpu_LO[i] = tcg_global_mem_new(tcg_env, 15535 offsetof(CPUMIPSState, active_tc.LO[i]), 15536 regnames_LO[i]); 15537 } 15538 cpu_dspctrl = tcg_global_mem_new(tcg_env, 15539 offsetof(CPUMIPSState, 15540 active_tc.DSPControl), 15541 "DSPControl"); 15542 bcond = tcg_global_mem_new(tcg_env, 15543 offsetof(CPUMIPSState, bcond), "bcond"); 15544 btarget = tcg_global_mem_new(tcg_env, 15545 offsetof(CPUMIPSState, btarget), "btarget"); 15546 hflags = tcg_global_mem_new_i32(tcg_env, 15547 offsetof(CPUMIPSState, hflags), "hflags"); 15548 15549 fpu_fcr0 = tcg_global_mem_new_i32(tcg_env, 15550 offsetof(CPUMIPSState, active_fpu.fcr0), 15551 "fcr0"); 15552 fpu_fcr31 = tcg_global_mem_new_i32(tcg_env, 15553 offsetof(CPUMIPSState, active_fpu.fcr31), 15554 "fcr31"); 15555 cpu_lladdr = tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, lladdr), 15556 "lladdr"); 15557 cpu_llval = tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, llval), 15558 "llval"); 15559 15560 if (TARGET_LONG_BITS == 32) { 15561 mxu_translate_init(); 15562 } 15563 } 15564 15565 void mips_restore_state_to_opc(CPUState *cs, 15566 const TranslationBlock *tb, 15567 const uint64_t *data) 15568 { 15569 MIPSCPU *cpu = MIPS_CPU(cs); 15570 CPUMIPSState *env = &cpu->env; 15571 15572 env->active_tc.PC = data[0]; 15573 env->hflags &= ~MIPS_HFLAG_BMASK; 15574 env->hflags |= data[1]; 15575 switch (env->hflags & MIPS_HFLAG_BMASK_BASE) { 15576 case MIPS_HFLAG_BR: 15577 break; 15578 case MIPS_HFLAG_BC: 15579 case MIPS_HFLAG_BL: 15580 case MIPS_HFLAG_B: 15581 env->btarget = data[2]; 15582 break; 15583 } 15584 } 15585