xref: /qemu/target/mips/tcg/vr54xx.decode (revision d051d0e1)
1# MIPS VR5432 instruction set extensions
2#
3# Copyright (C) 2021  Philippe Mathieu-Daudé
4#
5# SPDX-License-Identifier: LGPL-2.1-or-later
6#
7# Reference: VR5432 Microprocessor User’s Manual
8#            (Document Number U13751EU5V0UM00)
9
10&r              rs rt rd
11
12@rs_rt_rd       ...... rs:5  rt:5  rd:5  ..... ......   &r
13
14MULS            000000 ..... ..... ..... 00011011000    @rs_rt_rd
15MULSU           000000 ..... ..... ..... 00011011001    @rs_rt_rd
16MACC            000000 ..... ..... ..... 00101011000    @rs_rt_rd
17MACCU           000000 ..... ..... ..... 00101011001    @rs_rt_rd
18MSAC            000000 ..... ..... ..... 00111011000    @rs_rt_rd
19MSACU           000000 ..... ..... ..... 00111011001    @rs_rt_rd
20MULHI           000000 ..... ..... ..... 01001011000    @rs_rt_rd
21MULHIU          000000 ..... ..... ..... 01001011001    @rs_rt_rd
22MULSHI          000000 ..... ..... ..... 01011011000    @rs_rt_rd
23MULSHIU         000000 ..... ..... ..... 01011011001    @rs_rt_rd
24MACCHI          000000 ..... ..... ..... 01101011000    @rs_rt_rd
25MACCHIU         000000 ..... ..... ..... 01101011001    @rs_rt_rd
26MSACHI          000000 ..... ..... ..... 01111011000    @rs_rt_rd
27MSACHIU         000000 ..... ..... ..... 01111011001    @rs_rt_rd
28