1 /* 2 * QEMU OpenRISC CPU 3 * 4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/qemu-print.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "fpu/softfloat-helpers.h" 26 #include "tcg/tcg.h" 27 28 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) 29 { 30 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 31 32 cpu->env.pc = value; 33 cpu->env.dflag = 0; 34 } 35 36 static vaddr openrisc_cpu_get_pc(CPUState *cs) 37 { 38 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 39 40 return cpu->env.pc; 41 } 42 43 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, 44 const TranslationBlock *tb) 45 { 46 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 47 48 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 49 cpu->env.pc = tb->pc; 50 } 51 52 static void openrisc_restore_state_to_opc(CPUState *cs, 53 const TranslationBlock *tb, 54 const uint64_t *data) 55 { 56 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 57 58 cpu->env.pc = data[0]; 59 cpu->env.dflag = data[1] & 1; 60 if (data[1] & 2) { 61 cpu->env.ppc = cpu->env.pc - 4; 62 } 63 } 64 65 static bool openrisc_cpu_has_work(CPUState *cs) 66 { 67 return cs->interrupt_request & (CPU_INTERRUPT_HARD | 68 CPU_INTERRUPT_TIMER); 69 } 70 71 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) 72 { 73 info->print_insn = print_insn_or1k; 74 } 75 76 static void openrisc_cpu_reset_hold(Object *obj) 77 { 78 CPUState *s = CPU(obj); 79 OpenRISCCPU *cpu = OPENRISC_CPU(s); 80 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); 81 82 if (occ->parent_phases.hold) { 83 occ->parent_phases.hold(obj); 84 } 85 86 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); 87 88 cpu->env.pc = 0x100; 89 cpu->env.sr = SR_FO | SR_SM; 90 cpu->env.lock_addr = -1; 91 s->exception_index = -1; 92 cpu_set_fpcsr(&cpu->env, 0); 93 94 set_float_detect_tininess(float_tininess_before_rounding, 95 &cpu->env.fp_status); 96 97 #ifndef CONFIG_USER_ONLY 98 cpu->env.picmr = 0x00000000; 99 cpu->env.picsr = 0x00000000; 100 101 cpu->env.ttmr = 0x00000000; 102 #endif 103 } 104 105 #ifndef CONFIG_USER_ONLY 106 static void openrisc_cpu_set_irq(void *opaque, int irq, int level) 107 { 108 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; 109 CPUState *cs = CPU(cpu); 110 uint32_t irq_bit; 111 112 if (irq > 31 || irq < 0) { 113 return; 114 } 115 116 irq_bit = 1U << irq; 117 118 if (level) { 119 cpu->env.picsr |= irq_bit; 120 } else { 121 cpu->env.picsr &= ~irq_bit; 122 } 123 124 if (cpu->env.picsr & cpu->env.picmr) { 125 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 126 } else { 127 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 128 } 129 } 130 #endif 131 132 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) 133 { 134 CPUState *cs = CPU(dev); 135 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); 136 Error *local_err = NULL; 137 138 cpu_exec_realizefn(cs, &local_err); 139 if (local_err != NULL) { 140 error_propagate(errp, local_err); 141 return; 142 } 143 144 qemu_init_vcpu(cs); 145 cpu_reset(cs); 146 147 occ->parent_realize(dev, errp); 148 } 149 150 static void openrisc_cpu_initfn(Object *obj) 151 { 152 #ifndef CONFIG_USER_ONLY 153 qdev_init_gpio_in_named(DEVICE(obj), openrisc_cpu_set_irq, "IRQ", NR_IRQS); 154 #endif 155 } 156 157 /* CPU models */ 158 159 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) 160 { 161 ObjectClass *oc; 162 char *typename; 163 164 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); 165 oc = object_class_by_name(typename); 166 g_free(typename); 167 168 return oc; 169 } 170 171 static void or1200_initfn(Object *obj) 172 { 173 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 174 175 cpu->env.vr = 0x13000008; 176 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 177 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 178 CPUCFGR_EVBARP; 179 180 /* 1Way, TLB_SIZE entries. */ 181 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 182 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 183 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 184 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 185 } 186 187 static void openrisc_any_initfn(Object *obj) 188 { 189 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 190 191 cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ 192 cpu->env.vr2 = 0; /* No version specific id */ 193 cpu->env.avr = 0x01030000; /* Architecture v1.3 */ 194 195 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 196 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 197 CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S; 198 199 /* 1Way, TLB_SIZE entries. */ 200 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 201 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 202 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 203 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 204 } 205 206 #ifndef CONFIG_USER_ONLY 207 #include "hw/core/sysemu-cpu-ops.h" 208 209 static const struct SysemuCPUOps openrisc_sysemu_ops = { 210 .get_phys_page_debug = openrisc_cpu_get_phys_page_debug, 211 }; 212 #endif 213 214 #include "hw/core/tcg-cpu-ops.h" 215 216 static const struct TCGCPUOps openrisc_tcg_ops = { 217 .initialize = openrisc_translate_init, 218 .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, 219 .restore_state_to_opc = openrisc_restore_state_to_opc, 220 221 #ifndef CONFIG_USER_ONLY 222 .tlb_fill = openrisc_cpu_tlb_fill, 223 .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, 224 .do_interrupt = openrisc_cpu_do_interrupt, 225 #endif /* !CONFIG_USER_ONLY */ 226 }; 227 228 static void openrisc_cpu_class_init(ObjectClass *oc, void *data) 229 { 230 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); 231 CPUClass *cc = CPU_CLASS(occ); 232 DeviceClass *dc = DEVICE_CLASS(oc); 233 ResettableClass *rc = RESETTABLE_CLASS(oc); 234 235 device_class_set_parent_realize(dc, openrisc_cpu_realizefn, 236 &occ->parent_realize); 237 resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL, 238 &occ->parent_phases); 239 240 cc->class_by_name = openrisc_cpu_class_by_name; 241 cc->has_work = openrisc_cpu_has_work; 242 cc->dump_state = openrisc_cpu_dump_state; 243 cc->set_pc = openrisc_cpu_set_pc; 244 cc->get_pc = openrisc_cpu_get_pc; 245 cc->gdb_read_register = openrisc_cpu_gdb_read_register; 246 cc->gdb_write_register = openrisc_cpu_gdb_write_register; 247 #ifndef CONFIG_USER_ONLY 248 dc->vmsd = &vmstate_openrisc_cpu; 249 cc->sysemu_ops = &openrisc_sysemu_ops; 250 #endif 251 cc->gdb_num_core_regs = 32 + 3; 252 cc->disas_set_info = openrisc_disas_set_info; 253 cc->tcg_ops = &openrisc_tcg_ops; 254 } 255 256 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ 257 { \ 258 .parent = TYPE_OPENRISC_CPU, \ 259 .instance_init = initfn, \ 260 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \ 261 } 262 263 static const TypeInfo openrisc_cpus_type_infos[] = { 264 { /* base class should be registered first */ 265 .name = TYPE_OPENRISC_CPU, 266 .parent = TYPE_CPU, 267 .instance_size = sizeof(OpenRISCCPU), 268 .instance_align = __alignof(OpenRISCCPU), 269 .instance_init = openrisc_cpu_initfn, 270 .abstract = true, 271 .class_size = sizeof(OpenRISCCPUClass), 272 .class_init = openrisc_cpu_class_init, 273 }, 274 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn), 275 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn), 276 }; 277 278 DEFINE_TYPES(openrisc_cpus_type_infos) 279