1 /* 2 * QEMU OpenRISC CPU 3 * 4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/qemu-print.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 26 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) 27 { 28 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 29 30 cpu->env.pc = value; 31 cpu->env.dflag = 0; 32 } 33 34 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, 35 const TranslationBlock *tb) 36 { 37 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 38 39 cpu->env.pc = tb->pc; 40 } 41 42 43 static bool openrisc_cpu_has_work(CPUState *cs) 44 { 45 return cs->interrupt_request & (CPU_INTERRUPT_HARD | 46 CPU_INTERRUPT_TIMER); 47 } 48 49 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) 50 { 51 info->print_insn = print_insn_or1k; 52 } 53 54 static void openrisc_cpu_reset(DeviceState *dev) 55 { 56 CPUState *s = CPU(dev); 57 OpenRISCCPU *cpu = OPENRISC_CPU(s); 58 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); 59 60 occ->parent_reset(dev); 61 62 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); 63 64 cpu->env.pc = 0x100; 65 cpu->env.sr = SR_FO | SR_SM; 66 cpu->env.lock_addr = -1; 67 s->exception_index = -1; 68 cpu_set_fpcsr(&cpu->env, 0); 69 70 #ifndef CONFIG_USER_ONLY 71 cpu->env.picmr = 0x00000000; 72 cpu->env.picsr = 0x00000000; 73 74 cpu->env.ttmr = 0x00000000; 75 #endif 76 } 77 78 #ifndef CONFIG_USER_ONLY 79 static void openrisc_cpu_set_irq(void *opaque, int irq, int level) 80 { 81 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; 82 CPUState *cs = CPU(cpu); 83 uint32_t irq_bit; 84 85 if (irq > 31 || irq < 0) { 86 return; 87 } 88 89 irq_bit = 1U << irq; 90 91 if (level) { 92 cpu->env.picsr |= irq_bit; 93 } else { 94 cpu->env.picsr &= ~irq_bit; 95 } 96 97 if (cpu->env.picsr & cpu->env.picmr) { 98 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 99 } else { 100 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 101 } 102 } 103 #endif 104 105 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) 106 { 107 CPUState *cs = CPU(dev); 108 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); 109 Error *local_err = NULL; 110 111 cpu_exec_realizefn(cs, &local_err); 112 if (local_err != NULL) { 113 error_propagate(errp, local_err); 114 return; 115 } 116 117 qemu_init_vcpu(cs); 118 cpu_reset(cs); 119 120 occ->parent_realize(dev, errp); 121 } 122 123 static void openrisc_cpu_initfn(Object *obj) 124 { 125 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 126 127 cpu_set_cpustate_pointers(cpu); 128 129 #ifndef CONFIG_USER_ONLY 130 qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS); 131 #endif 132 } 133 134 /* CPU models */ 135 136 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) 137 { 138 ObjectClass *oc; 139 char *typename; 140 141 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); 142 oc = object_class_by_name(typename); 143 g_free(typename); 144 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || 145 object_class_is_abstract(oc))) { 146 return NULL; 147 } 148 return oc; 149 } 150 151 static void or1200_initfn(Object *obj) 152 { 153 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 154 155 cpu->env.vr = 0x13000008; 156 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 157 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 158 CPUCFGR_EVBARP; 159 160 /* 1Way, TLB_SIZE entries. */ 161 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 162 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 163 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 164 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 165 } 166 167 static void openrisc_any_initfn(Object *obj) 168 { 169 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 170 171 cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ 172 cpu->env.vr2 = 0; /* No version specific id */ 173 cpu->env.avr = 0x01030000; /* Architecture v1.3 */ 174 175 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 176 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 177 CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S; 178 179 /* 1Way, TLB_SIZE entries. */ 180 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 181 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 182 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 183 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 184 } 185 186 #ifndef CONFIG_USER_ONLY 187 #include "hw/core/sysemu-cpu-ops.h" 188 189 static const struct SysemuCPUOps openrisc_sysemu_ops = { 190 .get_phys_page_debug = openrisc_cpu_get_phys_page_debug, 191 }; 192 #endif 193 194 #include "hw/core/tcg-cpu-ops.h" 195 196 static const struct TCGCPUOps openrisc_tcg_ops = { 197 .initialize = openrisc_translate_init, 198 .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, 199 200 #ifndef CONFIG_USER_ONLY 201 .tlb_fill = openrisc_cpu_tlb_fill, 202 .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, 203 .do_interrupt = openrisc_cpu_do_interrupt, 204 #endif /* !CONFIG_USER_ONLY */ 205 }; 206 207 static void openrisc_cpu_class_init(ObjectClass *oc, void *data) 208 { 209 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); 210 CPUClass *cc = CPU_CLASS(occ); 211 DeviceClass *dc = DEVICE_CLASS(oc); 212 213 device_class_set_parent_realize(dc, openrisc_cpu_realizefn, 214 &occ->parent_realize); 215 device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset); 216 217 cc->class_by_name = openrisc_cpu_class_by_name; 218 cc->has_work = openrisc_cpu_has_work; 219 cc->dump_state = openrisc_cpu_dump_state; 220 cc->set_pc = openrisc_cpu_set_pc; 221 cc->gdb_read_register = openrisc_cpu_gdb_read_register; 222 cc->gdb_write_register = openrisc_cpu_gdb_write_register; 223 #ifndef CONFIG_USER_ONLY 224 dc->vmsd = &vmstate_openrisc_cpu; 225 cc->sysemu_ops = &openrisc_sysemu_ops; 226 #endif 227 cc->gdb_num_core_regs = 32 + 3; 228 cc->disas_set_info = openrisc_disas_set_info; 229 cc->tcg_ops = &openrisc_tcg_ops; 230 } 231 232 /* Sort alphabetically by type name, except for "any". */ 233 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b) 234 { 235 ObjectClass *class_a = (ObjectClass *)a; 236 ObjectClass *class_b = (ObjectClass *)b; 237 const char *name_a, *name_b; 238 239 name_a = object_class_get_name(class_a); 240 name_b = object_class_get_name(class_b); 241 if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) { 242 return 1; 243 } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) { 244 return -1; 245 } else { 246 return strcmp(name_a, name_b); 247 } 248 } 249 250 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data) 251 { 252 ObjectClass *oc = data; 253 const char *typename; 254 char *name; 255 256 typename = object_class_get_name(oc); 257 name = g_strndup(typename, 258 strlen(typename) - strlen("-" TYPE_OPENRISC_CPU)); 259 qemu_printf(" %s\n", name); 260 g_free(name); 261 } 262 263 void cpu_openrisc_list(void) 264 { 265 GSList *list; 266 267 list = object_class_get_list(TYPE_OPENRISC_CPU, false); 268 list = g_slist_sort(list, openrisc_cpu_list_compare); 269 qemu_printf("Available CPUs:\n"); 270 g_slist_foreach(list, openrisc_cpu_list_entry, NULL); 271 g_slist_free(list); 272 } 273 274 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ 275 { \ 276 .parent = TYPE_OPENRISC_CPU, \ 277 .instance_init = initfn, \ 278 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \ 279 } 280 281 static const TypeInfo openrisc_cpus_type_infos[] = { 282 { /* base class should be registered first */ 283 .name = TYPE_OPENRISC_CPU, 284 .parent = TYPE_CPU, 285 .instance_size = sizeof(OpenRISCCPU), 286 .instance_init = openrisc_cpu_initfn, 287 .abstract = true, 288 .class_size = sizeof(OpenRISCCPUClass), 289 .class_init = openrisc_cpu_class_init, 290 }, 291 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn), 292 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn), 293 }; 294 295 DEFINE_TYPES(openrisc_cpus_type_infos) 296