1 /* 2 * OpenRISC virtual CPU header. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef OPENRISC_CPU_H 21 #define OPENRISC_CPU_H 22 23 #include "exec/cpu-defs.h" 24 #include "hw/core/cpu.h" 25 #include "qom/object.h" 26 27 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ 28 struct OpenRISCCPU; 29 30 #define TYPE_OPENRISC_CPU "or1k-cpu" 31 32 typedef struct OpenRISCCPU OpenRISCCPU; 33 typedef struct OpenRISCCPUClass OpenRISCCPUClass; 34 DECLARE_OBJ_CHECKERS(OpenRISCCPU, OpenRISCCPUClass, 35 OPENRISC_CPU, TYPE_OPENRISC_CPU) 36 37 /** 38 * OpenRISCCPUClass: 39 * @parent_realize: The parent class' realize handler. 40 * @parent_reset: The parent class' reset handler. 41 * 42 * A OpenRISC CPU model. 43 */ 44 struct OpenRISCCPUClass { 45 /*< private >*/ 46 CPUClass parent_class; 47 /*< public >*/ 48 49 DeviceRealize parent_realize; 50 DeviceReset parent_reset; 51 }; 52 53 #define TARGET_INSN_START_EXTRA_WORDS 1 54 55 enum { 56 MMU_NOMMU_IDX = 0, 57 MMU_SUPERVISOR_IDX = 1, 58 MMU_USER_IDX = 2, 59 }; 60 61 #define SET_FP_CAUSE(reg, v) do {\ 62 (reg) = ((reg) & ~(0x3f << 12)) | \ 63 ((v & 0x3f) << 12);\ 64 } while (0) 65 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 66 #define UPDATE_FP_FLAGS(reg, v) do {\ 67 (reg) |= ((v & 0x1f) << 2);\ 68 } while (0) 69 70 /* Interrupt */ 71 #define NR_IRQS 32 72 73 /* Unit presece register */ 74 enum { 75 UPR_UP = (1 << 0), 76 UPR_DCP = (1 << 1), 77 UPR_ICP = (1 << 2), 78 UPR_DMP = (1 << 3), 79 UPR_IMP = (1 << 4), 80 UPR_MP = (1 << 5), 81 UPR_DUP = (1 << 6), 82 UPR_PCUR = (1 << 7), 83 UPR_PMP = (1 << 8), 84 UPR_PICP = (1 << 9), 85 UPR_TTP = (1 << 10), 86 UPR_CUP = (255 << 24), 87 }; 88 89 /* CPU configure register */ 90 enum { 91 CPUCFGR_NSGF = (15 << 0), 92 CPUCFGR_CGF = (1 << 4), 93 CPUCFGR_OB32S = (1 << 5), 94 CPUCFGR_OB64S = (1 << 6), 95 CPUCFGR_OF32S = (1 << 7), 96 CPUCFGR_OF64S = (1 << 8), 97 CPUCFGR_OV64S = (1 << 9), 98 CPUCFGR_ND = (1 << 10), 99 CPUCFGR_AVRP = (1 << 11), 100 CPUCFGR_EVBARP = (1 << 12), 101 CPUCFGR_ISRP = (1 << 13), 102 CPUCFGR_AECSRP = (1 << 14), 103 CPUCFGR_OF64A32S = (1 << 15), 104 }; 105 106 /* DMMU configure register */ 107 enum { 108 DMMUCFGR_NTW = (3 << 0), 109 DMMUCFGR_NTS = (7 << 2), 110 DMMUCFGR_NAE = (7 << 5), 111 DMMUCFGR_CRI = (1 << 8), 112 DMMUCFGR_PRI = (1 << 9), 113 DMMUCFGR_TEIRI = (1 << 10), 114 DMMUCFGR_HTR = (1 << 11), 115 }; 116 117 /* IMMU configure register */ 118 enum { 119 IMMUCFGR_NTW = (3 << 0), 120 IMMUCFGR_NTS = (7 << 2), 121 IMMUCFGR_NAE = (7 << 5), 122 IMMUCFGR_CRI = (1 << 8), 123 IMMUCFGR_PRI = (1 << 9), 124 IMMUCFGR_TEIRI = (1 << 10), 125 IMMUCFGR_HTR = (1 << 11), 126 }; 127 128 /* Power management register */ 129 enum { 130 PMR_SDF = (15 << 0), 131 PMR_DME = (1 << 4), 132 PMR_SME = (1 << 5), 133 PMR_DCGE = (1 << 6), 134 PMR_SUME = (1 << 7), 135 }; 136 137 /* Float point control status register */ 138 enum { 139 FPCSR_FPEE = 1, 140 FPCSR_RM = (3 << 1), 141 FPCSR_OVF = (1 << 3), 142 FPCSR_UNF = (1 << 4), 143 FPCSR_SNF = (1 << 5), 144 FPCSR_QNF = (1 << 6), 145 FPCSR_ZF = (1 << 7), 146 FPCSR_IXF = (1 << 8), 147 FPCSR_IVF = (1 << 9), 148 FPCSR_INF = (1 << 10), 149 FPCSR_DZF = (1 << 11), 150 }; 151 152 /* Exceptions indices */ 153 enum { 154 EXCP_RESET = 0x1, 155 EXCP_BUSERR = 0x2, 156 EXCP_DPF = 0x3, 157 EXCP_IPF = 0x4, 158 EXCP_TICK = 0x5, 159 EXCP_ALIGN = 0x6, 160 EXCP_ILLEGAL = 0x7, 161 EXCP_INT = 0x8, 162 EXCP_DTLBMISS = 0x9, 163 EXCP_ITLBMISS = 0xa, 164 EXCP_RANGE = 0xb, 165 EXCP_SYSCALL = 0xc, 166 EXCP_FPE = 0xd, 167 EXCP_TRAP = 0xe, 168 EXCP_NR, 169 }; 170 171 /* Supervisor register */ 172 enum { 173 SR_SM = (1 << 0), 174 SR_TEE = (1 << 1), 175 SR_IEE = (1 << 2), 176 SR_DCE = (1 << 3), 177 SR_ICE = (1 << 4), 178 SR_DME = (1 << 5), 179 SR_IME = (1 << 6), 180 SR_LEE = (1 << 7), 181 SR_CE = (1 << 8), 182 SR_F = (1 << 9), 183 SR_CY = (1 << 10), 184 SR_OV = (1 << 11), 185 SR_OVE = (1 << 12), 186 SR_DSX = (1 << 13), 187 SR_EPH = (1 << 14), 188 SR_FO = (1 << 15), 189 SR_SUMRA = (1 << 16), 190 SR_SCE = (1 << 17), 191 }; 192 193 /* Tick Timer Mode Register */ 194 enum { 195 TTMR_TP = (0xfffffff), 196 TTMR_IP = (1 << 28), 197 TTMR_IE = (1 << 29), 198 TTMR_M = (3 << 30), 199 }; 200 201 /* Timer Mode */ 202 enum { 203 TIMER_NONE = (0 << 30), 204 TIMER_INTR = (1 << 30), 205 TIMER_SHOT = (2 << 30), 206 TIMER_CONT = (3 << 30), 207 }; 208 209 /* TLB size */ 210 enum { 211 TLB_SIZE = 128, 212 TLB_MASK = TLB_SIZE - 1, 213 }; 214 215 /* TLB prot */ 216 enum { 217 URE = (1 << 6), 218 UWE = (1 << 7), 219 SRE = (1 << 8), 220 SWE = (1 << 9), 221 222 SXE = (1 << 6), 223 UXE = (1 << 7), 224 }; 225 226 typedef struct OpenRISCTLBEntry { 227 uint32_t mr; 228 uint32_t tr; 229 } OpenRISCTLBEntry; 230 231 #ifndef CONFIG_USER_ONLY 232 typedef struct CPUOpenRISCTLBContext { 233 OpenRISCTLBEntry itlb[TLB_SIZE]; 234 OpenRISCTLBEntry dtlb[TLB_SIZE]; 235 236 int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, 237 hwaddr *physical, 238 int *prot, 239 target_ulong address, int rw); 240 int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu, 241 hwaddr *physical, 242 int *prot, 243 target_ulong address, int rw); 244 } CPUOpenRISCTLBContext; 245 #endif 246 247 typedef struct CPUOpenRISCState { 248 target_ulong shadow_gpr[16][32]; /* Shadow registers */ 249 250 target_ulong pc; /* Program counter */ 251 target_ulong ppc; /* Prev PC */ 252 target_ulong jmp_pc; /* Jump PC */ 253 254 uint64_t mac; /* Multiply registers MACHI:MACLO */ 255 256 target_ulong epcr; /* Exception PC register */ 257 target_ulong eear; /* Exception EA register */ 258 259 target_ulong sr_f; /* the SR_F bit, values 0, 1. */ 260 target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */ 261 target_long sr_ov; /* the SR_OV bit (in the sign bit only) */ 262 uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */ 263 uint32_t esr; /* Exception supervisor register */ 264 uint32_t evbar; /* Exception vector base address register */ 265 uint32_t pmr; /* Power Management Register */ 266 uint32_t fpcsr; /* Float register */ 267 float_status fp_status; 268 269 target_ulong lock_addr; 270 target_ulong lock_value; 271 272 uint32_t dflag; /* In delay slot (boolean) */ 273 274 #ifndef CONFIG_USER_ONLY 275 CPUOpenRISCTLBContext tlb; 276 #endif 277 278 /* Fields up to this point are cleared by a CPU reset */ 279 struct {} end_reset_fields; 280 281 /* Fields from here on are preserved across CPU reset. */ 282 uint32_t vr; /* Version register */ 283 uint32_t vr2; /* Version register 2 */ 284 uint32_t avr; /* Architecture version register */ 285 uint32_t upr; /* Unit presence register */ 286 uint32_t cpucfgr; /* CPU configure register */ 287 uint32_t dmmucfgr; /* DMMU configure register */ 288 uint32_t immucfgr; /* IMMU configure register */ 289 290 #ifndef CONFIG_USER_ONLY 291 QEMUTimer *timer; 292 uint32_t ttmr; /* Timer tick mode register */ 293 int is_counting; 294 295 uint32_t picmr; /* Interrupt mask register */ 296 uint32_t picsr; /* Interrupt contrl register*/ 297 #endif 298 void *irq[32]; /* Interrupt irq input */ 299 } CPUOpenRISCState; 300 301 /** 302 * OpenRISCCPU: 303 * @env: #CPUOpenRISCState 304 * 305 * A OpenRISC CPU. 306 */ 307 struct OpenRISCCPU { 308 /*< private >*/ 309 CPUState parent_obj; 310 /*< public >*/ 311 312 CPUNegativeOffsetState neg; 313 CPUOpenRISCState env; 314 }; 315 316 317 void cpu_openrisc_list(void); 318 void openrisc_cpu_do_interrupt(CPUState *cpu); 319 bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); 320 void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 321 hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 322 int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 323 int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 324 void openrisc_translate_init(void); 325 bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 326 MMUAccessType access_type, int mmu_idx, 327 bool probe, uintptr_t retaddr); 328 int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); 329 int print_insn_or1k(bfd_vma addr, disassemble_info *info); 330 331 #define cpu_list cpu_openrisc_list 332 #define cpu_signal_handler cpu_openrisc_signal_handler 333 334 #ifndef CONFIG_USER_ONLY 335 extern const VMStateDescription vmstate_openrisc_cpu; 336 337 /* hw/openrisc_pic.c */ 338 void cpu_openrisc_pic_init(OpenRISCCPU *cpu); 339 340 /* hw/openrisc_timer.c */ 341 void cpu_openrisc_clock_init(OpenRISCCPU *cpu); 342 uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu); 343 void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val); 344 void cpu_openrisc_count_update(OpenRISCCPU *cpu); 345 void cpu_openrisc_timer_update(OpenRISCCPU *cpu); 346 void cpu_openrisc_count_start(OpenRISCCPU *cpu); 347 void cpu_openrisc_count_stop(OpenRISCCPU *cpu); 348 #endif 349 350 #define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU 351 #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX 352 #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU 353 354 typedef CPUOpenRISCState CPUArchState; 355 typedef OpenRISCCPU ArchCPU; 356 357 #include "exec/cpu-all.h" 358 359 #define TB_FLAGS_SM SR_SM 360 #define TB_FLAGS_DME SR_DME 361 #define TB_FLAGS_IME SR_IME 362 #define TB_FLAGS_OVE SR_OVE 363 #define TB_FLAGS_DFLAG 2 /* reuse SR_TEE */ 364 #define TB_FLAGS_R0_0 4 /* reuse SR_IEE */ 365 366 static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i) 367 { 368 return env->shadow_gpr[0][i]; 369 } 370 371 static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val) 372 { 373 env->shadow_gpr[0][i] = val; 374 } 375 376 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, 377 target_ulong *pc, 378 target_ulong *cs_base, uint32_t *flags) 379 { 380 *pc = env->pc; 381 *cs_base = 0; 382 *flags = (env->dflag ? TB_FLAGS_DFLAG : 0) 383 | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) 384 | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); 385 } 386 387 static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) 388 { 389 int ret = MMU_NOMMU_IDX; /* mmu is disabled */ 390 391 if (env->sr & (ifetch ? SR_IME : SR_DME)) { 392 /* The mmu is enabled; test supervisor state. */ 393 ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; 394 } 395 396 return ret; 397 } 398 399 static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) 400 { 401 return (env->sr 402 + env->sr_f * SR_F 403 + env->sr_cy * SR_CY 404 + (env->sr_ov < 0) * SR_OV); 405 } 406 407 static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val) 408 { 409 env->sr_f = (val & SR_F) != 0; 410 env->sr_cy = (val & SR_CY) != 0; 411 env->sr_ov = (val & SR_OV ? -1 : 0); 412 env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO; 413 } 414 415 void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val); 416 417 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 418 419 #endif /* OPENRISC_CPU_H */ 420