1 /* 2 * OpenRISC interrupt. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/exec-all.h" 23 #include "qemu-common.h" 24 #include "exec/gdbstub.h" 25 #include "qemu/host-utils.h" 26 #ifndef CONFIG_USER_ONLY 27 #include "hw/loader.h" 28 #endif 29 30 void openrisc_cpu_do_interrupt(CPUState *cs) 31 { 32 #ifndef CONFIG_USER_ONLY 33 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 34 CPUOpenRISCState *env = &cpu->env; 35 int exception = cs->exception_index; 36 37 env->epcr = env->pc; 38 if (exception == EXCP_SYSCALL) { 39 env->epcr += 4; 40 } 41 /* When we have an illegal instruction the error effective address 42 shall be set to the illegal instruction address. */ 43 if (exception == EXCP_ILLEGAL) { 44 env->eear = env->pc; 45 } 46 47 /* During exceptions esr is populared with the pre-exception sr. */ 48 env->esr = cpu_get_sr(env); 49 /* In parallel sr is updated to disable mmu, interrupts, timers and 50 set the delay slot exception flag. */ 51 env->sr &= ~SR_DME; 52 env->sr &= ~SR_IME; 53 env->sr |= SR_SM; 54 env->sr &= ~SR_IEE; 55 env->sr &= ~SR_TEE; 56 env->pmr &= ~PMR_DME; 57 env->pmr &= ~PMR_SME; 58 env->lock_addr = -1; 59 60 /* Set/clear dsx to indicate if we are in a delay slot exception. */ 61 if (env->dflag) { 62 env->dflag = 0; 63 env->sr |= SR_DSX; 64 env->epcr -= 4; 65 } else { 66 env->sr &= ~SR_DSX; 67 } 68 69 if (exception > 0 && exception < EXCP_NR) { 70 static const char * const int_name[EXCP_NR] = { 71 [EXCP_RESET] = "RESET", 72 [EXCP_BUSERR] = "BUSERR (bus error)", 73 [EXCP_DPF] = "DFP (data protection fault)", 74 [EXCP_IPF] = "IPF (code protection fault)", 75 [EXCP_TICK] = "TICK (timer interrupt)", 76 [EXCP_ALIGN] = "ALIGN", 77 [EXCP_ILLEGAL] = "ILLEGAL", 78 [EXCP_INT] = "INT (device interrupt)", 79 [EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)", 80 [EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)", 81 [EXCP_RANGE] = "RANGE", 82 [EXCP_SYSCALL] = "SYSCALL", 83 [EXCP_FPE] = "FPE", 84 [EXCP_TRAP] = "TRAP", 85 }; 86 87 qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]); 88 89 hwaddr vect_pc = exception << 8; 90 if (env->cpucfgr & CPUCFGR_EVBARP) { 91 vect_pc |= env->evbar; 92 } 93 if (env->sr & SR_EPH) { 94 vect_pc |= 0xf0000000; 95 } 96 env->pc = vect_pc; 97 } else { 98 cpu_abort(cs, "Unhandled exception 0x%x\n", exception); 99 } 100 #endif 101 102 cs->exception_index = -1; 103 } 104 105 bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 106 { 107 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 108 CPUOpenRISCState *env = &cpu->env; 109 int idx = -1; 110 111 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { 112 idx = EXCP_INT; 113 } 114 if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) { 115 idx = EXCP_TICK; 116 } 117 if (idx >= 0) { 118 cs->exception_index = idx; 119 openrisc_cpu_do_interrupt(cs); 120 return true; 121 } 122 return false; 123 } 124