1 /* 2 * QEMU PowerPC CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 #ifndef QEMU_PPC_CPU_QOM_H 21 #define QEMU_PPC_CPU_QOM_H 22 23 #include "qom/cpu.h" 24 25 #ifdef TARGET_PPC64 26 #define TYPE_POWERPC_CPU "powerpc64-cpu" 27 #elif defined(TARGET_PPCEMB) 28 #define TYPE_POWERPC_CPU "embedded-powerpc-cpu" 29 #else 30 #define TYPE_POWERPC_CPU "powerpc-cpu" 31 #endif 32 33 #define POWERPC_CPU_CLASS(klass) \ 34 OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU) 35 #define POWERPC_CPU(obj) \ 36 OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU) 37 #define POWERPC_CPU_GET_CLASS(obj) \ 38 OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU) 39 40 typedef struct PowerPCCPU PowerPCCPU; 41 typedef struct CPUPPCState CPUPPCState; 42 typedef struct ppc_tb_t ppc_tb_t; 43 typedef struct ppc_dcr_t ppc_dcr_t; 44 45 /*****************************************************************************/ 46 /* MMU model */ 47 typedef enum powerpc_mmu_t powerpc_mmu_t; 48 enum powerpc_mmu_t { 49 POWERPC_MMU_UNKNOWN = 0x00000000, 50 /* Standard 32 bits PowerPC MMU */ 51 POWERPC_MMU_32B = 0x00000001, 52 /* PowerPC 6xx MMU with software TLB */ 53 POWERPC_MMU_SOFT_6xx = 0x00000002, 54 /* PowerPC 74xx MMU with software TLB */ 55 POWERPC_MMU_SOFT_74xx = 0x00000003, 56 /* PowerPC 4xx MMU with software TLB */ 57 POWERPC_MMU_SOFT_4xx = 0x00000004, 58 /* PowerPC 4xx MMU with software TLB and zones protections */ 59 POWERPC_MMU_SOFT_4xx_Z = 0x00000005, 60 /* PowerPC MMU in real mode only */ 61 POWERPC_MMU_REAL = 0x00000006, 62 /* Freescale MPC8xx MMU model */ 63 POWERPC_MMU_MPC8xx = 0x00000007, 64 /* BookE MMU model */ 65 POWERPC_MMU_BOOKE = 0x00000008, 66 /* BookE 2.06 MMU model */ 67 POWERPC_MMU_BOOKE206 = 0x00000009, 68 /* PowerPC 601 MMU model (specific BATs format) */ 69 POWERPC_MMU_601 = 0x0000000A, 70 #define POWERPC_MMU_64 0x00010000 71 #define POWERPC_MMU_1TSEG 0x00020000 72 #define POWERPC_MMU_AMR 0x00040000 73 #define POWERPC_MMU_64K 0x00080000 74 #define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */ 75 /* 64 bits PowerPC MMU */ 76 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, 77 /* Architecture 2.03 and later (has LPCR) */ 78 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, 79 /* Architecture 2.06 variant */ 80 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG 81 | POWERPC_MMU_64K 82 | POWERPC_MMU_AMR | 0x00000003, 83 /* Architecture 2.07 variant */ 84 POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG 85 | POWERPC_MMU_64K 86 | POWERPC_MMU_AMR | 0x00000004, 87 /* Architecture 3.00 variant */ 88 POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG 89 | POWERPC_MMU_64K 90 | POWERPC_MMU_AMR | POWERPC_MMU_V3 91 | 0x00000005, 92 }; 93 #define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF)) 94 #define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B) 95 #define POWERPC_MMU_VER_2_03 POWERPC_MMU_VER(POWERPC_MMU_2_03) 96 #define POWERPC_MMU_VER_2_06 POWERPC_MMU_VER(POWERPC_MMU_2_06) 97 #define POWERPC_MMU_VER_2_07 POWERPC_MMU_VER(POWERPC_MMU_2_07) 98 #define POWERPC_MMU_VER_3_00 POWERPC_MMU_VER(POWERPC_MMU_3_00) 99 100 /*****************************************************************************/ 101 /* Exception model */ 102 typedef enum powerpc_excp_t powerpc_excp_t; 103 enum powerpc_excp_t { 104 POWERPC_EXCP_UNKNOWN = 0, 105 /* Standard PowerPC exception model */ 106 POWERPC_EXCP_STD, 107 /* PowerPC 40x exception model */ 108 POWERPC_EXCP_40x, 109 /* PowerPC 601 exception model */ 110 POWERPC_EXCP_601, 111 /* PowerPC 602 exception model */ 112 POWERPC_EXCP_602, 113 /* PowerPC 603 exception model */ 114 POWERPC_EXCP_603, 115 /* PowerPC 603e exception model */ 116 POWERPC_EXCP_603E, 117 /* PowerPC G2 exception model */ 118 POWERPC_EXCP_G2, 119 /* PowerPC 604 exception model */ 120 POWERPC_EXCP_604, 121 /* PowerPC 7x0 exception model */ 122 POWERPC_EXCP_7x0, 123 /* PowerPC 7x5 exception model */ 124 POWERPC_EXCP_7x5, 125 /* PowerPC 74xx exception model */ 126 POWERPC_EXCP_74xx, 127 /* BookE exception model */ 128 POWERPC_EXCP_BOOKE, 129 /* PowerPC 970 exception model */ 130 POWERPC_EXCP_970, 131 /* POWER7 exception model */ 132 POWERPC_EXCP_POWER7, 133 /* POWER8 exception model */ 134 POWERPC_EXCP_POWER8, 135 }; 136 137 /*****************************************************************************/ 138 /* PM instructions */ 139 typedef enum { 140 PPC_PM_DOZE, 141 PPC_PM_NAP, 142 PPC_PM_SLEEP, 143 PPC_PM_RVWINKLE, 144 } powerpc_pm_insn_t; 145 146 /*****************************************************************************/ 147 /* Input pins model */ 148 typedef enum powerpc_input_t powerpc_input_t; 149 enum powerpc_input_t { 150 PPC_FLAGS_INPUT_UNKNOWN = 0, 151 /* PowerPC 6xx bus */ 152 PPC_FLAGS_INPUT_6xx, 153 /* BookE bus */ 154 PPC_FLAGS_INPUT_BookE, 155 /* PowerPC 405 bus */ 156 PPC_FLAGS_INPUT_405, 157 /* PowerPC 970 bus */ 158 PPC_FLAGS_INPUT_970, 159 /* PowerPC POWER7 bus */ 160 PPC_FLAGS_INPUT_POWER7, 161 /* PowerPC 401 bus */ 162 PPC_FLAGS_INPUT_401, 163 /* Freescale RCPU bus */ 164 PPC_FLAGS_INPUT_RCPU, 165 }; 166 167 struct ppc_segment_page_sizes; 168 169 /** 170 * PowerPCCPUClass: 171 * @parent_realize: The parent class' realize handler. 172 * @parent_reset: The parent class' reset handler. 173 * 174 * A PowerPC CPU model. 175 */ 176 typedef struct PowerPCCPUClass { 177 /*< private >*/ 178 CPUClass parent_class; 179 /*< public >*/ 180 181 DeviceRealize parent_realize; 182 DeviceUnrealize parent_unrealize; 183 void (*parent_reset)(CPUState *cpu); 184 185 uint32_t pvr; 186 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr); 187 uint64_t pcr_mask; /* Available bits in PCR register */ 188 uint64_t pcr_supported; /* Bits for supported PowerISA versions */ 189 uint32_t svr; 190 uint64_t insns_flags; 191 uint64_t insns_flags2; 192 uint64_t msr_mask; 193 powerpc_mmu_t mmu_model; 194 powerpc_excp_t excp_model; 195 powerpc_input_t bus_model; 196 uint32_t flags; 197 int bfd_mach; 198 uint32_t l1_dcache_size, l1_icache_size; 199 const struct ppc_segment_page_sizes *sps; 200 struct ppc_radix_page_info *radix_page_info; 201 void (*init_proc)(CPUPPCState *env); 202 int (*check_pow)(CPUPPCState *env); 203 int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx); 204 bool (*interrupts_big_endian)(PowerPCCPU *cpu); 205 } PowerPCCPUClass; 206 207 #ifndef CONFIG_USER_ONLY 208 typedef struct PPCTimebase { 209 uint64_t guest_timebase; 210 int64_t time_of_the_day_ns; 211 } PPCTimebase; 212 213 extern const struct VMStateDescription vmstate_ppc_timebase; 214 215 #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ 216 .name = (stringify(_field)), \ 217 .version_id = (_version), \ 218 .size = sizeof(PPCTimebase), \ 219 .vmsd = &vmstate_ppc_timebase, \ 220 .flags = VMS_STRUCT, \ 221 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ 222 } 223 224 void cpu_ppc_clock_vm_state_change(void *opaque, int running, 225 RunState state); 226 #endif 227 228 #endif 229