1 /* 2 * QEMU PowerPC CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 #ifndef QEMU_PPC_CPU_QOM_H 21 #define QEMU_PPC_CPU_QOM_H 22 23 #include "hw/core/cpu.h" 24 #include "qom/object.h" 25 26 #ifdef TARGET_PPC64 27 #define TYPE_POWERPC_CPU "powerpc64-cpu" 28 #else 29 #define TYPE_POWERPC_CPU "powerpc-cpu" 30 #endif 31 32 typedef struct PowerPCCPU PowerPCCPU; 33 typedef struct PowerPCCPUClass PowerPCCPUClass; 34 DECLARE_OBJ_CHECKERS(PowerPCCPU, PowerPCCPUClass, 35 POWERPC_CPU, TYPE_POWERPC_CPU) 36 37 typedef struct CPUPPCState CPUPPCState; 38 typedef struct ppc_tb_t ppc_tb_t; 39 typedef struct ppc_dcr_t ppc_dcr_t; 40 41 /*****************************************************************************/ 42 /* MMU model */ 43 typedef enum powerpc_mmu_t powerpc_mmu_t; 44 enum powerpc_mmu_t { 45 POWERPC_MMU_UNKNOWN = 0x00000000, 46 /* Standard 32 bits PowerPC MMU */ 47 POWERPC_MMU_32B = 0x00000001, 48 /* PowerPC 6xx MMU with software TLB */ 49 POWERPC_MMU_SOFT_6xx = 0x00000002, 50 /* PowerPC 74xx MMU with software TLB */ 51 POWERPC_MMU_SOFT_74xx = 0x00000003, 52 /* PowerPC 4xx MMU with software TLB */ 53 POWERPC_MMU_SOFT_4xx = 0x00000004, 54 /* PowerPC 4xx MMU with software TLB and zones protections */ 55 POWERPC_MMU_SOFT_4xx_Z = 0x00000005, 56 /* PowerPC MMU in real mode only */ 57 POWERPC_MMU_REAL = 0x00000006, 58 /* Freescale MPC8xx MMU model */ 59 POWERPC_MMU_MPC8xx = 0x00000007, 60 /* BookE MMU model */ 61 POWERPC_MMU_BOOKE = 0x00000008, 62 /* BookE 2.06 MMU model */ 63 POWERPC_MMU_BOOKE206 = 0x00000009, 64 /* PowerPC 601 MMU model (specific BATs format) */ 65 POWERPC_MMU_601 = 0x0000000A, 66 #define POWERPC_MMU_64 0x00010000 67 /* 64 bits PowerPC MMU */ 68 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, 69 /* Architecture 2.03 and later (has LPCR) */ 70 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, 71 /* Architecture 2.06 variant */ 72 POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003, 73 /* Architecture 2.07 variant */ 74 POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004, 75 /* Architecture 3.00 variant */ 76 POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005, 77 }; 78 79 /*****************************************************************************/ 80 /* Exception model */ 81 typedef enum powerpc_excp_t powerpc_excp_t; 82 enum powerpc_excp_t { 83 POWERPC_EXCP_UNKNOWN = 0, 84 /* Standard PowerPC exception model */ 85 POWERPC_EXCP_STD, 86 /* PowerPC 40x exception model */ 87 POWERPC_EXCP_40x, 88 /* PowerPC 601 exception model */ 89 POWERPC_EXCP_601, 90 /* PowerPC 602 exception model */ 91 POWERPC_EXCP_602, 92 /* PowerPC 603 exception model */ 93 POWERPC_EXCP_603, 94 /* PowerPC 603e exception model */ 95 POWERPC_EXCP_603E, 96 /* PowerPC G2 exception model */ 97 POWERPC_EXCP_G2, 98 /* PowerPC 604 exception model */ 99 POWERPC_EXCP_604, 100 /* PowerPC 7x0 exception model */ 101 POWERPC_EXCP_7x0, 102 /* PowerPC 7x5 exception model */ 103 POWERPC_EXCP_7x5, 104 /* PowerPC 74xx exception model */ 105 POWERPC_EXCP_74xx, 106 /* BookE exception model */ 107 POWERPC_EXCP_BOOKE, 108 /* PowerPC 970 exception model */ 109 POWERPC_EXCP_970, 110 /* POWER7 exception model */ 111 POWERPC_EXCP_POWER7, 112 /* POWER8 exception model */ 113 POWERPC_EXCP_POWER8, 114 /* POWER9 exception model */ 115 POWERPC_EXCP_POWER9, 116 }; 117 118 /*****************************************************************************/ 119 /* PM instructions */ 120 typedef enum { 121 PPC_PM_DOZE, 122 PPC_PM_NAP, 123 PPC_PM_SLEEP, 124 PPC_PM_RVWINKLE, 125 PPC_PM_STOP, 126 } powerpc_pm_insn_t; 127 128 /*****************************************************************************/ 129 /* Input pins model */ 130 typedef enum powerpc_input_t powerpc_input_t; 131 enum powerpc_input_t { 132 PPC_FLAGS_INPUT_UNKNOWN = 0, 133 /* PowerPC 6xx bus */ 134 PPC_FLAGS_INPUT_6xx, 135 /* BookE bus */ 136 PPC_FLAGS_INPUT_BookE, 137 /* PowerPC 405 bus */ 138 PPC_FLAGS_INPUT_405, 139 /* PowerPC 970 bus */ 140 PPC_FLAGS_INPUT_970, 141 /* PowerPC POWER7 bus */ 142 PPC_FLAGS_INPUT_POWER7, 143 /* PowerPC POWER9 bus */ 144 PPC_FLAGS_INPUT_POWER9, 145 /* PowerPC 401 bus */ 146 PPC_FLAGS_INPUT_401, 147 /* Freescale RCPU bus */ 148 PPC_FLAGS_INPUT_RCPU, 149 }; 150 151 typedef struct PPCHash64Options PPCHash64Options; 152 153 /** 154 * PowerPCCPUClass: 155 * @parent_realize: The parent class' realize handler. 156 * @parent_reset: The parent class' reset handler. 157 * 158 * A PowerPC CPU model. 159 */ 160 struct PowerPCCPUClass { 161 /*< private >*/ 162 CPUClass parent_class; 163 /*< public >*/ 164 165 DeviceRealize parent_realize; 166 DeviceUnrealize parent_unrealize; 167 DeviceReset parent_reset; 168 void (*parent_parse_features)(const char *type, char *str, Error **errp); 169 170 uint32_t pvr; 171 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr); 172 uint64_t pcr_mask; /* Available bits in PCR register */ 173 uint64_t pcr_supported; /* Bits for supported PowerISA versions */ 174 uint32_t svr; 175 uint64_t insns_flags; 176 uint64_t insns_flags2; 177 uint64_t msr_mask; 178 uint64_t lpcr_mask; /* Available bits in the LPCR */ 179 uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */ 180 powerpc_mmu_t mmu_model; 181 powerpc_excp_t excp_model; 182 powerpc_input_t bus_model; 183 uint32_t flags; 184 int bfd_mach; 185 uint32_t l1_dcache_size, l1_icache_size; 186 #ifndef CONFIG_USER_ONLY 187 unsigned int gdb_num_sprs; 188 const char *gdb_spr_xml; 189 #endif 190 const PPCHash64Options *hash64_opts; 191 struct ppc_radix_page_info *radix_page_info; 192 uint32_t lrg_decr_bits; 193 int n_host_threads; 194 void (*init_proc)(CPUPPCState *env); 195 int (*check_pow)(CPUPPCState *env); 196 int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx); 197 bool (*interrupts_big_endian)(PowerPCCPU *cpu); 198 }; 199 200 #ifndef CONFIG_USER_ONLY 201 typedef struct PPCTimebase { 202 uint64_t guest_timebase; 203 int64_t time_of_the_day_ns; 204 bool runstate_paused; 205 } PPCTimebase; 206 207 extern const VMStateDescription vmstate_ppc_timebase; 208 209 #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ 210 .name = (stringify(_field)), \ 211 .version_id = (_version), \ 212 .size = sizeof(PPCTimebase), \ 213 .vmsd = &vmstate_ppc_timebase, \ 214 .flags = VMS_STRUCT, \ 215 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ 216 } 217 218 void cpu_ppc_clock_vm_state_change(void *opaque, int running, 219 RunState state); 220 #endif 221 222 #endif 223