1 /* 2 * QEMU PowerPC CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 #ifndef QEMU_PPC_CPU_QOM_H 21 #define QEMU_PPC_CPU_QOM_H 22 23 #include "qom/cpu.h" 24 25 #ifdef TARGET_PPC64 26 #define TYPE_POWERPC_CPU "powerpc64-cpu" 27 #else 28 #define TYPE_POWERPC_CPU "powerpc-cpu" 29 #endif 30 31 #define POWERPC_CPU_CLASS(klass) \ 32 OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU) 33 #define POWERPC_CPU(obj) \ 34 OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU) 35 #define POWERPC_CPU_GET_CLASS(obj) \ 36 OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU) 37 38 typedef struct PowerPCCPU PowerPCCPU; 39 typedef struct CPUPPCState CPUPPCState; 40 typedef struct ppc_tb_t ppc_tb_t; 41 typedef struct ppc_dcr_t ppc_dcr_t; 42 43 /*****************************************************************************/ 44 /* MMU model */ 45 typedef enum powerpc_mmu_t powerpc_mmu_t; 46 enum powerpc_mmu_t { 47 POWERPC_MMU_UNKNOWN = 0x00000000, 48 /* Standard 32 bits PowerPC MMU */ 49 POWERPC_MMU_32B = 0x00000001, 50 /* PowerPC 6xx MMU with software TLB */ 51 POWERPC_MMU_SOFT_6xx = 0x00000002, 52 /* PowerPC 74xx MMU with software TLB */ 53 POWERPC_MMU_SOFT_74xx = 0x00000003, 54 /* PowerPC 4xx MMU with software TLB */ 55 POWERPC_MMU_SOFT_4xx = 0x00000004, 56 /* PowerPC 4xx MMU with software TLB and zones protections */ 57 POWERPC_MMU_SOFT_4xx_Z = 0x00000005, 58 /* PowerPC MMU in real mode only */ 59 POWERPC_MMU_REAL = 0x00000006, 60 /* Freescale MPC8xx MMU model */ 61 POWERPC_MMU_MPC8xx = 0x00000007, 62 /* BookE MMU model */ 63 POWERPC_MMU_BOOKE = 0x00000008, 64 /* BookE 2.06 MMU model */ 65 POWERPC_MMU_BOOKE206 = 0x00000009, 66 /* PowerPC 601 MMU model (specific BATs format) */ 67 POWERPC_MMU_601 = 0x0000000A, 68 #define POWERPC_MMU_64 0x00010000 69 /* 64 bits PowerPC MMU */ 70 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, 71 /* Architecture 2.03 and later (has LPCR) */ 72 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, 73 /* Architecture 2.06 variant */ 74 POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003, 75 /* Architecture 2.07 variant */ 76 POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004, 77 /* Architecture 3.00 variant */ 78 POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005, 79 }; 80 81 /*****************************************************************************/ 82 /* Exception model */ 83 typedef enum powerpc_excp_t powerpc_excp_t; 84 enum powerpc_excp_t { 85 POWERPC_EXCP_UNKNOWN = 0, 86 /* Standard PowerPC exception model */ 87 POWERPC_EXCP_STD, 88 /* PowerPC 40x exception model */ 89 POWERPC_EXCP_40x, 90 /* PowerPC 601 exception model */ 91 POWERPC_EXCP_601, 92 /* PowerPC 602 exception model */ 93 POWERPC_EXCP_602, 94 /* PowerPC 603 exception model */ 95 POWERPC_EXCP_603, 96 /* PowerPC 603e exception model */ 97 POWERPC_EXCP_603E, 98 /* PowerPC G2 exception model */ 99 POWERPC_EXCP_G2, 100 /* PowerPC 604 exception model */ 101 POWERPC_EXCP_604, 102 /* PowerPC 7x0 exception model */ 103 POWERPC_EXCP_7x0, 104 /* PowerPC 7x5 exception model */ 105 POWERPC_EXCP_7x5, 106 /* PowerPC 74xx exception model */ 107 POWERPC_EXCP_74xx, 108 /* BookE exception model */ 109 POWERPC_EXCP_BOOKE, 110 /* PowerPC 970 exception model */ 111 POWERPC_EXCP_970, 112 /* POWER7 exception model */ 113 POWERPC_EXCP_POWER7, 114 /* POWER8 exception model */ 115 POWERPC_EXCP_POWER8, 116 }; 117 118 /*****************************************************************************/ 119 /* PM instructions */ 120 typedef enum { 121 PPC_PM_DOZE, 122 PPC_PM_NAP, 123 PPC_PM_SLEEP, 124 PPC_PM_RVWINKLE, 125 } powerpc_pm_insn_t; 126 127 /*****************************************************************************/ 128 /* Input pins model */ 129 typedef enum powerpc_input_t powerpc_input_t; 130 enum powerpc_input_t { 131 PPC_FLAGS_INPUT_UNKNOWN = 0, 132 /* PowerPC 6xx bus */ 133 PPC_FLAGS_INPUT_6xx, 134 /* BookE bus */ 135 PPC_FLAGS_INPUT_BookE, 136 /* PowerPC 405 bus */ 137 PPC_FLAGS_INPUT_405, 138 /* PowerPC 970 bus */ 139 PPC_FLAGS_INPUT_970, 140 /* PowerPC POWER7 bus */ 141 PPC_FLAGS_INPUT_POWER7, 142 /* PowerPC 401 bus */ 143 PPC_FLAGS_INPUT_401, 144 /* Freescale RCPU bus */ 145 PPC_FLAGS_INPUT_RCPU, 146 }; 147 148 typedef struct PPCHash64Options PPCHash64Options; 149 150 /** 151 * PowerPCCPUClass: 152 * @parent_realize: The parent class' realize handler. 153 * @parent_reset: The parent class' reset handler. 154 * 155 * A PowerPC CPU model. 156 */ 157 typedef struct PowerPCCPUClass { 158 /*< private >*/ 159 CPUClass parent_class; 160 /*< public >*/ 161 162 DeviceRealize parent_realize; 163 DeviceUnrealize parent_unrealize; 164 void (*parent_reset)(CPUState *cpu); 165 void (*parent_parse_features)(const char *type, char *str, Error **errp); 166 167 uint32_t pvr; 168 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr); 169 uint64_t pcr_mask; /* Available bits in PCR register */ 170 uint64_t pcr_supported; /* Bits for supported PowerISA versions */ 171 uint32_t svr; 172 uint64_t insns_flags; 173 uint64_t insns_flags2; 174 uint64_t msr_mask; 175 uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */ 176 powerpc_mmu_t mmu_model; 177 powerpc_excp_t excp_model; 178 powerpc_input_t bus_model; 179 uint32_t flags; 180 int bfd_mach; 181 uint32_t l1_dcache_size, l1_icache_size; 182 const PPCHash64Options *hash64_opts; 183 struct ppc_radix_page_info *radix_page_info; 184 void (*init_proc)(CPUPPCState *env); 185 int (*check_pow)(CPUPPCState *env); 186 int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx); 187 bool (*interrupts_big_endian)(PowerPCCPU *cpu); 188 } PowerPCCPUClass; 189 190 #ifndef CONFIG_USER_ONLY 191 typedef struct PPCTimebase { 192 uint64_t guest_timebase; 193 int64_t time_of_the_day_ns; 194 } PPCTimebase; 195 196 extern const struct VMStateDescription vmstate_ppc_timebase; 197 198 #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ 199 .name = (stringify(_field)), \ 200 .version_id = (_version), \ 201 .size = sizeof(PPCTimebase), \ 202 .vmsd = &vmstate_ppc_timebase, \ 203 .flags = VMS_STRUCT, \ 204 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ 205 } 206 207 void cpu_ppc_clock_vm_state_change(void *opaque, int running, 208 RunState state); 209 #endif 210 211 #endif 212