1 /* 2 * PowerPC emulation cpu definitions for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_CPU_H 21 #define PPC_CPU_H 22 23 #include "qemu-common.h" 24 #include "qemu/int128.h" 25 26 //#define PPC_EMULATE_32BITS_HYPV 27 28 #if defined (TARGET_PPC64) 29 /* PowerPC 64 definitions */ 30 #define TARGET_LONG_BITS 64 31 #define TARGET_PAGE_BITS 12 32 33 /* Note that the official physical address space bits is 62-M where M 34 is implementation dependent. I've not looked up M for the set of 35 cpus we emulate at the system level. */ 36 #define TARGET_PHYS_ADDR_SPACE_BITS 62 37 38 /* Note that the PPC environment architecture talks about 80 bit virtual 39 addresses, with segmentation. Obviously that's not all visible to a 40 single process, which is all we're concerned with here. */ 41 #ifdef TARGET_ABI32 42 # define TARGET_VIRT_ADDR_SPACE_BITS 32 43 #else 44 # define TARGET_VIRT_ADDR_SPACE_BITS 64 45 #endif 46 47 #define TARGET_PAGE_BITS_64K 16 48 #define TARGET_PAGE_BITS_16M 24 49 50 #else /* defined (TARGET_PPC64) */ 51 /* PowerPC 32 definitions */ 52 #define TARGET_LONG_BITS 32 53 54 #if defined(TARGET_PPCEMB) 55 /* Specific definitions for PowerPC embedded */ 56 /* BookE have 36 bits physical address space */ 57 #if defined(CONFIG_USER_ONLY) 58 /* It looks like a lot of Linux programs assume page size 59 * is 4kB long. This is evil, but we have to deal with it... 60 */ 61 #define TARGET_PAGE_BITS 12 62 #else /* defined(CONFIG_USER_ONLY) */ 63 /* Pages can be 1 kB small */ 64 #define TARGET_PAGE_BITS 10 65 #endif /* defined(CONFIG_USER_ONLY) */ 66 #else /* defined(TARGET_PPCEMB) */ 67 /* "standard" PowerPC 32 definitions */ 68 #define TARGET_PAGE_BITS 12 69 #endif /* defined(TARGET_PPCEMB) */ 70 71 #define TARGET_PHYS_ADDR_SPACE_BITS 36 72 #define TARGET_VIRT_ADDR_SPACE_BITS 32 73 74 #endif /* defined (TARGET_PPC64) */ 75 76 #define CPUArchState struct CPUPPCState 77 78 #include "exec/cpu-defs.h" 79 #include "cpu-qom.h" 80 #include "fpu/softfloat.h" 81 82 #if defined (TARGET_PPC64) 83 #define PPC_ELF_MACHINE EM_PPC64 84 #else 85 #define PPC_ELF_MACHINE EM_PPC 86 #endif 87 88 /*****************************************************************************/ 89 /* Exception vectors definitions */ 90 enum { 91 POWERPC_EXCP_NONE = -1, 92 /* The 64 first entries are used by the PowerPC embedded specification */ 93 POWERPC_EXCP_CRITICAL = 0, /* Critical input */ 94 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */ 95 POWERPC_EXCP_DSI = 2, /* Data storage exception */ 96 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */ 97 POWERPC_EXCP_EXTERNAL = 4, /* External input */ 98 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */ 99 POWERPC_EXCP_PROGRAM = 6, /* Program exception */ 100 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */ 101 POWERPC_EXCP_SYSCALL = 8, /* System call exception */ 102 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */ 103 POWERPC_EXCP_DECR = 10, /* Decrementer exception */ 104 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */ 105 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */ 106 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */ 107 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */ 108 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */ 109 /* Vectors 16 to 31 are reserved */ 110 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */ 111 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */ 112 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */ 113 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */ 114 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */ 115 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */ 116 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */ 117 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/ 118 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */ 119 /* Vectors 42 to 63 are reserved */ 120 /* Exceptions defined in the PowerPC server specification */ 121 /* Server doorbell variants */ 122 #define POWERPC_EXCP_SDOOR POWERPC_EXCP_GDOORI 123 #define POWERPC_EXCP_SDOOR_HV POWERPC_EXCP_DOORI 124 POWERPC_EXCP_RESET = 64, /* System reset exception */ 125 POWERPC_EXCP_DSEG = 65, /* Data segment exception */ 126 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */ 127 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */ 128 POWERPC_EXCP_TRACE = 68, /* Trace exception */ 129 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */ 130 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */ 131 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */ 132 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */ 133 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */ 134 /* 40x specific exceptions */ 135 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */ 136 /* 601 specific exceptions */ 137 POWERPC_EXCP_IO = 75, /* IO error exception */ 138 POWERPC_EXCP_RUNM = 76, /* Run mode exception */ 139 /* 602 specific exceptions */ 140 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */ 141 /* 602/603 specific exceptions */ 142 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */ 143 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */ 144 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */ 145 /* Exceptions available on most PowerPC */ 146 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */ 147 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */ 148 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */ 149 POWERPC_EXCP_SMI = 84, /* System management interrupt */ 150 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */ 151 /* 7xx/74xx specific exceptions */ 152 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */ 153 /* 74xx specific exceptions */ 154 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */ 155 /* 970FX specific exceptions */ 156 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */ 157 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */ 158 /* Freescale embedded cores specific exceptions */ 159 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */ 160 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */ 161 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */ 162 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */ 163 /* VSX Unavailable (Power ISA 2.06 and later) */ 164 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */ 165 POWERPC_EXCP_FU = 95, /* Facility Unavailable */ 166 /* Additional ISA 2.06 and later server exceptions */ 167 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */ 168 POWERPC_EXCP_HV_MAINT = 97, /* HMI */ 169 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */ 170 /* EOL */ 171 POWERPC_EXCP_NB = 99, 172 /* QEMU exceptions: used internally during code translation */ 173 POWERPC_EXCP_STOP = 0x200, /* stop translation */ 174 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ 175 /* QEMU exceptions: special cases we want to stop translation */ 176 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ 177 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ 178 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */ 179 }; 180 181 /* Exceptions error codes */ 182 enum { 183 /* Exception subtypes for POWERPC_EXCP_ALIGN */ 184 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ 185 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ 186 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ 187 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ 188 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ 189 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ 190 /* Exception subtypes for POWERPC_EXCP_PROGRAM */ 191 /* FP exceptions */ 192 POWERPC_EXCP_FP = 0x10, 193 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */ 194 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */ 195 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */ 196 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */ 197 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */ 198 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ 199 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ 200 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ 201 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ 202 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ 203 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ 204 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ 205 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ 206 /* Invalid instruction */ 207 POWERPC_EXCP_INVAL = 0x20, 208 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ 209 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ 210 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ 211 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ 212 /* Privileged instruction */ 213 POWERPC_EXCP_PRIV = 0x30, 214 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ 215 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */ 216 /* Trap */ 217 POWERPC_EXCP_TRAP = 0x40, 218 }; 219 220 #define PPC_INPUT(env) (env->bus_model) 221 222 /*****************************************************************************/ 223 typedef struct opc_handler_t opc_handler_t; 224 225 /*****************************************************************************/ 226 /* Types used to describe some PowerPC registers */ 227 typedef struct DisasContext DisasContext; 228 typedef struct ppc_spr_t ppc_spr_t; 229 typedef union ppc_avr_t ppc_avr_t; 230 typedef union ppc_tlb_t ppc_tlb_t; 231 232 /* SPR access micro-ops generations callbacks */ 233 struct ppc_spr_t { 234 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num); 235 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num); 236 #if !defined(CONFIG_USER_ONLY) 237 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num); 238 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num); 239 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num); 240 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num); 241 #endif 242 const char *name; 243 target_ulong default_value; 244 #ifdef CONFIG_KVM 245 /* We (ab)use the fact that all the SPRs will have ids for the 246 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning, 247 * don't sync this */ 248 uint64_t one_reg_id; 249 #endif 250 }; 251 252 /* Altivec registers (128 bits) */ 253 union ppc_avr_t { 254 float32 f[4]; 255 uint8_t u8[16]; 256 uint16_t u16[8]; 257 uint32_t u32[4]; 258 int8_t s8[16]; 259 int16_t s16[8]; 260 int32_t s32[4]; 261 uint64_t u64[2]; 262 int64_t s64[2]; 263 #ifdef CONFIG_INT128 264 __uint128_t u128; 265 #endif 266 Int128 s128; 267 }; 268 269 #if !defined(CONFIG_USER_ONLY) 270 /* Software TLB cache */ 271 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; 272 struct ppc6xx_tlb_t { 273 target_ulong pte0; 274 target_ulong pte1; 275 target_ulong EPN; 276 }; 277 278 typedef struct ppcemb_tlb_t ppcemb_tlb_t; 279 struct ppcemb_tlb_t { 280 uint64_t RPN; 281 target_ulong EPN; 282 target_ulong PID; 283 target_ulong size; 284 uint32_t prot; 285 uint32_t attr; /* Storage attributes */ 286 }; 287 288 typedef struct ppcmas_tlb_t { 289 uint32_t mas8; 290 uint32_t mas1; 291 uint64_t mas2; 292 uint64_t mas7_3; 293 } ppcmas_tlb_t; 294 295 union ppc_tlb_t { 296 ppc6xx_tlb_t *tlb6; 297 ppcemb_tlb_t *tlbe; 298 ppcmas_tlb_t *tlbm; 299 }; 300 301 /* possible TLB variants */ 302 #define TLB_NONE 0 303 #define TLB_6XX 1 304 #define TLB_EMB 2 305 #define TLB_MAS 3 306 #endif 307 308 #define SDR_32_HTABORG 0xFFFF0000UL 309 #define SDR_32_HTABMASK 0x000001FFUL 310 311 #if defined(TARGET_PPC64) 312 #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL 313 #define SDR_64_HTABSIZE 0x000000000000001FULL 314 #endif /* defined(TARGET_PPC64 */ 315 316 typedef struct ppc_slb_t ppc_slb_t; 317 struct ppc_slb_t { 318 uint64_t esid; 319 uint64_t vsid; 320 const struct ppc_one_seg_page_size *sps; 321 }; 322 323 #define MAX_SLB_ENTRIES 64 324 #define SEGMENT_SHIFT_256M 28 325 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1)) 326 327 #define SEGMENT_SHIFT_1T 40 328 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1)) 329 330 331 /*****************************************************************************/ 332 /* Machine state register bits definition */ 333 #define MSR_SF 63 /* Sixty-four-bit mode hflags */ 334 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */ 335 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ 336 #define MSR_SHV 60 /* hypervisor state hflags */ 337 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */ 338 #define MSR_TS1 33 339 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */ 340 #define MSR_CM 31 /* Computation mode for BookE hflags */ 341 #define MSR_ICM 30 /* Interrupt computation mode for BookE */ 342 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */ 343 #define MSR_GS 28 /* guest state for BookE */ 344 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ 345 #define MSR_VR 25 /* altivec available x hflags */ 346 #define MSR_SPE 25 /* SPE enable for BookE x hflags */ 347 #define MSR_AP 23 /* Access privilege state on 602 hflags */ 348 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */ 349 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */ 350 #define MSR_KEY 19 /* key bit on 603e */ 351 #define MSR_POW 18 /* Power management */ 352 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */ 353 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */ 354 #define MSR_ILE 16 /* Interrupt little-endian mode */ 355 #define MSR_EE 15 /* External interrupt enable */ 356 #define MSR_PR 14 /* Problem state hflags */ 357 #define MSR_FP 13 /* Floating point available hflags */ 358 #define MSR_ME 12 /* Machine check interrupt enable */ 359 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */ 360 #define MSR_SE 10 /* Single-step trace enable x hflags */ 361 #define MSR_DWE 10 /* Debug wait enable on 405 x */ 362 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */ 363 #define MSR_BE 9 /* Branch trace enable x hflags */ 364 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ 365 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */ 366 #define MSR_AL 7 /* AL bit on POWER */ 367 #define MSR_EP 6 /* Exception prefix on 601 */ 368 #define MSR_IR 5 /* Instruction relocate */ 369 #define MSR_DR 4 /* Data relocate */ 370 #define MSR_IS 5 /* Instruction address space (BookE) */ 371 #define MSR_DS 4 /* Data address space (BookE) */ 372 #define MSR_PE 3 /* Protection enable on 403 */ 373 #define MSR_PX 2 /* Protection exclusive on 403 x */ 374 #define MSR_PMM 2 /* Performance monitor mark on POWER x */ 375 #define MSR_RI 1 /* Recoverable interrupt 1 */ 376 #define MSR_LE 0 /* Little-endian mode 1 hflags */ 377 378 /* LPCR bits */ 379 #define LPCR_VPM0 (1ull << (63 - 0)) 380 #define LPCR_VPM1 (1ull << (63 - 1)) 381 #define LPCR_ISL (1ull << (63 - 2)) 382 #define LPCR_KBV (1ull << (63 - 3)) 383 #define LPCR_DPFD_SHIFT (63 - 11) 384 #define LPCR_DPFD (0x3ull << LPCR_DPFD_SHIFT) 385 #define LPCR_VRMASD_SHIFT (63 - 16) 386 #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT) 387 #define LPCR_RMLS_SHIFT (63 - 37) 388 #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT) 389 #define LPCR_ILE (1ull << (63 - 38)) 390 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ 391 #define LPCR_AIL (3ull << LPCR_AIL_SHIFT) 392 #define LPCR_ONL (1ull << (63 - 45)) 393 #define LPCR_P7_PECE0 (1ull << (63 - 49)) 394 #define LPCR_P7_PECE1 (1ull << (63 - 50)) 395 #define LPCR_P7_PECE2 (1ull << (63 - 51)) 396 #define LPCR_P8_PECE0 (1ull << (63 - 47)) 397 #define LPCR_P8_PECE1 (1ull << (63 - 48)) 398 #define LPCR_P8_PECE2 (1ull << (63 - 49)) 399 #define LPCR_P8_PECE3 (1ull << (63 - 50)) 400 #define LPCR_P8_PECE4 (1ull << (63 - 51)) 401 #define LPCR_MER (1ull << (63 - 52)) 402 #define LPCR_TC (1ull << (63 - 54)) 403 #define LPCR_LPES0 (1ull << (63 - 60)) 404 #define LPCR_LPES1 (1ull << (63 - 61)) 405 #define LPCR_RMI (1ull << (63 - 62)) 406 #define LPCR_HDICE (1ull << (63 - 63)) 407 408 #define msr_sf ((env->msr >> MSR_SF) & 1) 409 #define msr_isf ((env->msr >> MSR_ISF) & 1) 410 #define msr_shv ((env->msr >> MSR_SHV) & 1) 411 #define msr_cm ((env->msr >> MSR_CM) & 1) 412 #define msr_icm ((env->msr >> MSR_ICM) & 1) 413 #define msr_thv ((env->msr >> MSR_THV) & 1) 414 #define msr_gs ((env->msr >> MSR_GS) & 1) 415 #define msr_ucle ((env->msr >> MSR_UCLE) & 1) 416 #define msr_vr ((env->msr >> MSR_VR) & 1) 417 #define msr_spe ((env->msr >> MSR_SPE) & 1) 418 #define msr_ap ((env->msr >> MSR_AP) & 1) 419 #define msr_vsx ((env->msr >> MSR_VSX) & 1) 420 #define msr_sa ((env->msr >> MSR_SA) & 1) 421 #define msr_key ((env->msr >> MSR_KEY) & 1) 422 #define msr_pow ((env->msr >> MSR_POW) & 1) 423 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1) 424 #define msr_ce ((env->msr >> MSR_CE) & 1) 425 #define msr_ile ((env->msr >> MSR_ILE) & 1) 426 #define msr_ee ((env->msr >> MSR_EE) & 1) 427 #define msr_pr ((env->msr >> MSR_PR) & 1) 428 #define msr_fp ((env->msr >> MSR_FP) & 1) 429 #define msr_me ((env->msr >> MSR_ME) & 1) 430 #define msr_fe0 ((env->msr >> MSR_FE0) & 1) 431 #define msr_se ((env->msr >> MSR_SE) & 1) 432 #define msr_dwe ((env->msr >> MSR_DWE) & 1) 433 #define msr_uble ((env->msr >> MSR_UBLE) & 1) 434 #define msr_be ((env->msr >> MSR_BE) & 1) 435 #define msr_de ((env->msr >> MSR_DE) & 1) 436 #define msr_fe1 ((env->msr >> MSR_FE1) & 1) 437 #define msr_al ((env->msr >> MSR_AL) & 1) 438 #define msr_ep ((env->msr >> MSR_EP) & 1) 439 #define msr_ir ((env->msr >> MSR_IR) & 1) 440 #define msr_dr ((env->msr >> MSR_DR) & 1) 441 #define msr_is ((env->msr >> MSR_IS) & 1) 442 #define msr_ds ((env->msr >> MSR_DS) & 1) 443 #define msr_pe ((env->msr >> MSR_PE) & 1) 444 #define msr_px ((env->msr >> MSR_PX) & 1) 445 #define msr_pmm ((env->msr >> MSR_PMM) & 1) 446 #define msr_ri ((env->msr >> MSR_RI) & 1) 447 #define msr_le ((env->msr >> MSR_LE) & 1) 448 #define msr_ts ((env->msr >> MSR_TS1) & 3) 449 #define msr_tm ((env->msr >> MSR_TM) & 1) 450 451 /* Hypervisor bit is more specific */ 452 #if defined(TARGET_PPC64) 453 #define MSR_HVB (1ULL << MSR_SHV) 454 #define msr_hv msr_shv 455 #else 456 #if defined(PPC_EMULATE_32BITS_HYPV) 457 #define MSR_HVB (1ULL << MSR_THV) 458 #define msr_hv msr_thv 459 #else 460 #define MSR_HVB (0ULL) 461 #define msr_hv (0) 462 #endif 463 #endif 464 465 /* Facility Status and Control (FSCR) bits */ 466 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */ 467 #define FSCR_TAR (63 - 55) /* Target Address Register */ 468 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */ 469 #define FSCR_IC_MASK (0xFFULL) 470 #define FSCR_IC_POS (63 - 7) 471 #define FSCR_IC_DSCR_SPR3 2 472 #define FSCR_IC_PMU 3 473 #define FSCR_IC_BHRB 4 474 #define FSCR_IC_TM 5 475 #define FSCR_IC_EBB 7 476 #define FSCR_IC_TAR 8 477 478 /* Exception state register bits definition */ 479 #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */ 480 #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */ 481 #define ESR_PTR (1 << (63 - 38)) /* Trap */ 482 #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */ 483 #define ESR_ST (1 << (63 - 40)) /* Store Operation */ 484 #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */ 485 #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */ 486 #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */ 487 #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */ 488 #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */ 489 #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */ 490 #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */ 491 #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */ 492 #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */ 493 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */ 494 #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */ 495 496 /* Transaction EXception And Summary Register bits */ 497 #define TEXASR_FAILURE_PERSISTENT (63 - 7) 498 #define TEXASR_DISALLOWED (63 - 8) 499 #define TEXASR_NESTING_OVERFLOW (63 - 9) 500 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10) 501 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11) 502 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12) 503 #define TEXASR_TRANSACTION_CONFLICT (63 - 13) 504 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14) 505 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15) 506 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16) 507 #define TEXASR_ABORT (63 - 31) 508 #define TEXASR_SUSPENDED (63 - 32) 509 #define TEXASR_PRIVILEGE_HV (63 - 34) 510 #define TEXASR_PRIVILEGE_PR (63 - 35) 511 #define TEXASR_FAILURE_SUMMARY (63 - 36) 512 #define TEXASR_TFIAR_EXACT (63 - 37) 513 #define TEXASR_ROT (63 - 38) 514 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */ 515 516 enum { 517 POWERPC_FLAG_NONE = 0x00000000, 518 /* Flag for MSR bit 25 signification (VRE/SPE) */ 519 POWERPC_FLAG_SPE = 0x00000001, 520 POWERPC_FLAG_VRE = 0x00000002, 521 /* Flag for MSR bit 17 signification (TGPR/CE) */ 522 POWERPC_FLAG_TGPR = 0x00000004, 523 POWERPC_FLAG_CE = 0x00000008, 524 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */ 525 POWERPC_FLAG_SE = 0x00000010, 526 POWERPC_FLAG_DWE = 0x00000020, 527 POWERPC_FLAG_UBLE = 0x00000040, 528 /* Flag for MSR bit 9 signification (BE/DE) */ 529 POWERPC_FLAG_BE = 0x00000080, 530 POWERPC_FLAG_DE = 0x00000100, 531 /* Flag for MSR bit 2 signification (PX/PMM) */ 532 POWERPC_FLAG_PX = 0x00000200, 533 POWERPC_FLAG_PMM = 0x00000400, 534 /* Flag for special features */ 535 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */ 536 POWERPC_FLAG_RTC_CLK = 0x00010000, 537 POWERPC_FLAG_BUS_CLK = 0x00020000, 538 /* Has CFAR */ 539 POWERPC_FLAG_CFAR = 0x00040000, 540 /* Has VSX */ 541 POWERPC_FLAG_VSX = 0x00080000, 542 /* Has Transaction Memory (ISA 2.07) */ 543 POWERPC_FLAG_TM = 0x00100000, 544 }; 545 546 /*****************************************************************************/ 547 /* Floating point status and control register */ 548 #define FPSCR_FX 31 /* Floating-point exception summary */ 549 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */ 550 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */ 551 #define FPSCR_OX 28 /* Floating-point overflow exception */ 552 #define FPSCR_UX 27 /* Floating-point underflow exception */ 553 #define FPSCR_ZX 26 /* Floating-point zero divide exception */ 554 #define FPSCR_XX 25 /* Floating-point inexact exception */ 555 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */ 556 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */ 557 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */ 558 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */ 559 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */ 560 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */ 561 #define FPSCR_FR 18 /* Floating-point fraction rounded */ 562 #define FPSCR_FI 17 /* Floating-point fraction inexact */ 563 #define FPSCR_C 16 /* Floating-point result class descriptor */ 564 #define FPSCR_FL 15 /* Floating-point less than or negative */ 565 #define FPSCR_FG 14 /* Floating-point greater than or negative */ 566 #define FPSCR_FE 13 /* Floating-point equal or zero */ 567 #define FPSCR_FU 12 /* Floating-point unordered or NaN */ 568 #define FPSCR_FPCC 12 /* Floating-point condition code */ 569 #define FPSCR_FPRF 12 /* Floating-point result flags */ 570 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */ 571 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */ 572 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */ 573 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */ 574 #define FPSCR_OE 6 /* Floating-point overflow exception enable */ 575 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */ 576 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */ 577 #define FPSCR_XE 3 /* Floating-point inexact exception enable */ 578 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */ 579 #define FPSCR_RN1 1 580 #define FPSCR_RN 0 /* Floating-point rounding control */ 581 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1) 582 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1) 583 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1) 584 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1) 585 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1) 586 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1) 587 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1) 588 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1) 589 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1) 590 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1) 591 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1) 592 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1) 593 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF) 594 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1) 595 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1) 596 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1) 597 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1) 598 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1) 599 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1) 600 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1) 601 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1) 602 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1) 603 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3) 604 /* Invalid operation exception summary */ 605 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \ 606 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \ 607 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \ 608 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \ 609 (1 << FPSCR_VXCVI))) 610 /* exception summary */ 611 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F) 612 /* enabled exception summary */ 613 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \ 614 0x1F) 615 616 #define FP_FX (1ull << FPSCR_FX) 617 #define FP_FEX (1ull << FPSCR_FEX) 618 #define FP_VX (1ull << FPSCR_VX) 619 #define FP_OX (1ull << FPSCR_OX) 620 #define FP_UX (1ull << FPSCR_UX) 621 #define FP_ZX (1ull << FPSCR_ZX) 622 #define FP_XX (1ull << FPSCR_XX) 623 #define FP_VXSNAN (1ull << FPSCR_VXSNAN) 624 #define FP_VXISI (1ull << FPSCR_VXISI) 625 #define FP_VXIDI (1ull << FPSCR_VXIDI) 626 #define FP_VXZDZ (1ull << FPSCR_VXZDZ) 627 #define FP_VXIMZ (1ull << FPSCR_VXIMZ) 628 #define FP_VXVC (1ull << FPSCR_VXVC) 629 #define FP_FR (1ull << FSPCR_FR) 630 #define FP_FI (1ull << FPSCR_FI) 631 #define FP_C (1ull << FPSCR_C) 632 #define FP_FL (1ull << FPSCR_FL) 633 #define FP_FG (1ull << FPSCR_FG) 634 #define FP_FE (1ull << FPSCR_FE) 635 #define FP_FU (1ull << FPSCR_FU) 636 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU) 637 #define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU) 638 #define FP_VXSOFT (1ull << FPSCR_VXSOFT) 639 #define FP_VXSQRT (1ull << FPSCR_VXSQRT) 640 #define FP_VXCVI (1ull << FPSCR_VXCVI) 641 #define FP_VE (1ull << FPSCR_VE) 642 #define FP_OE (1ull << FPSCR_OE) 643 #define FP_UE (1ull << FPSCR_UE) 644 #define FP_ZE (1ull << FPSCR_ZE) 645 #define FP_XE (1ull << FPSCR_XE) 646 #define FP_NI (1ull << FPSCR_NI) 647 #define FP_RN1 (1ull << FPSCR_RN1) 648 #define FP_RN (1ull << FPSCR_RN) 649 650 /* the exception bits which can be cleared by mcrfs - includes FX */ 651 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \ 652 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \ 653 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \ 654 FP_VXSQRT | FP_VXCVI) 655 656 /*****************************************************************************/ 657 /* Vector status and control register */ 658 #define VSCR_NJ 16 /* Vector non-java */ 659 #define VSCR_SAT 0 /* Vector saturation */ 660 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1) 661 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1) 662 663 /*****************************************************************************/ 664 /* BookE e500 MMU registers */ 665 666 #define MAS0_NV_SHIFT 0 667 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT) 668 669 #define MAS0_WQ_SHIFT 12 670 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT) 671 /* Write TLB entry regardless of reservation */ 672 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT) 673 /* Write TLB entry only already in use */ 674 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT) 675 /* Clear TLB entry */ 676 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT) 677 678 #define MAS0_HES_SHIFT 14 679 #define MAS0_HES (1 << MAS0_HES_SHIFT) 680 681 #define MAS0_ESEL_SHIFT 16 682 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT) 683 684 #define MAS0_TLBSEL_SHIFT 28 685 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT) 686 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT) 687 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT) 688 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT) 689 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT) 690 691 #define MAS0_ATSEL_SHIFT 31 692 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT) 693 #define MAS0_ATSEL_TLB 0 694 #define MAS0_ATSEL_LRAT MAS0_ATSEL 695 696 #define MAS1_TSIZE_SHIFT 7 697 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT) 698 699 #define MAS1_TS_SHIFT 12 700 #define MAS1_TS (1 << MAS1_TS_SHIFT) 701 702 #define MAS1_IND_SHIFT 13 703 #define MAS1_IND (1 << MAS1_IND_SHIFT) 704 705 #define MAS1_TID_SHIFT 16 706 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT) 707 708 #define MAS1_IPROT_SHIFT 30 709 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT) 710 711 #define MAS1_VALID_SHIFT 31 712 #define MAS1_VALID 0x80000000 713 714 #define MAS2_EPN_SHIFT 12 715 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT) 716 717 #define MAS2_ACM_SHIFT 6 718 #define MAS2_ACM (1 << MAS2_ACM_SHIFT) 719 720 #define MAS2_VLE_SHIFT 5 721 #define MAS2_VLE (1 << MAS2_VLE_SHIFT) 722 723 #define MAS2_W_SHIFT 4 724 #define MAS2_W (1 << MAS2_W_SHIFT) 725 726 #define MAS2_I_SHIFT 3 727 #define MAS2_I (1 << MAS2_I_SHIFT) 728 729 #define MAS2_M_SHIFT 2 730 #define MAS2_M (1 << MAS2_M_SHIFT) 731 732 #define MAS2_G_SHIFT 1 733 #define MAS2_G (1 << MAS2_G_SHIFT) 734 735 #define MAS2_E_SHIFT 0 736 #define MAS2_E (1 << MAS2_E_SHIFT) 737 738 #define MAS3_RPN_SHIFT 12 739 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT) 740 741 #define MAS3_U0 0x00000200 742 #define MAS3_U1 0x00000100 743 #define MAS3_U2 0x00000080 744 #define MAS3_U3 0x00000040 745 #define MAS3_UX 0x00000020 746 #define MAS3_SX 0x00000010 747 #define MAS3_UW 0x00000008 748 #define MAS3_SW 0x00000004 749 #define MAS3_UR 0x00000002 750 #define MAS3_SR 0x00000001 751 #define MAS3_SPSIZE_SHIFT 1 752 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT) 753 754 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT 755 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK 756 #define MAS4_TIDSELD_MASK 0x00030000 757 #define MAS4_TIDSELD_PID0 0x00000000 758 #define MAS4_TIDSELD_PID1 0x00010000 759 #define MAS4_TIDSELD_PID2 0x00020000 760 #define MAS4_TIDSELD_PIDZ 0x00030000 761 #define MAS4_INDD 0x00008000 /* Default IND */ 762 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT 763 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK 764 #define MAS4_ACMD 0x00000040 765 #define MAS4_VLED 0x00000020 766 #define MAS4_WD 0x00000010 767 #define MAS4_ID 0x00000008 768 #define MAS4_MD 0x00000004 769 #define MAS4_GD 0x00000002 770 #define MAS4_ED 0x00000001 771 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */ 772 #define MAS4_WIMGED_SHIFT 0 773 774 #define MAS5_SGS 0x80000000 775 #define MAS5_SLPID_MASK 0x00000fff 776 777 #define MAS6_SPID0 0x3fff0000 778 #define MAS6_SPID1 0x00007ffe 779 #define MAS6_ISIZE(x) MAS1_TSIZE(x) 780 #define MAS6_SAS 0x00000001 781 #define MAS6_SPID MAS6_SPID0 782 #define MAS6_SIND 0x00000002 /* Indirect page */ 783 #define MAS6_SIND_SHIFT 1 784 #define MAS6_SPID_MASK 0x3fff0000 785 #define MAS6_SPID_SHIFT 16 786 #define MAS6_ISIZE_MASK 0x00000f80 787 #define MAS6_ISIZE_SHIFT 7 788 789 #define MAS7_RPN 0xffffffff 790 791 #define MAS8_TGS 0x80000000 792 #define MAS8_VF 0x40000000 793 #define MAS8_TLBPID 0x00000fff 794 795 /* Bit definitions for MMUCFG */ 796 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ 797 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */ 798 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */ 799 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */ 800 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */ 801 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */ 802 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */ 803 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */ 804 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */ 805 806 /* Bit definitions for MMUCSR0 */ 807 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */ 808 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */ 809 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */ 810 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */ 811 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \ 812 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI) 813 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */ 814 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */ 815 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */ 816 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */ 817 818 /* TLBnCFG encoding */ 819 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */ 820 #define TLBnCFG_HES 0x00002000 /* HW select supported */ 821 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */ 822 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */ 823 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */ 824 #define TLBnCFG_IND 0x00020000 /* IND entries supported */ 825 #define TLBnCFG_PT 0x00040000 /* Can load from page table */ 826 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */ 827 #define TLBnCFG_MINSIZE_SHIFT 20 828 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */ 829 #define TLBnCFG_MAXSIZE_SHIFT 16 830 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */ 831 #define TLBnCFG_ASSOC_SHIFT 24 832 833 /* TLBnPS encoding */ 834 #define TLBnPS_4K 0x00000004 835 #define TLBnPS_8K 0x00000008 836 #define TLBnPS_16K 0x00000010 837 #define TLBnPS_32K 0x00000020 838 #define TLBnPS_64K 0x00000040 839 #define TLBnPS_128K 0x00000080 840 #define TLBnPS_256K 0x00000100 841 #define TLBnPS_512K 0x00000200 842 #define TLBnPS_1M 0x00000400 843 #define TLBnPS_2M 0x00000800 844 #define TLBnPS_4M 0x00001000 845 #define TLBnPS_8M 0x00002000 846 #define TLBnPS_16M 0x00004000 847 #define TLBnPS_32M 0x00008000 848 #define TLBnPS_64M 0x00010000 849 #define TLBnPS_128M 0x00020000 850 #define TLBnPS_256M 0x00040000 851 #define TLBnPS_512M 0x00080000 852 #define TLBnPS_1G 0x00100000 853 #define TLBnPS_2G 0x00200000 854 #define TLBnPS_4G 0x00400000 855 #define TLBnPS_8G 0x00800000 856 #define TLBnPS_16G 0x01000000 857 #define TLBnPS_32G 0x02000000 858 #define TLBnPS_64G 0x04000000 859 #define TLBnPS_128G 0x08000000 860 #define TLBnPS_256G 0x10000000 861 862 /* tlbilx action encoding */ 863 #define TLBILX_T_ALL 0 864 #define TLBILX_T_TID 1 865 #define TLBILX_T_FULLMATCH 3 866 #define TLBILX_T_CLASS0 4 867 #define TLBILX_T_CLASS1 5 868 #define TLBILX_T_CLASS2 6 869 #define TLBILX_T_CLASS3 7 870 871 /* BookE 2.06 helper defines */ 872 873 #define BOOKE206_FLUSH_TLB0 (1 << 0) 874 #define BOOKE206_FLUSH_TLB1 (1 << 1) 875 #define BOOKE206_FLUSH_TLB2 (1 << 2) 876 #define BOOKE206_FLUSH_TLB3 (1 << 3) 877 878 /* number of possible TLBs */ 879 #define BOOKE206_MAX_TLBN 4 880 881 /*****************************************************************************/ 882 /* Embedded.Processor Control */ 883 884 #define DBELL_TYPE_SHIFT 27 885 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT) 886 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT) 887 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT) 888 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT) 889 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT) 890 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT) 891 892 #define DBELL_BRDCAST (1 << 26) 893 #define DBELL_LPIDTAG_SHIFT 14 894 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT) 895 #define DBELL_PIRTAG_MASK 0x3fff 896 897 /*****************************************************************************/ 898 /* Segment page size information, used by recent hash MMUs 899 * The format of this structure mirrors kvm_ppc_smmu_info 900 */ 901 902 #define PPC_PAGE_SIZES_MAX_SZ 8 903 904 struct ppc_one_page_size { 905 uint32_t page_shift; /* Page shift (or 0) */ 906 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */ 907 }; 908 909 struct ppc_one_seg_page_size { 910 uint32_t page_shift; /* Base page shift of segment (or 0) */ 911 uint32_t slb_enc; /* SLB encoding for BookS */ 912 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ]; 913 }; 914 915 struct ppc_segment_page_sizes { 916 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ]; 917 }; 918 919 920 /*****************************************************************************/ 921 /* The whole PowerPC CPU context */ 922 #define NB_MMU_MODES 8 923 924 #define PPC_CPU_OPCODES_LEN 0x40 925 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20 926 927 struct CPUPPCState { 928 /* First are the most commonly used resources 929 * during translated code execution 930 */ 931 /* general purpose registers */ 932 target_ulong gpr[32]; 933 /* Storage for GPR MSB, used by the SPE extension */ 934 target_ulong gprh[32]; 935 /* LR */ 936 target_ulong lr; 937 /* CTR */ 938 target_ulong ctr; 939 /* condition register */ 940 uint32_t crf[8]; 941 #if defined(TARGET_PPC64) 942 /* CFAR */ 943 target_ulong cfar; 944 #endif 945 /* XER (with SO, OV, CA split out) */ 946 target_ulong xer; 947 target_ulong so; 948 target_ulong ov; 949 target_ulong ca; 950 /* Reservation address */ 951 target_ulong reserve_addr; 952 /* Reservation value */ 953 target_ulong reserve_val; 954 target_ulong reserve_val2; 955 /* Reservation store address */ 956 target_ulong reserve_ea; 957 /* Reserved store source register and size */ 958 target_ulong reserve_info; 959 960 /* Those ones are used in supervisor mode only */ 961 /* machine state register */ 962 target_ulong msr; 963 /* temporary general purpose registers */ 964 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */ 965 966 /* Floating point execution context */ 967 float_status fp_status; 968 /* floating point registers */ 969 float64 fpr[32]; 970 /* floating point status and control register */ 971 target_ulong fpscr; 972 973 /* Next instruction pointer */ 974 target_ulong nip; 975 976 int access_type; /* when a memory exception occurs, the access 977 type is stored here */ 978 979 CPU_COMMON 980 981 /* MMU context - only relevant for full system emulation */ 982 #if !defined(CONFIG_USER_ONLY) 983 #if defined(TARGET_PPC64) 984 /* PowerPC 64 SLB area */ 985 ppc_slb_t slb[MAX_SLB_ENTRIES]; 986 int32_t slb_nr; 987 /* tcg TLB needs flush (deferred slb inval instruction typically) */ 988 #endif 989 /* segment registers */ 990 hwaddr htab_base; 991 /* mask used to normalize hash value to PTEG index */ 992 hwaddr htab_mask; 993 target_ulong sr[32]; 994 /* externally stored hash table */ 995 uint8_t *external_htab; 996 /* BATs */ 997 uint32_t nb_BATs; 998 target_ulong DBAT[2][8]; 999 target_ulong IBAT[2][8]; 1000 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */ 1001 int32_t nb_tlb; /* Total number of TLB */ 1002 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ 1003 int nb_ways; /* Number of ways in the TLB set */ 1004 int last_way; /* Last used way used to allocate TLB in a LRU way */ 1005 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ 1006 int nb_pids; /* Number of available PID registers */ 1007 int tlb_type; /* Type of TLB we're dealing with */ 1008 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */ 1009 /* 403 dedicated access protection registers */ 1010 target_ulong pb[4]; 1011 bool tlb_dirty; /* Set to non-zero when modifying TLB */ 1012 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */ 1013 uint32_t tlb_need_flush; /* Delayed flush needed */ 1014 #define TLB_NEED_LOCAL_FLUSH 0x1 1015 #define TLB_NEED_GLOBAL_FLUSH 0x2 1016 #endif 1017 1018 /* Other registers */ 1019 /* Special purpose registers */ 1020 target_ulong spr[1024]; 1021 ppc_spr_t spr_cb[1024]; 1022 /* Altivec registers */ 1023 ppc_avr_t avr[32]; 1024 uint32_t vscr; 1025 /* VSX registers */ 1026 uint64_t vsr[32]; 1027 /* SPE registers */ 1028 uint64_t spe_acc; 1029 uint32_t spe_fscr; 1030 /* SPE and Altivec can share a status since they will never be used 1031 * simultaneously */ 1032 float_status vec_status; 1033 1034 /* Internal devices resources */ 1035 /* Time base and decrementer */ 1036 ppc_tb_t *tb_env; 1037 /* Device control registers */ 1038 ppc_dcr_t *dcr_env; 1039 1040 int dcache_line_size; 1041 int icache_line_size; 1042 1043 /* Those resources are used during exception processing */ 1044 /* CPU model definition */ 1045 target_ulong msr_mask; 1046 powerpc_mmu_t mmu_model; 1047 powerpc_excp_t excp_model; 1048 powerpc_input_t bus_model; 1049 int bfd_mach; 1050 uint32_t flags; 1051 uint64_t insns_flags; 1052 uint64_t insns_flags2; 1053 #if defined(TARGET_PPC64) 1054 struct ppc_segment_page_sizes sps; 1055 ppc_slb_t vrma_slb; 1056 target_ulong rmls; 1057 bool ci_large_pages; 1058 #endif 1059 1060 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1061 uint64_t vpa_addr; 1062 uint64_t slb_shadow_addr, slb_shadow_size; 1063 uint64_t dtl_addr, dtl_size; 1064 #endif /* TARGET_PPC64 */ 1065 1066 int error_code; 1067 uint32_t pending_interrupts; 1068 #if !defined(CONFIG_USER_ONLY) 1069 /* This is the IRQ controller, which is implementation dependent 1070 * and only relevant when emulating a complete machine. 1071 */ 1072 uint32_t irq_input_state; 1073 void **irq_inputs; 1074 /* Exception vectors */ 1075 target_ulong excp_vectors[POWERPC_EXCP_NB]; 1076 target_ulong excp_prefix; 1077 target_ulong ivor_mask; 1078 target_ulong ivpr_mask; 1079 target_ulong hreset_vector; 1080 hwaddr mpic_iack; 1081 /* true when the external proxy facility mode is enabled */ 1082 bool mpic_proxy; 1083 /* set when the processor has an HV mode, thus HV priv 1084 * instructions and SPRs are diallowed if MSR:HV is 0 1085 */ 1086 bool has_hv_mode; 1087 /* On P7/P8, set when in PM state, we need to handle resume 1088 * in a special way (such as routing some resume causes to 1089 * 0x100), so flag this here. 1090 */ 1091 bool in_pm_state; 1092 #endif 1093 1094 /* Those resources are used only during code translation */ 1095 /* opcode handlers */ 1096 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN]; 1097 1098 /* Those resources are used only in QEMU core */ 1099 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */ 1100 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */ 1101 int immu_idx; /* precomputed MMU index to speed up insn access */ 1102 int dmmu_idx; /* precomputed MMU index to speed up data accesses */ 1103 1104 /* Power management */ 1105 int (*check_pow)(CPUPPCState *env); 1106 1107 #if !defined(CONFIG_USER_ONLY) 1108 void *load_info; /* Holds boot loading state. */ 1109 #endif 1110 1111 /* booke timers */ 1112 1113 /* Specifies bit locations of the Time Base used to signal a fixed timer 1114 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer) 1115 * 1116 * 0 selects the least significant bit. 1117 * 63 selects the most significant bit. 1118 */ 1119 uint8_t fit_period[4]; 1120 uint8_t wdt_period[4]; 1121 1122 /* Transactional memory state */ 1123 target_ulong tm_gpr[32]; 1124 ppc_avr_t tm_vsr[64]; 1125 uint64_t tm_cr; 1126 uint64_t tm_lr; 1127 uint64_t tm_ctr; 1128 uint64_t tm_fpscr; 1129 uint64_t tm_amr; 1130 uint64_t tm_ppr; 1131 uint64_t tm_vrsave; 1132 uint32_t tm_vscr; 1133 uint64_t tm_dscr; 1134 uint64_t tm_tar; 1135 }; 1136 1137 #define SET_FIT_PERIOD(a_, b_, c_, d_) \ 1138 do { \ 1139 env->fit_period[0] = (a_); \ 1140 env->fit_period[1] = (b_); \ 1141 env->fit_period[2] = (c_); \ 1142 env->fit_period[3] = (d_); \ 1143 } while (0) 1144 1145 #define SET_WDT_PERIOD(a_, b_, c_, d_) \ 1146 do { \ 1147 env->wdt_period[0] = (a_); \ 1148 env->wdt_period[1] = (b_); \ 1149 env->wdt_period[2] = (c_); \ 1150 env->wdt_period[3] = (d_); \ 1151 } while (0) 1152 1153 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor; 1154 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass; 1155 1156 /** 1157 * PowerPCCPU: 1158 * @env: #CPUPPCState 1159 * @cpu_dt_id: CPU index used in the device tree. KVM uses this index too 1160 * @max_compat: Maximal supported logical PVR from the command line 1161 * @compat_pvr: Current logical PVR, zero if in "raw" mode 1162 * 1163 * A PowerPC CPU. 1164 */ 1165 struct PowerPCCPU { 1166 /*< private >*/ 1167 CPUState parent_obj; 1168 /*< public >*/ 1169 1170 CPUPPCState env; 1171 int cpu_dt_id; 1172 uint32_t max_compat; 1173 uint32_t compat_pvr; 1174 PPCVirtualHypervisor *vhyp; 1175 1176 /* Fields related to migration compatibility hacks */ 1177 bool pre_2_8_migration; 1178 target_ulong mig_msr_mask; 1179 uint64_t mig_insns_flags; 1180 uint64_t mig_insns_flags2; 1181 uint32_t mig_nb_BATs; 1182 }; 1183 1184 static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env) 1185 { 1186 return container_of(env, PowerPCCPU, env); 1187 } 1188 1189 #define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e)) 1190 1191 #define ENV_OFFSET offsetof(PowerPCCPU, env) 1192 1193 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); 1194 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); 1195 1196 struct PPCVirtualHypervisor { 1197 Object parent; 1198 }; 1199 1200 struct PPCVirtualHypervisorClass { 1201 InterfaceClass parent; 1202 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu); 1203 }; 1204 1205 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor" 1206 #define PPC_VIRTUAL_HYPERVISOR(obj) \ 1207 OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR) 1208 #define PPC_VIRTUAL_HYPERVISOR_CLASS(klass) \ 1209 OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \ 1210 TYPE_PPC_VIRTUAL_HYPERVISOR) 1211 #define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \ 1212 OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \ 1213 TYPE_PPC_VIRTUAL_HYPERVISOR) 1214 1215 void ppc_cpu_do_interrupt(CPUState *cpu); 1216 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); 1217 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, 1218 int flags); 1219 void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f, 1220 fprintf_function cpu_fprintf, int flags); 1221 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 1222 int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 1223 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg); 1224 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1225 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg); 1226 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1227 int cpuid, void *opaque); 1228 #ifndef CONFIG_USER_ONLY 1229 void ppc_cpu_do_system_reset(CPUState *cs); 1230 extern const struct VMStateDescription vmstate_ppc_cpu; 1231 #endif 1232 1233 /*****************************************************************************/ 1234 PowerPCCPU *cpu_ppc_init(const char *cpu_model); 1235 void ppc_translate_init(void); 1236 const char *ppc_cpu_lookup_alias(const char *alias); 1237 /* you can call this signal handler from your SIGBUS and SIGSEGV 1238 signal handlers to inform the virtual CPU of exceptions. non zero 1239 is returned if the signal was handled by the virtual CPU. */ 1240 int cpu_ppc_signal_handler (int host_signum, void *pinfo, 1241 void *puc); 1242 #if defined(CONFIG_USER_ONLY) 1243 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, 1244 int mmu_idx); 1245 #endif 1246 1247 #if !defined(CONFIG_USER_ONLY) 1248 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value); 1249 #endif /* !defined(CONFIG_USER_ONLY) */ 1250 void ppc_store_msr (CPUPPCState *env, target_ulong value); 1251 1252 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf); 1253 #if defined(TARGET_PPC64) 1254 #endif 1255 1256 /* Time-base and decrementer management */ 1257 #ifndef NO_CPU_IO_DEFS 1258 uint64_t cpu_ppc_load_tbl (CPUPPCState *env); 1259 uint32_t cpu_ppc_load_tbu (CPUPPCState *env); 1260 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value); 1261 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value); 1262 uint64_t cpu_ppc_load_atbl (CPUPPCState *env); 1263 uint32_t cpu_ppc_load_atbu (CPUPPCState *env); 1264 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value); 1265 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value); 1266 bool ppc_decr_clear_on_delivery(CPUPPCState *env); 1267 uint32_t cpu_ppc_load_decr (CPUPPCState *env); 1268 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value); 1269 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env); 1270 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value); 1271 uint64_t cpu_ppc_load_purr (CPUPPCState *env); 1272 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env); 1273 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env); 1274 #if !defined(CONFIG_USER_ONLY) 1275 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value); 1276 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value); 1277 target_ulong load_40x_pit (CPUPPCState *env); 1278 void store_40x_pit (CPUPPCState *env, target_ulong val); 1279 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val); 1280 void store_40x_sler (CPUPPCState *env, uint32_t val); 1281 void store_booke_tcr (CPUPPCState *env, target_ulong val); 1282 void store_booke_tsr (CPUPPCState *env, target_ulong val); 1283 void ppc_tlb_invalidate_all (CPUPPCState *env); 1284 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr); 1285 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp); 1286 void cpu_ppc_set_papr(PowerPCCPU *cpu); 1287 #endif 1288 #endif 1289 1290 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask); 1291 1292 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) 1293 { 1294 uint64_t gprv; 1295 1296 gprv = env->gpr[gprn]; 1297 if (env->flags & POWERPC_FLAG_SPE) { 1298 /* If the CPU implements the SPE extension, we have to get the 1299 * high bits of the GPR from the gprh storage area 1300 */ 1301 gprv &= 0xFFFFFFFFULL; 1302 gprv |= (uint64_t)env->gprh[gprn] << 32; 1303 } 1304 1305 return gprv; 1306 } 1307 1308 /* Device control registers */ 1309 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp); 1310 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val); 1311 1312 #define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model)) 1313 1314 #define cpu_signal_handler cpu_ppc_signal_handler 1315 #define cpu_list ppc_cpu_list 1316 1317 /* MMU modes definitions */ 1318 #define MMU_USER_IDX 0 1319 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch) 1320 { 1321 return ifetch ? env->immu_idx : env->dmmu_idx; 1322 } 1323 1324 /* Compatibility modes */ 1325 #if defined(TARGET_PPC64) 1326 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr, 1327 uint32_t min_compat_pvr, uint32_t max_compat_pvr); 1328 void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp); 1329 #if !defined(CONFIG_USER_ONLY) 1330 void ppc_set_compat_all(uint32_t compat_pvr, Error **errp); 1331 #endif 1332 int ppc_compat_max_threads(PowerPCCPU *cpu); 1333 #endif /* defined(TARGET_PPC64) */ 1334 1335 #include "exec/cpu-all.h" 1336 1337 /*****************************************************************************/ 1338 /* CRF definitions */ 1339 #define CRF_LT_BIT 3 1340 #define CRF_GT_BIT 2 1341 #define CRF_EQ_BIT 1 1342 #define CRF_SO_BIT 0 1343 #define CRF_LT (1 << CRF_LT_BIT) 1344 #define CRF_GT (1 << CRF_GT_BIT) 1345 #define CRF_EQ (1 << CRF_EQ_BIT) 1346 #define CRF_SO (1 << CRF_SO_BIT) 1347 /* For SPE extensions */ 1348 #define CRF_CH (1 << CRF_LT_BIT) 1349 #define CRF_CL (1 << CRF_GT_BIT) 1350 #define CRF_CH_OR_CL (1 << CRF_EQ_BIT) 1351 #define CRF_CH_AND_CL (1 << CRF_SO_BIT) 1352 1353 /* XER definitions */ 1354 #define XER_SO 31 1355 #define XER_OV 30 1356 #define XER_CA 29 1357 #define XER_CMP 8 1358 #define XER_BC 0 1359 #define xer_so (env->so) 1360 #define xer_ov (env->ov) 1361 #define xer_ca (env->ca) 1362 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF) 1363 #define xer_bc ((env->xer >> XER_BC) & 0x7F) 1364 1365 /* SPR definitions */ 1366 #define SPR_MQ (0x000) 1367 #define SPR_XER (0x001) 1368 #define SPR_601_VRTCU (0x004) 1369 #define SPR_601_VRTCL (0x005) 1370 #define SPR_601_UDECR (0x006) 1371 #define SPR_LR (0x008) 1372 #define SPR_CTR (0x009) 1373 #define SPR_UAMR (0x00C) 1374 #define SPR_DSCR (0x011) 1375 #define SPR_DSISR (0x012) 1376 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */ 1377 #define SPR_601_RTCU (0x014) 1378 #define SPR_601_RTCL (0x015) 1379 #define SPR_DECR (0x016) 1380 #define SPR_SDR1 (0x019) 1381 #define SPR_SRR0 (0x01A) 1382 #define SPR_SRR1 (0x01B) 1383 #define SPR_CFAR (0x01C) 1384 #define SPR_AMR (0x01D) 1385 #define SPR_ACOP (0x01F) 1386 #define SPR_BOOKE_PID (0x030) 1387 #define SPR_BOOKS_PID (0x030) 1388 #define SPR_BOOKE_DECAR (0x036) 1389 #define SPR_BOOKE_CSRR0 (0x03A) 1390 #define SPR_BOOKE_CSRR1 (0x03B) 1391 #define SPR_BOOKE_DEAR (0x03D) 1392 #define SPR_IAMR (0x03D) 1393 #define SPR_BOOKE_ESR (0x03E) 1394 #define SPR_BOOKE_IVPR (0x03F) 1395 #define SPR_MPC_EIE (0x050) 1396 #define SPR_MPC_EID (0x051) 1397 #define SPR_MPC_NRI (0x052) 1398 #define SPR_TFHAR (0x080) 1399 #define SPR_TFIAR (0x081) 1400 #define SPR_TEXASR (0x082) 1401 #define SPR_TEXASRU (0x083) 1402 #define SPR_UCTRL (0x088) 1403 #define SPR_MPC_CMPA (0x090) 1404 #define SPR_MPC_CMPB (0x091) 1405 #define SPR_MPC_CMPC (0x092) 1406 #define SPR_MPC_CMPD (0x093) 1407 #define SPR_MPC_ECR (0x094) 1408 #define SPR_MPC_DER (0x095) 1409 #define SPR_MPC_COUNTA (0x096) 1410 #define SPR_MPC_COUNTB (0x097) 1411 #define SPR_CTRL (0x098) 1412 #define SPR_MPC_CMPE (0x098) 1413 #define SPR_MPC_CMPF (0x099) 1414 #define SPR_FSCR (0x099) 1415 #define SPR_MPC_CMPG (0x09A) 1416 #define SPR_MPC_CMPH (0x09B) 1417 #define SPR_MPC_LCTRL1 (0x09C) 1418 #define SPR_MPC_LCTRL2 (0x09D) 1419 #define SPR_UAMOR (0x09D) 1420 #define SPR_MPC_ICTRL (0x09E) 1421 #define SPR_MPC_BAR (0x09F) 1422 #define SPR_PSPB (0x09F) 1423 #define SPR_DAWR (0x0B4) 1424 #define SPR_RPR (0x0BA) 1425 #define SPR_CIABR (0x0BB) 1426 #define SPR_DAWRX (0x0BC) 1427 #define SPR_HFSCR (0x0BE) 1428 #define SPR_VRSAVE (0x100) 1429 #define SPR_USPRG0 (0x100) 1430 #define SPR_USPRG1 (0x101) 1431 #define SPR_USPRG2 (0x102) 1432 #define SPR_USPRG3 (0x103) 1433 #define SPR_USPRG4 (0x104) 1434 #define SPR_USPRG5 (0x105) 1435 #define SPR_USPRG6 (0x106) 1436 #define SPR_USPRG7 (0x107) 1437 #define SPR_VTBL (0x10C) 1438 #define SPR_VTBU (0x10D) 1439 #define SPR_SPRG0 (0x110) 1440 #define SPR_SPRG1 (0x111) 1441 #define SPR_SPRG2 (0x112) 1442 #define SPR_SPRG3 (0x113) 1443 #define SPR_SPRG4 (0x114) 1444 #define SPR_SCOMC (0x114) 1445 #define SPR_SPRG5 (0x115) 1446 #define SPR_SCOMD (0x115) 1447 #define SPR_SPRG6 (0x116) 1448 #define SPR_SPRG7 (0x117) 1449 #define SPR_ASR (0x118) 1450 #define SPR_EAR (0x11A) 1451 #define SPR_TBL (0x11C) 1452 #define SPR_TBU (0x11D) 1453 #define SPR_TBU40 (0x11E) 1454 #define SPR_SVR (0x11E) 1455 #define SPR_BOOKE_PIR (0x11E) 1456 #define SPR_PVR (0x11F) 1457 #define SPR_HSPRG0 (0x130) 1458 #define SPR_BOOKE_DBSR (0x130) 1459 #define SPR_HSPRG1 (0x131) 1460 #define SPR_HDSISR (0x132) 1461 #define SPR_HDAR (0x133) 1462 #define SPR_BOOKE_EPCR (0x133) 1463 #define SPR_SPURR (0x134) 1464 #define SPR_BOOKE_DBCR0 (0x134) 1465 #define SPR_IBCR (0x135) 1466 #define SPR_PURR (0x135) 1467 #define SPR_BOOKE_DBCR1 (0x135) 1468 #define SPR_DBCR (0x136) 1469 #define SPR_HDEC (0x136) 1470 #define SPR_BOOKE_DBCR2 (0x136) 1471 #define SPR_HIOR (0x137) 1472 #define SPR_MBAR (0x137) 1473 #define SPR_RMOR (0x138) 1474 #define SPR_BOOKE_IAC1 (0x138) 1475 #define SPR_HRMOR (0x139) 1476 #define SPR_BOOKE_IAC2 (0x139) 1477 #define SPR_HSRR0 (0x13A) 1478 #define SPR_BOOKE_IAC3 (0x13A) 1479 #define SPR_HSRR1 (0x13B) 1480 #define SPR_BOOKE_IAC4 (0x13B) 1481 #define SPR_BOOKE_DAC1 (0x13C) 1482 #define SPR_MMCRH (0x13C) 1483 #define SPR_DABR2 (0x13D) 1484 #define SPR_BOOKE_DAC2 (0x13D) 1485 #define SPR_TFMR (0x13D) 1486 #define SPR_BOOKE_DVC1 (0x13E) 1487 #define SPR_LPCR (0x13E) 1488 #define SPR_BOOKE_DVC2 (0x13F) 1489 #define SPR_LPIDR (0x13F) 1490 #define SPR_BOOKE_TSR (0x150) 1491 #define SPR_HMER (0x150) 1492 #define SPR_HMEER (0x151) 1493 #define SPR_PCR (0x152) 1494 #define SPR_BOOKE_LPIDR (0x152) 1495 #define SPR_BOOKE_TCR (0x154) 1496 #define SPR_BOOKE_TLB0PS (0x158) 1497 #define SPR_BOOKE_TLB1PS (0x159) 1498 #define SPR_BOOKE_TLB2PS (0x15A) 1499 #define SPR_BOOKE_TLB3PS (0x15B) 1500 #define SPR_AMOR (0x15D) 1501 #define SPR_BOOKE_MAS7_MAS3 (0x174) 1502 #define SPR_BOOKE_IVOR0 (0x190) 1503 #define SPR_BOOKE_IVOR1 (0x191) 1504 #define SPR_BOOKE_IVOR2 (0x192) 1505 #define SPR_BOOKE_IVOR3 (0x193) 1506 #define SPR_BOOKE_IVOR4 (0x194) 1507 #define SPR_BOOKE_IVOR5 (0x195) 1508 #define SPR_BOOKE_IVOR6 (0x196) 1509 #define SPR_BOOKE_IVOR7 (0x197) 1510 #define SPR_BOOKE_IVOR8 (0x198) 1511 #define SPR_BOOKE_IVOR9 (0x199) 1512 #define SPR_BOOKE_IVOR10 (0x19A) 1513 #define SPR_BOOKE_IVOR11 (0x19B) 1514 #define SPR_BOOKE_IVOR12 (0x19C) 1515 #define SPR_BOOKE_IVOR13 (0x19D) 1516 #define SPR_BOOKE_IVOR14 (0x19E) 1517 #define SPR_BOOKE_IVOR15 (0x19F) 1518 #define SPR_BOOKE_IVOR38 (0x1B0) 1519 #define SPR_BOOKE_IVOR39 (0x1B1) 1520 #define SPR_BOOKE_IVOR40 (0x1B2) 1521 #define SPR_BOOKE_IVOR41 (0x1B3) 1522 #define SPR_BOOKE_IVOR42 (0x1B4) 1523 #define SPR_BOOKE_GIVOR2 (0x1B8) 1524 #define SPR_BOOKE_GIVOR3 (0x1B9) 1525 #define SPR_BOOKE_GIVOR4 (0x1BA) 1526 #define SPR_BOOKE_GIVOR8 (0x1BB) 1527 #define SPR_BOOKE_GIVOR13 (0x1BC) 1528 #define SPR_BOOKE_GIVOR14 (0x1BD) 1529 #define SPR_TIR (0x1BE) 1530 #define SPR_BOOKE_SPEFSCR (0x200) 1531 #define SPR_Exxx_BBEAR (0x201) 1532 #define SPR_Exxx_BBTAR (0x202) 1533 #define SPR_Exxx_L1CFG0 (0x203) 1534 #define SPR_Exxx_L1CFG1 (0x204) 1535 #define SPR_Exxx_NPIDR (0x205) 1536 #define SPR_ATBL (0x20E) 1537 #define SPR_ATBU (0x20F) 1538 #define SPR_IBAT0U (0x210) 1539 #define SPR_BOOKE_IVOR32 (0x210) 1540 #define SPR_RCPU_MI_GRA (0x210) 1541 #define SPR_IBAT0L (0x211) 1542 #define SPR_BOOKE_IVOR33 (0x211) 1543 #define SPR_IBAT1U (0x212) 1544 #define SPR_BOOKE_IVOR34 (0x212) 1545 #define SPR_IBAT1L (0x213) 1546 #define SPR_BOOKE_IVOR35 (0x213) 1547 #define SPR_IBAT2U (0x214) 1548 #define SPR_BOOKE_IVOR36 (0x214) 1549 #define SPR_IBAT2L (0x215) 1550 #define SPR_BOOKE_IVOR37 (0x215) 1551 #define SPR_IBAT3U (0x216) 1552 #define SPR_IBAT3L (0x217) 1553 #define SPR_DBAT0U (0x218) 1554 #define SPR_RCPU_L2U_GRA (0x218) 1555 #define SPR_DBAT0L (0x219) 1556 #define SPR_DBAT1U (0x21A) 1557 #define SPR_DBAT1L (0x21B) 1558 #define SPR_DBAT2U (0x21C) 1559 #define SPR_DBAT2L (0x21D) 1560 #define SPR_DBAT3U (0x21E) 1561 #define SPR_DBAT3L (0x21F) 1562 #define SPR_IBAT4U (0x230) 1563 #define SPR_RPCU_BBCMCR (0x230) 1564 #define SPR_MPC_IC_CST (0x230) 1565 #define SPR_Exxx_CTXCR (0x230) 1566 #define SPR_IBAT4L (0x231) 1567 #define SPR_MPC_IC_ADR (0x231) 1568 #define SPR_Exxx_DBCR3 (0x231) 1569 #define SPR_IBAT5U (0x232) 1570 #define SPR_MPC_IC_DAT (0x232) 1571 #define SPR_Exxx_DBCNT (0x232) 1572 #define SPR_IBAT5L (0x233) 1573 #define SPR_IBAT6U (0x234) 1574 #define SPR_IBAT6L (0x235) 1575 #define SPR_IBAT7U (0x236) 1576 #define SPR_IBAT7L (0x237) 1577 #define SPR_DBAT4U (0x238) 1578 #define SPR_RCPU_L2U_MCR (0x238) 1579 #define SPR_MPC_DC_CST (0x238) 1580 #define SPR_Exxx_ALTCTXCR (0x238) 1581 #define SPR_DBAT4L (0x239) 1582 #define SPR_MPC_DC_ADR (0x239) 1583 #define SPR_DBAT5U (0x23A) 1584 #define SPR_BOOKE_MCSRR0 (0x23A) 1585 #define SPR_MPC_DC_DAT (0x23A) 1586 #define SPR_DBAT5L (0x23B) 1587 #define SPR_BOOKE_MCSRR1 (0x23B) 1588 #define SPR_DBAT6U (0x23C) 1589 #define SPR_BOOKE_MCSR (0x23C) 1590 #define SPR_DBAT6L (0x23D) 1591 #define SPR_Exxx_MCAR (0x23D) 1592 #define SPR_DBAT7U (0x23E) 1593 #define SPR_BOOKE_DSRR0 (0x23E) 1594 #define SPR_DBAT7L (0x23F) 1595 #define SPR_BOOKE_DSRR1 (0x23F) 1596 #define SPR_BOOKE_SPRG8 (0x25C) 1597 #define SPR_BOOKE_SPRG9 (0x25D) 1598 #define SPR_BOOKE_MAS0 (0x270) 1599 #define SPR_BOOKE_MAS1 (0x271) 1600 #define SPR_BOOKE_MAS2 (0x272) 1601 #define SPR_BOOKE_MAS3 (0x273) 1602 #define SPR_BOOKE_MAS4 (0x274) 1603 #define SPR_BOOKE_MAS5 (0x275) 1604 #define SPR_BOOKE_MAS6 (0x276) 1605 #define SPR_BOOKE_PID1 (0x279) 1606 #define SPR_BOOKE_PID2 (0x27A) 1607 #define SPR_MPC_DPDR (0x280) 1608 #define SPR_MPC_IMMR (0x288) 1609 #define SPR_BOOKE_TLB0CFG (0x2B0) 1610 #define SPR_BOOKE_TLB1CFG (0x2B1) 1611 #define SPR_BOOKE_TLB2CFG (0x2B2) 1612 #define SPR_BOOKE_TLB3CFG (0x2B3) 1613 #define SPR_BOOKE_EPR (0x2BE) 1614 #define SPR_PERF0 (0x300) 1615 #define SPR_RCPU_MI_RBA0 (0x300) 1616 #define SPR_MPC_MI_CTR (0x300) 1617 #define SPR_POWER_USIER (0x300) 1618 #define SPR_PERF1 (0x301) 1619 #define SPR_RCPU_MI_RBA1 (0x301) 1620 #define SPR_POWER_UMMCR2 (0x301) 1621 #define SPR_PERF2 (0x302) 1622 #define SPR_RCPU_MI_RBA2 (0x302) 1623 #define SPR_MPC_MI_AP (0x302) 1624 #define SPR_POWER_UMMCRA (0x302) 1625 #define SPR_PERF3 (0x303) 1626 #define SPR_RCPU_MI_RBA3 (0x303) 1627 #define SPR_MPC_MI_EPN (0x303) 1628 #define SPR_POWER_UPMC1 (0x303) 1629 #define SPR_PERF4 (0x304) 1630 #define SPR_POWER_UPMC2 (0x304) 1631 #define SPR_PERF5 (0x305) 1632 #define SPR_MPC_MI_TWC (0x305) 1633 #define SPR_POWER_UPMC3 (0x305) 1634 #define SPR_PERF6 (0x306) 1635 #define SPR_MPC_MI_RPN (0x306) 1636 #define SPR_POWER_UPMC4 (0x306) 1637 #define SPR_PERF7 (0x307) 1638 #define SPR_POWER_UPMC5 (0x307) 1639 #define SPR_PERF8 (0x308) 1640 #define SPR_RCPU_L2U_RBA0 (0x308) 1641 #define SPR_MPC_MD_CTR (0x308) 1642 #define SPR_POWER_UPMC6 (0x308) 1643 #define SPR_PERF9 (0x309) 1644 #define SPR_RCPU_L2U_RBA1 (0x309) 1645 #define SPR_MPC_MD_CASID (0x309) 1646 #define SPR_970_UPMC7 (0X309) 1647 #define SPR_PERFA (0x30A) 1648 #define SPR_RCPU_L2U_RBA2 (0x30A) 1649 #define SPR_MPC_MD_AP (0x30A) 1650 #define SPR_970_UPMC8 (0X30A) 1651 #define SPR_PERFB (0x30B) 1652 #define SPR_RCPU_L2U_RBA3 (0x30B) 1653 #define SPR_MPC_MD_EPN (0x30B) 1654 #define SPR_POWER_UMMCR0 (0X30B) 1655 #define SPR_PERFC (0x30C) 1656 #define SPR_MPC_MD_TWB (0x30C) 1657 #define SPR_POWER_USIAR (0X30C) 1658 #define SPR_PERFD (0x30D) 1659 #define SPR_MPC_MD_TWC (0x30D) 1660 #define SPR_POWER_USDAR (0X30D) 1661 #define SPR_PERFE (0x30E) 1662 #define SPR_MPC_MD_RPN (0x30E) 1663 #define SPR_POWER_UMMCR1 (0X30E) 1664 #define SPR_PERFF (0x30F) 1665 #define SPR_MPC_MD_TW (0x30F) 1666 #define SPR_UPERF0 (0x310) 1667 #define SPR_POWER_SIER (0x310) 1668 #define SPR_UPERF1 (0x311) 1669 #define SPR_POWER_MMCR2 (0x311) 1670 #define SPR_UPERF2 (0x312) 1671 #define SPR_POWER_MMCRA (0X312) 1672 #define SPR_UPERF3 (0x313) 1673 #define SPR_POWER_PMC1 (0X313) 1674 #define SPR_UPERF4 (0x314) 1675 #define SPR_POWER_PMC2 (0X314) 1676 #define SPR_UPERF5 (0x315) 1677 #define SPR_POWER_PMC3 (0X315) 1678 #define SPR_UPERF6 (0x316) 1679 #define SPR_POWER_PMC4 (0X316) 1680 #define SPR_UPERF7 (0x317) 1681 #define SPR_POWER_PMC5 (0X317) 1682 #define SPR_UPERF8 (0x318) 1683 #define SPR_POWER_PMC6 (0X318) 1684 #define SPR_UPERF9 (0x319) 1685 #define SPR_970_PMC7 (0X319) 1686 #define SPR_UPERFA (0x31A) 1687 #define SPR_970_PMC8 (0X31A) 1688 #define SPR_UPERFB (0x31B) 1689 #define SPR_POWER_MMCR0 (0X31B) 1690 #define SPR_UPERFC (0x31C) 1691 #define SPR_POWER_SIAR (0X31C) 1692 #define SPR_UPERFD (0x31D) 1693 #define SPR_POWER_SDAR (0X31D) 1694 #define SPR_UPERFE (0x31E) 1695 #define SPR_POWER_MMCR1 (0X31E) 1696 #define SPR_UPERFF (0x31F) 1697 #define SPR_RCPU_MI_RA0 (0x320) 1698 #define SPR_MPC_MI_DBCAM (0x320) 1699 #define SPR_BESCRS (0x320) 1700 #define SPR_RCPU_MI_RA1 (0x321) 1701 #define SPR_MPC_MI_DBRAM0 (0x321) 1702 #define SPR_BESCRSU (0x321) 1703 #define SPR_RCPU_MI_RA2 (0x322) 1704 #define SPR_MPC_MI_DBRAM1 (0x322) 1705 #define SPR_BESCRR (0x322) 1706 #define SPR_RCPU_MI_RA3 (0x323) 1707 #define SPR_BESCRRU (0x323) 1708 #define SPR_EBBHR (0x324) 1709 #define SPR_EBBRR (0x325) 1710 #define SPR_BESCR (0x326) 1711 #define SPR_RCPU_L2U_RA0 (0x328) 1712 #define SPR_MPC_MD_DBCAM (0x328) 1713 #define SPR_RCPU_L2U_RA1 (0x329) 1714 #define SPR_MPC_MD_DBRAM0 (0x329) 1715 #define SPR_RCPU_L2U_RA2 (0x32A) 1716 #define SPR_MPC_MD_DBRAM1 (0x32A) 1717 #define SPR_RCPU_L2U_RA3 (0x32B) 1718 #define SPR_TAR (0x32F) 1719 #define SPR_IC (0x350) 1720 #define SPR_VTB (0x351) 1721 #define SPR_MMCRC (0x353) 1722 #define SPR_440_INV0 (0x370) 1723 #define SPR_440_INV1 (0x371) 1724 #define SPR_440_INV2 (0x372) 1725 #define SPR_440_INV3 (0x373) 1726 #define SPR_440_ITV0 (0x374) 1727 #define SPR_440_ITV1 (0x375) 1728 #define SPR_440_ITV2 (0x376) 1729 #define SPR_440_ITV3 (0x377) 1730 #define SPR_440_CCR1 (0x378) 1731 #define SPR_TACR (0x378) 1732 #define SPR_TCSCR (0x379) 1733 #define SPR_CSIGR (0x37a) 1734 #define SPR_DCRIPR (0x37B) 1735 #define SPR_POWER_SPMC1 (0x37C) 1736 #define SPR_POWER_SPMC2 (0x37D) 1737 #define SPR_POWER_MMCRS (0x37E) 1738 #define SPR_WORT (0x37F) 1739 #define SPR_PPR (0x380) 1740 #define SPR_750_GQR0 (0x390) 1741 #define SPR_440_DNV0 (0x390) 1742 #define SPR_750_GQR1 (0x391) 1743 #define SPR_440_DNV1 (0x391) 1744 #define SPR_750_GQR2 (0x392) 1745 #define SPR_440_DNV2 (0x392) 1746 #define SPR_750_GQR3 (0x393) 1747 #define SPR_440_DNV3 (0x393) 1748 #define SPR_750_GQR4 (0x394) 1749 #define SPR_440_DTV0 (0x394) 1750 #define SPR_750_GQR5 (0x395) 1751 #define SPR_440_DTV1 (0x395) 1752 #define SPR_750_GQR6 (0x396) 1753 #define SPR_440_DTV2 (0x396) 1754 #define SPR_750_GQR7 (0x397) 1755 #define SPR_440_DTV3 (0x397) 1756 #define SPR_750_THRM4 (0x398) 1757 #define SPR_750CL_HID2 (0x398) 1758 #define SPR_440_DVLIM (0x398) 1759 #define SPR_750_WPAR (0x399) 1760 #define SPR_440_IVLIM (0x399) 1761 #define SPR_TSCR (0x399) 1762 #define SPR_750_DMAU (0x39A) 1763 #define SPR_750_DMAL (0x39B) 1764 #define SPR_440_RSTCFG (0x39B) 1765 #define SPR_BOOKE_DCDBTRL (0x39C) 1766 #define SPR_BOOKE_DCDBTRH (0x39D) 1767 #define SPR_BOOKE_ICDBTRL (0x39E) 1768 #define SPR_BOOKE_ICDBTRH (0x39F) 1769 #define SPR_74XX_UMMCR2 (0x3A0) 1770 #define SPR_7XX_UPMC5 (0x3A1) 1771 #define SPR_7XX_UPMC6 (0x3A2) 1772 #define SPR_UBAMR (0x3A7) 1773 #define SPR_7XX_UMMCR0 (0x3A8) 1774 #define SPR_7XX_UPMC1 (0x3A9) 1775 #define SPR_7XX_UPMC2 (0x3AA) 1776 #define SPR_7XX_USIAR (0x3AB) 1777 #define SPR_7XX_UMMCR1 (0x3AC) 1778 #define SPR_7XX_UPMC3 (0x3AD) 1779 #define SPR_7XX_UPMC4 (0x3AE) 1780 #define SPR_USDA (0x3AF) 1781 #define SPR_40x_ZPR (0x3B0) 1782 #define SPR_BOOKE_MAS7 (0x3B0) 1783 #define SPR_74XX_MMCR2 (0x3B0) 1784 #define SPR_7XX_PMC5 (0x3B1) 1785 #define SPR_40x_PID (0x3B1) 1786 #define SPR_7XX_PMC6 (0x3B2) 1787 #define SPR_440_MMUCR (0x3B2) 1788 #define SPR_4xx_CCR0 (0x3B3) 1789 #define SPR_BOOKE_EPLC (0x3B3) 1790 #define SPR_405_IAC3 (0x3B4) 1791 #define SPR_BOOKE_EPSC (0x3B4) 1792 #define SPR_405_IAC4 (0x3B5) 1793 #define SPR_405_DVC1 (0x3B6) 1794 #define SPR_405_DVC2 (0x3B7) 1795 #define SPR_BAMR (0x3B7) 1796 #define SPR_7XX_MMCR0 (0x3B8) 1797 #define SPR_7XX_PMC1 (0x3B9) 1798 #define SPR_40x_SGR (0x3B9) 1799 #define SPR_7XX_PMC2 (0x3BA) 1800 #define SPR_40x_DCWR (0x3BA) 1801 #define SPR_7XX_SIAR (0x3BB) 1802 #define SPR_405_SLER (0x3BB) 1803 #define SPR_7XX_MMCR1 (0x3BC) 1804 #define SPR_405_SU0R (0x3BC) 1805 #define SPR_401_SKR (0x3BC) 1806 #define SPR_7XX_PMC3 (0x3BD) 1807 #define SPR_405_DBCR1 (0x3BD) 1808 #define SPR_7XX_PMC4 (0x3BE) 1809 #define SPR_SDA (0x3BF) 1810 #define SPR_403_VTBL (0x3CC) 1811 #define SPR_403_VTBU (0x3CD) 1812 #define SPR_DMISS (0x3D0) 1813 #define SPR_DCMP (0x3D1) 1814 #define SPR_HASH1 (0x3D2) 1815 #define SPR_HASH2 (0x3D3) 1816 #define SPR_BOOKE_ICDBDR (0x3D3) 1817 #define SPR_TLBMISS (0x3D4) 1818 #define SPR_IMISS (0x3D4) 1819 #define SPR_40x_ESR (0x3D4) 1820 #define SPR_PTEHI (0x3D5) 1821 #define SPR_ICMP (0x3D5) 1822 #define SPR_40x_DEAR (0x3D5) 1823 #define SPR_PTELO (0x3D6) 1824 #define SPR_RPA (0x3D6) 1825 #define SPR_40x_EVPR (0x3D6) 1826 #define SPR_L3PM (0x3D7) 1827 #define SPR_403_CDBCR (0x3D7) 1828 #define SPR_L3ITCR0 (0x3D8) 1829 #define SPR_TCR (0x3D8) 1830 #define SPR_40x_TSR (0x3D8) 1831 #define SPR_IBR (0x3DA) 1832 #define SPR_40x_TCR (0x3DA) 1833 #define SPR_ESASRR (0x3DB) 1834 #define SPR_40x_PIT (0x3DB) 1835 #define SPR_403_TBL (0x3DC) 1836 #define SPR_403_TBU (0x3DD) 1837 #define SPR_SEBR (0x3DE) 1838 #define SPR_40x_SRR2 (0x3DE) 1839 #define SPR_SER (0x3DF) 1840 #define SPR_40x_SRR3 (0x3DF) 1841 #define SPR_L3OHCR (0x3E8) 1842 #define SPR_L3ITCR1 (0x3E9) 1843 #define SPR_L3ITCR2 (0x3EA) 1844 #define SPR_L3ITCR3 (0x3EB) 1845 #define SPR_HID0 (0x3F0) 1846 #define SPR_40x_DBSR (0x3F0) 1847 #define SPR_HID1 (0x3F1) 1848 #define SPR_IABR (0x3F2) 1849 #define SPR_40x_DBCR0 (0x3F2) 1850 #define SPR_601_HID2 (0x3F2) 1851 #define SPR_Exxx_L1CSR0 (0x3F2) 1852 #define SPR_ICTRL (0x3F3) 1853 #define SPR_HID2 (0x3F3) 1854 #define SPR_750CL_HID4 (0x3F3) 1855 #define SPR_Exxx_L1CSR1 (0x3F3) 1856 #define SPR_440_DBDR (0x3F3) 1857 #define SPR_LDSTDB (0x3F4) 1858 #define SPR_750_TDCL (0x3F4) 1859 #define SPR_40x_IAC1 (0x3F4) 1860 #define SPR_MMUCSR0 (0x3F4) 1861 #define SPR_970_HID4 (0x3F4) 1862 #define SPR_DABR (0x3F5) 1863 #define DABR_MASK (~(target_ulong)0x7) 1864 #define SPR_Exxx_BUCSR (0x3F5) 1865 #define SPR_40x_IAC2 (0x3F5) 1866 #define SPR_601_HID5 (0x3F5) 1867 #define SPR_40x_DAC1 (0x3F6) 1868 #define SPR_MSSCR0 (0x3F6) 1869 #define SPR_970_HID5 (0x3F6) 1870 #define SPR_MSSSR0 (0x3F7) 1871 #define SPR_MSSCR1 (0x3F7) 1872 #define SPR_DABRX (0x3F7) 1873 #define SPR_40x_DAC2 (0x3F7) 1874 #define SPR_MMUCFG (0x3F7) 1875 #define SPR_LDSTCR (0x3F8) 1876 #define SPR_L2PMCR (0x3F8) 1877 #define SPR_750FX_HID2 (0x3F8) 1878 #define SPR_Exxx_L1FINV0 (0x3F8) 1879 #define SPR_L2CR (0x3F9) 1880 #define SPR_L3CR (0x3FA) 1881 #define SPR_750_TDCH (0x3FA) 1882 #define SPR_IABR2 (0x3FA) 1883 #define SPR_40x_DCCR (0x3FA) 1884 #define SPR_ICTC (0x3FB) 1885 #define SPR_40x_ICCR (0x3FB) 1886 #define SPR_THRM1 (0x3FC) 1887 #define SPR_403_PBL1 (0x3FC) 1888 #define SPR_SP (0x3FD) 1889 #define SPR_THRM2 (0x3FD) 1890 #define SPR_403_PBU1 (0x3FD) 1891 #define SPR_604_HID13 (0x3FD) 1892 #define SPR_LT (0x3FE) 1893 #define SPR_THRM3 (0x3FE) 1894 #define SPR_RCPU_FPECR (0x3FE) 1895 #define SPR_403_PBL2 (0x3FE) 1896 #define SPR_PIR (0x3FF) 1897 #define SPR_403_PBU2 (0x3FF) 1898 #define SPR_601_HID15 (0x3FF) 1899 #define SPR_604_HID15 (0x3FF) 1900 #define SPR_E500_SVR (0x3FF) 1901 1902 /* Disable MAS Interrupt Updates for Hypervisor */ 1903 #define EPCR_DMIUH (1 << 22) 1904 /* Disable Guest TLB Management Instructions */ 1905 #define EPCR_DGTMI (1 << 23) 1906 /* Guest Interrupt Computation Mode */ 1907 #define EPCR_GICM (1 << 24) 1908 /* Interrupt Computation Mode */ 1909 #define EPCR_ICM (1 << 25) 1910 /* Disable Embedded Hypervisor Debug */ 1911 #define EPCR_DUVD (1 << 26) 1912 /* Instruction Storage Interrupt Directed to Guest State */ 1913 #define EPCR_ISIGS (1 << 27) 1914 /* Data Storage Interrupt Directed to Guest State */ 1915 #define EPCR_DSIGS (1 << 28) 1916 /* Instruction TLB Error Interrupt Directed to Guest State */ 1917 #define EPCR_ITLBGS (1 << 29) 1918 /* Data TLB Error Interrupt Directed to Guest State */ 1919 #define EPCR_DTLBGS (1 << 30) 1920 /* External Input Interrupt Directed to Guest State */ 1921 #define EPCR_EXTGS (1 << 31) 1922 1923 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ 1924 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */ 1925 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */ 1926 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ 1927 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ 1928 1929 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ 1930 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */ 1931 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */ 1932 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ 1933 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ 1934 1935 /* HID0 bits */ 1936 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */ 1937 #define HID0_DOZE (1 << 23) /* pre-2.06 */ 1938 #define HID0_NAP (1 << 22) /* pre-2.06 */ 1939 #define HID0_HILE (1ull << (63 - 19)) /* POWER8 */ 1940 1941 /*****************************************************************************/ 1942 /* PowerPC Instructions types definitions */ 1943 enum { 1944 PPC_NONE = 0x0000000000000000ULL, 1945 /* PowerPC base instructions set */ 1946 PPC_INSNS_BASE = 0x0000000000000001ULL, 1947 /* integer operations instructions */ 1948 #define PPC_INTEGER PPC_INSNS_BASE 1949 /* flow control instructions */ 1950 #define PPC_FLOW PPC_INSNS_BASE 1951 /* virtual memory instructions */ 1952 #define PPC_MEM PPC_INSNS_BASE 1953 /* ld/st with reservation instructions */ 1954 #define PPC_RES PPC_INSNS_BASE 1955 /* spr/msr access instructions */ 1956 #define PPC_MISC PPC_INSNS_BASE 1957 /* Deprecated instruction sets */ 1958 /* Original POWER instruction set */ 1959 PPC_POWER = 0x0000000000000002ULL, 1960 /* POWER2 instruction set extension */ 1961 PPC_POWER2 = 0x0000000000000004ULL, 1962 /* Power RTC support */ 1963 PPC_POWER_RTC = 0x0000000000000008ULL, 1964 /* Power-to-PowerPC bridge (601) */ 1965 PPC_POWER_BR = 0x0000000000000010ULL, 1966 /* 64 bits PowerPC instruction set */ 1967 PPC_64B = 0x0000000000000020ULL, 1968 /* New 64 bits extensions (PowerPC 2.0x) */ 1969 PPC_64BX = 0x0000000000000040ULL, 1970 /* 64 bits hypervisor extensions */ 1971 PPC_64H = 0x0000000000000080ULL, 1972 /* New wait instruction (PowerPC 2.0x) */ 1973 PPC_WAIT = 0x0000000000000100ULL, 1974 /* Time base mftb instruction */ 1975 PPC_MFTB = 0x0000000000000200ULL, 1976 1977 /* Fixed-point unit extensions */ 1978 /* PowerPC 602 specific */ 1979 PPC_602_SPEC = 0x0000000000000400ULL, 1980 /* isel instruction */ 1981 PPC_ISEL = 0x0000000000000800ULL, 1982 /* popcntb instruction */ 1983 PPC_POPCNTB = 0x0000000000001000ULL, 1984 /* string load / store */ 1985 PPC_STRING = 0x0000000000002000ULL, 1986 /* real mode cache inhibited load / store */ 1987 PPC_CILDST = 0x0000000000004000ULL, 1988 1989 /* Floating-point unit extensions */ 1990 /* Optional floating point instructions */ 1991 PPC_FLOAT = 0x0000000000010000ULL, 1992 /* New floating-point extensions (PowerPC 2.0x) */ 1993 PPC_FLOAT_EXT = 0x0000000000020000ULL, 1994 PPC_FLOAT_FSQRT = 0x0000000000040000ULL, 1995 PPC_FLOAT_FRES = 0x0000000000080000ULL, 1996 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL, 1997 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL, 1998 PPC_FLOAT_FSEL = 0x0000000000400000ULL, 1999 PPC_FLOAT_STFIWX = 0x0000000000800000ULL, 2000 2001 /* Vector/SIMD extensions */ 2002 /* Altivec support */ 2003 PPC_ALTIVEC = 0x0000000001000000ULL, 2004 /* PowerPC 2.03 SPE extension */ 2005 PPC_SPE = 0x0000000002000000ULL, 2006 /* PowerPC 2.03 SPE single-precision floating-point extension */ 2007 PPC_SPE_SINGLE = 0x0000000004000000ULL, 2008 /* PowerPC 2.03 SPE double-precision floating-point extension */ 2009 PPC_SPE_DOUBLE = 0x0000000008000000ULL, 2010 2011 /* Optional memory control instructions */ 2012 PPC_MEM_TLBIA = 0x0000000010000000ULL, 2013 PPC_MEM_TLBIE = 0x0000000020000000ULL, 2014 PPC_MEM_TLBSYNC = 0x0000000040000000ULL, 2015 /* sync instruction */ 2016 PPC_MEM_SYNC = 0x0000000080000000ULL, 2017 /* eieio instruction */ 2018 PPC_MEM_EIEIO = 0x0000000100000000ULL, 2019 2020 /* Cache control instructions */ 2021 PPC_CACHE = 0x0000000200000000ULL, 2022 /* icbi instruction */ 2023 PPC_CACHE_ICBI = 0x0000000400000000ULL, 2024 /* dcbz instruction */ 2025 PPC_CACHE_DCBZ = 0x0000000800000000ULL, 2026 /* dcba instruction */ 2027 PPC_CACHE_DCBA = 0x0000002000000000ULL, 2028 /* Freescale cache locking instructions */ 2029 PPC_CACHE_LOCK = 0x0000004000000000ULL, 2030 2031 /* MMU related extensions */ 2032 /* external control instructions */ 2033 PPC_EXTERN = 0x0000010000000000ULL, 2034 /* segment register access instructions */ 2035 PPC_SEGMENT = 0x0000020000000000ULL, 2036 /* PowerPC 6xx TLB management instructions */ 2037 PPC_6xx_TLB = 0x0000040000000000ULL, 2038 /* PowerPC 74xx TLB management instructions */ 2039 PPC_74xx_TLB = 0x0000080000000000ULL, 2040 /* PowerPC 40x TLB management instructions */ 2041 PPC_40x_TLB = 0x0000100000000000ULL, 2042 /* segment register access instructions for PowerPC 64 "bridge" */ 2043 PPC_SEGMENT_64B = 0x0000200000000000ULL, 2044 /* SLB management */ 2045 PPC_SLBI = 0x0000400000000000ULL, 2046 2047 /* Embedded PowerPC dedicated instructions */ 2048 PPC_WRTEE = 0x0001000000000000ULL, 2049 /* PowerPC 40x exception model */ 2050 PPC_40x_EXCP = 0x0002000000000000ULL, 2051 /* PowerPC 405 Mac instructions */ 2052 PPC_405_MAC = 0x0004000000000000ULL, 2053 /* PowerPC 440 specific instructions */ 2054 PPC_440_SPEC = 0x0008000000000000ULL, 2055 /* BookE (embedded) PowerPC specification */ 2056 PPC_BOOKE = 0x0010000000000000ULL, 2057 /* mfapidi instruction */ 2058 PPC_MFAPIDI = 0x0020000000000000ULL, 2059 /* tlbiva instruction */ 2060 PPC_TLBIVA = 0x0040000000000000ULL, 2061 /* tlbivax instruction */ 2062 PPC_TLBIVAX = 0x0080000000000000ULL, 2063 /* PowerPC 4xx dedicated instructions */ 2064 PPC_4xx_COMMON = 0x0100000000000000ULL, 2065 /* PowerPC 40x ibct instructions */ 2066 PPC_40x_ICBT = 0x0200000000000000ULL, 2067 /* rfmci is not implemented in all BookE PowerPC */ 2068 PPC_RFMCI = 0x0400000000000000ULL, 2069 /* rfdi instruction */ 2070 PPC_RFDI = 0x0800000000000000ULL, 2071 /* DCR accesses */ 2072 PPC_DCR = 0x1000000000000000ULL, 2073 /* DCR extended accesse */ 2074 PPC_DCRX = 0x2000000000000000ULL, 2075 /* user-mode DCR access, implemented in PowerPC 460 */ 2076 PPC_DCRUX = 0x4000000000000000ULL, 2077 /* popcntw and popcntd instructions */ 2078 PPC_POPCNTWD = 0x8000000000000000ULL, 2079 2080 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \ 2081 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \ 2082 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \ 2083 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \ 2084 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \ 2085 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \ 2086 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \ 2087 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \ 2088 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \ 2089 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \ 2090 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \ 2091 | PPC_MEM_SYNC | PPC_MEM_EIEIO \ 2092 | PPC_CACHE | PPC_CACHE_ICBI \ 2093 | PPC_CACHE_DCBZ \ 2094 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \ 2095 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \ 2096 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \ 2097 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \ 2098 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \ 2099 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \ 2100 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \ 2101 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \ 2102 | PPC_POPCNTWD | PPC_CILDST) 2103 2104 /* extended type values */ 2105 2106 /* BookE 2.06 PowerPC specification */ 2107 PPC2_BOOKE206 = 0x0000000000000001ULL, 2108 /* VSX (extensions to Altivec / VMX) */ 2109 PPC2_VSX = 0x0000000000000002ULL, 2110 /* Decimal Floating Point (DFP) */ 2111 PPC2_DFP = 0x0000000000000004ULL, 2112 /* Embedded.Processor Control */ 2113 PPC2_PRCNTL = 0x0000000000000008ULL, 2114 /* Byte-reversed, indexed, double-word load and store */ 2115 PPC2_DBRX = 0x0000000000000010ULL, 2116 /* Book I 2.05 PowerPC specification */ 2117 PPC2_ISA205 = 0x0000000000000020ULL, 2118 /* VSX additions in ISA 2.07 */ 2119 PPC2_VSX207 = 0x0000000000000040ULL, 2120 /* ISA 2.06B bpermd */ 2121 PPC2_PERM_ISA206 = 0x0000000000000080ULL, 2122 /* ISA 2.06B divide extended variants */ 2123 PPC2_DIVE_ISA206 = 0x0000000000000100ULL, 2124 /* ISA 2.06B larx/stcx. instructions */ 2125 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL, 2126 /* ISA 2.06B floating point integer conversion */ 2127 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL, 2128 /* ISA 2.06B floating point test instructions */ 2129 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL, 2130 /* ISA 2.07 bctar instruction */ 2131 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL, 2132 /* ISA 2.07 load/store quadword */ 2133 PPC2_LSQ_ISA207 = 0x0000000000002000ULL, 2134 /* ISA 2.07 Altivec */ 2135 PPC2_ALTIVEC_207 = 0x0000000000004000ULL, 2136 /* PowerISA 2.07 Book3s specification */ 2137 PPC2_ISA207S = 0x0000000000008000ULL, 2138 /* Double precision floating point conversion for signed integer 64 */ 2139 PPC2_FP_CVT_S64 = 0x0000000000010000ULL, 2140 /* Transactional Memory (ISA 2.07, Book II) */ 2141 PPC2_TM = 0x0000000000020000ULL, 2142 /* Server PM instructgions (ISA 2.06, Book III) */ 2143 PPC2_PM_ISA206 = 0x0000000000040000ULL, 2144 /* POWER ISA 3.0 */ 2145 PPC2_ISA300 = 0x0000000000080000ULL, 2146 2147 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ 2148 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ 2149 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ 2150 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ 2151 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ 2152 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ 2153 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ 2154 PPC2_ISA300) 2155 }; 2156 2157 /*****************************************************************************/ 2158 /* Memory access type : 2159 * may be needed for precise access rights control and precise exceptions. 2160 */ 2161 enum { 2162 /* 1 bit to define user level / supervisor access */ 2163 ACCESS_USER = 0x00, 2164 ACCESS_SUPER = 0x01, 2165 /* Type of instruction that generated the access */ 2166 ACCESS_CODE = 0x10, /* Code fetch access */ 2167 ACCESS_INT = 0x20, /* Integer load/store access */ 2168 ACCESS_FLOAT = 0x30, /* floating point load/store access */ 2169 ACCESS_RES = 0x40, /* load/store with reservation */ 2170 ACCESS_EXT = 0x50, /* external access */ 2171 ACCESS_CACHE = 0x60, /* Cache manipulation */ 2172 }; 2173 2174 /* Hardware interruption sources: 2175 * all those exception can be raised simulteaneously 2176 */ 2177 /* Input pins definitions */ 2178 enum { 2179 /* 6xx bus input pins */ 2180 PPC6xx_INPUT_HRESET = 0, 2181 PPC6xx_INPUT_SRESET = 1, 2182 PPC6xx_INPUT_CKSTP_IN = 2, 2183 PPC6xx_INPUT_MCP = 3, 2184 PPC6xx_INPUT_SMI = 4, 2185 PPC6xx_INPUT_INT = 5, 2186 PPC6xx_INPUT_TBEN = 6, 2187 PPC6xx_INPUT_WAKEUP = 7, 2188 PPC6xx_INPUT_NB, 2189 }; 2190 2191 enum { 2192 /* Embedded PowerPC input pins */ 2193 PPCBookE_INPUT_HRESET = 0, 2194 PPCBookE_INPUT_SRESET = 1, 2195 PPCBookE_INPUT_CKSTP_IN = 2, 2196 PPCBookE_INPUT_MCP = 3, 2197 PPCBookE_INPUT_SMI = 4, 2198 PPCBookE_INPUT_INT = 5, 2199 PPCBookE_INPUT_CINT = 6, 2200 PPCBookE_INPUT_NB, 2201 }; 2202 2203 enum { 2204 /* PowerPC E500 input pins */ 2205 PPCE500_INPUT_RESET_CORE = 0, 2206 PPCE500_INPUT_MCK = 1, 2207 PPCE500_INPUT_CINT = 3, 2208 PPCE500_INPUT_INT = 4, 2209 PPCE500_INPUT_DEBUG = 6, 2210 PPCE500_INPUT_NB, 2211 }; 2212 2213 enum { 2214 /* PowerPC 40x input pins */ 2215 PPC40x_INPUT_RESET_CORE = 0, 2216 PPC40x_INPUT_RESET_CHIP = 1, 2217 PPC40x_INPUT_RESET_SYS = 2, 2218 PPC40x_INPUT_CINT = 3, 2219 PPC40x_INPUT_INT = 4, 2220 PPC40x_INPUT_HALT = 5, 2221 PPC40x_INPUT_DEBUG = 6, 2222 PPC40x_INPUT_NB, 2223 }; 2224 2225 enum { 2226 /* RCPU input pins */ 2227 PPCRCPU_INPUT_PORESET = 0, 2228 PPCRCPU_INPUT_HRESET = 1, 2229 PPCRCPU_INPUT_SRESET = 2, 2230 PPCRCPU_INPUT_IRQ0 = 3, 2231 PPCRCPU_INPUT_IRQ1 = 4, 2232 PPCRCPU_INPUT_IRQ2 = 5, 2233 PPCRCPU_INPUT_IRQ3 = 6, 2234 PPCRCPU_INPUT_IRQ4 = 7, 2235 PPCRCPU_INPUT_IRQ5 = 8, 2236 PPCRCPU_INPUT_IRQ6 = 9, 2237 PPCRCPU_INPUT_IRQ7 = 10, 2238 PPCRCPU_INPUT_NB, 2239 }; 2240 2241 #if defined(TARGET_PPC64) 2242 enum { 2243 /* PowerPC 970 input pins */ 2244 PPC970_INPUT_HRESET = 0, 2245 PPC970_INPUT_SRESET = 1, 2246 PPC970_INPUT_CKSTP = 2, 2247 PPC970_INPUT_TBEN = 3, 2248 PPC970_INPUT_MCP = 4, 2249 PPC970_INPUT_INT = 5, 2250 PPC970_INPUT_THINT = 6, 2251 PPC970_INPUT_NB, 2252 }; 2253 2254 enum { 2255 /* POWER7 input pins */ 2256 POWER7_INPUT_INT = 0, 2257 /* POWER7 probably has other inputs, but we don't care about them 2258 * for any existing machine. We can wire these up when we need 2259 * them */ 2260 POWER7_INPUT_NB, 2261 }; 2262 #endif 2263 2264 /* Hardware exceptions definitions */ 2265 enum { 2266 /* External hardware exception sources */ 2267 PPC_INTERRUPT_RESET = 0, /* Reset exception */ 2268 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */ 2269 PPC_INTERRUPT_MCK, /* Machine check exception */ 2270 PPC_INTERRUPT_EXT, /* External interrupt */ 2271 PPC_INTERRUPT_SMI, /* System management interrupt */ 2272 PPC_INTERRUPT_CEXT, /* Critical external interrupt */ 2273 PPC_INTERRUPT_DEBUG, /* External debug exception */ 2274 PPC_INTERRUPT_THERM, /* Thermal exception */ 2275 /* Internal hardware exception sources */ 2276 PPC_INTERRUPT_DECR, /* Decrementer exception */ 2277 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */ 2278 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */ 2279 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */ 2280 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */ 2281 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */ 2282 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */ 2283 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */ 2284 PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */ 2285 PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */ 2286 }; 2287 2288 /* Processor Compatibility mask (PCR) */ 2289 enum { 2290 PCR_COMPAT_2_05 = 1ull << (63-62), 2291 PCR_COMPAT_2_06 = 1ull << (63-61), 2292 PCR_COMPAT_2_07 = 1ull << (63-60), 2293 PCR_COMPAT_3_00 = 1ull << (63-59), 2294 PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */ 2295 PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */ 2296 PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */ 2297 }; 2298 2299 /* HMER/HMEER */ 2300 enum { 2301 HMER_MALFUNCTION_ALERT = 1ull << (63 - 0), 2302 HMER_PROC_RECV_DONE = 1ull << (63 - 2), 2303 HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3), 2304 HMER_TFAC_ERROR = 1ull << (63 - 4), 2305 HMER_TFMR_PARITY_ERROR = 1ull << (63 - 5), 2306 HMER_XSCOM_FAIL = 1ull << (63 - 8), 2307 HMER_XSCOM_DONE = 1ull << (63 - 9), 2308 HMER_PROC_RECV_AGAIN = 1ull << (63 - 11), 2309 HMER_WARN_RISE = 1ull << (63 - 14), 2310 HMER_WARN_FALL = 1ull << (63 - 15), 2311 HMER_SCOM_FIR_HMI = 1ull << (63 - 16), 2312 HMER_TRIG_FIR_HMI = 1ull << (63 - 17), 2313 HMER_HYP_RESOURCE_ERR = 1ull << (63 - 20), 2314 HMER_XSCOM_STATUS_MASK = 7ull << (63 - 23), 2315 HMER_XSCOM_STATUS_LSH = (63 - 23), 2316 }; 2317 2318 /* Alternate Interrupt Location (AIL) */ 2319 enum { 2320 AIL_NONE = 0, 2321 AIL_RESERVED = 1, 2322 AIL_0001_8000 = 2, 2323 AIL_C000_0000_0000_4000 = 3, 2324 }; 2325 2326 /*****************************************************************************/ 2327 2328 static inline target_ulong cpu_read_xer(CPUPPCState *env) 2329 { 2330 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA); 2331 } 2332 2333 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer) 2334 { 2335 env->so = (xer >> XER_SO) & 1; 2336 env->ov = (xer >> XER_OV) & 1; 2337 env->ca = (xer >> XER_CA) & 1; 2338 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)); 2339 } 2340 2341 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, 2342 target_ulong *cs_base, uint32_t *flags) 2343 { 2344 *pc = env->nip; 2345 *cs_base = 0; 2346 *flags = env->hflags; 2347 } 2348 2349 void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception); 2350 void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception, 2351 uintptr_t raddr); 2352 void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception, 2353 uint32_t error_code); 2354 void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception, 2355 uint32_t error_code, uintptr_t raddr); 2356 2357 #if !defined(CONFIG_USER_ONLY) 2358 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm) 2359 { 2360 uintptr_t tlbml = (uintptr_t)tlbm; 2361 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm; 2362 2363 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]); 2364 } 2365 2366 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn) 2367 { 2368 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; 2369 int r = tlbncfg & TLBnCFG_N_ENTRY; 2370 return r; 2371 } 2372 2373 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn) 2374 { 2375 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; 2376 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT; 2377 return r; 2378 } 2379 2380 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm) 2381 { 2382 int id = booke206_tlbm_id(env, tlbm); 2383 int end = 0; 2384 int i; 2385 2386 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 2387 end += booke206_tlb_size(env, i); 2388 if (id < end) { 2389 return i; 2390 } 2391 } 2392 2393 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id); 2394 return 0; 2395 } 2396 2397 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb) 2398 { 2399 int tlbn = booke206_tlbm_to_tlbn(env, tlb); 2400 int tlbid = booke206_tlbm_id(env, tlb); 2401 return tlbid & (booke206_tlb_ways(env, tlbn) - 1); 2402 } 2403 2404 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn, 2405 target_ulong ea, int way) 2406 { 2407 int r; 2408 uint32_t ways = booke206_tlb_ways(env, tlbn); 2409 int ways_bits = ctz32(ways); 2410 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn)); 2411 int i; 2412 2413 way &= ways - 1; 2414 ea >>= MAS2_EPN_SHIFT; 2415 ea &= (1 << (tlb_bits - ways_bits)) - 1; 2416 r = (ea << ways_bits) | way; 2417 2418 if (r >= booke206_tlb_size(env, tlbn)) { 2419 return NULL; 2420 } 2421 2422 /* bump up to tlbn index */ 2423 for (i = 0; i < tlbn; i++) { 2424 r += booke206_tlb_size(env, i); 2425 } 2426 2427 return &env->tlb.tlbm[r]; 2428 } 2429 2430 /* returns bitmap of supported page sizes for a given TLB */ 2431 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn) 2432 { 2433 bool mav2 = false; 2434 uint32_t ret = 0; 2435 2436 if (mav2) { 2437 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn]; 2438 } else { 2439 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; 2440 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT; 2441 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT; 2442 int i; 2443 for (i = min; i <= max; i++) { 2444 ret |= (1 << (i << 1)); 2445 } 2446 } 2447 2448 return ret; 2449 } 2450 2451 #endif 2452 2453 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr) 2454 { 2455 if (env->mmu_model == POWERPC_MMU_BOOKE206) { 2456 return msr & (1ULL << MSR_CM); 2457 } 2458 2459 return msr & (1ULL << MSR_SF); 2460 } 2461 2462 /** 2463 * Check whether register rx is in the range between start and 2464 * start + nregs (as needed by the LSWX and LSWI instructions) 2465 */ 2466 static inline bool lsw_reg_in_range(int start, int nregs, int rx) 2467 { 2468 return (start + nregs <= 32 && rx >= start && rx < start + nregs) || 2469 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32)); 2470 } 2471 2472 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env); 2473 2474 /** 2475 * ppc_get_vcpu_dt_id: 2476 * @cs: a PowerPCCPU struct. 2477 * 2478 * Returns a device-tree ID for a CPU. 2479 */ 2480 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu); 2481 2482 /** 2483 * ppc_get_vcpu_by_dt_id: 2484 * @cpu_dt_id: a device tree id 2485 * 2486 * Searches for a CPU by @cpu_dt_id. 2487 * 2488 * Returns: a PowerPCCPU struct 2489 */ 2490 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id); 2491 2492 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); 2493 #endif /* PPC_CPU_H */ 2494