1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_tcg.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(CPUPPCState *env) 154 { 155 /* Integer processing */ 156 spr_register(env, SPR_XER, "XER", 157 &spr_read_xer, &spr_write_xer, 158 &spr_read_xer, &spr_write_xer, 159 0x00000000); 160 /* Branch control */ 161 spr_register(env, SPR_LR, "LR", 162 &spr_read_lr, &spr_write_lr, 163 &spr_read_lr, &spr_write_lr, 164 0x00000000); 165 spr_register(env, SPR_CTR, "CTR", 166 &spr_read_ctr, &spr_write_ctr, 167 &spr_read_ctr, &spr_write_ctr, 168 0x00000000); 169 /* Interrupt processing */ 170 spr_register(env, SPR_SRR0, "SRR0", 171 SPR_NOACCESS, SPR_NOACCESS, 172 &spr_read_generic, &spr_write_generic, 173 0x00000000); 174 spr_register(env, SPR_SRR1, "SRR1", 175 SPR_NOACCESS, SPR_NOACCESS, 176 &spr_read_generic, &spr_write_generic, 177 0x00000000); 178 /* Processor control */ 179 spr_register(env, SPR_SPRG0, "SPRG0", 180 SPR_NOACCESS, SPR_NOACCESS, 181 &spr_read_generic, &spr_write_generic, 182 0x00000000); 183 spr_register(env, SPR_SPRG1, "SPRG1", 184 SPR_NOACCESS, SPR_NOACCESS, 185 &spr_read_generic, &spr_write_generic, 186 0x00000000); 187 spr_register(env, SPR_SPRG2, "SPRG2", 188 SPR_NOACCESS, SPR_NOACCESS, 189 &spr_read_generic, &spr_write_generic, 190 0x00000000); 191 spr_register(env, SPR_SPRG3, "SPRG3", 192 SPR_NOACCESS, SPR_NOACCESS, 193 &spr_read_generic, &spr_write_generic, 194 0x00000000); 195 } 196 197 /* SPR common to all non-embedded PowerPC, including 601 */ 198 static void register_ne_601_sprs(CPUPPCState *env) 199 { 200 /* Exception processing */ 201 spr_register_kvm(env, SPR_DSISR, "DSISR", 202 SPR_NOACCESS, SPR_NOACCESS, 203 &spr_read_generic, &spr_write_generic, 204 KVM_REG_PPC_DSISR, 0x00000000); 205 spr_register_kvm(env, SPR_DAR, "DAR", 206 SPR_NOACCESS, SPR_NOACCESS, 207 &spr_read_generic, &spr_write_generic, 208 KVM_REG_PPC_DAR, 0x00000000); 209 /* Timer */ 210 spr_register(env, SPR_DECR, "DECR", 211 SPR_NOACCESS, SPR_NOACCESS, 212 &spr_read_decr, &spr_write_decr, 213 0x00000000); 214 } 215 216 /* Storage Description Register 1 */ 217 static void register_sdr1_sprs(CPUPPCState *env) 218 { 219 #ifndef CONFIG_USER_ONLY 220 if (env->has_hv_mode) { 221 /* 222 * SDR1 is a hypervisor resource on CPUs which have a 223 * hypervisor mode 224 */ 225 spr_register_hv(env, SPR_SDR1, "SDR1", 226 SPR_NOACCESS, SPR_NOACCESS, 227 SPR_NOACCESS, SPR_NOACCESS, 228 &spr_read_generic, &spr_write_sdr1, 229 0x00000000); 230 } else { 231 spr_register(env, SPR_SDR1, "SDR1", 232 SPR_NOACCESS, SPR_NOACCESS, 233 &spr_read_generic, &spr_write_sdr1, 234 0x00000000); 235 } 236 #endif 237 } 238 239 /* BATs 0-3 */ 240 static void register_low_BATs(CPUPPCState *env) 241 { 242 #if !defined(CONFIG_USER_ONLY) 243 spr_register(env, SPR_IBAT0U, "IBAT0U", 244 SPR_NOACCESS, SPR_NOACCESS, 245 &spr_read_ibat, &spr_write_ibatu, 246 0x00000000); 247 spr_register(env, SPR_IBAT0L, "IBAT0L", 248 SPR_NOACCESS, SPR_NOACCESS, 249 &spr_read_ibat, &spr_write_ibatl, 250 0x00000000); 251 spr_register(env, SPR_IBAT1U, "IBAT1U", 252 SPR_NOACCESS, SPR_NOACCESS, 253 &spr_read_ibat, &spr_write_ibatu, 254 0x00000000); 255 spr_register(env, SPR_IBAT1L, "IBAT1L", 256 SPR_NOACCESS, SPR_NOACCESS, 257 &spr_read_ibat, &spr_write_ibatl, 258 0x00000000); 259 spr_register(env, SPR_IBAT2U, "IBAT2U", 260 SPR_NOACCESS, SPR_NOACCESS, 261 &spr_read_ibat, &spr_write_ibatu, 262 0x00000000); 263 spr_register(env, SPR_IBAT2L, "IBAT2L", 264 SPR_NOACCESS, SPR_NOACCESS, 265 &spr_read_ibat, &spr_write_ibatl, 266 0x00000000); 267 spr_register(env, SPR_IBAT3U, "IBAT3U", 268 SPR_NOACCESS, SPR_NOACCESS, 269 &spr_read_ibat, &spr_write_ibatu, 270 0x00000000); 271 spr_register(env, SPR_IBAT3L, "IBAT3L", 272 SPR_NOACCESS, SPR_NOACCESS, 273 &spr_read_ibat, &spr_write_ibatl, 274 0x00000000); 275 spr_register(env, SPR_DBAT0U, "DBAT0U", 276 SPR_NOACCESS, SPR_NOACCESS, 277 &spr_read_dbat, &spr_write_dbatu, 278 0x00000000); 279 spr_register(env, SPR_DBAT0L, "DBAT0L", 280 SPR_NOACCESS, SPR_NOACCESS, 281 &spr_read_dbat, &spr_write_dbatl, 282 0x00000000); 283 spr_register(env, SPR_DBAT1U, "DBAT1U", 284 SPR_NOACCESS, SPR_NOACCESS, 285 &spr_read_dbat, &spr_write_dbatu, 286 0x00000000); 287 spr_register(env, SPR_DBAT1L, "DBAT1L", 288 SPR_NOACCESS, SPR_NOACCESS, 289 &spr_read_dbat, &spr_write_dbatl, 290 0x00000000); 291 spr_register(env, SPR_DBAT2U, "DBAT2U", 292 SPR_NOACCESS, SPR_NOACCESS, 293 &spr_read_dbat, &spr_write_dbatu, 294 0x00000000); 295 spr_register(env, SPR_DBAT2L, "DBAT2L", 296 SPR_NOACCESS, SPR_NOACCESS, 297 &spr_read_dbat, &spr_write_dbatl, 298 0x00000000); 299 spr_register(env, SPR_DBAT3U, "DBAT3U", 300 SPR_NOACCESS, SPR_NOACCESS, 301 &spr_read_dbat, &spr_write_dbatu, 302 0x00000000); 303 spr_register(env, SPR_DBAT3L, "DBAT3L", 304 SPR_NOACCESS, SPR_NOACCESS, 305 &spr_read_dbat, &spr_write_dbatl, 306 0x00000000); 307 env->nb_BATs += 4; 308 #endif 309 } 310 311 /* BATs 4-7 */ 312 static void register_high_BATs(CPUPPCState *env) 313 { 314 #if !defined(CONFIG_USER_ONLY) 315 spr_register(env, SPR_IBAT4U, "IBAT4U", 316 SPR_NOACCESS, SPR_NOACCESS, 317 &spr_read_ibat_h, &spr_write_ibatu_h, 318 0x00000000); 319 spr_register(env, SPR_IBAT4L, "IBAT4L", 320 SPR_NOACCESS, SPR_NOACCESS, 321 &spr_read_ibat_h, &spr_write_ibatl_h, 322 0x00000000); 323 spr_register(env, SPR_IBAT5U, "IBAT5U", 324 SPR_NOACCESS, SPR_NOACCESS, 325 &spr_read_ibat_h, &spr_write_ibatu_h, 326 0x00000000); 327 spr_register(env, SPR_IBAT5L, "IBAT5L", 328 SPR_NOACCESS, SPR_NOACCESS, 329 &spr_read_ibat_h, &spr_write_ibatl_h, 330 0x00000000); 331 spr_register(env, SPR_IBAT6U, "IBAT6U", 332 SPR_NOACCESS, SPR_NOACCESS, 333 &spr_read_ibat_h, &spr_write_ibatu_h, 334 0x00000000); 335 spr_register(env, SPR_IBAT6L, "IBAT6L", 336 SPR_NOACCESS, SPR_NOACCESS, 337 &spr_read_ibat_h, &spr_write_ibatl_h, 338 0x00000000); 339 spr_register(env, SPR_IBAT7U, "IBAT7U", 340 SPR_NOACCESS, SPR_NOACCESS, 341 &spr_read_ibat_h, &spr_write_ibatu_h, 342 0x00000000); 343 spr_register(env, SPR_IBAT7L, "IBAT7L", 344 SPR_NOACCESS, SPR_NOACCESS, 345 &spr_read_ibat_h, &spr_write_ibatl_h, 346 0x00000000); 347 spr_register(env, SPR_DBAT4U, "DBAT4U", 348 SPR_NOACCESS, SPR_NOACCESS, 349 &spr_read_dbat_h, &spr_write_dbatu_h, 350 0x00000000); 351 spr_register(env, SPR_DBAT4L, "DBAT4L", 352 SPR_NOACCESS, SPR_NOACCESS, 353 &spr_read_dbat_h, &spr_write_dbatl_h, 354 0x00000000); 355 spr_register(env, SPR_DBAT5U, "DBAT5U", 356 SPR_NOACCESS, SPR_NOACCESS, 357 &spr_read_dbat_h, &spr_write_dbatu_h, 358 0x00000000); 359 spr_register(env, SPR_DBAT5L, "DBAT5L", 360 SPR_NOACCESS, SPR_NOACCESS, 361 &spr_read_dbat_h, &spr_write_dbatl_h, 362 0x00000000); 363 spr_register(env, SPR_DBAT6U, "DBAT6U", 364 SPR_NOACCESS, SPR_NOACCESS, 365 &spr_read_dbat_h, &spr_write_dbatu_h, 366 0x00000000); 367 spr_register(env, SPR_DBAT6L, "DBAT6L", 368 SPR_NOACCESS, SPR_NOACCESS, 369 &spr_read_dbat_h, &spr_write_dbatl_h, 370 0x00000000); 371 spr_register(env, SPR_DBAT7U, "DBAT7U", 372 SPR_NOACCESS, SPR_NOACCESS, 373 &spr_read_dbat_h, &spr_write_dbatu_h, 374 0x00000000); 375 spr_register(env, SPR_DBAT7L, "DBAT7L", 376 SPR_NOACCESS, SPR_NOACCESS, 377 &spr_read_dbat_h, &spr_write_dbatl_h, 378 0x00000000); 379 env->nb_BATs += 4; 380 #endif 381 } 382 383 /* Generic PowerPC time base */ 384 static void register_tbl(CPUPPCState *env) 385 { 386 spr_register(env, SPR_VTBL, "TBL", 387 &spr_read_tbl, SPR_NOACCESS, 388 &spr_read_tbl, SPR_NOACCESS, 389 0x00000000); 390 spr_register(env, SPR_TBL, "TBL", 391 &spr_read_tbl, SPR_NOACCESS, 392 &spr_read_tbl, &spr_write_tbl, 393 0x00000000); 394 spr_register(env, SPR_VTBU, "TBU", 395 &spr_read_tbu, SPR_NOACCESS, 396 &spr_read_tbu, SPR_NOACCESS, 397 0x00000000); 398 spr_register(env, SPR_TBU, "TBU", 399 &spr_read_tbu, SPR_NOACCESS, 400 &spr_read_tbu, &spr_write_tbu, 401 0x00000000); 402 } 403 404 /* Softare table search registers */ 405 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 406 { 407 #if !defined(CONFIG_USER_ONLY) 408 env->nb_tlb = nb_tlbs; 409 env->nb_ways = nb_ways; 410 env->id_tlbs = 1; 411 env->tlb_type = TLB_6XX; 412 spr_register(env, SPR_DMISS, "DMISS", 413 SPR_NOACCESS, SPR_NOACCESS, 414 &spr_read_generic, SPR_NOACCESS, 415 0x00000000); 416 spr_register(env, SPR_DCMP, "DCMP", 417 SPR_NOACCESS, SPR_NOACCESS, 418 &spr_read_generic, SPR_NOACCESS, 419 0x00000000); 420 spr_register(env, SPR_HASH1, "HASH1", 421 SPR_NOACCESS, SPR_NOACCESS, 422 &spr_read_generic, SPR_NOACCESS, 423 0x00000000); 424 spr_register(env, SPR_HASH2, "HASH2", 425 SPR_NOACCESS, SPR_NOACCESS, 426 &spr_read_generic, SPR_NOACCESS, 427 0x00000000); 428 spr_register(env, SPR_IMISS, "IMISS", 429 SPR_NOACCESS, SPR_NOACCESS, 430 &spr_read_generic, SPR_NOACCESS, 431 0x00000000); 432 spr_register(env, SPR_ICMP, "ICMP", 433 SPR_NOACCESS, SPR_NOACCESS, 434 &spr_read_generic, SPR_NOACCESS, 435 0x00000000); 436 spr_register(env, SPR_RPA, "RPA", 437 SPR_NOACCESS, SPR_NOACCESS, 438 &spr_read_generic, &spr_write_generic, 439 0x00000000); 440 #endif 441 } 442 443 /* SPR common to MPC755 and G2 */ 444 static void register_G2_755_sprs(CPUPPCState *env) 445 { 446 /* SGPRs */ 447 spr_register(env, SPR_SPRG4, "SPRG4", 448 SPR_NOACCESS, SPR_NOACCESS, 449 &spr_read_generic, &spr_write_generic, 450 0x00000000); 451 spr_register(env, SPR_SPRG5, "SPRG5", 452 SPR_NOACCESS, SPR_NOACCESS, 453 &spr_read_generic, &spr_write_generic, 454 0x00000000); 455 spr_register(env, SPR_SPRG6, "SPRG6", 456 SPR_NOACCESS, SPR_NOACCESS, 457 &spr_read_generic, &spr_write_generic, 458 0x00000000); 459 spr_register(env, SPR_SPRG7, "SPRG7", 460 SPR_NOACCESS, SPR_NOACCESS, 461 &spr_read_generic, &spr_write_generic, 462 0x00000000); 463 } 464 465 /* SPR common to all 7xx PowerPC implementations */ 466 static void register_7xx_sprs(CPUPPCState *env) 467 { 468 /* Breakpoints */ 469 /* XXX : not implemented */ 470 spr_register_kvm(env, SPR_DABR, "DABR", 471 SPR_NOACCESS, SPR_NOACCESS, 472 &spr_read_generic, &spr_write_generic, 473 KVM_REG_PPC_DABR, 0x00000000); 474 /* XXX : not implemented */ 475 spr_register(env, SPR_IABR, "IABR", 476 SPR_NOACCESS, SPR_NOACCESS, 477 &spr_read_generic, &spr_write_generic, 478 0x00000000); 479 /* Cache management */ 480 /* XXX : not implemented */ 481 spr_register(env, SPR_ICTC, "ICTC", 482 SPR_NOACCESS, SPR_NOACCESS, 483 &spr_read_generic, &spr_write_generic, 484 0x00000000); 485 /* Performance monitors */ 486 /* XXX : not implemented */ 487 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 488 SPR_NOACCESS, SPR_NOACCESS, 489 &spr_read_generic, &spr_write_generic, 490 0x00000000); 491 /* XXX : not implemented */ 492 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 493 SPR_NOACCESS, SPR_NOACCESS, 494 &spr_read_generic, &spr_write_generic, 495 0x00000000); 496 /* XXX : not implemented */ 497 spr_register(env, SPR_7XX_PMC1, "PMC1", 498 SPR_NOACCESS, SPR_NOACCESS, 499 &spr_read_generic, &spr_write_generic, 500 0x00000000); 501 /* XXX : not implemented */ 502 spr_register(env, SPR_7XX_PMC2, "PMC2", 503 SPR_NOACCESS, SPR_NOACCESS, 504 &spr_read_generic, &spr_write_generic, 505 0x00000000); 506 /* XXX : not implemented */ 507 spr_register(env, SPR_7XX_PMC3, "PMC3", 508 SPR_NOACCESS, SPR_NOACCESS, 509 &spr_read_generic, &spr_write_generic, 510 0x00000000); 511 /* XXX : not implemented */ 512 spr_register(env, SPR_7XX_PMC4, "PMC4", 513 SPR_NOACCESS, SPR_NOACCESS, 514 &spr_read_generic, &spr_write_generic, 515 0x00000000); 516 /* XXX : not implemented */ 517 spr_register(env, SPR_7XX_SIAR, "SIAR", 518 SPR_NOACCESS, SPR_NOACCESS, 519 &spr_read_generic, SPR_NOACCESS, 520 0x00000000); 521 /* XXX : not implemented */ 522 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 523 &spr_read_ureg, SPR_NOACCESS, 524 &spr_read_ureg, SPR_NOACCESS, 525 0x00000000); 526 /* XXX : not implemented */ 527 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 528 &spr_read_ureg, SPR_NOACCESS, 529 &spr_read_ureg, SPR_NOACCESS, 530 0x00000000); 531 /* XXX : not implemented */ 532 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 533 &spr_read_ureg, SPR_NOACCESS, 534 &spr_read_ureg, SPR_NOACCESS, 535 0x00000000); 536 /* XXX : not implemented */ 537 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 538 &spr_read_ureg, SPR_NOACCESS, 539 &spr_read_ureg, SPR_NOACCESS, 540 0x00000000); 541 /* XXX : not implemented */ 542 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 543 &spr_read_ureg, SPR_NOACCESS, 544 &spr_read_ureg, SPR_NOACCESS, 545 0x00000000); 546 /* XXX : not implemented */ 547 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 548 &spr_read_ureg, SPR_NOACCESS, 549 &spr_read_ureg, SPR_NOACCESS, 550 0x00000000); 551 /* XXX : not implemented */ 552 spr_register(env, SPR_7XX_USIAR, "USIAR", 553 &spr_read_ureg, SPR_NOACCESS, 554 &spr_read_ureg, SPR_NOACCESS, 555 0x00000000); 556 /* External access control */ 557 /* XXX : not implemented */ 558 spr_register(env, SPR_EAR, "EAR", 559 SPR_NOACCESS, SPR_NOACCESS, 560 &spr_read_generic, &spr_write_generic, 561 0x00000000); 562 } 563 564 #ifdef TARGET_PPC64 565 static void register_amr_sprs(CPUPPCState *env) 566 { 567 #ifndef CONFIG_USER_ONLY 568 /* 569 * Virtual Page Class Key protection 570 * 571 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 572 * userspace accessible, 29 is privileged. So we only need to set 573 * the kvm ONE_REG id on one of them, we use 29 574 */ 575 spr_register(env, SPR_UAMR, "UAMR", 576 &spr_read_generic, &spr_write_amr, 577 &spr_read_generic, &spr_write_amr, 578 0); 579 spr_register_kvm_hv(env, SPR_AMR, "AMR", 580 SPR_NOACCESS, SPR_NOACCESS, 581 &spr_read_generic, &spr_write_amr, 582 &spr_read_generic, &spr_write_generic, 583 KVM_REG_PPC_AMR, 0); 584 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 585 SPR_NOACCESS, SPR_NOACCESS, 586 &spr_read_generic, &spr_write_uamor, 587 &spr_read_generic, &spr_write_generic, 588 KVM_REG_PPC_UAMOR, 0); 589 spr_register_hv(env, SPR_AMOR, "AMOR", 590 SPR_NOACCESS, SPR_NOACCESS, 591 SPR_NOACCESS, SPR_NOACCESS, 592 &spr_read_generic, &spr_write_generic, 593 0); 594 #endif /* !CONFIG_USER_ONLY */ 595 } 596 597 static void register_iamr_sprs(CPUPPCState *env) 598 { 599 #ifndef CONFIG_USER_ONLY 600 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 601 SPR_NOACCESS, SPR_NOACCESS, 602 &spr_read_generic, &spr_write_iamr, 603 &spr_read_generic, &spr_write_generic, 604 KVM_REG_PPC_IAMR, 0); 605 #endif /* !CONFIG_USER_ONLY */ 606 } 607 #endif /* TARGET_PPC64 */ 608 609 static void register_thrm_sprs(CPUPPCState *env) 610 { 611 /* Thermal management */ 612 /* XXX : not implemented */ 613 spr_register(env, SPR_THRM1, "THRM1", 614 SPR_NOACCESS, SPR_NOACCESS, 615 &spr_read_thrm, &spr_write_generic, 616 0x00000000); 617 /* XXX : not implemented */ 618 spr_register(env, SPR_THRM2, "THRM2", 619 SPR_NOACCESS, SPR_NOACCESS, 620 &spr_read_thrm, &spr_write_generic, 621 0x00000000); 622 /* XXX : not implemented */ 623 spr_register(env, SPR_THRM3, "THRM3", 624 SPR_NOACCESS, SPR_NOACCESS, 625 &spr_read_thrm, &spr_write_generic, 626 0x00000000); 627 } 628 629 /* SPR specific to PowerPC 604 implementation */ 630 static void register_604_sprs(CPUPPCState *env) 631 { 632 /* Processor identification */ 633 spr_register(env, SPR_PIR, "PIR", 634 SPR_NOACCESS, SPR_NOACCESS, 635 &spr_read_generic, &spr_write_pir, 636 0x00000000); 637 /* Breakpoints */ 638 /* XXX : not implemented */ 639 spr_register(env, SPR_IABR, "IABR", 640 SPR_NOACCESS, SPR_NOACCESS, 641 &spr_read_generic, &spr_write_generic, 642 0x00000000); 643 /* XXX : not implemented */ 644 spr_register_kvm(env, SPR_DABR, "DABR", 645 SPR_NOACCESS, SPR_NOACCESS, 646 &spr_read_generic, &spr_write_generic, 647 KVM_REG_PPC_DABR, 0x00000000); 648 /* Performance counters */ 649 /* XXX : not implemented */ 650 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 651 SPR_NOACCESS, SPR_NOACCESS, 652 &spr_read_generic, &spr_write_generic, 653 0x00000000); 654 /* XXX : not implemented */ 655 spr_register(env, SPR_7XX_PMC1, "PMC1", 656 SPR_NOACCESS, SPR_NOACCESS, 657 &spr_read_generic, &spr_write_generic, 658 0x00000000); 659 /* XXX : not implemented */ 660 spr_register(env, SPR_7XX_PMC2, "PMC2", 661 SPR_NOACCESS, SPR_NOACCESS, 662 &spr_read_generic, &spr_write_generic, 663 0x00000000); 664 /* XXX : not implemented */ 665 spr_register(env, SPR_7XX_SIAR, "SIAR", 666 SPR_NOACCESS, SPR_NOACCESS, 667 &spr_read_generic, SPR_NOACCESS, 668 0x00000000); 669 /* XXX : not implemented */ 670 spr_register(env, SPR_SDA, "SDA", 671 SPR_NOACCESS, SPR_NOACCESS, 672 &spr_read_generic, SPR_NOACCESS, 673 0x00000000); 674 /* External access control */ 675 /* XXX : not implemented */ 676 spr_register(env, SPR_EAR, "EAR", 677 SPR_NOACCESS, SPR_NOACCESS, 678 &spr_read_generic, &spr_write_generic, 679 0x00000000); 680 } 681 682 /* SPR specific to PowerPC 603 implementation */ 683 static void register_603_sprs(CPUPPCState *env) 684 { 685 /* External access control */ 686 /* XXX : not implemented */ 687 spr_register(env, SPR_EAR, "EAR", 688 SPR_NOACCESS, SPR_NOACCESS, 689 &spr_read_generic, &spr_write_generic, 690 0x00000000); 691 /* Breakpoints */ 692 /* XXX : not implemented */ 693 spr_register(env, SPR_IABR, "IABR", 694 SPR_NOACCESS, SPR_NOACCESS, 695 &spr_read_generic, &spr_write_generic, 696 0x00000000); 697 698 } 699 700 /* SPR specific to PowerPC G2 implementation */ 701 static void register_G2_sprs(CPUPPCState *env) 702 { 703 /* Memory base address */ 704 /* MBAR */ 705 /* XXX : not implemented */ 706 spr_register(env, SPR_MBAR, "MBAR", 707 SPR_NOACCESS, SPR_NOACCESS, 708 &spr_read_generic, &spr_write_generic, 709 0x00000000); 710 /* Exception processing */ 711 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 712 SPR_NOACCESS, SPR_NOACCESS, 713 &spr_read_generic, &spr_write_generic, 714 0x00000000); 715 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 716 SPR_NOACCESS, SPR_NOACCESS, 717 &spr_read_generic, &spr_write_generic, 718 0x00000000); 719 /* Breakpoints */ 720 /* XXX : not implemented */ 721 spr_register(env, SPR_DABR, "DABR", 722 SPR_NOACCESS, SPR_NOACCESS, 723 &spr_read_generic, &spr_write_generic, 724 0x00000000); 725 /* XXX : not implemented */ 726 spr_register(env, SPR_DABR2, "DABR2", 727 SPR_NOACCESS, SPR_NOACCESS, 728 &spr_read_generic, &spr_write_generic, 729 0x00000000); 730 /* XXX : not implemented */ 731 spr_register(env, SPR_IABR, "IABR", 732 SPR_NOACCESS, SPR_NOACCESS, 733 &spr_read_generic, &spr_write_generic, 734 0x00000000); 735 /* XXX : not implemented */ 736 spr_register(env, SPR_IABR2, "IABR2", 737 SPR_NOACCESS, SPR_NOACCESS, 738 &spr_read_generic, &spr_write_generic, 739 0x00000000); 740 /* XXX : not implemented */ 741 spr_register(env, SPR_IBCR, "IBCR", 742 SPR_NOACCESS, SPR_NOACCESS, 743 &spr_read_generic, &spr_write_generic, 744 0x00000000); 745 /* XXX : not implemented */ 746 spr_register(env, SPR_DBCR, "DBCR", 747 SPR_NOACCESS, SPR_NOACCESS, 748 &spr_read_generic, &spr_write_generic, 749 0x00000000); 750 } 751 752 /* SPR specific to PowerPC 602 implementation */ 753 static void register_602_sprs(CPUPPCState *env) 754 { 755 /* ESA registers */ 756 /* XXX : not implemented */ 757 spr_register(env, SPR_SER, "SER", 758 SPR_NOACCESS, SPR_NOACCESS, 759 &spr_read_generic, &spr_write_generic, 760 0x00000000); 761 /* XXX : not implemented */ 762 spr_register(env, SPR_SEBR, "SEBR", 763 SPR_NOACCESS, SPR_NOACCESS, 764 &spr_read_generic, &spr_write_generic, 765 0x00000000); 766 /* XXX : not implemented */ 767 spr_register(env, SPR_ESASRR, "ESASRR", 768 SPR_NOACCESS, SPR_NOACCESS, 769 &spr_read_generic, &spr_write_generic, 770 0x00000000); 771 /* Floating point status */ 772 /* XXX : not implemented */ 773 spr_register(env, SPR_SP, "SP", 774 SPR_NOACCESS, SPR_NOACCESS, 775 &spr_read_generic, &spr_write_generic, 776 0x00000000); 777 /* XXX : not implemented */ 778 spr_register(env, SPR_LT, "LT", 779 SPR_NOACCESS, SPR_NOACCESS, 780 &spr_read_generic, &spr_write_generic, 781 0x00000000); 782 /* Watchdog timer */ 783 /* XXX : not implemented */ 784 spr_register(env, SPR_TCR, "TCR", 785 SPR_NOACCESS, SPR_NOACCESS, 786 &spr_read_generic, &spr_write_generic, 787 0x00000000); 788 /* Interrupt base */ 789 spr_register(env, SPR_IBR, "IBR", 790 SPR_NOACCESS, SPR_NOACCESS, 791 &spr_read_generic, &spr_write_generic, 792 0x00000000); 793 /* XXX : not implemented */ 794 spr_register(env, SPR_IABR, "IABR", 795 SPR_NOACCESS, SPR_NOACCESS, 796 &spr_read_generic, &spr_write_generic, 797 0x00000000); 798 } 799 800 /* SPR specific to PowerPC 601 implementation */ 801 static void register_601_sprs(CPUPPCState *env) 802 { 803 /* Multiplication/division register */ 804 /* MQ */ 805 spr_register(env, SPR_MQ, "MQ", 806 &spr_read_generic, &spr_write_generic, 807 &spr_read_generic, &spr_write_generic, 808 0x00000000); 809 /* RTC registers */ 810 spr_register(env, SPR_601_RTCU, "RTCU", 811 SPR_NOACCESS, SPR_NOACCESS, 812 SPR_NOACCESS, &spr_write_601_rtcu, 813 0x00000000); 814 spr_register(env, SPR_601_VRTCU, "RTCU", 815 &spr_read_601_rtcu, SPR_NOACCESS, 816 &spr_read_601_rtcu, SPR_NOACCESS, 817 0x00000000); 818 spr_register(env, SPR_601_RTCL, "RTCL", 819 SPR_NOACCESS, SPR_NOACCESS, 820 SPR_NOACCESS, &spr_write_601_rtcl, 821 0x00000000); 822 spr_register(env, SPR_601_VRTCL, "RTCL", 823 &spr_read_601_rtcl, SPR_NOACCESS, 824 &spr_read_601_rtcl, SPR_NOACCESS, 825 0x00000000); 826 /* Timer */ 827 #if 0 /* ? */ 828 spr_register(env, SPR_601_UDECR, "UDECR", 829 &spr_read_decr, SPR_NOACCESS, 830 &spr_read_decr, SPR_NOACCESS, 831 0x00000000); 832 #endif 833 /* External access control */ 834 /* XXX : not implemented */ 835 spr_register(env, SPR_EAR, "EAR", 836 SPR_NOACCESS, SPR_NOACCESS, 837 &spr_read_generic, &spr_write_generic, 838 0x00000000); 839 /* Memory management */ 840 #if !defined(CONFIG_USER_ONLY) 841 spr_register(env, SPR_IBAT0U, "IBAT0U", 842 SPR_NOACCESS, SPR_NOACCESS, 843 &spr_read_601_ubat, &spr_write_601_ubatu, 844 0x00000000); 845 spr_register(env, SPR_IBAT0L, "IBAT0L", 846 SPR_NOACCESS, SPR_NOACCESS, 847 &spr_read_601_ubat, &spr_write_601_ubatl, 848 0x00000000); 849 spr_register(env, SPR_IBAT1U, "IBAT1U", 850 SPR_NOACCESS, SPR_NOACCESS, 851 &spr_read_601_ubat, &spr_write_601_ubatu, 852 0x00000000); 853 spr_register(env, SPR_IBAT1L, "IBAT1L", 854 SPR_NOACCESS, SPR_NOACCESS, 855 &spr_read_601_ubat, &spr_write_601_ubatl, 856 0x00000000); 857 spr_register(env, SPR_IBAT2U, "IBAT2U", 858 SPR_NOACCESS, SPR_NOACCESS, 859 &spr_read_601_ubat, &spr_write_601_ubatu, 860 0x00000000); 861 spr_register(env, SPR_IBAT2L, "IBAT2L", 862 SPR_NOACCESS, SPR_NOACCESS, 863 &spr_read_601_ubat, &spr_write_601_ubatl, 864 0x00000000); 865 spr_register(env, SPR_IBAT3U, "IBAT3U", 866 SPR_NOACCESS, SPR_NOACCESS, 867 &spr_read_601_ubat, &spr_write_601_ubatu, 868 0x00000000); 869 spr_register(env, SPR_IBAT3L, "IBAT3L", 870 SPR_NOACCESS, SPR_NOACCESS, 871 &spr_read_601_ubat, &spr_write_601_ubatl, 872 0x00000000); 873 env->nb_BATs = 4; 874 #endif 875 } 876 877 static void register_74xx_sprs(CPUPPCState *env) 878 { 879 /* Processor identification */ 880 spr_register(env, SPR_PIR, "PIR", 881 SPR_NOACCESS, SPR_NOACCESS, 882 &spr_read_generic, &spr_write_pir, 883 0x00000000); 884 /* XXX : not implemented */ 885 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 886 SPR_NOACCESS, SPR_NOACCESS, 887 &spr_read_generic, &spr_write_generic, 888 0x00000000); 889 /* XXX : not implemented */ 890 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 891 &spr_read_ureg, SPR_NOACCESS, 892 &spr_read_ureg, SPR_NOACCESS, 893 0x00000000); 894 /* XXX: not implemented */ 895 spr_register(env, SPR_BAMR, "BAMR", 896 SPR_NOACCESS, SPR_NOACCESS, 897 &spr_read_generic, &spr_write_generic, 898 0x00000000); 899 /* XXX : not implemented */ 900 spr_register(env, SPR_MSSCR0, "MSSCR0", 901 SPR_NOACCESS, SPR_NOACCESS, 902 &spr_read_generic, &spr_write_generic, 903 0x00000000); 904 /* Hardware implementation registers */ 905 /* XXX : not implemented */ 906 spr_register(env, SPR_HID0, "HID0", 907 SPR_NOACCESS, SPR_NOACCESS, 908 &spr_read_generic, &spr_write_generic, 909 0x00000000); 910 /* XXX : not implemented */ 911 spr_register(env, SPR_HID1, "HID1", 912 SPR_NOACCESS, SPR_NOACCESS, 913 &spr_read_generic, &spr_write_generic, 914 0x00000000); 915 /* Altivec */ 916 spr_register(env, SPR_VRSAVE, "VRSAVE", 917 &spr_read_generic, &spr_write_generic, 918 &spr_read_generic, &spr_write_generic, 919 0x00000000); 920 /* XXX : not implemented */ 921 spr_register(env, SPR_L2CR, "L2CR", 922 SPR_NOACCESS, SPR_NOACCESS, 923 &spr_read_generic, spr_access_nop, 924 0x00000000); 925 } 926 927 static void register_l3_ctrl(CPUPPCState *env) 928 { 929 /* L3CR */ 930 /* XXX : not implemented */ 931 spr_register(env, SPR_L3CR, "L3CR", 932 SPR_NOACCESS, SPR_NOACCESS, 933 &spr_read_generic, &spr_write_generic, 934 0x00000000); 935 /* L3ITCR0 */ 936 /* XXX : not implemented */ 937 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 938 SPR_NOACCESS, SPR_NOACCESS, 939 &spr_read_generic, &spr_write_generic, 940 0x00000000); 941 /* L3PM */ 942 /* XXX : not implemented */ 943 spr_register(env, SPR_L3PM, "L3PM", 944 SPR_NOACCESS, SPR_NOACCESS, 945 &spr_read_generic, &spr_write_generic, 946 0x00000000); 947 } 948 949 static void register_usprg3_sprs(CPUPPCState *env) 950 { 951 spr_register(env, SPR_USPRG3, "USPRG3", 952 &spr_read_ureg, SPR_NOACCESS, 953 &spr_read_ureg, SPR_NOACCESS, 954 0x00000000); 955 } 956 957 static void register_usprgh_sprs(CPUPPCState *env) 958 { 959 spr_register(env, SPR_USPRG4, "USPRG4", 960 &spr_read_ureg, SPR_NOACCESS, 961 &spr_read_ureg, SPR_NOACCESS, 962 0x00000000); 963 spr_register(env, SPR_USPRG5, "USPRG5", 964 &spr_read_ureg, SPR_NOACCESS, 965 &spr_read_ureg, SPR_NOACCESS, 966 0x00000000); 967 spr_register(env, SPR_USPRG6, "USPRG6", 968 &spr_read_ureg, SPR_NOACCESS, 969 &spr_read_ureg, SPR_NOACCESS, 970 0x00000000); 971 spr_register(env, SPR_USPRG7, "USPRG7", 972 &spr_read_ureg, SPR_NOACCESS, 973 &spr_read_ureg, SPR_NOACCESS, 974 0x00000000); 975 } 976 977 /* PowerPC BookE SPR */ 978 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 979 { 980 const char *ivor_names[64] = { 981 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 982 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 983 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 984 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 985 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 986 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 987 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 988 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 989 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 990 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 991 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 992 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 993 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 994 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 995 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 996 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 997 }; 998 #define SPR_BOOKE_IVORxx (-1) 999 int ivor_sprn[64] = { 1000 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 1001 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 1002 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 1003 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 1004 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1005 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1006 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1007 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1008 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 1009 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 1010 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 1011 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1012 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1013 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1014 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1015 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1016 }; 1017 int i; 1018 1019 /* Interrupt processing */ 1020 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1021 SPR_NOACCESS, SPR_NOACCESS, 1022 &spr_read_generic, &spr_write_generic, 1023 0x00000000); 1024 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1025 SPR_NOACCESS, SPR_NOACCESS, 1026 &spr_read_generic, &spr_write_generic, 1027 0x00000000); 1028 /* Debug */ 1029 /* XXX : not implemented */ 1030 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1031 SPR_NOACCESS, SPR_NOACCESS, 1032 &spr_read_generic, &spr_write_generic, 1033 0x00000000); 1034 /* XXX : not implemented */ 1035 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 1036 SPR_NOACCESS, SPR_NOACCESS, 1037 &spr_read_generic, &spr_write_generic, 1038 0x00000000); 1039 /* XXX : not implemented */ 1040 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 1041 SPR_NOACCESS, SPR_NOACCESS, 1042 &spr_read_generic, &spr_write_generic, 1043 0x00000000); 1044 /* XXX : not implemented */ 1045 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 1046 SPR_NOACCESS, SPR_NOACCESS, 1047 &spr_read_generic, &spr_write_generic, 1048 0x00000000); 1049 /* XXX : not implemented */ 1050 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1051 SPR_NOACCESS, SPR_NOACCESS, 1052 &spr_read_generic, &spr_write_40x_dbcr0, 1053 0x00000000); 1054 /* XXX : not implemented */ 1055 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1056 SPR_NOACCESS, SPR_NOACCESS, 1057 &spr_read_generic, &spr_write_generic, 1058 0x00000000); 1059 /* XXX : not implemented */ 1060 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1061 SPR_NOACCESS, SPR_NOACCESS, 1062 &spr_read_generic, &spr_write_generic, 1063 0x00000000); 1064 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1065 SPR_NOACCESS, SPR_NOACCESS, 1066 &spr_read_generic, &spr_write_generic, 1067 0x00000000); 1068 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1069 SPR_NOACCESS, SPR_NOACCESS, 1070 &spr_read_generic, &spr_write_generic, 1071 0x00000000); 1072 /* XXX : not implemented */ 1073 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1074 SPR_NOACCESS, SPR_NOACCESS, 1075 &spr_read_generic, &spr_write_clear, 1076 0x00000000); 1077 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1078 SPR_NOACCESS, SPR_NOACCESS, 1079 &spr_read_generic, &spr_write_generic, 1080 0x00000000); 1081 spr_register(env, SPR_BOOKE_ESR, "ESR", 1082 SPR_NOACCESS, SPR_NOACCESS, 1083 &spr_read_generic, &spr_write_generic, 1084 0x00000000); 1085 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1086 SPR_NOACCESS, SPR_NOACCESS, 1087 &spr_read_generic, &spr_write_excp_prefix, 1088 0x00000000); 1089 /* Exception vectors */ 1090 for (i = 0; i < 64; i++) { 1091 if (ivor_mask & (1ULL << i)) { 1092 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1093 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1094 exit(1); 1095 } 1096 spr_register(env, ivor_sprn[i], ivor_names[i], 1097 SPR_NOACCESS, SPR_NOACCESS, 1098 &spr_read_generic, &spr_write_excp_vector, 1099 0x00000000); 1100 } 1101 } 1102 spr_register(env, SPR_BOOKE_PID, "PID", 1103 SPR_NOACCESS, SPR_NOACCESS, 1104 &spr_read_generic, &spr_write_booke_pid, 1105 0x00000000); 1106 spr_register(env, SPR_BOOKE_TCR, "TCR", 1107 SPR_NOACCESS, SPR_NOACCESS, 1108 &spr_read_generic, &spr_write_booke_tcr, 1109 0x00000000); 1110 spr_register(env, SPR_BOOKE_TSR, "TSR", 1111 SPR_NOACCESS, SPR_NOACCESS, 1112 &spr_read_generic, &spr_write_booke_tsr, 1113 0x00000000); 1114 /* Timer */ 1115 spr_register(env, SPR_DECR, "DECR", 1116 SPR_NOACCESS, SPR_NOACCESS, 1117 &spr_read_decr, &spr_write_decr, 1118 0x00000000); 1119 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1120 SPR_NOACCESS, SPR_NOACCESS, 1121 SPR_NOACCESS, &spr_write_generic, 1122 0x00000000); 1123 /* SPRGs */ 1124 spr_register(env, SPR_USPRG0, "USPRG0", 1125 &spr_read_generic, &spr_write_generic, 1126 &spr_read_generic, &spr_write_generic, 1127 0x00000000); 1128 spr_register(env, SPR_SPRG4, "SPRG4", 1129 SPR_NOACCESS, SPR_NOACCESS, 1130 &spr_read_generic, &spr_write_generic, 1131 0x00000000); 1132 spr_register(env, SPR_SPRG5, "SPRG5", 1133 SPR_NOACCESS, SPR_NOACCESS, 1134 &spr_read_generic, &spr_write_generic, 1135 0x00000000); 1136 spr_register(env, SPR_SPRG6, "SPRG6", 1137 SPR_NOACCESS, SPR_NOACCESS, 1138 &spr_read_generic, &spr_write_generic, 1139 0x00000000); 1140 spr_register(env, SPR_SPRG7, "SPRG7", 1141 SPR_NOACCESS, SPR_NOACCESS, 1142 &spr_read_generic, &spr_write_generic, 1143 0x00000000); 1144 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1145 SPR_NOACCESS, SPR_NOACCESS, 1146 &spr_read_generic, &spr_write_generic, 1147 0x00000000); 1148 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1149 SPR_NOACCESS, SPR_NOACCESS, 1150 &spr_read_generic, &spr_write_generic, 1151 0x00000000); 1152 } 1153 1154 #if !defined(CONFIG_USER_ONLY) 1155 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1156 uint32_t maxsize, uint32_t flags, 1157 uint32_t nentries) 1158 { 1159 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1160 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1161 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1162 flags | nentries; 1163 } 1164 #endif /* !CONFIG_USER_ONLY */ 1165 1166 /* BookE 2.06 storage control registers */ 1167 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1168 uint32_t *tlbncfg, uint32_t mmucfg) 1169 { 1170 #if !defined(CONFIG_USER_ONLY) 1171 const char *mas_names[8] = { 1172 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1173 }; 1174 int mas_sprn[8] = { 1175 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1176 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1177 }; 1178 int i; 1179 1180 /* TLB assist registers */ 1181 /* XXX : not implemented */ 1182 for (i = 0; i < 8; i++) { 1183 if (mas_mask & (1 << i)) { 1184 spr_register(env, mas_sprn[i], mas_names[i], 1185 SPR_NOACCESS, SPR_NOACCESS, 1186 &spr_read_generic, 1187 (i == 2 && (env->insns_flags & PPC_64B)) 1188 ? &spr_write_generic : &spr_write_generic32, 1189 0x00000000); 1190 } 1191 } 1192 if (env->nb_pids > 1) { 1193 /* XXX : not implemented */ 1194 spr_register(env, SPR_BOOKE_PID1, "PID1", 1195 SPR_NOACCESS, SPR_NOACCESS, 1196 &spr_read_generic, &spr_write_booke_pid, 1197 0x00000000); 1198 } 1199 if (env->nb_pids > 2) { 1200 /* XXX : not implemented */ 1201 spr_register(env, SPR_BOOKE_PID2, "PID2", 1202 SPR_NOACCESS, SPR_NOACCESS, 1203 &spr_read_generic, &spr_write_booke_pid, 1204 0x00000000); 1205 } 1206 1207 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1208 SPR_NOACCESS, SPR_NOACCESS, 1209 &spr_read_generic, &spr_write_eplc, 1210 0x00000000); 1211 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1212 SPR_NOACCESS, SPR_NOACCESS, 1213 &spr_read_generic, &spr_write_epsc, 1214 0x00000000); 1215 1216 /* XXX : not implemented */ 1217 spr_register(env, SPR_MMUCFG, "MMUCFG", 1218 SPR_NOACCESS, SPR_NOACCESS, 1219 &spr_read_generic, SPR_NOACCESS, 1220 mmucfg); 1221 switch (env->nb_ways) { 1222 case 4: 1223 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1224 SPR_NOACCESS, SPR_NOACCESS, 1225 &spr_read_generic, SPR_NOACCESS, 1226 tlbncfg[3]); 1227 /* Fallthru */ 1228 case 3: 1229 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1230 SPR_NOACCESS, SPR_NOACCESS, 1231 &spr_read_generic, SPR_NOACCESS, 1232 tlbncfg[2]); 1233 /* Fallthru */ 1234 case 2: 1235 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1236 SPR_NOACCESS, SPR_NOACCESS, 1237 &spr_read_generic, SPR_NOACCESS, 1238 tlbncfg[1]); 1239 /* Fallthru */ 1240 case 1: 1241 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1242 SPR_NOACCESS, SPR_NOACCESS, 1243 &spr_read_generic, SPR_NOACCESS, 1244 tlbncfg[0]); 1245 /* Fallthru */ 1246 case 0: 1247 default: 1248 break; 1249 } 1250 #endif 1251 1252 register_usprgh_sprs(env); 1253 } 1254 1255 /* SPR specific to PowerPC 440 implementation */ 1256 static void register_440_sprs(CPUPPCState *env) 1257 { 1258 /* Cache control */ 1259 /* XXX : not implemented */ 1260 spr_register(env, SPR_440_DNV0, "DNV0", 1261 SPR_NOACCESS, SPR_NOACCESS, 1262 &spr_read_generic, &spr_write_generic, 1263 0x00000000); 1264 /* XXX : not implemented */ 1265 spr_register(env, SPR_440_DNV1, "DNV1", 1266 SPR_NOACCESS, SPR_NOACCESS, 1267 &spr_read_generic, &spr_write_generic, 1268 0x00000000); 1269 /* XXX : not implemented */ 1270 spr_register(env, SPR_440_DNV2, "DNV2", 1271 SPR_NOACCESS, SPR_NOACCESS, 1272 &spr_read_generic, &spr_write_generic, 1273 0x00000000); 1274 /* XXX : not implemented */ 1275 spr_register(env, SPR_440_DNV3, "DNV3", 1276 SPR_NOACCESS, SPR_NOACCESS, 1277 &spr_read_generic, &spr_write_generic, 1278 0x00000000); 1279 /* XXX : not implemented */ 1280 spr_register(env, SPR_440_DTV0, "DTV0", 1281 SPR_NOACCESS, SPR_NOACCESS, 1282 &spr_read_generic, &spr_write_generic, 1283 0x00000000); 1284 /* XXX : not implemented */ 1285 spr_register(env, SPR_440_DTV1, "DTV1", 1286 SPR_NOACCESS, SPR_NOACCESS, 1287 &spr_read_generic, &spr_write_generic, 1288 0x00000000); 1289 /* XXX : not implemented */ 1290 spr_register(env, SPR_440_DTV2, "DTV2", 1291 SPR_NOACCESS, SPR_NOACCESS, 1292 &spr_read_generic, &spr_write_generic, 1293 0x00000000); 1294 /* XXX : not implemented */ 1295 spr_register(env, SPR_440_DTV3, "DTV3", 1296 SPR_NOACCESS, SPR_NOACCESS, 1297 &spr_read_generic, &spr_write_generic, 1298 0x00000000); 1299 /* XXX : not implemented */ 1300 spr_register(env, SPR_440_DVLIM, "DVLIM", 1301 SPR_NOACCESS, SPR_NOACCESS, 1302 &spr_read_generic, &spr_write_generic, 1303 0x00000000); 1304 /* XXX : not implemented */ 1305 spr_register(env, SPR_440_INV0, "INV0", 1306 SPR_NOACCESS, SPR_NOACCESS, 1307 &spr_read_generic, &spr_write_generic, 1308 0x00000000); 1309 /* XXX : not implemented */ 1310 spr_register(env, SPR_440_INV1, "INV1", 1311 SPR_NOACCESS, SPR_NOACCESS, 1312 &spr_read_generic, &spr_write_generic, 1313 0x00000000); 1314 /* XXX : not implemented */ 1315 spr_register(env, SPR_440_INV2, "INV2", 1316 SPR_NOACCESS, SPR_NOACCESS, 1317 &spr_read_generic, &spr_write_generic, 1318 0x00000000); 1319 /* XXX : not implemented */ 1320 spr_register(env, SPR_440_INV3, "INV3", 1321 SPR_NOACCESS, SPR_NOACCESS, 1322 &spr_read_generic, &spr_write_generic, 1323 0x00000000); 1324 /* XXX : not implemented */ 1325 spr_register(env, SPR_440_ITV0, "ITV0", 1326 SPR_NOACCESS, SPR_NOACCESS, 1327 &spr_read_generic, &spr_write_generic, 1328 0x00000000); 1329 /* XXX : not implemented */ 1330 spr_register(env, SPR_440_ITV1, "ITV1", 1331 SPR_NOACCESS, SPR_NOACCESS, 1332 &spr_read_generic, &spr_write_generic, 1333 0x00000000); 1334 /* XXX : not implemented */ 1335 spr_register(env, SPR_440_ITV2, "ITV2", 1336 SPR_NOACCESS, SPR_NOACCESS, 1337 &spr_read_generic, &spr_write_generic, 1338 0x00000000); 1339 /* XXX : not implemented */ 1340 spr_register(env, SPR_440_ITV3, "ITV3", 1341 SPR_NOACCESS, SPR_NOACCESS, 1342 &spr_read_generic, &spr_write_generic, 1343 0x00000000); 1344 /* XXX : not implemented */ 1345 spr_register(env, SPR_440_IVLIM, "IVLIM", 1346 SPR_NOACCESS, SPR_NOACCESS, 1347 &spr_read_generic, &spr_write_generic, 1348 0x00000000); 1349 /* Cache debug */ 1350 /* XXX : not implemented */ 1351 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1352 SPR_NOACCESS, SPR_NOACCESS, 1353 &spr_read_generic, SPR_NOACCESS, 1354 0x00000000); 1355 /* XXX : not implemented */ 1356 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1357 SPR_NOACCESS, SPR_NOACCESS, 1358 &spr_read_generic, SPR_NOACCESS, 1359 0x00000000); 1360 /* XXX : not implemented */ 1361 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1362 SPR_NOACCESS, SPR_NOACCESS, 1363 &spr_read_generic, SPR_NOACCESS, 1364 0x00000000); 1365 /* XXX : not implemented */ 1366 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1367 SPR_NOACCESS, SPR_NOACCESS, 1368 &spr_read_generic, SPR_NOACCESS, 1369 0x00000000); 1370 /* XXX : not implemented */ 1371 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1372 SPR_NOACCESS, SPR_NOACCESS, 1373 &spr_read_generic, SPR_NOACCESS, 1374 0x00000000); 1375 /* XXX : not implemented */ 1376 spr_register(env, SPR_440_DBDR, "DBDR", 1377 SPR_NOACCESS, SPR_NOACCESS, 1378 &spr_read_generic, &spr_write_generic, 1379 0x00000000); 1380 /* Processor control */ 1381 spr_register(env, SPR_4xx_CCR0, "CCR0", 1382 SPR_NOACCESS, SPR_NOACCESS, 1383 &spr_read_generic, &spr_write_generic, 1384 0x00000000); 1385 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1386 SPR_NOACCESS, SPR_NOACCESS, 1387 &spr_read_generic, SPR_NOACCESS, 1388 0x00000000); 1389 /* Storage control */ 1390 spr_register(env, SPR_440_MMUCR, "MMUCR", 1391 SPR_NOACCESS, SPR_NOACCESS, 1392 &spr_read_generic, &spr_write_generic, 1393 0x00000000); 1394 } 1395 1396 /* SPR shared between PowerPC 40x implementations */ 1397 static void register_40x_sprs(CPUPPCState *env) 1398 { 1399 /* Cache */ 1400 /* not emulated, as QEMU do not emulate caches */ 1401 spr_register(env, SPR_40x_DCCR, "DCCR", 1402 SPR_NOACCESS, SPR_NOACCESS, 1403 &spr_read_generic, &spr_write_generic, 1404 0x00000000); 1405 /* not emulated, as QEMU do not emulate caches */ 1406 spr_register(env, SPR_40x_ICCR, "ICCR", 1407 SPR_NOACCESS, SPR_NOACCESS, 1408 &spr_read_generic, &spr_write_generic, 1409 0x00000000); 1410 /* not emulated, as QEMU do not emulate caches */ 1411 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1412 SPR_NOACCESS, SPR_NOACCESS, 1413 &spr_read_generic, SPR_NOACCESS, 1414 0x00000000); 1415 /* Exception */ 1416 spr_register(env, SPR_40x_DEAR, "DEAR", 1417 SPR_NOACCESS, SPR_NOACCESS, 1418 &spr_read_generic, &spr_write_generic, 1419 0x00000000); 1420 spr_register(env, SPR_40x_ESR, "ESR", 1421 SPR_NOACCESS, SPR_NOACCESS, 1422 &spr_read_generic, &spr_write_generic, 1423 0x00000000); 1424 spr_register(env, SPR_40x_EVPR, "EVPR", 1425 SPR_NOACCESS, SPR_NOACCESS, 1426 &spr_read_generic, &spr_write_excp_prefix, 1427 0x00000000); 1428 spr_register(env, SPR_40x_SRR2, "SRR2", 1429 &spr_read_generic, &spr_write_generic, 1430 &spr_read_generic, &spr_write_generic, 1431 0x00000000); 1432 spr_register(env, SPR_40x_SRR3, "SRR3", 1433 &spr_read_generic, &spr_write_generic, 1434 &spr_read_generic, &spr_write_generic, 1435 0x00000000); 1436 /* Timers */ 1437 spr_register(env, SPR_40x_PIT, "PIT", 1438 SPR_NOACCESS, SPR_NOACCESS, 1439 &spr_read_40x_pit, &spr_write_40x_pit, 1440 0x00000000); 1441 spr_register(env, SPR_40x_TCR, "TCR", 1442 SPR_NOACCESS, SPR_NOACCESS, 1443 &spr_read_generic, &spr_write_booke_tcr, 1444 0x00000000); 1445 spr_register(env, SPR_40x_TSR, "TSR", 1446 SPR_NOACCESS, SPR_NOACCESS, 1447 &spr_read_generic, &spr_write_booke_tsr, 1448 0x00000000); 1449 } 1450 1451 /* SPR specific to PowerPC 405 implementation */ 1452 static void register_405_sprs(CPUPPCState *env) 1453 { 1454 /* MMU */ 1455 spr_register(env, SPR_40x_PID, "PID", 1456 SPR_NOACCESS, SPR_NOACCESS, 1457 &spr_read_generic, &spr_write_generic, 1458 0x00000000); 1459 spr_register(env, SPR_4xx_CCR0, "CCR0", 1460 SPR_NOACCESS, SPR_NOACCESS, 1461 &spr_read_generic, &spr_write_generic, 1462 0x00700000); 1463 /* Debug interface */ 1464 /* XXX : not implemented */ 1465 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1466 SPR_NOACCESS, SPR_NOACCESS, 1467 &spr_read_generic, &spr_write_40x_dbcr0, 1468 0x00000000); 1469 /* XXX : not implemented */ 1470 spr_register(env, SPR_405_DBCR1, "DBCR1", 1471 SPR_NOACCESS, SPR_NOACCESS, 1472 &spr_read_generic, &spr_write_generic, 1473 0x00000000); 1474 /* XXX : not implemented */ 1475 spr_register(env, SPR_40x_DBSR, "DBSR", 1476 SPR_NOACCESS, SPR_NOACCESS, 1477 &spr_read_generic, &spr_write_clear, 1478 /* Last reset was system reset */ 1479 0x00000300); 1480 /* XXX : not implemented */ 1481 spr_register(env, SPR_40x_DAC1, "DAC1", 1482 SPR_NOACCESS, SPR_NOACCESS, 1483 &spr_read_generic, &spr_write_generic, 1484 0x00000000); 1485 spr_register(env, SPR_40x_DAC2, "DAC2", 1486 SPR_NOACCESS, SPR_NOACCESS, 1487 &spr_read_generic, &spr_write_generic, 1488 0x00000000); 1489 /* XXX : not implemented */ 1490 spr_register(env, SPR_405_DVC1, "DVC1", 1491 SPR_NOACCESS, SPR_NOACCESS, 1492 &spr_read_generic, &spr_write_generic, 1493 0x00000000); 1494 /* XXX : not implemented */ 1495 spr_register(env, SPR_405_DVC2, "DVC2", 1496 SPR_NOACCESS, SPR_NOACCESS, 1497 &spr_read_generic, &spr_write_generic, 1498 0x00000000); 1499 /* XXX : not implemented */ 1500 spr_register(env, SPR_40x_IAC1, "IAC1", 1501 SPR_NOACCESS, SPR_NOACCESS, 1502 &spr_read_generic, &spr_write_generic, 1503 0x00000000); 1504 spr_register(env, SPR_40x_IAC2, "IAC2", 1505 SPR_NOACCESS, SPR_NOACCESS, 1506 &spr_read_generic, &spr_write_generic, 1507 0x00000000); 1508 /* XXX : not implemented */ 1509 spr_register(env, SPR_405_IAC3, "IAC3", 1510 SPR_NOACCESS, SPR_NOACCESS, 1511 &spr_read_generic, &spr_write_generic, 1512 0x00000000); 1513 /* XXX : not implemented */ 1514 spr_register(env, SPR_405_IAC4, "IAC4", 1515 SPR_NOACCESS, SPR_NOACCESS, 1516 &spr_read_generic, &spr_write_generic, 1517 0x00000000); 1518 /* Storage control */ 1519 /* XXX: TODO: not implemented */ 1520 spr_register(env, SPR_405_SLER, "SLER", 1521 SPR_NOACCESS, SPR_NOACCESS, 1522 &spr_read_generic, &spr_write_40x_sler, 1523 0x00000000); 1524 spr_register(env, SPR_40x_ZPR, "ZPR", 1525 SPR_NOACCESS, SPR_NOACCESS, 1526 &spr_read_generic, &spr_write_generic, 1527 0x00000000); 1528 /* XXX : not implemented */ 1529 spr_register(env, SPR_405_SU0R, "SU0R", 1530 SPR_NOACCESS, SPR_NOACCESS, 1531 &spr_read_generic, &spr_write_generic, 1532 0x00000000); 1533 /* SPRG */ 1534 spr_register(env, SPR_USPRG0, "USPRG0", 1535 &spr_read_ureg, SPR_NOACCESS, 1536 &spr_read_ureg, SPR_NOACCESS, 1537 0x00000000); 1538 spr_register(env, SPR_SPRG4, "SPRG4", 1539 SPR_NOACCESS, SPR_NOACCESS, 1540 &spr_read_generic, &spr_write_generic, 1541 0x00000000); 1542 spr_register(env, SPR_SPRG5, "SPRG5", 1543 SPR_NOACCESS, SPR_NOACCESS, 1544 spr_read_generic, &spr_write_generic, 1545 0x00000000); 1546 spr_register(env, SPR_SPRG6, "SPRG6", 1547 SPR_NOACCESS, SPR_NOACCESS, 1548 spr_read_generic, &spr_write_generic, 1549 0x00000000); 1550 spr_register(env, SPR_SPRG7, "SPRG7", 1551 SPR_NOACCESS, SPR_NOACCESS, 1552 spr_read_generic, &spr_write_generic, 1553 0x00000000); 1554 register_usprgh_sprs(env); 1555 } 1556 1557 1558 static void register_5xx_8xx_sprs(CPUPPCState *env) 1559 { 1560 /* Exception processing */ 1561 spr_register_kvm(env, SPR_DSISR, "DSISR", 1562 SPR_NOACCESS, SPR_NOACCESS, 1563 &spr_read_generic, &spr_write_generic, 1564 KVM_REG_PPC_DSISR, 0x00000000); 1565 spr_register_kvm(env, SPR_DAR, "DAR", 1566 SPR_NOACCESS, SPR_NOACCESS, 1567 &spr_read_generic, &spr_write_generic, 1568 KVM_REG_PPC_DAR, 0x00000000); 1569 /* Timer */ 1570 spr_register(env, SPR_DECR, "DECR", 1571 SPR_NOACCESS, SPR_NOACCESS, 1572 &spr_read_decr, &spr_write_decr, 1573 0x00000000); 1574 /* XXX : not implemented */ 1575 spr_register(env, SPR_MPC_EIE, "EIE", 1576 SPR_NOACCESS, SPR_NOACCESS, 1577 &spr_read_generic, &spr_write_generic, 1578 0x00000000); 1579 /* XXX : not implemented */ 1580 spr_register(env, SPR_MPC_EID, "EID", 1581 SPR_NOACCESS, SPR_NOACCESS, 1582 &spr_read_generic, &spr_write_generic, 1583 0x00000000); 1584 /* XXX : not implemented */ 1585 spr_register(env, SPR_MPC_NRI, "NRI", 1586 SPR_NOACCESS, SPR_NOACCESS, 1587 &spr_read_generic, &spr_write_generic, 1588 0x00000000); 1589 /* XXX : not implemented */ 1590 spr_register(env, SPR_MPC_CMPA, "CMPA", 1591 SPR_NOACCESS, SPR_NOACCESS, 1592 &spr_read_generic, &spr_write_generic, 1593 0x00000000); 1594 /* XXX : not implemented */ 1595 spr_register(env, SPR_MPC_CMPB, "CMPB", 1596 SPR_NOACCESS, SPR_NOACCESS, 1597 &spr_read_generic, &spr_write_generic, 1598 0x00000000); 1599 /* XXX : not implemented */ 1600 spr_register(env, SPR_MPC_CMPC, "CMPC", 1601 SPR_NOACCESS, SPR_NOACCESS, 1602 &spr_read_generic, &spr_write_generic, 1603 0x00000000); 1604 /* XXX : not implemented */ 1605 spr_register(env, SPR_MPC_CMPD, "CMPD", 1606 SPR_NOACCESS, SPR_NOACCESS, 1607 &spr_read_generic, &spr_write_generic, 1608 0x00000000); 1609 /* XXX : not implemented */ 1610 spr_register(env, SPR_MPC_ECR, "ECR", 1611 SPR_NOACCESS, SPR_NOACCESS, 1612 &spr_read_generic, &spr_write_generic, 1613 0x00000000); 1614 /* XXX : not implemented */ 1615 spr_register(env, SPR_MPC_DER, "DER", 1616 SPR_NOACCESS, SPR_NOACCESS, 1617 &spr_read_generic, &spr_write_generic, 1618 0x00000000); 1619 /* XXX : not implemented */ 1620 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1621 SPR_NOACCESS, SPR_NOACCESS, 1622 &spr_read_generic, &spr_write_generic, 1623 0x00000000); 1624 /* XXX : not implemented */ 1625 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1626 SPR_NOACCESS, SPR_NOACCESS, 1627 &spr_read_generic, &spr_write_generic, 1628 0x00000000); 1629 /* XXX : not implemented */ 1630 spr_register(env, SPR_MPC_CMPE, "CMPE", 1631 SPR_NOACCESS, SPR_NOACCESS, 1632 &spr_read_generic, &spr_write_generic, 1633 0x00000000); 1634 /* XXX : not implemented */ 1635 spr_register(env, SPR_MPC_CMPF, "CMPF", 1636 SPR_NOACCESS, SPR_NOACCESS, 1637 &spr_read_generic, &spr_write_generic, 1638 0x00000000); 1639 /* XXX : not implemented */ 1640 spr_register(env, SPR_MPC_CMPG, "CMPG", 1641 SPR_NOACCESS, SPR_NOACCESS, 1642 &spr_read_generic, &spr_write_generic, 1643 0x00000000); 1644 /* XXX : not implemented */ 1645 spr_register(env, SPR_MPC_CMPH, "CMPH", 1646 SPR_NOACCESS, SPR_NOACCESS, 1647 &spr_read_generic, &spr_write_generic, 1648 0x00000000); 1649 /* XXX : not implemented */ 1650 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1651 SPR_NOACCESS, SPR_NOACCESS, 1652 &spr_read_generic, &spr_write_generic, 1653 0x00000000); 1654 /* XXX : not implemented */ 1655 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1656 SPR_NOACCESS, SPR_NOACCESS, 1657 &spr_read_generic, &spr_write_generic, 1658 0x00000000); 1659 /* XXX : not implemented */ 1660 spr_register(env, SPR_MPC_BAR, "BAR", 1661 SPR_NOACCESS, SPR_NOACCESS, 1662 &spr_read_generic, &spr_write_generic, 1663 0x00000000); 1664 /* XXX : not implemented */ 1665 spr_register(env, SPR_MPC_DPDR, "DPDR", 1666 SPR_NOACCESS, SPR_NOACCESS, 1667 &spr_read_generic, &spr_write_generic, 1668 0x00000000); 1669 /* XXX : not implemented */ 1670 spr_register(env, SPR_MPC_IMMR, "IMMR", 1671 SPR_NOACCESS, SPR_NOACCESS, 1672 &spr_read_generic, &spr_write_generic, 1673 0x00000000); 1674 } 1675 1676 static void register_5xx_sprs(CPUPPCState *env) 1677 { 1678 /* XXX : not implemented */ 1679 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1680 SPR_NOACCESS, SPR_NOACCESS, 1681 &spr_read_generic, &spr_write_generic, 1682 0x00000000); 1683 /* XXX : not implemented */ 1684 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1685 SPR_NOACCESS, SPR_NOACCESS, 1686 &spr_read_generic, &spr_write_generic, 1687 0x00000000); 1688 /* XXX : not implemented */ 1689 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1690 SPR_NOACCESS, SPR_NOACCESS, 1691 &spr_read_generic, &spr_write_generic, 1692 0x00000000); 1693 /* XXX : not implemented */ 1694 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1695 SPR_NOACCESS, SPR_NOACCESS, 1696 &spr_read_generic, &spr_write_generic, 1697 0x00000000); 1698 /* XXX : not implemented */ 1699 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1700 SPR_NOACCESS, SPR_NOACCESS, 1701 &spr_read_generic, &spr_write_generic, 1702 0x00000000); 1703 /* XXX : not implemented */ 1704 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1705 SPR_NOACCESS, SPR_NOACCESS, 1706 &spr_read_generic, &spr_write_generic, 1707 0x00000000); 1708 /* XXX : not implemented */ 1709 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1710 SPR_NOACCESS, SPR_NOACCESS, 1711 &spr_read_generic, &spr_write_generic, 1712 0x00000000); 1713 /* XXX : not implemented */ 1714 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1715 SPR_NOACCESS, SPR_NOACCESS, 1716 &spr_read_generic, &spr_write_generic, 1717 0x00000000); 1718 /* XXX : not implemented */ 1719 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1720 SPR_NOACCESS, SPR_NOACCESS, 1721 &spr_read_generic, &spr_write_generic, 1722 0x00000000); 1723 /* XXX : not implemented */ 1724 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1725 SPR_NOACCESS, SPR_NOACCESS, 1726 &spr_read_generic, &spr_write_generic, 1727 0x00000000); 1728 /* XXX : not implemented */ 1729 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1730 SPR_NOACCESS, SPR_NOACCESS, 1731 &spr_read_generic, &spr_write_generic, 1732 0x00000000); 1733 /* XXX : not implemented */ 1734 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1735 SPR_NOACCESS, SPR_NOACCESS, 1736 &spr_read_generic, &spr_write_generic, 1737 0x00000000); 1738 /* XXX : not implemented */ 1739 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1740 SPR_NOACCESS, SPR_NOACCESS, 1741 &spr_read_generic, &spr_write_generic, 1742 0x00000000); 1743 /* XXX : not implemented */ 1744 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1745 SPR_NOACCESS, SPR_NOACCESS, 1746 &spr_read_generic, &spr_write_generic, 1747 0x00000000); 1748 /* XXX : not implemented */ 1749 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1750 SPR_NOACCESS, SPR_NOACCESS, 1751 &spr_read_generic, &spr_write_generic, 1752 0x00000000); 1753 /* XXX : not implemented */ 1754 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1755 SPR_NOACCESS, SPR_NOACCESS, 1756 &spr_read_generic, &spr_write_generic, 1757 0x00000000); 1758 /* XXX : not implemented */ 1759 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1760 SPR_NOACCESS, SPR_NOACCESS, 1761 &spr_read_generic, &spr_write_generic, 1762 0x00000000); 1763 /* XXX : not implemented */ 1764 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1765 SPR_NOACCESS, SPR_NOACCESS, 1766 &spr_read_generic, &spr_write_generic, 1767 0x00000000); 1768 /* XXX : not implemented */ 1769 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1770 SPR_NOACCESS, SPR_NOACCESS, 1771 &spr_read_generic, &spr_write_generic, 1772 0x00000000); 1773 /* XXX : not implemented */ 1774 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1775 SPR_NOACCESS, SPR_NOACCESS, 1776 &spr_read_generic, &spr_write_generic, 1777 0x00000000); 1778 /* XXX : not implemented */ 1779 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1780 SPR_NOACCESS, SPR_NOACCESS, 1781 &spr_read_generic, &spr_write_generic, 1782 0x00000000); 1783 } 1784 1785 static void register_8xx_sprs(CPUPPCState *env) 1786 { 1787 /* XXX : not implemented */ 1788 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1789 SPR_NOACCESS, SPR_NOACCESS, 1790 &spr_read_generic, &spr_write_generic, 1791 0x00000000); 1792 /* XXX : not implemented */ 1793 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1794 SPR_NOACCESS, SPR_NOACCESS, 1795 &spr_read_generic, &spr_write_generic, 1796 0x00000000); 1797 /* XXX : not implemented */ 1798 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1799 SPR_NOACCESS, SPR_NOACCESS, 1800 &spr_read_generic, &spr_write_generic, 1801 0x00000000); 1802 /* XXX : not implemented */ 1803 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1804 SPR_NOACCESS, SPR_NOACCESS, 1805 &spr_read_generic, &spr_write_generic, 1806 0x00000000); 1807 /* XXX : not implemented */ 1808 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1809 SPR_NOACCESS, SPR_NOACCESS, 1810 &spr_read_generic, &spr_write_generic, 1811 0x00000000); 1812 /* XXX : not implemented */ 1813 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1814 SPR_NOACCESS, SPR_NOACCESS, 1815 &spr_read_generic, &spr_write_generic, 1816 0x00000000); 1817 /* XXX : not implemented */ 1818 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1819 SPR_NOACCESS, SPR_NOACCESS, 1820 &spr_read_generic, &spr_write_generic, 1821 0x00000000); 1822 /* XXX : not implemented */ 1823 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1824 SPR_NOACCESS, SPR_NOACCESS, 1825 &spr_read_generic, &spr_write_generic, 1826 0x00000000); 1827 /* XXX : not implemented */ 1828 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1829 SPR_NOACCESS, SPR_NOACCESS, 1830 &spr_read_generic, &spr_write_generic, 1831 0x00000000); 1832 /* XXX : not implemented */ 1833 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1834 SPR_NOACCESS, SPR_NOACCESS, 1835 &spr_read_generic, &spr_write_generic, 1836 0x00000000); 1837 /* XXX : not implemented */ 1838 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1839 SPR_NOACCESS, SPR_NOACCESS, 1840 &spr_read_generic, &spr_write_generic, 1841 0x00000000); 1842 /* XXX : not implemented */ 1843 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1844 SPR_NOACCESS, SPR_NOACCESS, 1845 &spr_read_generic, &spr_write_generic, 1846 0x00000000); 1847 /* XXX : not implemented */ 1848 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1849 SPR_NOACCESS, SPR_NOACCESS, 1850 &spr_read_generic, &spr_write_generic, 1851 0x00000000); 1852 /* XXX : not implemented */ 1853 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1854 SPR_NOACCESS, SPR_NOACCESS, 1855 &spr_read_generic, &spr_write_generic, 1856 0x00000000); 1857 /* XXX : not implemented */ 1858 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1859 SPR_NOACCESS, SPR_NOACCESS, 1860 &spr_read_generic, &spr_write_generic, 1861 0x00000000); 1862 /* XXX : not implemented */ 1863 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1864 SPR_NOACCESS, SPR_NOACCESS, 1865 &spr_read_generic, &spr_write_generic, 1866 0x00000000); 1867 /* XXX : not implemented */ 1868 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1869 SPR_NOACCESS, SPR_NOACCESS, 1870 &spr_read_generic, &spr_write_generic, 1871 0x00000000); 1872 /* XXX : not implemented */ 1873 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1874 SPR_NOACCESS, SPR_NOACCESS, 1875 &spr_read_generic, &spr_write_generic, 1876 0x00000000); 1877 /* XXX : not implemented */ 1878 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1879 SPR_NOACCESS, SPR_NOACCESS, 1880 &spr_read_generic, &spr_write_generic, 1881 0x00000000); 1882 /* XXX : not implemented */ 1883 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1884 SPR_NOACCESS, SPR_NOACCESS, 1885 &spr_read_generic, &spr_write_generic, 1886 0x00000000); 1887 /* XXX : not implemented */ 1888 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1889 SPR_NOACCESS, SPR_NOACCESS, 1890 &spr_read_generic, &spr_write_generic, 1891 0x00000000); 1892 /* XXX : not implemented */ 1893 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1894 SPR_NOACCESS, SPR_NOACCESS, 1895 &spr_read_generic, &spr_write_generic, 1896 0x00000000); 1897 /* XXX : not implemented */ 1898 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1899 SPR_NOACCESS, SPR_NOACCESS, 1900 &spr_read_generic, &spr_write_generic, 1901 0x00000000); 1902 /* XXX : not implemented */ 1903 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1904 SPR_NOACCESS, SPR_NOACCESS, 1905 &spr_read_generic, &spr_write_generic, 1906 0x00000000); 1907 /* XXX : not implemented */ 1908 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1909 SPR_NOACCESS, SPR_NOACCESS, 1910 &spr_read_generic, &spr_write_generic, 1911 0x00000000); 1912 } 1913 1914 /* 1915 * AMR => SPR 29 (Power 2.04) 1916 * CTRL => SPR 136 (Power 2.04) 1917 * CTRL => SPR 152 (Power 2.04) 1918 * SCOMC => SPR 276 (64 bits ?) 1919 * SCOMD => SPR 277 (64 bits ?) 1920 * TBU40 => SPR 286 (Power 2.04 hypv) 1921 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1922 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1923 * HDSISR => SPR 306 (Power 2.04 hypv) 1924 * HDAR => SPR 307 (Power 2.04 hypv) 1925 * PURR => SPR 309 (Power 2.04 hypv) 1926 * HDEC => SPR 310 (Power 2.04 hypv) 1927 * HIOR => SPR 311 (hypv) 1928 * RMOR => SPR 312 (970) 1929 * HRMOR => SPR 313 (Power 2.04 hypv) 1930 * HSRR0 => SPR 314 (Power 2.04 hypv) 1931 * HSRR1 => SPR 315 (Power 2.04 hypv) 1932 * LPIDR => SPR 317 (970) 1933 * EPR => SPR 702 (Power 2.04 emb) 1934 * perf => 768-783 (Power 2.04) 1935 * perf => 784-799 (Power 2.04) 1936 * PPR => SPR 896 (Power 2.04) 1937 * DABRX => 1015 (Power 2.04 hypv) 1938 * FPECR => SPR 1022 (?) 1939 * ... and more (thermal management, performance counters, ...) 1940 */ 1941 1942 /*****************************************************************************/ 1943 /* Exception vectors models */ 1944 static void init_excp_4xx_softmmu(CPUPPCState *env) 1945 { 1946 #if !defined(CONFIG_USER_ONLY) 1947 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1948 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1949 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1950 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1951 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1952 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1953 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1954 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1955 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1956 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1957 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1958 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1959 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1960 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1961 env->ivor_mask = 0x0000FFF0UL; 1962 env->ivpr_mask = 0xFFFF0000UL; 1963 /* Hardware reset vector */ 1964 env->hreset_vector = 0xFFFFFFFCUL; 1965 #endif 1966 } 1967 1968 static void init_excp_MPC5xx(CPUPPCState *env) 1969 { 1970 #if !defined(CONFIG_USER_ONLY) 1971 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1972 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1973 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1974 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1975 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1976 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1977 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1978 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1979 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1980 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1981 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1982 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1983 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1984 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1985 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1986 env->ivor_mask = 0x0000FFF0UL; 1987 env->ivpr_mask = 0xFFFF0000UL; 1988 /* Hardware reset vector */ 1989 env->hreset_vector = 0x00000100UL; 1990 #endif 1991 } 1992 1993 static void init_excp_MPC8xx(CPUPPCState *env) 1994 { 1995 #if !defined(CONFIG_USER_ONLY) 1996 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1997 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1998 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1999 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2000 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2001 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2002 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2003 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2004 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2005 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2006 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2007 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2008 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2009 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 2010 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 2011 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 2012 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 2013 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2014 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2015 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2016 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2017 env->ivor_mask = 0x0000FFF0UL; 2018 env->ivpr_mask = 0xFFFF0000UL; 2019 /* Hardware reset vector */ 2020 env->hreset_vector = 0x00000100UL; 2021 #endif 2022 } 2023 2024 static void init_excp_G2(CPUPPCState *env) 2025 { 2026 #if !defined(CONFIG_USER_ONLY) 2027 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2028 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2029 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2030 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2031 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2032 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2033 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2034 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2035 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2036 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 2037 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2038 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2039 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2040 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2041 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2042 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2043 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2044 /* Hardware reset vector */ 2045 env->hreset_vector = 0x00000100UL; 2046 #endif 2047 } 2048 2049 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 2050 { 2051 #if !defined(CONFIG_USER_ONLY) 2052 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 2053 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2054 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2055 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2056 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2057 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2058 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2059 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2060 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2061 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2062 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2063 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2064 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2065 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2066 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2067 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2068 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2069 /* 2070 * These two are the same IVOR as POWERPC_EXCP_VPU and 2071 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 2072 * powerpc_excp(). 2073 */ 2074 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 2075 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 2076 2077 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 2078 env->ivor_mask = 0x0000FFF7UL; 2079 env->ivpr_mask = ivpr_mask; 2080 /* Hardware reset vector */ 2081 env->hreset_vector = 0xFFFFFFFCUL; 2082 #endif 2083 } 2084 2085 static void init_excp_BookE(CPUPPCState *env) 2086 { 2087 #if !defined(CONFIG_USER_ONLY) 2088 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2089 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2090 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2091 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2092 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2093 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2094 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2095 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2096 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2097 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2098 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2099 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2100 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2101 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2102 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2103 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2104 env->ivor_mask = 0x0000FFF0UL; 2105 env->ivpr_mask = 0xFFFF0000UL; 2106 /* Hardware reset vector */ 2107 env->hreset_vector = 0xFFFFFFFCUL; 2108 #endif 2109 } 2110 2111 static void init_excp_601(CPUPPCState *env) 2112 { 2113 #if !defined(CONFIG_USER_ONLY) 2114 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2115 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2116 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2117 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2118 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2119 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2120 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2121 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2122 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2123 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; 2124 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2125 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; 2126 /* Hardware reset vector */ 2127 env->hreset_vector = 0x00000100UL; 2128 #endif 2129 } 2130 2131 static void init_excp_602(CPUPPCState *env) 2132 { 2133 #if !defined(CONFIG_USER_ONLY) 2134 /* XXX: exception prefix has a special behavior on 602 */ 2135 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2136 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2137 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2138 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2139 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2140 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2141 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2142 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2143 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2144 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2145 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2146 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2147 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2148 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2149 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2150 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2151 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500; 2152 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600; 2153 /* Hardware reset vector */ 2154 env->hreset_vector = 0x00000100UL; 2155 #endif 2156 } 2157 2158 static void init_excp_603(CPUPPCState *env) 2159 { 2160 #if !defined(CONFIG_USER_ONLY) 2161 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2162 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2163 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2164 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2165 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2166 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2167 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2168 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2169 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2170 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2171 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2172 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2173 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2174 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2175 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2176 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2177 /* Hardware reset vector */ 2178 env->hreset_vector = 0x00000100UL; 2179 #endif 2180 } 2181 2182 static void init_excp_604(CPUPPCState *env) 2183 { 2184 #if !defined(CONFIG_USER_ONLY) 2185 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2186 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2187 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2188 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2189 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2190 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2191 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2192 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2193 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2194 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2195 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2196 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2197 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2198 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2199 /* Hardware reset vector */ 2200 env->hreset_vector = 0x00000100UL; 2201 #endif 2202 } 2203 2204 static void init_excp_7x0(CPUPPCState *env) 2205 { 2206 #if !defined(CONFIG_USER_ONLY) 2207 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2208 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2209 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2210 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2211 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2212 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2213 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2214 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2215 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2216 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2217 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2218 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2219 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2220 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2221 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2222 /* Hardware reset vector */ 2223 env->hreset_vector = 0x00000100UL; 2224 #endif 2225 } 2226 2227 static void init_excp_750cl(CPUPPCState *env) 2228 { 2229 #if !defined(CONFIG_USER_ONLY) 2230 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2231 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2232 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2233 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2234 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2235 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2236 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2237 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2238 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2239 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2240 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2241 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2242 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2243 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2244 /* Hardware reset vector */ 2245 env->hreset_vector = 0x00000100UL; 2246 #endif 2247 } 2248 2249 static void init_excp_750cx(CPUPPCState *env) 2250 { 2251 #if !defined(CONFIG_USER_ONLY) 2252 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2253 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2254 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2255 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2256 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2257 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2258 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2259 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2260 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2261 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2262 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2263 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2264 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2265 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2266 /* Hardware reset vector */ 2267 env->hreset_vector = 0x00000100UL; 2268 #endif 2269 } 2270 2271 /* XXX: Check if this is correct */ 2272 static void init_excp_7x5(CPUPPCState *env) 2273 { 2274 #if !defined(CONFIG_USER_ONLY) 2275 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2276 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2277 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2278 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2279 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2280 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2281 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2282 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2283 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2284 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2285 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2286 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2287 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2288 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2289 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2290 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2291 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2292 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2293 /* Hardware reset vector */ 2294 env->hreset_vector = 0x00000100UL; 2295 #endif 2296 } 2297 2298 static void init_excp_7400(CPUPPCState *env) 2299 { 2300 #if !defined(CONFIG_USER_ONLY) 2301 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2302 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2303 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2304 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2305 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2306 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2307 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2308 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2309 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2310 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2311 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2312 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2313 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2314 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2315 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2316 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2317 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2318 /* Hardware reset vector */ 2319 env->hreset_vector = 0x00000100UL; 2320 #endif 2321 } 2322 2323 static void init_excp_7450(CPUPPCState *env) 2324 { 2325 #if !defined(CONFIG_USER_ONLY) 2326 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2327 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2328 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2329 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2330 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2331 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2332 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2333 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2334 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2335 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2336 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2337 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2338 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2339 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2340 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2341 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2342 /* Hardware reset vector */ 2343 env->hreset_vector = 0x00000100UL; 2344 #endif 2345 } 2346 2347 #if defined(TARGET_PPC64) 2348 static void init_excp_970(CPUPPCState *env) 2349 { 2350 #if !defined(CONFIG_USER_ONLY) 2351 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2352 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2353 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2354 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2355 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2356 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2357 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2358 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2359 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2360 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2361 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2362 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2363 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2364 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2365 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2366 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2367 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2368 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2369 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2370 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2371 /* Hardware reset vector */ 2372 env->hreset_vector = 0x0000000000000100ULL; 2373 #endif 2374 } 2375 2376 static void init_excp_POWER7(CPUPPCState *env) 2377 { 2378 #if !defined(CONFIG_USER_ONLY) 2379 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2380 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2381 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2382 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2383 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2384 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2385 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2386 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2387 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2388 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2389 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2390 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2391 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2392 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2393 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2394 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2395 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2396 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2397 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2398 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2399 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2400 /* Hardware reset vector */ 2401 env->hreset_vector = 0x0000000000000100ULL; 2402 #endif 2403 } 2404 2405 static void init_excp_POWER8(CPUPPCState *env) 2406 { 2407 init_excp_POWER7(env); 2408 2409 #if !defined(CONFIG_USER_ONLY) 2410 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2411 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2412 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2413 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2414 #endif 2415 } 2416 2417 static void init_excp_POWER9(CPUPPCState *env) 2418 { 2419 init_excp_POWER8(env); 2420 2421 #if !defined(CONFIG_USER_ONLY) 2422 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2423 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2424 #endif 2425 } 2426 2427 static void init_excp_POWER10(CPUPPCState *env) 2428 { 2429 init_excp_POWER9(env); 2430 } 2431 2432 #endif 2433 2434 /*****************************************************************************/ 2435 /* Power management enable checks */ 2436 static int check_pow_none(CPUPPCState *env) 2437 { 2438 return 0; 2439 } 2440 2441 static int check_pow_nocheck(CPUPPCState *env) 2442 { 2443 return 1; 2444 } 2445 2446 static int check_pow_hid0(CPUPPCState *env) 2447 { 2448 if (env->spr[SPR_HID0] & 0x00E00000) { 2449 return 1; 2450 } 2451 2452 return 0; 2453 } 2454 2455 static int check_pow_hid0_74xx(CPUPPCState *env) 2456 { 2457 if (env->spr[SPR_HID0] & 0x00600000) { 2458 return 1; 2459 } 2460 2461 return 0; 2462 } 2463 2464 /*****************************************************************************/ 2465 /* PowerPC implementations definitions */ 2466 2467 #define POWERPC_FAMILY(_name) \ 2468 static void \ 2469 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2470 \ 2471 static const TypeInfo \ 2472 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2473 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2474 .parent = TYPE_POWERPC_CPU, \ 2475 .abstract = true, \ 2476 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2477 }; \ 2478 \ 2479 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2480 { \ 2481 type_register_static( \ 2482 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2483 } \ 2484 \ 2485 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2486 \ 2487 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2488 2489 static void init_proc_405(CPUPPCState *env) 2490 { 2491 /* Time base */ 2492 register_tbl(env); 2493 register_40x_sprs(env); 2494 register_405_sprs(env); 2495 /* Bus access control */ 2496 /* not emulated, as QEMU never does speculative access */ 2497 spr_register(env, SPR_40x_SGR, "SGR", 2498 SPR_NOACCESS, SPR_NOACCESS, 2499 &spr_read_generic, &spr_write_generic, 2500 0xFFFFFFFF); 2501 /* not emulated, as QEMU do not emulate caches */ 2502 spr_register(env, SPR_40x_DCWR, "DCWR", 2503 SPR_NOACCESS, SPR_NOACCESS, 2504 &spr_read_generic, &spr_write_generic, 2505 0x00000000); 2506 /* Memory management */ 2507 #if !defined(CONFIG_USER_ONLY) 2508 env->nb_tlb = 64; 2509 env->nb_ways = 1; 2510 env->id_tlbs = 0; 2511 env->tlb_type = TLB_EMB; 2512 #endif 2513 init_excp_4xx_softmmu(env); 2514 env->dcache_line_size = 32; 2515 env->icache_line_size = 32; 2516 /* Allocate hardware IRQ controller */ 2517 ppc40x_irq_init(env_archcpu(env)); 2518 2519 SET_FIT_PERIOD(8, 12, 16, 20); 2520 SET_WDT_PERIOD(16, 20, 24, 28); 2521 } 2522 2523 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2524 { 2525 DeviceClass *dc = DEVICE_CLASS(oc); 2526 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2527 2528 dc->desc = "PowerPC 405"; 2529 pcc->init_proc = init_proc_405; 2530 pcc->check_pow = check_pow_nocheck; 2531 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2532 PPC_DCR | PPC_WRTEE | 2533 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2534 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2535 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2536 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2537 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2538 pcc->msr_mask = (1ull << MSR_POW) | 2539 (1ull << MSR_CE) | 2540 (1ull << MSR_EE) | 2541 (1ull << MSR_PR) | 2542 (1ull << MSR_FP) | 2543 (1ull << MSR_DWE) | 2544 (1ull << MSR_DE) | 2545 (1ull << MSR_IR) | 2546 (1ull << MSR_DR); 2547 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2548 pcc->excp_model = POWERPC_EXCP_40x; 2549 pcc->bus_model = PPC_FLAGS_INPUT_405; 2550 pcc->bfd_mach = bfd_mach_ppc_403; 2551 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2552 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2553 } 2554 2555 static void init_proc_440EP(CPUPPCState *env) 2556 { 2557 /* Time base */ 2558 register_tbl(env); 2559 register_BookE_sprs(env, 0x000000000000FFFFULL); 2560 register_440_sprs(env); 2561 register_usprgh_sprs(env); 2562 /* Processor identification */ 2563 spr_register(env, SPR_BOOKE_PIR, "PIR", 2564 SPR_NOACCESS, SPR_NOACCESS, 2565 &spr_read_generic, &spr_write_pir, 2566 0x00000000); 2567 /* XXX : not implemented */ 2568 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2569 SPR_NOACCESS, SPR_NOACCESS, 2570 &spr_read_generic, &spr_write_generic, 2571 0x00000000); 2572 /* XXX : not implemented */ 2573 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2574 SPR_NOACCESS, SPR_NOACCESS, 2575 &spr_read_generic, &spr_write_generic, 2576 0x00000000); 2577 /* XXX : not implemented */ 2578 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2579 SPR_NOACCESS, SPR_NOACCESS, 2580 &spr_read_generic, &spr_write_generic, 2581 0x00000000); 2582 /* XXX : not implemented */ 2583 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2584 SPR_NOACCESS, SPR_NOACCESS, 2585 &spr_read_generic, &spr_write_generic, 2586 0x00000000); 2587 /* XXX : not implemented */ 2588 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2589 SPR_NOACCESS, SPR_NOACCESS, 2590 &spr_read_generic, &spr_write_generic, 2591 0x00000000); 2592 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2593 SPR_NOACCESS, SPR_NOACCESS, 2594 &spr_read_generic, &spr_write_generic, 2595 0x00000000); 2596 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2597 SPR_NOACCESS, SPR_NOACCESS, 2598 &spr_read_generic, &spr_write_generic, 2599 0x00000000); 2600 /* XXX : not implemented */ 2601 spr_register(env, SPR_440_CCR1, "CCR1", 2602 SPR_NOACCESS, SPR_NOACCESS, 2603 &spr_read_generic, &spr_write_generic, 2604 0x00000000); 2605 /* Memory management */ 2606 #if !defined(CONFIG_USER_ONLY) 2607 env->nb_tlb = 64; 2608 env->nb_ways = 1; 2609 env->id_tlbs = 0; 2610 env->tlb_type = TLB_EMB; 2611 #endif 2612 init_excp_BookE(env); 2613 env->dcache_line_size = 32; 2614 env->icache_line_size = 32; 2615 ppc40x_irq_init(env_archcpu(env)); 2616 2617 SET_FIT_PERIOD(12, 16, 20, 24); 2618 SET_WDT_PERIOD(20, 24, 28, 32); 2619 } 2620 2621 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2622 { 2623 DeviceClass *dc = DEVICE_CLASS(oc); 2624 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2625 2626 dc->desc = "PowerPC 440 EP"; 2627 pcc->init_proc = init_proc_440EP; 2628 pcc->check_pow = check_pow_nocheck; 2629 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2630 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2631 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2632 PPC_FLOAT_STFIWX | 2633 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2634 PPC_CACHE | PPC_CACHE_ICBI | 2635 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2636 PPC_MEM_TLBSYNC | PPC_MFTB | 2637 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2638 PPC_440_SPEC; 2639 pcc->msr_mask = (1ull << MSR_POW) | 2640 (1ull << MSR_CE) | 2641 (1ull << MSR_EE) | 2642 (1ull << MSR_PR) | 2643 (1ull << MSR_FP) | 2644 (1ull << MSR_ME) | 2645 (1ull << MSR_FE0) | 2646 (1ull << MSR_DWE) | 2647 (1ull << MSR_DE) | 2648 (1ull << MSR_FE1) | 2649 (1ull << MSR_IR) | 2650 (1ull << MSR_DR); 2651 pcc->mmu_model = POWERPC_MMU_BOOKE; 2652 pcc->excp_model = POWERPC_EXCP_BOOKE; 2653 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2654 pcc->bfd_mach = bfd_mach_ppc_403; 2655 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2656 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2657 } 2658 2659 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2660 { 2661 DeviceClass *dc = DEVICE_CLASS(oc); 2662 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2663 2664 dc->desc = "PowerPC 460 EX"; 2665 pcc->init_proc = init_proc_440EP; 2666 pcc->check_pow = check_pow_nocheck; 2667 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2668 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2669 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2670 PPC_FLOAT_STFIWX | 2671 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2672 PPC_CACHE | PPC_CACHE_ICBI | 2673 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2674 PPC_MEM_TLBSYNC | PPC_MFTB | 2675 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2676 PPC_440_SPEC; 2677 pcc->msr_mask = (1ull << MSR_POW) | 2678 (1ull << MSR_CE) | 2679 (1ull << MSR_EE) | 2680 (1ull << MSR_PR) | 2681 (1ull << MSR_FP) | 2682 (1ull << MSR_ME) | 2683 (1ull << MSR_FE0) | 2684 (1ull << MSR_DWE) | 2685 (1ull << MSR_DE) | 2686 (1ull << MSR_FE1) | 2687 (1ull << MSR_IR) | 2688 (1ull << MSR_DR); 2689 pcc->mmu_model = POWERPC_MMU_BOOKE; 2690 pcc->excp_model = POWERPC_EXCP_BOOKE; 2691 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2692 pcc->bfd_mach = bfd_mach_ppc_403; 2693 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2694 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2695 } 2696 2697 static void init_proc_440GP(CPUPPCState *env) 2698 { 2699 /* Time base */ 2700 register_tbl(env); 2701 register_BookE_sprs(env, 0x000000000000FFFFULL); 2702 register_440_sprs(env); 2703 register_usprgh_sprs(env); 2704 /* Processor identification */ 2705 spr_register(env, SPR_BOOKE_PIR, "PIR", 2706 SPR_NOACCESS, SPR_NOACCESS, 2707 &spr_read_generic, &spr_write_pir, 2708 0x00000000); 2709 /* XXX : not implemented */ 2710 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2711 SPR_NOACCESS, SPR_NOACCESS, 2712 &spr_read_generic, &spr_write_generic, 2713 0x00000000); 2714 /* XXX : not implemented */ 2715 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2716 SPR_NOACCESS, SPR_NOACCESS, 2717 &spr_read_generic, &spr_write_generic, 2718 0x00000000); 2719 /* XXX : not implemented */ 2720 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2721 SPR_NOACCESS, SPR_NOACCESS, 2722 &spr_read_generic, &spr_write_generic, 2723 0x00000000); 2724 /* XXX : not implemented */ 2725 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2726 SPR_NOACCESS, SPR_NOACCESS, 2727 &spr_read_generic, &spr_write_generic, 2728 0x00000000); 2729 /* Memory management */ 2730 #if !defined(CONFIG_USER_ONLY) 2731 env->nb_tlb = 64; 2732 env->nb_ways = 1; 2733 env->id_tlbs = 0; 2734 env->tlb_type = TLB_EMB; 2735 #endif 2736 init_excp_BookE(env); 2737 env->dcache_line_size = 32; 2738 env->icache_line_size = 32; 2739 /* XXX: TODO: allocate internal IRQ controller */ 2740 2741 SET_FIT_PERIOD(12, 16, 20, 24); 2742 SET_WDT_PERIOD(20, 24, 28, 32); 2743 } 2744 2745 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2746 { 2747 DeviceClass *dc = DEVICE_CLASS(oc); 2748 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2749 2750 dc->desc = "PowerPC 440 GP"; 2751 pcc->init_proc = init_proc_440GP; 2752 pcc->check_pow = check_pow_nocheck; 2753 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2754 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2755 PPC_CACHE | PPC_CACHE_ICBI | 2756 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2757 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2758 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2759 PPC_440_SPEC; 2760 pcc->msr_mask = (1ull << MSR_POW) | 2761 (1ull << MSR_CE) | 2762 (1ull << MSR_EE) | 2763 (1ull << MSR_PR) | 2764 (1ull << MSR_FP) | 2765 (1ull << MSR_ME) | 2766 (1ull << MSR_FE0) | 2767 (1ull << MSR_DWE) | 2768 (1ull << MSR_DE) | 2769 (1ull << MSR_FE1) | 2770 (1ull << MSR_IR) | 2771 (1ull << MSR_DR); 2772 pcc->mmu_model = POWERPC_MMU_BOOKE; 2773 pcc->excp_model = POWERPC_EXCP_BOOKE; 2774 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2775 pcc->bfd_mach = bfd_mach_ppc_403; 2776 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2777 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2778 } 2779 2780 static void init_proc_440x4(CPUPPCState *env) 2781 { 2782 /* Time base */ 2783 register_tbl(env); 2784 register_BookE_sprs(env, 0x000000000000FFFFULL); 2785 register_440_sprs(env); 2786 register_usprgh_sprs(env); 2787 /* Processor identification */ 2788 spr_register(env, SPR_BOOKE_PIR, "PIR", 2789 SPR_NOACCESS, SPR_NOACCESS, 2790 &spr_read_generic, &spr_write_pir, 2791 0x00000000); 2792 /* XXX : not implemented */ 2793 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2794 SPR_NOACCESS, SPR_NOACCESS, 2795 &spr_read_generic, &spr_write_generic, 2796 0x00000000); 2797 /* XXX : not implemented */ 2798 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2799 SPR_NOACCESS, SPR_NOACCESS, 2800 &spr_read_generic, &spr_write_generic, 2801 0x00000000); 2802 /* XXX : not implemented */ 2803 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2804 SPR_NOACCESS, SPR_NOACCESS, 2805 &spr_read_generic, &spr_write_generic, 2806 0x00000000); 2807 /* XXX : not implemented */ 2808 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2809 SPR_NOACCESS, SPR_NOACCESS, 2810 &spr_read_generic, &spr_write_generic, 2811 0x00000000); 2812 /* Memory management */ 2813 #if !defined(CONFIG_USER_ONLY) 2814 env->nb_tlb = 64; 2815 env->nb_ways = 1; 2816 env->id_tlbs = 0; 2817 env->tlb_type = TLB_EMB; 2818 #endif 2819 init_excp_BookE(env); 2820 env->dcache_line_size = 32; 2821 env->icache_line_size = 32; 2822 /* XXX: TODO: allocate internal IRQ controller */ 2823 2824 SET_FIT_PERIOD(12, 16, 20, 24); 2825 SET_WDT_PERIOD(20, 24, 28, 32); 2826 } 2827 2828 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data) 2829 { 2830 DeviceClass *dc = DEVICE_CLASS(oc); 2831 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2832 2833 dc->desc = "PowerPC 440x4"; 2834 pcc->init_proc = init_proc_440x4; 2835 pcc->check_pow = check_pow_nocheck; 2836 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2837 PPC_DCR | PPC_WRTEE | 2838 PPC_CACHE | PPC_CACHE_ICBI | 2839 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2840 PPC_MEM_TLBSYNC | PPC_MFTB | 2841 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2842 PPC_440_SPEC; 2843 pcc->msr_mask = (1ull << MSR_POW) | 2844 (1ull << MSR_CE) | 2845 (1ull << MSR_EE) | 2846 (1ull << MSR_PR) | 2847 (1ull << MSR_FP) | 2848 (1ull << MSR_ME) | 2849 (1ull << MSR_FE0) | 2850 (1ull << MSR_DWE) | 2851 (1ull << MSR_DE) | 2852 (1ull << MSR_FE1) | 2853 (1ull << MSR_IR) | 2854 (1ull << MSR_DR); 2855 pcc->mmu_model = POWERPC_MMU_BOOKE; 2856 pcc->excp_model = POWERPC_EXCP_BOOKE; 2857 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2858 pcc->bfd_mach = bfd_mach_ppc_403; 2859 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2860 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2861 } 2862 2863 static void init_proc_440x5(CPUPPCState *env) 2864 { 2865 /* Time base */ 2866 register_tbl(env); 2867 register_BookE_sprs(env, 0x000000000000FFFFULL); 2868 register_440_sprs(env); 2869 register_usprgh_sprs(env); 2870 /* Processor identification */ 2871 spr_register(env, SPR_BOOKE_PIR, "PIR", 2872 SPR_NOACCESS, SPR_NOACCESS, 2873 &spr_read_generic, &spr_write_pir, 2874 0x00000000); 2875 /* XXX : not implemented */ 2876 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2877 SPR_NOACCESS, SPR_NOACCESS, 2878 &spr_read_generic, &spr_write_generic, 2879 0x00000000); 2880 /* XXX : not implemented */ 2881 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2882 SPR_NOACCESS, SPR_NOACCESS, 2883 &spr_read_generic, &spr_write_generic, 2884 0x00000000); 2885 /* XXX : not implemented */ 2886 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2887 SPR_NOACCESS, SPR_NOACCESS, 2888 &spr_read_generic, &spr_write_generic, 2889 0x00000000); 2890 /* XXX : not implemented */ 2891 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2892 SPR_NOACCESS, SPR_NOACCESS, 2893 &spr_read_generic, &spr_write_generic, 2894 0x00000000); 2895 /* XXX : not implemented */ 2896 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2897 SPR_NOACCESS, SPR_NOACCESS, 2898 &spr_read_generic, &spr_write_generic, 2899 0x00000000); 2900 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2901 SPR_NOACCESS, SPR_NOACCESS, 2902 &spr_read_generic, &spr_write_generic, 2903 0x00000000); 2904 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2905 SPR_NOACCESS, SPR_NOACCESS, 2906 &spr_read_generic, &spr_write_generic, 2907 0x00000000); 2908 /* XXX : not implemented */ 2909 spr_register(env, SPR_440_CCR1, "CCR1", 2910 SPR_NOACCESS, SPR_NOACCESS, 2911 &spr_read_generic, &spr_write_generic, 2912 0x00000000); 2913 /* Memory management */ 2914 #if !defined(CONFIG_USER_ONLY) 2915 env->nb_tlb = 64; 2916 env->nb_ways = 1; 2917 env->id_tlbs = 0; 2918 env->tlb_type = TLB_EMB; 2919 #endif 2920 init_excp_BookE(env); 2921 env->dcache_line_size = 32; 2922 env->icache_line_size = 32; 2923 ppc40x_irq_init(env_archcpu(env)); 2924 2925 SET_FIT_PERIOD(12, 16, 20, 24); 2926 SET_WDT_PERIOD(20, 24, 28, 32); 2927 } 2928 2929 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2930 { 2931 DeviceClass *dc = DEVICE_CLASS(oc); 2932 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2933 2934 dc->desc = "PowerPC 440x5"; 2935 pcc->init_proc = init_proc_440x5; 2936 pcc->check_pow = check_pow_nocheck; 2937 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2938 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2939 PPC_CACHE | PPC_CACHE_ICBI | 2940 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2941 PPC_MEM_TLBSYNC | PPC_MFTB | 2942 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2943 PPC_440_SPEC; 2944 pcc->msr_mask = (1ull << MSR_POW) | 2945 (1ull << MSR_CE) | 2946 (1ull << MSR_EE) | 2947 (1ull << MSR_PR) | 2948 (1ull << MSR_FP) | 2949 (1ull << MSR_ME) | 2950 (1ull << MSR_FE0) | 2951 (1ull << MSR_DWE) | 2952 (1ull << MSR_DE) | 2953 (1ull << MSR_FE1) | 2954 (1ull << MSR_IR) | 2955 (1ull << MSR_DR); 2956 pcc->mmu_model = POWERPC_MMU_BOOKE; 2957 pcc->excp_model = POWERPC_EXCP_BOOKE; 2958 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2959 pcc->bfd_mach = bfd_mach_ppc_403; 2960 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2961 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2962 } 2963 2964 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2965 { 2966 DeviceClass *dc = DEVICE_CLASS(oc); 2967 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2968 2969 dc->desc = "PowerPC 440x5 with double precision FPU"; 2970 pcc->init_proc = init_proc_440x5; 2971 pcc->check_pow = check_pow_nocheck; 2972 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2973 PPC_FLOAT | PPC_FLOAT_FSQRT | 2974 PPC_FLOAT_STFIWX | 2975 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2976 PPC_CACHE | PPC_CACHE_ICBI | 2977 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2978 PPC_MEM_TLBSYNC | PPC_MFTB | 2979 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2980 PPC_440_SPEC; 2981 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2982 pcc->msr_mask = (1ull << MSR_POW) | 2983 (1ull << MSR_CE) | 2984 (1ull << MSR_EE) | 2985 (1ull << MSR_PR) | 2986 (1ull << MSR_FP) | 2987 (1ull << MSR_ME) | 2988 (1ull << MSR_FE0) | 2989 (1ull << MSR_DWE) | 2990 (1ull << MSR_DE) | 2991 (1ull << MSR_FE1) | 2992 (1ull << MSR_IR) | 2993 (1ull << MSR_DR); 2994 pcc->mmu_model = POWERPC_MMU_BOOKE; 2995 pcc->excp_model = POWERPC_EXCP_BOOKE; 2996 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2997 pcc->bfd_mach = bfd_mach_ppc_403; 2998 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2999 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3000 } 3001 3002 static void init_proc_MPC5xx(CPUPPCState *env) 3003 { 3004 /* Time base */ 3005 register_tbl(env); 3006 register_5xx_8xx_sprs(env); 3007 register_5xx_sprs(env); 3008 init_excp_MPC5xx(env); 3009 env->dcache_line_size = 32; 3010 env->icache_line_size = 32; 3011 /* XXX: TODO: allocate internal IRQ controller */ 3012 } 3013 3014 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 3015 { 3016 DeviceClass *dc = DEVICE_CLASS(oc); 3017 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3018 3019 dc->desc = "Freescale 5xx cores (aka RCPU)"; 3020 pcc->init_proc = init_proc_MPC5xx; 3021 pcc->check_pow = check_pow_none; 3022 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3023 PPC_MEM_EIEIO | PPC_MEM_SYNC | 3024 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 3025 PPC_MFTB; 3026 pcc->msr_mask = (1ull << MSR_ILE) | 3027 (1ull << MSR_EE) | 3028 (1ull << MSR_PR) | 3029 (1ull << MSR_FP) | 3030 (1ull << MSR_ME) | 3031 (1ull << MSR_FE0) | 3032 (1ull << MSR_SE) | 3033 (1ull << MSR_DE) | 3034 (1ull << MSR_FE1) | 3035 (1ull << MSR_EP) | 3036 (1ull << MSR_RI) | 3037 (1ull << MSR_LE); 3038 pcc->mmu_model = POWERPC_MMU_REAL; 3039 pcc->excp_model = POWERPC_EXCP_603; 3040 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 3041 pcc->bfd_mach = bfd_mach_ppc_505; 3042 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3043 POWERPC_FLAG_BUS_CLK; 3044 } 3045 3046 static void init_proc_MPC8xx(CPUPPCState *env) 3047 { 3048 /* Time base */ 3049 register_tbl(env); 3050 register_5xx_8xx_sprs(env); 3051 register_8xx_sprs(env); 3052 init_excp_MPC8xx(env); 3053 env->dcache_line_size = 32; 3054 env->icache_line_size = 32; 3055 /* XXX: TODO: allocate internal IRQ controller */ 3056 } 3057 3058 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 3059 { 3060 DeviceClass *dc = DEVICE_CLASS(oc); 3061 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3062 3063 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 3064 pcc->init_proc = init_proc_MPC8xx; 3065 pcc->check_pow = check_pow_none; 3066 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3067 PPC_MEM_EIEIO | PPC_MEM_SYNC | 3068 PPC_CACHE_ICBI | PPC_MFTB; 3069 pcc->msr_mask = (1ull << MSR_ILE) | 3070 (1ull << MSR_EE) | 3071 (1ull << MSR_PR) | 3072 (1ull << MSR_FP) | 3073 (1ull << MSR_ME) | 3074 (1ull << MSR_SE) | 3075 (1ull << MSR_DE) | 3076 (1ull << MSR_EP) | 3077 (1ull << MSR_IR) | 3078 (1ull << MSR_DR) | 3079 (1ull << MSR_RI) | 3080 (1ull << MSR_LE); 3081 pcc->mmu_model = POWERPC_MMU_MPC8xx; 3082 pcc->excp_model = POWERPC_EXCP_603; 3083 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 3084 pcc->bfd_mach = bfd_mach_ppc_860; 3085 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3086 POWERPC_FLAG_BUS_CLK; 3087 } 3088 3089 /* Freescale 82xx cores (aka PowerQUICC-II) */ 3090 3091 static void init_proc_G2(CPUPPCState *env) 3092 { 3093 register_ne_601_sprs(env); 3094 register_sdr1_sprs(env); 3095 register_G2_755_sprs(env); 3096 register_G2_sprs(env); 3097 /* Time base */ 3098 register_tbl(env); 3099 /* External access control */ 3100 /* XXX : not implemented */ 3101 spr_register(env, SPR_EAR, "EAR", 3102 SPR_NOACCESS, SPR_NOACCESS, 3103 &spr_read_generic, &spr_write_generic, 3104 0x00000000); 3105 /* Hardware implementation register */ 3106 /* XXX : not implemented */ 3107 spr_register(env, SPR_HID0, "HID0", 3108 SPR_NOACCESS, SPR_NOACCESS, 3109 &spr_read_generic, &spr_write_generic, 3110 0x00000000); 3111 /* XXX : not implemented */ 3112 spr_register(env, SPR_HID1, "HID1", 3113 SPR_NOACCESS, SPR_NOACCESS, 3114 &spr_read_generic, &spr_write_generic, 3115 0x00000000); 3116 /* XXX : not implemented */ 3117 spr_register(env, SPR_HID2, "HID2", 3118 SPR_NOACCESS, SPR_NOACCESS, 3119 &spr_read_generic, &spr_write_generic, 3120 0x00000000); 3121 /* Memory management */ 3122 register_low_BATs(env); 3123 register_high_BATs(env); 3124 register_6xx_7xx_soft_tlb(env, 64, 2); 3125 init_excp_G2(env); 3126 env->dcache_line_size = 32; 3127 env->icache_line_size = 32; 3128 /* Allocate hardware IRQ controller */ 3129 ppc6xx_irq_init(env_archcpu(env)); 3130 } 3131 3132 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 3133 { 3134 DeviceClass *dc = DEVICE_CLASS(oc); 3135 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3136 3137 dc->desc = "PowerPC G2"; 3138 pcc->init_proc = init_proc_G2; 3139 pcc->check_pow = check_pow_hid0; 3140 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3141 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3142 PPC_FLOAT_STFIWX | 3143 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3144 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3145 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3146 PPC_SEGMENT | PPC_EXTERN; 3147 pcc->msr_mask = (1ull << MSR_POW) | 3148 (1ull << MSR_TGPR) | 3149 (1ull << MSR_EE) | 3150 (1ull << MSR_PR) | 3151 (1ull << MSR_FP) | 3152 (1ull << MSR_ME) | 3153 (1ull << MSR_FE0) | 3154 (1ull << MSR_SE) | 3155 (1ull << MSR_DE) | 3156 (1ull << MSR_FE1) | 3157 (1ull << MSR_AL) | 3158 (1ull << MSR_EP) | 3159 (1ull << MSR_IR) | 3160 (1ull << MSR_DR) | 3161 (1ull << MSR_RI); 3162 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3163 pcc->excp_model = POWERPC_EXCP_G2; 3164 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3165 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3166 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3167 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3168 } 3169 3170 static void init_proc_G2LE(CPUPPCState *env) 3171 { 3172 register_ne_601_sprs(env); 3173 register_sdr1_sprs(env); 3174 register_G2_755_sprs(env); 3175 register_G2_sprs(env); 3176 /* Time base */ 3177 register_tbl(env); 3178 /* External access control */ 3179 /* XXX : not implemented */ 3180 spr_register(env, SPR_EAR, "EAR", 3181 SPR_NOACCESS, SPR_NOACCESS, 3182 &spr_read_generic, &spr_write_generic, 3183 0x00000000); 3184 /* Hardware implementation register */ 3185 /* XXX : not implemented */ 3186 spr_register(env, SPR_HID0, "HID0", 3187 SPR_NOACCESS, SPR_NOACCESS, 3188 &spr_read_generic, &spr_write_generic, 3189 0x00000000); 3190 /* XXX : not implemented */ 3191 spr_register(env, SPR_HID1, "HID1", 3192 SPR_NOACCESS, SPR_NOACCESS, 3193 &spr_read_generic, &spr_write_generic, 3194 0x00000000); 3195 /* XXX : not implemented */ 3196 spr_register(env, SPR_HID2, "HID2", 3197 SPR_NOACCESS, SPR_NOACCESS, 3198 &spr_read_generic, &spr_write_generic, 3199 0x00000000); 3200 3201 /* Memory management */ 3202 register_low_BATs(env); 3203 register_high_BATs(env); 3204 register_6xx_7xx_soft_tlb(env, 64, 2); 3205 init_excp_G2(env); 3206 env->dcache_line_size = 32; 3207 env->icache_line_size = 32; 3208 /* Allocate hardware IRQ controller */ 3209 ppc6xx_irq_init(env_archcpu(env)); 3210 } 3211 3212 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 3213 { 3214 DeviceClass *dc = DEVICE_CLASS(oc); 3215 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3216 3217 dc->desc = "PowerPC G2LE"; 3218 pcc->init_proc = init_proc_G2LE; 3219 pcc->check_pow = check_pow_hid0; 3220 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3221 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3222 PPC_FLOAT_STFIWX | 3223 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3224 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3225 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3226 PPC_SEGMENT | PPC_EXTERN; 3227 pcc->msr_mask = (1ull << MSR_POW) | 3228 (1ull << MSR_TGPR) | 3229 (1ull << MSR_ILE) | 3230 (1ull << MSR_EE) | 3231 (1ull << MSR_PR) | 3232 (1ull << MSR_FP) | 3233 (1ull << MSR_ME) | 3234 (1ull << MSR_FE0) | 3235 (1ull << MSR_SE) | 3236 (1ull << MSR_DE) | 3237 (1ull << MSR_FE1) | 3238 (1ull << MSR_AL) | 3239 (1ull << MSR_EP) | 3240 (1ull << MSR_IR) | 3241 (1ull << MSR_DR) | 3242 (1ull << MSR_RI) | 3243 (1ull << MSR_LE); 3244 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3245 pcc->excp_model = POWERPC_EXCP_G2; 3246 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3247 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3248 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3249 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3250 } 3251 3252 static void init_proc_e200(CPUPPCState *env) 3253 { 3254 /* Time base */ 3255 register_tbl(env); 3256 register_BookE_sprs(env, 0x000000070000FFFFULL); 3257 /* XXX : not implemented */ 3258 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3259 &spr_read_spefscr, &spr_write_spefscr, 3260 &spr_read_spefscr, &spr_write_spefscr, 3261 0x00000000); 3262 /* Memory management */ 3263 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 3264 /* XXX : not implemented */ 3265 spr_register(env, SPR_HID0, "HID0", 3266 SPR_NOACCESS, SPR_NOACCESS, 3267 &spr_read_generic, &spr_write_generic, 3268 0x00000000); 3269 /* XXX : not implemented */ 3270 spr_register(env, SPR_HID1, "HID1", 3271 SPR_NOACCESS, SPR_NOACCESS, 3272 &spr_read_generic, &spr_write_generic, 3273 0x00000000); 3274 /* XXX : not implemented */ 3275 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 3276 SPR_NOACCESS, SPR_NOACCESS, 3277 &spr_read_generic, &spr_write_generic, 3278 0x00000000); 3279 /* XXX : not implemented */ 3280 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3281 SPR_NOACCESS, SPR_NOACCESS, 3282 &spr_read_generic, &spr_write_generic, 3283 0x00000000); 3284 /* XXX : not implemented */ 3285 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3286 SPR_NOACCESS, SPR_NOACCESS, 3287 &spr_read_generic, &spr_write_generic, 3288 0x00000000); 3289 /* XXX : not implemented */ 3290 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3291 SPR_NOACCESS, SPR_NOACCESS, 3292 &spr_read_generic, &spr_write_generic, 3293 0x00000000); 3294 /* XXX : not implemented */ 3295 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3296 SPR_NOACCESS, SPR_NOACCESS, 3297 &spr_read_generic, &spr_write_generic, 3298 0x00000000); 3299 /* XXX : not implemented */ 3300 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3301 &spr_read_generic, SPR_NOACCESS, 3302 &spr_read_generic, SPR_NOACCESS, 3303 0x00000000); 3304 /* XXX : not implemented */ 3305 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3306 SPR_NOACCESS, SPR_NOACCESS, 3307 &spr_read_generic, &spr_write_generic, 3308 0x00000000); 3309 /* XXX : not implemented */ 3310 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3311 SPR_NOACCESS, SPR_NOACCESS, 3312 &spr_read_generic, &spr_write_generic, 3313 0x00000000); 3314 /* XXX : not implemented */ 3315 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3316 SPR_NOACCESS, SPR_NOACCESS, 3317 &spr_read_generic, &spr_write_generic, 3318 0x00000000); 3319 /* XXX : not implemented */ 3320 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3321 SPR_NOACCESS, SPR_NOACCESS, 3322 &spr_read_generic, &spr_write_generic, 3323 0x00000000); 3324 /* XXX : not implemented */ 3325 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3326 SPR_NOACCESS, SPR_NOACCESS, 3327 &spr_read_generic, &spr_write_generic, 3328 0x00000000); 3329 /* XXX : not implemented */ 3330 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3331 SPR_NOACCESS, SPR_NOACCESS, 3332 &spr_read_generic, &spr_write_generic, 3333 0x00000000); 3334 /* XXX : not implemented */ 3335 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3336 SPR_NOACCESS, SPR_NOACCESS, 3337 &spr_read_generic, &spr_write_generic, 3338 0x00000000); /* TOFIX */ 3339 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3340 SPR_NOACCESS, SPR_NOACCESS, 3341 &spr_read_generic, &spr_write_generic, 3342 0x00000000); 3343 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3344 SPR_NOACCESS, SPR_NOACCESS, 3345 &spr_read_generic, &spr_write_generic, 3346 0x00000000); 3347 #if !defined(CONFIG_USER_ONLY) 3348 env->nb_tlb = 64; 3349 env->nb_ways = 1; 3350 env->id_tlbs = 0; 3351 env->tlb_type = TLB_EMB; 3352 #endif 3353 init_excp_e200(env, 0xFFFF0000UL); 3354 env->dcache_line_size = 32; 3355 env->icache_line_size = 32; 3356 /* XXX: TODO: allocate internal IRQ controller */ 3357 } 3358 3359 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3360 { 3361 DeviceClass *dc = DEVICE_CLASS(oc); 3362 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3363 3364 dc->desc = "e200 core"; 3365 pcc->init_proc = init_proc_e200; 3366 pcc->check_pow = check_pow_hid0; 3367 /* 3368 * XXX: unimplemented instructions: 3369 * dcblc 3370 * dcbtlst 3371 * dcbtstls 3372 * icblc 3373 * icbtls 3374 * tlbivax 3375 * all SPE multiply-accumulate instructions 3376 */ 3377 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3378 PPC_SPE | PPC_SPE_SINGLE | 3379 PPC_WRTEE | PPC_RFDI | 3380 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3381 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3382 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3383 PPC_BOOKE; 3384 pcc->msr_mask = (1ull << MSR_UCLE) | 3385 (1ull << MSR_SPE) | 3386 (1ull << MSR_POW) | 3387 (1ull << MSR_CE) | 3388 (1ull << MSR_EE) | 3389 (1ull << MSR_PR) | 3390 (1ull << MSR_FP) | 3391 (1ull << MSR_ME) | 3392 (1ull << MSR_FE0) | 3393 (1ull << MSR_DWE) | 3394 (1ull << MSR_DE) | 3395 (1ull << MSR_FE1) | 3396 (1ull << MSR_IR) | 3397 (1ull << MSR_DR); 3398 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3399 pcc->excp_model = POWERPC_EXCP_BOOKE; 3400 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3401 pcc->bfd_mach = bfd_mach_ppc_860; 3402 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3403 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3404 POWERPC_FLAG_BUS_CLK; 3405 } 3406 3407 static void init_proc_e300(CPUPPCState *env) 3408 { 3409 register_ne_601_sprs(env); 3410 register_sdr1_sprs(env); 3411 register_603_sprs(env); 3412 /* Time base */ 3413 register_tbl(env); 3414 /* hardware implementation registers */ 3415 /* XXX : not implemented */ 3416 spr_register(env, SPR_HID0, "HID0", 3417 SPR_NOACCESS, SPR_NOACCESS, 3418 &spr_read_generic, &spr_write_generic, 3419 0x00000000); 3420 /* XXX : not implemented */ 3421 spr_register(env, SPR_HID1, "HID1", 3422 SPR_NOACCESS, SPR_NOACCESS, 3423 &spr_read_generic, &spr_write_generic, 3424 0x00000000); 3425 /* XXX : not implemented */ 3426 spr_register(env, SPR_HID2, "HID2", 3427 SPR_NOACCESS, SPR_NOACCESS, 3428 &spr_read_generic, &spr_write_generic, 3429 0x00000000); 3430 /* Breakpoints */ 3431 /* XXX : not implemented */ 3432 spr_register(env, SPR_DABR, "DABR", 3433 SPR_NOACCESS, SPR_NOACCESS, 3434 &spr_read_generic, &spr_write_generic, 3435 0x00000000); 3436 /* XXX : not implemented */ 3437 spr_register(env, SPR_DABR2, "DABR2", 3438 SPR_NOACCESS, SPR_NOACCESS, 3439 &spr_read_generic, &spr_write_generic, 3440 0x00000000); 3441 /* XXX : not implemented */ 3442 spr_register(env, SPR_IABR2, "IABR2", 3443 SPR_NOACCESS, SPR_NOACCESS, 3444 &spr_read_generic, &spr_write_generic, 3445 0x00000000); 3446 /* XXX : not implemented */ 3447 spr_register(env, SPR_IBCR, "IBCR", 3448 SPR_NOACCESS, SPR_NOACCESS, 3449 &spr_read_generic, &spr_write_generic, 3450 0x00000000); 3451 /* XXX : not implemented */ 3452 spr_register(env, SPR_DBCR, "DBCR", 3453 SPR_NOACCESS, SPR_NOACCESS, 3454 &spr_read_generic, &spr_write_generic, 3455 0x00000000); 3456 /* Memory management */ 3457 register_low_BATs(env); 3458 register_high_BATs(env); 3459 register_6xx_7xx_soft_tlb(env, 64, 2); 3460 init_excp_603(env); 3461 env->dcache_line_size = 32; 3462 env->icache_line_size = 32; 3463 /* Allocate hardware IRQ controller */ 3464 ppc6xx_irq_init(env_archcpu(env)); 3465 } 3466 3467 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3468 { 3469 DeviceClass *dc = DEVICE_CLASS(oc); 3470 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3471 3472 dc->desc = "e300 core"; 3473 pcc->init_proc = init_proc_e300; 3474 pcc->check_pow = check_pow_hid0; 3475 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3476 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3477 PPC_FLOAT_STFIWX | 3478 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3479 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3480 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3481 PPC_SEGMENT | PPC_EXTERN; 3482 pcc->msr_mask = (1ull << MSR_POW) | 3483 (1ull << MSR_TGPR) | 3484 (1ull << MSR_ILE) | 3485 (1ull << MSR_EE) | 3486 (1ull << MSR_PR) | 3487 (1ull << MSR_FP) | 3488 (1ull << MSR_ME) | 3489 (1ull << MSR_FE0) | 3490 (1ull << MSR_SE) | 3491 (1ull << MSR_DE) | 3492 (1ull << MSR_FE1) | 3493 (1ull << MSR_AL) | 3494 (1ull << MSR_EP) | 3495 (1ull << MSR_IR) | 3496 (1ull << MSR_DR) | 3497 (1ull << MSR_RI) | 3498 (1ull << MSR_LE); 3499 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3500 pcc->excp_model = POWERPC_EXCP_603; 3501 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3502 pcc->bfd_mach = bfd_mach_ppc_603; 3503 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3504 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3505 } 3506 3507 enum fsl_e500_version { 3508 fsl_e500v1, 3509 fsl_e500v2, 3510 fsl_e500mc, 3511 fsl_e5500, 3512 fsl_e6500, 3513 }; 3514 3515 static void init_proc_e500(CPUPPCState *env, int version) 3516 { 3517 uint32_t tlbncfg[2]; 3518 uint64_t ivor_mask; 3519 uint64_t ivpr_mask = 0xFFFF0000ULL; 3520 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3521 | 0x0020; /* 32 kb */ 3522 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3523 | 0x0020; /* 32 kb */ 3524 uint32_t mmucfg = 0; 3525 #if !defined(CONFIG_USER_ONLY) 3526 int i; 3527 #endif 3528 3529 /* Time base */ 3530 register_tbl(env); 3531 /* 3532 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3533 * complain when accessing them. 3534 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3535 */ 3536 switch (version) { 3537 case fsl_e500v1: 3538 case fsl_e500v2: 3539 default: 3540 ivor_mask = 0x0000000F0000FFFFULL; 3541 break; 3542 case fsl_e500mc: 3543 case fsl_e5500: 3544 ivor_mask = 0x000003FE0000FFFFULL; 3545 break; 3546 case fsl_e6500: 3547 ivor_mask = 0x000003FF0000FFFFULL; 3548 break; 3549 } 3550 register_BookE_sprs(env, ivor_mask); 3551 register_usprg3_sprs(env); 3552 /* Processor identification */ 3553 spr_register(env, SPR_BOOKE_PIR, "PIR", 3554 SPR_NOACCESS, SPR_NOACCESS, 3555 &spr_read_generic, &spr_write_pir, 3556 0x00000000); 3557 /* XXX : not implemented */ 3558 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3559 &spr_read_spefscr, &spr_write_spefscr, 3560 &spr_read_spefscr, &spr_write_spefscr, 3561 0x00000000); 3562 #if !defined(CONFIG_USER_ONLY) 3563 /* Memory management */ 3564 env->nb_pids = 3; 3565 env->nb_ways = 2; 3566 env->id_tlbs = 0; 3567 switch (version) { 3568 case fsl_e500v1: 3569 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3570 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3571 break; 3572 case fsl_e500v2: 3573 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3574 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3575 break; 3576 case fsl_e500mc: 3577 case fsl_e5500: 3578 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3579 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3580 break; 3581 case fsl_e6500: 3582 mmucfg = 0x6510B45; 3583 env->nb_pids = 1; 3584 tlbncfg[0] = 0x08052400; 3585 tlbncfg[1] = 0x40028040; 3586 break; 3587 default: 3588 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3589 env->spr[SPR_PVR]); 3590 } 3591 #endif 3592 /* Cache sizes */ 3593 switch (version) { 3594 case fsl_e500v1: 3595 case fsl_e500v2: 3596 env->dcache_line_size = 32; 3597 env->icache_line_size = 32; 3598 break; 3599 case fsl_e500mc: 3600 case fsl_e5500: 3601 env->dcache_line_size = 64; 3602 env->icache_line_size = 64; 3603 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3604 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3605 break; 3606 case fsl_e6500: 3607 env->dcache_line_size = 32; 3608 env->icache_line_size = 32; 3609 l1cfg0 |= 0x0F83820; 3610 l1cfg1 |= 0x0B83820; 3611 break; 3612 default: 3613 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3614 env->spr[SPR_PVR]); 3615 } 3616 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3617 /* XXX : not implemented */ 3618 spr_register(env, SPR_HID0, "HID0", 3619 SPR_NOACCESS, SPR_NOACCESS, 3620 &spr_read_generic, &spr_write_generic, 3621 0x00000000); 3622 /* XXX : not implemented */ 3623 spr_register(env, SPR_HID1, "HID1", 3624 SPR_NOACCESS, SPR_NOACCESS, 3625 &spr_read_generic, &spr_write_generic, 3626 0x00000000); 3627 /* XXX : not implemented */ 3628 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3629 SPR_NOACCESS, SPR_NOACCESS, 3630 &spr_read_generic, &spr_write_generic, 3631 0x00000000); 3632 /* XXX : not implemented */ 3633 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3634 SPR_NOACCESS, SPR_NOACCESS, 3635 &spr_read_generic, &spr_write_generic, 3636 0x00000000); 3637 /* XXX : not implemented */ 3638 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3639 SPR_NOACCESS, SPR_NOACCESS, 3640 &spr_read_generic, &spr_write_generic, 3641 0x00000000); 3642 /* XXX : not implemented */ 3643 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3644 SPR_NOACCESS, SPR_NOACCESS, 3645 &spr_read_generic, &spr_write_generic, 3646 0x00000000); 3647 /* XXX : not implemented */ 3648 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3649 SPR_NOACCESS, SPR_NOACCESS, 3650 &spr_read_generic, &spr_write_generic, 3651 0x00000000); 3652 /* XXX : not implemented */ 3653 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3654 SPR_NOACCESS, SPR_NOACCESS, 3655 &spr_read_generic, &spr_write_generic, 3656 0x00000000); 3657 /* XXX : not implemented */ 3658 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3659 &spr_read_generic, SPR_NOACCESS, 3660 &spr_read_generic, SPR_NOACCESS, 3661 l1cfg0); 3662 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3663 &spr_read_generic, SPR_NOACCESS, 3664 &spr_read_generic, SPR_NOACCESS, 3665 l1cfg1); 3666 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3667 SPR_NOACCESS, SPR_NOACCESS, 3668 &spr_read_generic, &spr_write_e500_l1csr0, 3669 0x00000000); 3670 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3671 SPR_NOACCESS, SPR_NOACCESS, 3672 &spr_read_generic, &spr_write_e500_l1csr1, 3673 0x00000000); 3674 if (version != fsl_e500v1 && version != fsl_e500v2) { 3675 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3676 SPR_NOACCESS, SPR_NOACCESS, 3677 &spr_read_generic, &spr_write_e500_l2csr0, 3678 0x00000000); 3679 } 3680 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3681 SPR_NOACCESS, SPR_NOACCESS, 3682 &spr_read_generic, &spr_write_generic, 3683 0x00000000); 3684 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3685 SPR_NOACCESS, SPR_NOACCESS, 3686 &spr_read_generic, &spr_write_generic, 3687 0x00000000); 3688 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3689 SPR_NOACCESS, SPR_NOACCESS, 3690 &spr_read_generic, &spr_write_booke206_mmucsr0, 3691 0x00000000); 3692 spr_register(env, SPR_BOOKE_EPR, "EPR", 3693 SPR_NOACCESS, SPR_NOACCESS, 3694 &spr_read_generic, SPR_NOACCESS, 3695 0x00000000); 3696 /* XXX better abstract into Emb.xxx features */ 3697 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3698 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3699 SPR_NOACCESS, SPR_NOACCESS, 3700 &spr_read_generic, &spr_write_generic, 3701 0x00000000); 3702 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3703 SPR_NOACCESS, SPR_NOACCESS, 3704 &spr_read_mas73, &spr_write_mas73, 3705 0x00000000); 3706 ivpr_mask = (target_ulong)~0xFFFFULL; 3707 } 3708 3709 if (version == fsl_e6500) { 3710 /* Thread identification */ 3711 spr_register(env, SPR_TIR, "TIR", 3712 SPR_NOACCESS, SPR_NOACCESS, 3713 &spr_read_generic, SPR_NOACCESS, 3714 0x00000000); 3715 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3716 SPR_NOACCESS, SPR_NOACCESS, 3717 &spr_read_generic, SPR_NOACCESS, 3718 0x00000004); 3719 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3720 SPR_NOACCESS, SPR_NOACCESS, 3721 &spr_read_generic, SPR_NOACCESS, 3722 0x7FFFFFFC); 3723 } 3724 3725 #if !defined(CONFIG_USER_ONLY) 3726 env->nb_tlb = 0; 3727 env->tlb_type = TLB_MAS; 3728 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3729 env->nb_tlb += booke206_tlb_size(env, i); 3730 } 3731 #endif 3732 3733 init_excp_e200(env, ivpr_mask); 3734 /* Allocate hardware IRQ controller */ 3735 ppce500_irq_init(env_archcpu(env)); 3736 } 3737 3738 static void init_proc_e500v1(CPUPPCState *env) 3739 { 3740 init_proc_e500(env, fsl_e500v1); 3741 } 3742 3743 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3744 { 3745 DeviceClass *dc = DEVICE_CLASS(oc); 3746 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3747 3748 dc->desc = "e500v1 core"; 3749 pcc->init_proc = init_proc_e500v1; 3750 pcc->check_pow = check_pow_hid0; 3751 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3752 PPC_SPE | PPC_SPE_SINGLE | 3753 PPC_WRTEE | PPC_RFDI | 3754 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3755 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3756 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3757 pcc->insns_flags2 = PPC2_BOOKE206; 3758 pcc->msr_mask = (1ull << MSR_UCLE) | 3759 (1ull << MSR_SPE) | 3760 (1ull << MSR_POW) | 3761 (1ull << MSR_CE) | 3762 (1ull << MSR_EE) | 3763 (1ull << MSR_PR) | 3764 (1ull << MSR_FP) | 3765 (1ull << MSR_ME) | 3766 (1ull << MSR_FE0) | 3767 (1ull << MSR_DWE) | 3768 (1ull << MSR_DE) | 3769 (1ull << MSR_FE1) | 3770 (1ull << MSR_IR) | 3771 (1ull << MSR_DR); 3772 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3773 pcc->excp_model = POWERPC_EXCP_BOOKE; 3774 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3775 pcc->bfd_mach = bfd_mach_ppc_860; 3776 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3777 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3778 POWERPC_FLAG_BUS_CLK; 3779 } 3780 3781 static void init_proc_e500v2(CPUPPCState *env) 3782 { 3783 init_proc_e500(env, fsl_e500v2); 3784 } 3785 3786 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3787 { 3788 DeviceClass *dc = DEVICE_CLASS(oc); 3789 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3790 3791 dc->desc = "e500v2 core"; 3792 pcc->init_proc = init_proc_e500v2; 3793 pcc->check_pow = check_pow_hid0; 3794 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3795 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3796 PPC_WRTEE | PPC_RFDI | 3797 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3798 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3799 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3800 pcc->insns_flags2 = PPC2_BOOKE206; 3801 pcc->msr_mask = (1ull << MSR_UCLE) | 3802 (1ull << MSR_SPE) | 3803 (1ull << MSR_POW) | 3804 (1ull << MSR_CE) | 3805 (1ull << MSR_EE) | 3806 (1ull << MSR_PR) | 3807 (1ull << MSR_FP) | 3808 (1ull << MSR_ME) | 3809 (1ull << MSR_FE0) | 3810 (1ull << MSR_DWE) | 3811 (1ull << MSR_DE) | 3812 (1ull << MSR_FE1) | 3813 (1ull << MSR_IR) | 3814 (1ull << MSR_DR); 3815 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3816 pcc->excp_model = POWERPC_EXCP_BOOKE; 3817 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3818 pcc->bfd_mach = bfd_mach_ppc_860; 3819 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3820 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3821 POWERPC_FLAG_BUS_CLK; 3822 } 3823 3824 static void init_proc_e500mc(CPUPPCState *env) 3825 { 3826 init_proc_e500(env, fsl_e500mc); 3827 } 3828 3829 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3830 { 3831 DeviceClass *dc = DEVICE_CLASS(oc); 3832 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3833 3834 dc->desc = "e500mc core"; 3835 pcc->init_proc = init_proc_e500mc; 3836 pcc->check_pow = check_pow_none; 3837 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3838 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3839 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3840 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3841 PPC_FLOAT | PPC_FLOAT_FRES | 3842 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3843 PPC_FLOAT_STFIWX | PPC_WAIT | 3844 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3845 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3846 pcc->msr_mask = (1ull << MSR_GS) | 3847 (1ull << MSR_UCLE) | 3848 (1ull << MSR_CE) | 3849 (1ull << MSR_EE) | 3850 (1ull << MSR_PR) | 3851 (1ull << MSR_FP) | 3852 (1ull << MSR_ME) | 3853 (1ull << MSR_FE0) | 3854 (1ull << MSR_DE) | 3855 (1ull << MSR_FE1) | 3856 (1ull << MSR_IR) | 3857 (1ull << MSR_DR) | 3858 (1ull << MSR_PX) | 3859 (1ull << MSR_RI); 3860 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3861 pcc->excp_model = POWERPC_EXCP_BOOKE; 3862 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3863 /* FIXME: figure out the correct flag for e500mc */ 3864 pcc->bfd_mach = bfd_mach_ppc_e500; 3865 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3866 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3867 } 3868 3869 #ifdef TARGET_PPC64 3870 static void init_proc_e5500(CPUPPCState *env) 3871 { 3872 init_proc_e500(env, fsl_e5500); 3873 } 3874 3875 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3876 { 3877 DeviceClass *dc = DEVICE_CLASS(oc); 3878 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3879 3880 dc->desc = "e5500 core"; 3881 pcc->init_proc = init_proc_e5500; 3882 pcc->check_pow = check_pow_none; 3883 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3884 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3885 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3886 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3887 PPC_FLOAT | PPC_FLOAT_FRES | 3888 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3889 PPC_FLOAT_STFIWX | PPC_WAIT | 3890 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3891 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3892 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3893 PPC2_FP_CVT_S64; 3894 pcc->msr_mask = (1ull << MSR_CM) | 3895 (1ull << MSR_GS) | 3896 (1ull << MSR_UCLE) | 3897 (1ull << MSR_CE) | 3898 (1ull << MSR_EE) | 3899 (1ull << MSR_PR) | 3900 (1ull << MSR_FP) | 3901 (1ull << MSR_ME) | 3902 (1ull << MSR_FE0) | 3903 (1ull << MSR_DE) | 3904 (1ull << MSR_FE1) | 3905 (1ull << MSR_IR) | 3906 (1ull << MSR_DR) | 3907 (1ull << MSR_PX) | 3908 (1ull << MSR_RI); 3909 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3910 pcc->excp_model = POWERPC_EXCP_BOOKE; 3911 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3912 /* FIXME: figure out the correct flag for e5500 */ 3913 pcc->bfd_mach = bfd_mach_ppc_e500; 3914 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3915 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3916 } 3917 3918 static void init_proc_e6500(CPUPPCState *env) 3919 { 3920 init_proc_e500(env, fsl_e6500); 3921 } 3922 3923 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3924 { 3925 DeviceClass *dc = DEVICE_CLASS(oc); 3926 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3927 3928 dc->desc = "e6500 core"; 3929 pcc->init_proc = init_proc_e6500; 3930 pcc->check_pow = check_pow_none; 3931 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3932 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3933 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3934 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3935 PPC_FLOAT | PPC_FLOAT_FRES | 3936 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3937 PPC_FLOAT_STFIWX | PPC_WAIT | 3938 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3939 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3940 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3941 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3942 pcc->msr_mask = (1ull << MSR_CM) | 3943 (1ull << MSR_GS) | 3944 (1ull << MSR_UCLE) | 3945 (1ull << MSR_CE) | 3946 (1ull << MSR_EE) | 3947 (1ull << MSR_PR) | 3948 (1ull << MSR_FP) | 3949 (1ull << MSR_ME) | 3950 (1ull << MSR_FE0) | 3951 (1ull << MSR_DE) | 3952 (1ull << MSR_FE1) | 3953 (1ull << MSR_IS) | 3954 (1ull << MSR_DS) | 3955 (1ull << MSR_PX) | 3956 (1ull << MSR_RI) | 3957 (1ull << MSR_VR); 3958 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3959 pcc->excp_model = POWERPC_EXCP_BOOKE; 3960 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3961 pcc->bfd_mach = bfd_mach_ppc_e500; 3962 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3963 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3964 } 3965 3966 #endif 3967 3968 /* Non-embedded PowerPC */ 3969 3970 #define POWERPC_MSRR_601 (0x0000000000001040ULL) 3971 3972 static void init_proc_601(CPUPPCState *env) 3973 { 3974 register_ne_601_sprs(env); 3975 register_sdr1_sprs(env); 3976 register_601_sprs(env); 3977 /* Hardware implementation registers */ 3978 /* XXX : not implemented */ 3979 spr_register(env, SPR_HID0, "HID0", 3980 SPR_NOACCESS, SPR_NOACCESS, 3981 &spr_read_generic, &spr_write_hid0_601, 3982 0x80010080); 3983 /* XXX : not implemented */ 3984 spr_register(env, SPR_HID1, "HID1", 3985 SPR_NOACCESS, SPR_NOACCESS, 3986 &spr_read_generic, &spr_write_generic, 3987 0x00000000); 3988 /* XXX : not implemented */ 3989 spr_register(env, SPR_601_HID2, "HID2", 3990 SPR_NOACCESS, SPR_NOACCESS, 3991 &spr_read_generic, &spr_write_generic, 3992 0x00000000); 3993 /* XXX : not implemented */ 3994 spr_register(env, SPR_601_HID5, "HID5", 3995 SPR_NOACCESS, SPR_NOACCESS, 3996 &spr_read_generic, &spr_write_generic, 3997 0x00000000); 3998 /* Memory management */ 3999 init_excp_601(env); 4000 /* 4001 * XXX: beware that dcache line size is 64 4002 * but dcbz uses 32 bytes "sectors" 4003 * XXX: this breaks clcs instruction ! 4004 */ 4005 env->dcache_line_size = 32; 4006 env->icache_line_size = 64; 4007 /* Allocate hardware IRQ controller */ 4008 ppc6xx_irq_init(env_archcpu(env)); 4009 } 4010 4011 POWERPC_FAMILY(601)(ObjectClass *oc, void *data) 4012 { 4013 DeviceClass *dc = DEVICE_CLASS(oc); 4014 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4015 4016 dc->desc = "PowerPC 601"; 4017 pcc->init_proc = init_proc_601; 4018 pcc->check_pow = check_pow_none; 4019 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 4020 PPC_FLOAT | 4021 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4022 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 4023 PPC_SEGMENT | PPC_EXTERN; 4024 pcc->msr_mask = (1ull << MSR_EE) | 4025 (1ull << MSR_PR) | 4026 (1ull << MSR_FP) | 4027 (1ull << MSR_ME) | 4028 (1ull << MSR_FE0) | 4029 (1ull << MSR_SE) | 4030 (1ull << MSR_FE1) | 4031 (1ull << MSR_EP) | 4032 (1ull << MSR_IR) | 4033 (1ull << MSR_DR); 4034 pcc->mmu_model = POWERPC_MMU_601; 4035 pcc->excp_model = POWERPC_EXCP_601; 4036 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4037 pcc->bfd_mach = bfd_mach_ppc_601; 4038 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 4039 } 4040 4041 #define POWERPC_MSRR_601v (0x0000000000001040ULL) 4042 4043 static void init_proc_601v(CPUPPCState *env) 4044 { 4045 init_proc_601(env); 4046 /* XXX : not implemented */ 4047 spr_register(env, SPR_601_HID15, "HID15", 4048 SPR_NOACCESS, SPR_NOACCESS, 4049 &spr_read_generic, &spr_write_generic, 4050 0x00000000); 4051 } 4052 4053 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) 4054 { 4055 DeviceClass *dc = DEVICE_CLASS(oc); 4056 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4057 4058 dc->desc = "PowerPC 601v"; 4059 pcc->init_proc = init_proc_601v; 4060 pcc->check_pow = check_pow_none; 4061 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 4062 PPC_FLOAT | 4063 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4064 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 4065 PPC_SEGMENT | PPC_EXTERN; 4066 pcc->msr_mask = (1ull << MSR_EE) | 4067 (1ull << MSR_PR) | 4068 (1ull << MSR_FP) | 4069 (1ull << MSR_ME) | 4070 (1ull << MSR_FE0) | 4071 (1ull << MSR_SE) | 4072 (1ull << MSR_FE1) | 4073 (1ull << MSR_EP) | 4074 (1ull << MSR_IR) | 4075 (1ull << MSR_DR); 4076 pcc->mmu_model = POWERPC_MMU_601; 4077 pcc->excp_model = POWERPC_EXCP_601; 4078 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4079 pcc->bfd_mach = bfd_mach_ppc_601; 4080 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 4081 } 4082 4083 static void init_proc_602(CPUPPCState *env) 4084 { 4085 register_ne_601_sprs(env); 4086 register_sdr1_sprs(env); 4087 register_602_sprs(env); 4088 /* Time base */ 4089 register_tbl(env); 4090 /* hardware implementation registers */ 4091 /* XXX : not implemented */ 4092 spr_register(env, SPR_HID0, "HID0", 4093 SPR_NOACCESS, SPR_NOACCESS, 4094 &spr_read_generic, &spr_write_generic, 4095 0x00000000); 4096 /* XXX : not implemented */ 4097 spr_register(env, SPR_HID1, "HID1", 4098 SPR_NOACCESS, SPR_NOACCESS, 4099 &spr_read_generic, &spr_write_generic, 4100 0x00000000); 4101 /* Memory management */ 4102 register_low_BATs(env); 4103 register_6xx_7xx_soft_tlb(env, 64, 2); 4104 init_excp_602(env); 4105 env->dcache_line_size = 32; 4106 env->icache_line_size = 32; 4107 /* Allocate hardware IRQ controller */ 4108 ppc6xx_irq_init(env_archcpu(env)); 4109 } 4110 4111 POWERPC_FAMILY(602)(ObjectClass *oc, void *data) 4112 { 4113 DeviceClass *dc = DEVICE_CLASS(oc); 4114 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4115 4116 dc->desc = "PowerPC 602"; 4117 pcc->init_proc = init_proc_602; 4118 pcc->check_pow = check_pow_hid0; 4119 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4120 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4121 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4122 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4123 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4124 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | 4125 PPC_SEGMENT | PPC_602_SPEC; 4126 pcc->msr_mask = (1ull << MSR_VSX) | 4127 (1ull << MSR_SA) | 4128 (1ull << MSR_POW) | 4129 (1ull << MSR_TGPR) | 4130 (1ull << MSR_ILE) | 4131 (1ull << MSR_EE) | 4132 (1ull << MSR_PR) | 4133 (1ull << MSR_FP) | 4134 (1ull << MSR_ME) | 4135 (1ull << MSR_FE0) | 4136 (1ull << MSR_SE) | 4137 (1ull << MSR_DE) | 4138 (1ull << MSR_FE1) | 4139 (1ull << MSR_EP) | 4140 (1ull << MSR_IR) | 4141 (1ull << MSR_DR) | 4142 (1ull << MSR_RI) | 4143 (1ull << MSR_LE); 4144 /* XXX: 602 MMU is quite specific. Should add a special case */ 4145 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4146 pcc->excp_model = POWERPC_EXCP_602; 4147 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4148 pcc->bfd_mach = bfd_mach_ppc_602; 4149 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4150 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4151 } 4152 4153 static void init_proc_603(CPUPPCState *env) 4154 { 4155 register_ne_601_sprs(env); 4156 register_sdr1_sprs(env); 4157 register_603_sprs(env); 4158 /* Time base */ 4159 register_tbl(env); 4160 /* hardware implementation registers */ 4161 /* XXX : not implemented */ 4162 spr_register(env, SPR_HID0, "HID0", 4163 SPR_NOACCESS, SPR_NOACCESS, 4164 &spr_read_generic, &spr_write_generic, 4165 0x00000000); 4166 /* XXX : not implemented */ 4167 spr_register(env, SPR_HID1, "HID1", 4168 SPR_NOACCESS, SPR_NOACCESS, 4169 &spr_read_generic, &spr_write_generic, 4170 0x00000000); 4171 /* Memory management */ 4172 register_low_BATs(env); 4173 register_6xx_7xx_soft_tlb(env, 64, 2); 4174 init_excp_603(env); 4175 env->dcache_line_size = 32; 4176 env->icache_line_size = 32; 4177 /* Allocate hardware IRQ controller */ 4178 ppc6xx_irq_init(env_archcpu(env)); 4179 } 4180 4181 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 4182 { 4183 DeviceClass *dc = DEVICE_CLASS(oc); 4184 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4185 4186 dc->desc = "PowerPC 603"; 4187 pcc->init_proc = init_proc_603; 4188 pcc->check_pow = check_pow_hid0; 4189 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4190 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4191 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4192 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4193 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4194 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4195 PPC_SEGMENT | PPC_EXTERN; 4196 pcc->msr_mask = (1ull << MSR_POW) | 4197 (1ull << MSR_TGPR) | 4198 (1ull << MSR_ILE) | 4199 (1ull << MSR_EE) | 4200 (1ull << MSR_PR) | 4201 (1ull << MSR_FP) | 4202 (1ull << MSR_ME) | 4203 (1ull << MSR_FE0) | 4204 (1ull << MSR_SE) | 4205 (1ull << MSR_DE) | 4206 (1ull << MSR_FE1) | 4207 (1ull << MSR_EP) | 4208 (1ull << MSR_IR) | 4209 (1ull << MSR_DR) | 4210 (1ull << MSR_RI) | 4211 (1ull << MSR_LE); 4212 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4213 pcc->excp_model = POWERPC_EXCP_603; 4214 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4215 pcc->bfd_mach = bfd_mach_ppc_603; 4216 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4217 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4218 } 4219 4220 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 4221 { 4222 DeviceClass *dc = DEVICE_CLASS(oc); 4223 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4224 4225 dc->desc = "PowerPC 603e"; 4226 pcc->init_proc = init_proc_603; 4227 pcc->check_pow = check_pow_hid0; 4228 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4229 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4230 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4231 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4232 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4233 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4234 PPC_SEGMENT | PPC_EXTERN; 4235 pcc->msr_mask = (1ull << MSR_POW) | 4236 (1ull << MSR_TGPR) | 4237 (1ull << MSR_ILE) | 4238 (1ull << MSR_EE) | 4239 (1ull << MSR_PR) | 4240 (1ull << MSR_FP) | 4241 (1ull << MSR_ME) | 4242 (1ull << MSR_FE0) | 4243 (1ull << MSR_SE) | 4244 (1ull << MSR_DE) | 4245 (1ull << MSR_FE1) | 4246 (1ull << MSR_EP) | 4247 (1ull << MSR_IR) | 4248 (1ull << MSR_DR) | 4249 (1ull << MSR_RI) | 4250 (1ull << MSR_LE); 4251 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4252 pcc->excp_model = POWERPC_EXCP_603; 4253 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4254 pcc->bfd_mach = bfd_mach_ppc_ec603e; 4255 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4256 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4257 } 4258 4259 static void init_proc_604(CPUPPCState *env) 4260 { 4261 register_ne_601_sprs(env); 4262 register_sdr1_sprs(env); 4263 register_604_sprs(env); 4264 /* Time base */ 4265 register_tbl(env); 4266 /* Hardware implementation registers */ 4267 /* XXX : not implemented */ 4268 spr_register(env, SPR_HID0, "HID0", 4269 SPR_NOACCESS, SPR_NOACCESS, 4270 &spr_read_generic, &spr_write_generic, 4271 0x00000000); 4272 /* Memory management */ 4273 register_low_BATs(env); 4274 init_excp_604(env); 4275 env->dcache_line_size = 32; 4276 env->icache_line_size = 32; 4277 /* Allocate hardware IRQ controller */ 4278 ppc6xx_irq_init(env_archcpu(env)); 4279 } 4280 4281 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 4282 { 4283 DeviceClass *dc = DEVICE_CLASS(oc); 4284 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4285 4286 dc->desc = "PowerPC 604"; 4287 pcc->init_proc = init_proc_604; 4288 pcc->check_pow = check_pow_nocheck; 4289 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4290 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4291 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4292 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4293 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4294 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4295 PPC_SEGMENT | PPC_EXTERN; 4296 pcc->msr_mask = (1ull << MSR_POW) | 4297 (1ull << MSR_ILE) | 4298 (1ull << MSR_EE) | 4299 (1ull << MSR_PR) | 4300 (1ull << MSR_FP) | 4301 (1ull << MSR_ME) | 4302 (1ull << MSR_FE0) | 4303 (1ull << MSR_SE) | 4304 (1ull << MSR_DE) | 4305 (1ull << MSR_FE1) | 4306 (1ull << MSR_EP) | 4307 (1ull << MSR_IR) | 4308 (1ull << MSR_DR) | 4309 (1ull << MSR_PMM) | 4310 (1ull << MSR_RI) | 4311 (1ull << MSR_LE); 4312 pcc->mmu_model = POWERPC_MMU_32B; 4313 pcc->excp_model = POWERPC_EXCP_604; 4314 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4315 pcc->bfd_mach = bfd_mach_ppc_604; 4316 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4317 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4318 } 4319 4320 static void init_proc_604E(CPUPPCState *env) 4321 { 4322 register_ne_601_sprs(env); 4323 register_sdr1_sprs(env); 4324 register_604_sprs(env); 4325 /* XXX : not implemented */ 4326 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 4327 SPR_NOACCESS, SPR_NOACCESS, 4328 &spr_read_generic, &spr_write_generic, 4329 0x00000000); 4330 /* XXX : not implemented */ 4331 spr_register(env, SPR_7XX_PMC3, "PMC3", 4332 SPR_NOACCESS, SPR_NOACCESS, 4333 &spr_read_generic, &spr_write_generic, 4334 0x00000000); 4335 /* XXX : not implemented */ 4336 spr_register(env, SPR_7XX_PMC4, "PMC4", 4337 SPR_NOACCESS, SPR_NOACCESS, 4338 &spr_read_generic, &spr_write_generic, 4339 0x00000000); 4340 /* Time base */ 4341 register_tbl(env); 4342 /* Hardware implementation registers */ 4343 /* XXX : not implemented */ 4344 spr_register(env, SPR_HID0, "HID0", 4345 SPR_NOACCESS, SPR_NOACCESS, 4346 &spr_read_generic, &spr_write_generic, 4347 0x00000000); 4348 /* XXX : not implemented */ 4349 spr_register(env, SPR_HID1, "HID1", 4350 SPR_NOACCESS, SPR_NOACCESS, 4351 &spr_read_generic, &spr_write_generic, 4352 0x00000000); 4353 /* Memory management */ 4354 register_low_BATs(env); 4355 init_excp_604(env); 4356 env->dcache_line_size = 32; 4357 env->icache_line_size = 32; 4358 /* Allocate hardware IRQ controller */ 4359 ppc6xx_irq_init(env_archcpu(env)); 4360 } 4361 4362 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 4363 { 4364 DeviceClass *dc = DEVICE_CLASS(oc); 4365 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4366 4367 dc->desc = "PowerPC 604E"; 4368 pcc->init_proc = init_proc_604E; 4369 pcc->check_pow = check_pow_nocheck; 4370 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4371 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4372 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4373 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4374 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4375 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4376 PPC_SEGMENT | PPC_EXTERN; 4377 pcc->msr_mask = (1ull << MSR_POW) | 4378 (1ull << MSR_ILE) | 4379 (1ull << MSR_EE) | 4380 (1ull << MSR_PR) | 4381 (1ull << MSR_FP) | 4382 (1ull << MSR_ME) | 4383 (1ull << MSR_FE0) | 4384 (1ull << MSR_SE) | 4385 (1ull << MSR_DE) | 4386 (1ull << MSR_FE1) | 4387 (1ull << MSR_EP) | 4388 (1ull << MSR_IR) | 4389 (1ull << MSR_DR) | 4390 (1ull << MSR_PMM) | 4391 (1ull << MSR_RI) | 4392 (1ull << MSR_LE); 4393 pcc->mmu_model = POWERPC_MMU_32B; 4394 pcc->excp_model = POWERPC_EXCP_604; 4395 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4396 pcc->bfd_mach = bfd_mach_ppc_604; 4397 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4398 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4399 } 4400 4401 static void init_proc_740(CPUPPCState *env) 4402 { 4403 register_ne_601_sprs(env); 4404 register_sdr1_sprs(env); 4405 register_7xx_sprs(env); 4406 /* Time base */ 4407 register_tbl(env); 4408 /* Thermal management */ 4409 register_thrm_sprs(env); 4410 /* Hardware implementation registers */ 4411 /* XXX : not implemented */ 4412 spr_register(env, SPR_HID0, "HID0", 4413 SPR_NOACCESS, SPR_NOACCESS, 4414 &spr_read_generic, &spr_write_generic, 4415 0x00000000); 4416 /* XXX : not implemented */ 4417 spr_register(env, SPR_HID1, "HID1", 4418 SPR_NOACCESS, SPR_NOACCESS, 4419 &spr_read_generic, &spr_write_generic, 4420 0x00000000); 4421 /* Memory management */ 4422 register_low_BATs(env); 4423 init_excp_7x0(env); 4424 env->dcache_line_size = 32; 4425 env->icache_line_size = 32; 4426 /* Allocate hardware IRQ controller */ 4427 ppc6xx_irq_init(env_archcpu(env)); 4428 } 4429 4430 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 4431 { 4432 DeviceClass *dc = DEVICE_CLASS(oc); 4433 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4434 4435 dc->desc = "PowerPC 740"; 4436 pcc->init_proc = init_proc_740; 4437 pcc->check_pow = check_pow_hid0; 4438 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4439 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4440 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4441 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4442 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4443 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4444 PPC_SEGMENT | PPC_EXTERN; 4445 pcc->msr_mask = (1ull << MSR_POW) | 4446 (1ull << MSR_ILE) | 4447 (1ull << MSR_EE) | 4448 (1ull << MSR_PR) | 4449 (1ull << MSR_FP) | 4450 (1ull << MSR_ME) | 4451 (1ull << MSR_FE0) | 4452 (1ull << MSR_SE) | 4453 (1ull << MSR_DE) | 4454 (1ull << MSR_FE1) | 4455 (1ull << MSR_EP) | 4456 (1ull << MSR_IR) | 4457 (1ull << MSR_DR) | 4458 (1ull << MSR_PMM) | 4459 (1ull << MSR_RI) | 4460 (1ull << MSR_LE); 4461 pcc->mmu_model = POWERPC_MMU_32B; 4462 pcc->excp_model = POWERPC_EXCP_7x0; 4463 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4464 pcc->bfd_mach = bfd_mach_ppc_750; 4465 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4466 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4467 } 4468 4469 static void init_proc_750(CPUPPCState *env) 4470 { 4471 register_ne_601_sprs(env); 4472 register_sdr1_sprs(env); 4473 register_7xx_sprs(env); 4474 /* XXX : not implemented */ 4475 spr_register(env, SPR_L2CR, "L2CR", 4476 SPR_NOACCESS, SPR_NOACCESS, 4477 &spr_read_generic, spr_access_nop, 4478 0x00000000); 4479 /* Time base */ 4480 register_tbl(env); 4481 /* Thermal management */ 4482 register_thrm_sprs(env); 4483 /* Hardware implementation registers */ 4484 /* XXX : not implemented */ 4485 spr_register(env, SPR_HID0, "HID0", 4486 SPR_NOACCESS, SPR_NOACCESS, 4487 &spr_read_generic, &spr_write_generic, 4488 0x00000000); 4489 /* XXX : not implemented */ 4490 spr_register(env, SPR_HID1, "HID1", 4491 SPR_NOACCESS, SPR_NOACCESS, 4492 &spr_read_generic, &spr_write_generic, 4493 0x00000000); 4494 /* Memory management */ 4495 register_low_BATs(env); 4496 /* 4497 * XXX: high BATs are also present but are known to be bugged on 4498 * die version 1.x 4499 */ 4500 init_excp_7x0(env); 4501 env->dcache_line_size = 32; 4502 env->icache_line_size = 32; 4503 /* Allocate hardware IRQ controller */ 4504 ppc6xx_irq_init(env_archcpu(env)); 4505 } 4506 4507 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 4508 { 4509 DeviceClass *dc = DEVICE_CLASS(oc); 4510 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4511 4512 dc->desc = "PowerPC 750"; 4513 pcc->init_proc = init_proc_750; 4514 pcc->check_pow = check_pow_hid0; 4515 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4516 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4517 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4518 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4519 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4520 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4521 PPC_SEGMENT | PPC_EXTERN; 4522 pcc->msr_mask = (1ull << MSR_POW) | 4523 (1ull << MSR_ILE) | 4524 (1ull << MSR_EE) | 4525 (1ull << MSR_PR) | 4526 (1ull << MSR_FP) | 4527 (1ull << MSR_ME) | 4528 (1ull << MSR_FE0) | 4529 (1ull << MSR_SE) | 4530 (1ull << MSR_DE) | 4531 (1ull << MSR_FE1) | 4532 (1ull << MSR_EP) | 4533 (1ull << MSR_IR) | 4534 (1ull << MSR_DR) | 4535 (1ull << MSR_PMM) | 4536 (1ull << MSR_RI) | 4537 (1ull << MSR_LE); 4538 pcc->mmu_model = POWERPC_MMU_32B; 4539 pcc->excp_model = POWERPC_EXCP_7x0; 4540 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4541 pcc->bfd_mach = bfd_mach_ppc_750; 4542 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4543 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4544 } 4545 4546 static void init_proc_750cl(CPUPPCState *env) 4547 { 4548 register_ne_601_sprs(env); 4549 register_sdr1_sprs(env); 4550 register_7xx_sprs(env); 4551 /* XXX : not implemented */ 4552 spr_register(env, SPR_L2CR, "L2CR", 4553 SPR_NOACCESS, SPR_NOACCESS, 4554 &spr_read_generic, spr_access_nop, 4555 0x00000000); 4556 /* Time base */ 4557 register_tbl(env); 4558 /* Thermal management */ 4559 /* Those registers are fake on 750CL */ 4560 spr_register(env, SPR_THRM1, "THRM1", 4561 SPR_NOACCESS, SPR_NOACCESS, 4562 &spr_read_generic, &spr_write_generic, 4563 0x00000000); 4564 spr_register(env, SPR_THRM2, "THRM2", 4565 SPR_NOACCESS, SPR_NOACCESS, 4566 &spr_read_generic, &spr_write_generic, 4567 0x00000000); 4568 spr_register(env, SPR_THRM3, "THRM3", 4569 SPR_NOACCESS, SPR_NOACCESS, 4570 &spr_read_generic, &spr_write_generic, 4571 0x00000000); 4572 /* XXX: not implemented */ 4573 spr_register(env, SPR_750_TDCL, "TDCL", 4574 SPR_NOACCESS, SPR_NOACCESS, 4575 &spr_read_generic, &spr_write_generic, 4576 0x00000000); 4577 spr_register(env, SPR_750_TDCH, "TDCH", 4578 SPR_NOACCESS, SPR_NOACCESS, 4579 &spr_read_generic, &spr_write_generic, 4580 0x00000000); 4581 /* DMA */ 4582 /* XXX : not implemented */ 4583 spr_register(env, SPR_750_WPAR, "WPAR", 4584 SPR_NOACCESS, SPR_NOACCESS, 4585 &spr_read_generic, &spr_write_generic, 4586 0x00000000); 4587 spr_register(env, SPR_750_DMAL, "DMAL", 4588 SPR_NOACCESS, SPR_NOACCESS, 4589 &spr_read_generic, &spr_write_generic, 4590 0x00000000); 4591 spr_register(env, SPR_750_DMAU, "DMAU", 4592 SPR_NOACCESS, SPR_NOACCESS, 4593 &spr_read_generic, &spr_write_generic, 4594 0x00000000); 4595 /* Hardware implementation registers */ 4596 /* XXX : not implemented */ 4597 spr_register(env, SPR_HID0, "HID0", 4598 SPR_NOACCESS, SPR_NOACCESS, 4599 &spr_read_generic, &spr_write_generic, 4600 0x00000000); 4601 /* XXX : not implemented */ 4602 spr_register(env, SPR_HID1, "HID1", 4603 SPR_NOACCESS, SPR_NOACCESS, 4604 &spr_read_generic, &spr_write_generic, 4605 0x00000000); 4606 /* XXX : not implemented */ 4607 spr_register(env, SPR_750CL_HID2, "HID2", 4608 SPR_NOACCESS, SPR_NOACCESS, 4609 &spr_read_generic, &spr_write_generic, 4610 0x00000000); 4611 /* XXX : not implemented */ 4612 spr_register(env, SPR_750CL_HID4, "HID4", 4613 SPR_NOACCESS, SPR_NOACCESS, 4614 &spr_read_generic, &spr_write_generic, 4615 0x00000000); 4616 /* Quantization registers */ 4617 /* XXX : not implemented */ 4618 spr_register(env, SPR_750_GQR0, "GQR0", 4619 SPR_NOACCESS, SPR_NOACCESS, 4620 &spr_read_generic, &spr_write_generic, 4621 0x00000000); 4622 /* XXX : not implemented */ 4623 spr_register(env, SPR_750_GQR1, "GQR1", 4624 SPR_NOACCESS, SPR_NOACCESS, 4625 &spr_read_generic, &spr_write_generic, 4626 0x00000000); 4627 /* XXX : not implemented */ 4628 spr_register(env, SPR_750_GQR2, "GQR2", 4629 SPR_NOACCESS, SPR_NOACCESS, 4630 &spr_read_generic, &spr_write_generic, 4631 0x00000000); 4632 /* XXX : not implemented */ 4633 spr_register(env, SPR_750_GQR3, "GQR3", 4634 SPR_NOACCESS, SPR_NOACCESS, 4635 &spr_read_generic, &spr_write_generic, 4636 0x00000000); 4637 /* XXX : not implemented */ 4638 spr_register(env, SPR_750_GQR4, "GQR4", 4639 SPR_NOACCESS, SPR_NOACCESS, 4640 &spr_read_generic, &spr_write_generic, 4641 0x00000000); 4642 /* XXX : not implemented */ 4643 spr_register(env, SPR_750_GQR5, "GQR5", 4644 SPR_NOACCESS, SPR_NOACCESS, 4645 &spr_read_generic, &spr_write_generic, 4646 0x00000000); 4647 /* XXX : not implemented */ 4648 spr_register(env, SPR_750_GQR6, "GQR6", 4649 SPR_NOACCESS, SPR_NOACCESS, 4650 &spr_read_generic, &spr_write_generic, 4651 0x00000000); 4652 /* XXX : not implemented */ 4653 spr_register(env, SPR_750_GQR7, "GQR7", 4654 SPR_NOACCESS, SPR_NOACCESS, 4655 &spr_read_generic, &spr_write_generic, 4656 0x00000000); 4657 /* Memory management */ 4658 register_low_BATs(env); 4659 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4660 register_high_BATs(env); 4661 init_excp_750cl(env); 4662 env->dcache_line_size = 32; 4663 env->icache_line_size = 32; 4664 /* Allocate hardware IRQ controller */ 4665 ppc6xx_irq_init(env_archcpu(env)); 4666 } 4667 4668 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4669 { 4670 DeviceClass *dc = DEVICE_CLASS(oc); 4671 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4672 4673 dc->desc = "PowerPC 750 CL"; 4674 pcc->init_proc = init_proc_750cl; 4675 pcc->check_pow = check_pow_hid0; 4676 /* 4677 * XXX: not implemented: 4678 * cache lock instructions: 4679 * dcbz_l 4680 * floating point paired instructions 4681 * psq_lux 4682 * psq_lx 4683 * psq_stux 4684 * psq_stx 4685 * ps_abs 4686 * ps_add 4687 * ps_cmpo0 4688 * ps_cmpo1 4689 * ps_cmpu0 4690 * ps_cmpu1 4691 * ps_div 4692 * ps_madd 4693 * ps_madds0 4694 * ps_madds1 4695 * ps_merge00 4696 * ps_merge01 4697 * ps_merge10 4698 * ps_merge11 4699 * ps_mr 4700 * ps_msub 4701 * ps_mul 4702 * ps_muls0 4703 * ps_muls1 4704 * ps_nabs 4705 * ps_neg 4706 * ps_nmadd 4707 * ps_nmsub 4708 * ps_res 4709 * ps_rsqrte 4710 * ps_sel 4711 * ps_sub 4712 * ps_sum0 4713 * ps_sum1 4714 */ 4715 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4716 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4717 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4718 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4719 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4720 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4721 PPC_SEGMENT | PPC_EXTERN; 4722 pcc->msr_mask = (1ull << MSR_POW) | 4723 (1ull << MSR_ILE) | 4724 (1ull << MSR_EE) | 4725 (1ull << MSR_PR) | 4726 (1ull << MSR_FP) | 4727 (1ull << MSR_ME) | 4728 (1ull << MSR_FE0) | 4729 (1ull << MSR_SE) | 4730 (1ull << MSR_DE) | 4731 (1ull << MSR_FE1) | 4732 (1ull << MSR_EP) | 4733 (1ull << MSR_IR) | 4734 (1ull << MSR_DR) | 4735 (1ull << MSR_PMM) | 4736 (1ull << MSR_RI) | 4737 (1ull << MSR_LE); 4738 pcc->mmu_model = POWERPC_MMU_32B; 4739 pcc->excp_model = POWERPC_EXCP_7x0; 4740 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4741 pcc->bfd_mach = bfd_mach_ppc_750; 4742 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4743 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4744 } 4745 4746 static void init_proc_750cx(CPUPPCState *env) 4747 { 4748 register_ne_601_sprs(env); 4749 register_sdr1_sprs(env); 4750 register_7xx_sprs(env); 4751 /* XXX : not implemented */ 4752 spr_register(env, SPR_L2CR, "L2CR", 4753 SPR_NOACCESS, SPR_NOACCESS, 4754 &spr_read_generic, spr_access_nop, 4755 0x00000000); 4756 /* Time base */ 4757 register_tbl(env); 4758 /* Thermal management */ 4759 register_thrm_sprs(env); 4760 /* This register is not implemented but is present for compatibility */ 4761 spr_register(env, SPR_SDA, "SDA", 4762 SPR_NOACCESS, SPR_NOACCESS, 4763 &spr_read_generic, &spr_write_generic, 4764 0x00000000); 4765 /* Hardware implementation registers */ 4766 /* XXX : not implemented */ 4767 spr_register(env, SPR_HID0, "HID0", 4768 SPR_NOACCESS, SPR_NOACCESS, 4769 &spr_read_generic, &spr_write_generic, 4770 0x00000000); 4771 /* XXX : not implemented */ 4772 spr_register(env, SPR_HID1, "HID1", 4773 SPR_NOACCESS, SPR_NOACCESS, 4774 &spr_read_generic, &spr_write_generic, 4775 0x00000000); 4776 /* Memory management */ 4777 register_low_BATs(env); 4778 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4779 register_high_BATs(env); 4780 init_excp_750cx(env); 4781 env->dcache_line_size = 32; 4782 env->icache_line_size = 32; 4783 /* Allocate hardware IRQ controller */ 4784 ppc6xx_irq_init(env_archcpu(env)); 4785 } 4786 4787 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4788 { 4789 DeviceClass *dc = DEVICE_CLASS(oc); 4790 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4791 4792 dc->desc = "PowerPC 750CX"; 4793 pcc->init_proc = init_proc_750cx; 4794 pcc->check_pow = check_pow_hid0; 4795 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4796 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4797 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4798 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4799 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4800 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4801 PPC_SEGMENT | PPC_EXTERN; 4802 pcc->msr_mask = (1ull << MSR_POW) | 4803 (1ull << MSR_ILE) | 4804 (1ull << MSR_EE) | 4805 (1ull << MSR_PR) | 4806 (1ull << MSR_FP) | 4807 (1ull << MSR_ME) | 4808 (1ull << MSR_FE0) | 4809 (1ull << MSR_SE) | 4810 (1ull << MSR_DE) | 4811 (1ull << MSR_FE1) | 4812 (1ull << MSR_EP) | 4813 (1ull << MSR_IR) | 4814 (1ull << MSR_DR) | 4815 (1ull << MSR_PMM) | 4816 (1ull << MSR_RI) | 4817 (1ull << MSR_LE); 4818 pcc->mmu_model = POWERPC_MMU_32B; 4819 pcc->excp_model = POWERPC_EXCP_7x0; 4820 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4821 pcc->bfd_mach = bfd_mach_ppc_750; 4822 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4823 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4824 } 4825 4826 static void init_proc_750fx(CPUPPCState *env) 4827 { 4828 register_ne_601_sprs(env); 4829 register_sdr1_sprs(env); 4830 register_7xx_sprs(env); 4831 /* XXX : not implemented */ 4832 spr_register(env, SPR_L2CR, "L2CR", 4833 SPR_NOACCESS, SPR_NOACCESS, 4834 &spr_read_generic, spr_access_nop, 4835 0x00000000); 4836 /* Time base */ 4837 register_tbl(env); 4838 /* Thermal management */ 4839 register_thrm_sprs(env); 4840 /* XXX : not implemented */ 4841 spr_register(env, SPR_750_THRM4, "THRM4", 4842 SPR_NOACCESS, SPR_NOACCESS, 4843 &spr_read_generic, &spr_write_generic, 4844 0x00000000); 4845 /* Hardware implementation registers */ 4846 /* XXX : not implemented */ 4847 spr_register(env, SPR_HID0, "HID0", 4848 SPR_NOACCESS, SPR_NOACCESS, 4849 &spr_read_generic, &spr_write_generic, 4850 0x00000000); 4851 /* XXX : not implemented */ 4852 spr_register(env, SPR_HID1, "HID1", 4853 SPR_NOACCESS, SPR_NOACCESS, 4854 &spr_read_generic, &spr_write_generic, 4855 0x00000000); 4856 /* XXX : not implemented */ 4857 spr_register(env, SPR_750FX_HID2, "HID2", 4858 SPR_NOACCESS, SPR_NOACCESS, 4859 &spr_read_generic, &spr_write_generic, 4860 0x00000000); 4861 /* Memory management */ 4862 register_low_BATs(env); 4863 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4864 register_high_BATs(env); 4865 init_excp_7x0(env); 4866 env->dcache_line_size = 32; 4867 env->icache_line_size = 32; 4868 /* Allocate hardware IRQ controller */ 4869 ppc6xx_irq_init(env_archcpu(env)); 4870 } 4871 4872 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4873 { 4874 DeviceClass *dc = DEVICE_CLASS(oc); 4875 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4876 4877 dc->desc = "PowerPC 750FX"; 4878 pcc->init_proc = init_proc_750fx; 4879 pcc->check_pow = check_pow_hid0; 4880 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4881 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4882 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4883 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4884 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4885 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4886 PPC_SEGMENT | PPC_EXTERN; 4887 pcc->msr_mask = (1ull << MSR_POW) | 4888 (1ull << MSR_ILE) | 4889 (1ull << MSR_EE) | 4890 (1ull << MSR_PR) | 4891 (1ull << MSR_FP) | 4892 (1ull << MSR_ME) | 4893 (1ull << MSR_FE0) | 4894 (1ull << MSR_SE) | 4895 (1ull << MSR_DE) | 4896 (1ull << MSR_FE1) | 4897 (1ull << MSR_EP) | 4898 (1ull << MSR_IR) | 4899 (1ull << MSR_DR) | 4900 (1ull << MSR_PMM) | 4901 (1ull << MSR_RI) | 4902 (1ull << MSR_LE); 4903 pcc->mmu_model = POWERPC_MMU_32B; 4904 pcc->excp_model = POWERPC_EXCP_7x0; 4905 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4906 pcc->bfd_mach = bfd_mach_ppc_750; 4907 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4908 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4909 } 4910 4911 static void init_proc_750gx(CPUPPCState *env) 4912 { 4913 register_ne_601_sprs(env); 4914 register_sdr1_sprs(env); 4915 register_7xx_sprs(env); 4916 /* XXX : not implemented (XXX: different from 750fx) */ 4917 spr_register(env, SPR_L2CR, "L2CR", 4918 SPR_NOACCESS, SPR_NOACCESS, 4919 &spr_read_generic, spr_access_nop, 4920 0x00000000); 4921 /* Time base */ 4922 register_tbl(env); 4923 /* Thermal management */ 4924 register_thrm_sprs(env); 4925 /* XXX : not implemented */ 4926 spr_register(env, SPR_750_THRM4, "THRM4", 4927 SPR_NOACCESS, SPR_NOACCESS, 4928 &spr_read_generic, &spr_write_generic, 4929 0x00000000); 4930 /* Hardware implementation registers */ 4931 /* XXX : not implemented (XXX: different from 750fx) */ 4932 spr_register(env, SPR_HID0, "HID0", 4933 SPR_NOACCESS, SPR_NOACCESS, 4934 &spr_read_generic, &spr_write_generic, 4935 0x00000000); 4936 /* XXX : not implemented */ 4937 spr_register(env, SPR_HID1, "HID1", 4938 SPR_NOACCESS, SPR_NOACCESS, 4939 &spr_read_generic, &spr_write_generic, 4940 0x00000000); 4941 /* XXX : not implemented (XXX: different from 750fx) */ 4942 spr_register(env, SPR_750FX_HID2, "HID2", 4943 SPR_NOACCESS, SPR_NOACCESS, 4944 &spr_read_generic, &spr_write_generic, 4945 0x00000000); 4946 /* Memory management */ 4947 register_low_BATs(env); 4948 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4949 register_high_BATs(env); 4950 init_excp_7x0(env); 4951 env->dcache_line_size = 32; 4952 env->icache_line_size = 32; 4953 /* Allocate hardware IRQ controller */ 4954 ppc6xx_irq_init(env_archcpu(env)); 4955 } 4956 4957 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4958 { 4959 DeviceClass *dc = DEVICE_CLASS(oc); 4960 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4961 4962 dc->desc = "PowerPC 750GX"; 4963 pcc->init_proc = init_proc_750gx; 4964 pcc->check_pow = check_pow_hid0; 4965 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4966 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4967 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4968 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4969 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4970 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4971 PPC_SEGMENT | PPC_EXTERN; 4972 pcc->msr_mask = (1ull << MSR_POW) | 4973 (1ull << MSR_ILE) | 4974 (1ull << MSR_EE) | 4975 (1ull << MSR_PR) | 4976 (1ull << MSR_FP) | 4977 (1ull << MSR_ME) | 4978 (1ull << MSR_FE0) | 4979 (1ull << MSR_SE) | 4980 (1ull << MSR_DE) | 4981 (1ull << MSR_FE1) | 4982 (1ull << MSR_EP) | 4983 (1ull << MSR_IR) | 4984 (1ull << MSR_DR) | 4985 (1ull << MSR_PMM) | 4986 (1ull << MSR_RI) | 4987 (1ull << MSR_LE); 4988 pcc->mmu_model = POWERPC_MMU_32B; 4989 pcc->excp_model = POWERPC_EXCP_7x0; 4990 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4991 pcc->bfd_mach = bfd_mach_ppc_750; 4992 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4993 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4994 } 4995 4996 static void init_proc_745(CPUPPCState *env) 4997 { 4998 register_ne_601_sprs(env); 4999 register_sdr1_sprs(env); 5000 register_7xx_sprs(env); 5001 register_G2_755_sprs(env); 5002 /* Time base */ 5003 register_tbl(env); 5004 /* Thermal management */ 5005 register_thrm_sprs(env); 5006 /* Hardware implementation registers */ 5007 /* XXX : not implemented */ 5008 spr_register(env, SPR_HID0, "HID0", 5009 SPR_NOACCESS, SPR_NOACCESS, 5010 &spr_read_generic, &spr_write_generic, 5011 0x00000000); 5012 /* XXX : not implemented */ 5013 spr_register(env, SPR_HID1, "HID1", 5014 SPR_NOACCESS, SPR_NOACCESS, 5015 &spr_read_generic, &spr_write_generic, 5016 0x00000000); 5017 /* XXX : not implemented */ 5018 spr_register(env, SPR_HID2, "HID2", 5019 SPR_NOACCESS, SPR_NOACCESS, 5020 &spr_read_generic, &spr_write_generic, 5021 0x00000000); 5022 /* Memory management */ 5023 register_low_BATs(env); 5024 register_high_BATs(env); 5025 register_6xx_7xx_soft_tlb(env, 64, 2); 5026 init_excp_7x5(env); 5027 env->dcache_line_size = 32; 5028 env->icache_line_size = 32; 5029 /* Allocate hardware IRQ controller */ 5030 ppc6xx_irq_init(env_archcpu(env)); 5031 } 5032 5033 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 5034 { 5035 DeviceClass *dc = DEVICE_CLASS(oc); 5036 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5037 5038 dc->desc = "PowerPC 745"; 5039 pcc->init_proc = init_proc_745; 5040 pcc->check_pow = check_pow_hid0; 5041 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5042 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5043 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5044 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5045 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5046 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 5047 PPC_SEGMENT | PPC_EXTERN; 5048 pcc->msr_mask = (1ull << MSR_POW) | 5049 (1ull << MSR_ILE) | 5050 (1ull << MSR_EE) | 5051 (1ull << MSR_PR) | 5052 (1ull << MSR_FP) | 5053 (1ull << MSR_ME) | 5054 (1ull << MSR_FE0) | 5055 (1ull << MSR_SE) | 5056 (1ull << MSR_DE) | 5057 (1ull << MSR_FE1) | 5058 (1ull << MSR_EP) | 5059 (1ull << MSR_IR) | 5060 (1ull << MSR_DR) | 5061 (1ull << MSR_PMM) | 5062 (1ull << MSR_RI) | 5063 (1ull << MSR_LE); 5064 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5065 pcc->excp_model = POWERPC_EXCP_7x5; 5066 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5067 pcc->bfd_mach = bfd_mach_ppc_750; 5068 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5069 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5070 } 5071 5072 static void init_proc_755(CPUPPCState *env) 5073 { 5074 register_ne_601_sprs(env); 5075 register_sdr1_sprs(env); 5076 register_7xx_sprs(env); 5077 register_G2_755_sprs(env); 5078 /* Time base */ 5079 register_tbl(env); 5080 /* L2 cache control */ 5081 /* XXX : not implemented */ 5082 spr_register(env, SPR_L2CR, "L2CR", 5083 SPR_NOACCESS, SPR_NOACCESS, 5084 &spr_read_generic, spr_access_nop, 5085 0x00000000); 5086 /* XXX : not implemented */ 5087 spr_register(env, SPR_L2PMCR, "L2PMCR", 5088 SPR_NOACCESS, SPR_NOACCESS, 5089 &spr_read_generic, &spr_write_generic, 5090 0x00000000); 5091 /* Thermal management */ 5092 register_thrm_sprs(env); 5093 /* Hardware implementation registers */ 5094 /* XXX : not implemented */ 5095 spr_register(env, SPR_HID0, "HID0", 5096 SPR_NOACCESS, SPR_NOACCESS, 5097 &spr_read_generic, &spr_write_generic, 5098 0x00000000); 5099 /* XXX : not implemented */ 5100 spr_register(env, SPR_HID1, "HID1", 5101 SPR_NOACCESS, SPR_NOACCESS, 5102 &spr_read_generic, &spr_write_generic, 5103 0x00000000); 5104 /* XXX : not implemented */ 5105 spr_register(env, SPR_HID2, "HID2", 5106 SPR_NOACCESS, SPR_NOACCESS, 5107 &spr_read_generic, &spr_write_generic, 5108 0x00000000); 5109 /* Memory management */ 5110 register_low_BATs(env); 5111 register_high_BATs(env); 5112 register_6xx_7xx_soft_tlb(env, 64, 2); 5113 init_excp_7x5(env); 5114 env->dcache_line_size = 32; 5115 env->icache_line_size = 32; 5116 /* Allocate hardware IRQ controller */ 5117 ppc6xx_irq_init(env_archcpu(env)); 5118 } 5119 5120 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 5121 { 5122 DeviceClass *dc = DEVICE_CLASS(oc); 5123 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5124 5125 dc->desc = "PowerPC 755"; 5126 pcc->init_proc = init_proc_755; 5127 pcc->check_pow = check_pow_hid0; 5128 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5129 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5130 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5131 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5132 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5133 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 5134 PPC_SEGMENT | PPC_EXTERN; 5135 pcc->msr_mask = (1ull << MSR_POW) | 5136 (1ull << MSR_ILE) | 5137 (1ull << MSR_EE) | 5138 (1ull << MSR_PR) | 5139 (1ull << MSR_FP) | 5140 (1ull << MSR_ME) | 5141 (1ull << MSR_FE0) | 5142 (1ull << MSR_SE) | 5143 (1ull << MSR_DE) | 5144 (1ull << MSR_FE1) | 5145 (1ull << MSR_EP) | 5146 (1ull << MSR_IR) | 5147 (1ull << MSR_DR) | 5148 (1ull << MSR_PMM) | 5149 (1ull << MSR_RI) | 5150 (1ull << MSR_LE); 5151 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5152 pcc->excp_model = POWERPC_EXCP_7x5; 5153 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5154 pcc->bfd_mach = bfd_mach_ppc_750; 5155 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5156 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5157 } 5158 5159 static void init_proc_7400(CPUPPCState *env) 5160 { 5161 register_ne_601_sprs(env); 5162 register_sdr1_sprs(env); 5163 register_7xx_sprs(env); 5164 /* Time base */ 5165 register_tbl(env); 5166 /* 74xx specific SPR */ 5167 register_74xx_sprs(env); 5168 vscr_init(env, 0x00010000); 5169 /* XXX : not implemented */ 5170 spr_register(env, SPR_UBAMR, "UBAMR", 5171 &spr_read_ureg, SPR_NOACCESS, 5172 &spr_read_ureg, SPR_NOACCESS, 5173 0x00000000); 5174 /* XXX: this seems not implemented on all revisions. */ 5175 /* XXX : not implemented */ 5176 spr_register(env, SPR_MSSCR1, "MSSCR1", 5177 SPR_NOACCESS, SPR_NOACCESS, 5178 &spr_read_generic, &spr_write_generic, 5179 0x00000000); 5180 /* Thermal management */ 5181 register_thrm_sprs(env); 5182 /* Memory management */ 5183 register_low_BATs(env); 5184 init_excp_7400(env); 5185 env->dcache_line_size = 32; 5186 env->icache_line_size = 32; 5187 /* Allocate hardware IRQ controller */ 5188 ppc6xx_irq_init(env_archcpu(env)); 5189 } 5190 5191 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 5192 { 5193 DeviceClass *dc = DEVICE_CLASS(oc); 5194 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5195 5196 dc->desc = "PowerPC 7400 (aka G4)"; 5197 pcc->init_proc = init_proc_7400; 5198 pcc->check_pow = check_pow_hid0; 5199 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5200 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5201 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5202 PPC_FLOAT_STFIWX | 5203 PPC_CACHE | PPC_CACHE_ICBI | 5204 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5205 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5206 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5207 PPC_MEM_TLBIA | 5208 PPC_SEGMENT | PPC_EXTERN | 5209 PPC_ALTIVEC; 5210 pcc->msr_mask = (1ull << MSR_VR) | 5211 (1ull << MSR_POW) | 5212 (1ull << MSR_ILE) | 5213 (1ull << MSR_EE) | 5214 (1ull << MSR_PR) | 5215 (1ull << MSR_FP) | 5216 (1ull << MSR_ME) | 5217 (1ull << MSR_FE0) | 5218 (1ull << MSR_SE) | 5219 (1ull << MSR_DE) | 5220 (1ull << MSR_FE1) | 5221 (1ull << MSR_EP) | 5222 (1ull << MSR_IR) | 5223 (1ull << MSR_DR) | 5224 (1ull << MSR_PMM) | 5225 (1ull << MSR_RI) | 5226 (1ull << MSR_LE); 5227 pcc->mmu_model = POWERPC_MMU_32B; 5228 pcc->excp_model = POWERPC_EXCP_74xx; 5229 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5230 pcc->bfd_mach = bfd_mach_ppc_7400; 5231 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5232 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5233 POWERPC_FLAG_BUS_CLK; 5234 } 5235 5236 static void init_proc_7410(CPUPPCState *env) 5237 { 5238 register_ne_601_sprs(env); 5239 register_sdr1_sprs(env); 5240 register_7xx_sprs(env); 5241 /* Time base */ 5242 register_tbl(env); 5243 /* 74xx specific SPR */ 5244 register_74xx_sprs(env); 5245 vscr_init(env, 0x00010000); 5246 /* XXX : not implemented */ 5247 spr_register(env, SPR_UBAMR, "UBAMR", 5248 &spr_read_ureg, SPR_NOACCESS, 5249 &spr_read_ureg, SPR_NOACCESS, 5250 0x00000000); 5251 /* Thermal management */ 5252 register_thrm_sprs(env); 5253 /* L2PMCR */ 5254 /* XXX : not implemented */ 5255 spr_register(env, SPR_L2PMCR, "L2PMCR", 5256 SPR_NOACCESS, SPR_NOACCESS, 5257 &spr_read_generic, &spr_write_generic, 5258 0x00000000); 5259 /* LDSTDB */ 5260 /* XXX : not implemented */ 5261 spr_register(env, SPR_LDSTDB, "LDSTDB", 5262 SPR_NOACCESS, SPR_NOACCESS, 5263 &spr_read_generic, &spr_write_generic, 5264 0x00000000); 5265 /* Memory management */ 5266 register_low_BATs(env); 5267 init_excp_7400(env); 5268 env->dcache_line_size = 32; 5269 env->icache_line_size = 32; 5270 /* Allocate hardware IRQ controller */ 5271 ppc6xx_irq_init(env_archcpu(env)); 5272 } 5273 5274 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 5275 { 5276 DeviceClass *dc = DEVICE_CLASS(oc); 5277 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5278 5279 dc->desc = "PowerPC 7410 (aka G4)"; 5280 pcc->init_proc = init_proc_7410; 5281 pcc->check_pow = check_pow_hid0; 5282 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5283 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5284 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5285 PPC_FLOAT_STFIWX | 5286 PPC_CACHE | PPC_CACHE_ICBI | 5287 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5288 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5289 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5290 PPC_MEM_TLBIA | 5291 PPC_SEGMENT | PPC_EXTERN | 5292 PPC_ALTIVEC; 5293 pcc->msr_mask = (1ull << MSR_VR) | 5294 (1ull << MSR_POW) | 5295 (1ull << MSR_ILE) | 5296 (1ull << MSR_EE) | 5297 (1ull << MSR_PR) | 5298 (1ull << MSR_FP) | 5299 (1ull << MSR_ME) | 5300 (1ull << MSR_FE0) | 5301 (1ull << MSR_SE) | 5302 (1ull << MSR_DE) | 5303 (1ull << MSR_FE1) | 5304 (1ull << MSR_EP) | 5305 (1ull << MSR_IR) | 5306 (1ull << MSR_DR) | 5307 (1ull << MSR_PMM) | 5308 (1ull << MSR_RI) | 5309 (1ull << MSR_LE); 5310 pcc->mmu_model = POWERPC_MMU_32B; 5311 pcc->excp_model = POWERPC_EXCP_74xx; 5312 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5313 pcc->bfd_mach = bfd_mach_ppc_7400; 5314 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5315 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5316 POWERPC_FLAG_BUS_CLK; 5317 } 5318 5319 static void init_proc_7440(CPUPPCState *env) 5320 { 5321 register_ne_601_sprs(env); 5322 register_sdr1_sprs(env); 5323 register_7xx_sprs(env); 5324 /* Time base */ 5325 register_tbl(env); 5326 /* 74xx specific SPR */ 5327 register_74xx_sprs(env); 5328 vscr_init(env, 0x00010000); 5329 /* XXX : not implemented */ 5330 spr_register(env, SPR_UBAMR, "UBAMR", 5331 &spr_read_ureg, SPR_NOACCESS, 5332 &spr_read_ureg, SPR_NOACCESS, 5333 0x00000000); 5334 /* LDSTCR */ 5335 /* XXX : not implemented */ 5336 spr_register(env, SPR_LDSTCR, "LDSTCR", 5337 SPR_NOACCESS, SPR_NOACCESS, 5338 &spr_read_generic, &spr_write_generic, 5339 0x00000000); 5340 /* ICTRL */ 5341 /* XXX : not implemented */ 5342 spr_register(env, SPR_ICTRL, "ICTRL", 5343 SPR_NOACCESS, SPR_NOACCESS, 5344 &spr_read_generic, &spr_write_generic, 5345 0x00000000); 5346 /* MSSSR0 */ 5347 /* XXX : not implemented */ 5348 spr_register(env, SPR_MSSSR0, "MSSSR0", 5349 SPR_NOACCESS, SPR_NOACCESS, 5350 &spr_read_generic, &spr_write_generic, 5351 0x00000000); 5352 /* PMC */ 5353 /* XXX : not implemented */ 5354 spr_register(env, SPR_7XX_PMC5, "PMC5", 5355 SPR_NOACCESS, SPR_NOACCESS, 5356 &spr_read_generic, &spr_write_generic, 5357 0x00000000); 5358 /* XXX : not implemented */ 5359 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5360 &spr_read_ureg, SPR_NOACCESS, 5361 &spr_read_ureg, SPR_NOACCESS, 5362 0x00000000); 5363 /* XXX : not implemented */ 5364 spr_register(env, SPR_7XX_PMC6, "PMC6", 5365 SPR_NOACCESS, SPR_NOACCESS, 5366 &spr_read_generic, &spr_write_generic, 5367 0x00000000); 5368 /* XXX : not implemented */ 5369 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5370 &spr_read_ureg, SPR_NOACCESS, 5371 &spr_read_ureg, SPR_NOACCESS, 5372 0x00000000); 5373 /* Memory management */ 5374 register_low_BATs(env); 5375 init_excp_7450(env); 5376 env->dcache_line_size = 32; 5377 env->icache_line_size = 32; 5378 /* Allocate hardware IRQ controller */ 5379 ppc6xx_irq_init(env_archcpu(env)); 5380 } 5381 5382 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 5383 { 5384 DeviceClass *dc = DEVICE_CLASS(oc); 5385 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5386 5387 dc->desc = "PowerPC 7440 (aka G4)"; 5388 pcc->init_proc = init_proc_7440; 5389 pcc->check_pow = check_pow_hid0_74xx; 5390 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5391 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5392 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5393 PPC_FLOAT_STFIWX | 5394 PPC_CACHE | PPC_CACHE_ICBI | 5395 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5396 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5397 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5398 PPC_MEM_TLBIA | 5399 PPC_SEGMENT | PPC_EXTERN | 5400 PPC_ALTIVEC; 5401 pcc->msr_mask = (1ull << MSR_VR) | 5402 (1ull << MSR_POW) | 5403 (1ull << MSR_ILE) | 5404 (1ull << MSR_EE) | 5405 (1ull << MSR_PR) | 5406 (1ull << MSR_FP) | 5407 (1ull << MSR_ME) | 5408 (1ull << MSR_FE0) | 5409 (1ull << MSR_SE) | 5410 (1ull << MSR_DE) | 5411 (1ull << MSR_FE1) | 5412 (1ull << MSR_EP) | 5413 (1ull << MSR_IR) | 5414 (1ull << MSR_DR) | 5415 (1ull << MSR_PMM) | 5416 (1ull << MSR_RI) | 5417 (1ull << MSR_LE); 5418 pcc->mmu_model = POWERPC_MMU_32B; 5419 pcc->excp_model = POWERPC_EXCP_74xx; 5420 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5421 pcc->bfd_mach = bfd_mach_ppc_7400; 5422 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5423 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5424 POWERPC_FLAG_BUS_CLK; 5425 } 5426 5427 static void init_proc_7450(CPUPPCState *env) 5428 { 5429 register_ne_601_sprs(env); 5430 register_sdr1_sprs(env); 5431 register_7xx_sprs(env); 5432 /* Time base */ 5433 register_tbl(env); 5434 /* 74xx specific SPR */ 5435 register_74xx_sprs(env); 5436 vscr_init(env, 0x00010000); 5437 /* Level 3 cache control */ 5438 register_l3_ctrl(env); 5439 /* L3ITCR1 */ 5440 /* XXX : not implemented */ 5441 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5442 SPR_NOACCESS, SPR_NOACCESS, 5443 &spr_read_generic, &spr_write_generic, 5444 0x00000000); 5445 /* L3ITCR2 */ 5446 /* XXX : not implemented */ 5447 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5448 SPR_NOACCESS, SPR_NOACCESS, 5449 &spr_read_generic, &spr_write_generic, 5450 0x00000000); 5451 /* L3ITCR3 */ 5452 /* XXX : not implemented */ 5453 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5454 SPR_NOACCESS, SPR_NOACCESS, 5455 &spr_read_generic, &spr_write_generic, 5456 0x00000000); 5457 /* L3OHCR */ 5458 /* XXX : not implemented */ 5459 spr_register(env, SPR_L3OHCR, "L3OHCR", 5460 SPR_NOACCESS, SPR_NOACCESS, 5461 &spr_read_generic, &spr_write_generic, 5462 0x00000000); 5463 /* XXX : not implemented */ 5464 spr_register(env, SPR_UBAMR, "UBAMR", 5465 &spr_read_ureg, SPR_NOACCESS, 5466 &spr_read_ureg, SPR_NOACCESS, 5467 0x00000000); 5468 /* LDSTCR */ 5469 /* XXX : not implemented */ 5470 spr_register(env, SPR_LDSTCR, "LDSTCR", 5471 SPR_NOACCESS, SPR_NOACCESS, 5472 &spr_read_generic, &spr_write_generic, 5473 0x00000000); 5474 /* ICTRL */ 5475 /* XXX : not implemented */ 5476 spr_register(env, SPR_ICTRL, "ICTRL", 5477 SPR_NOACCESS, SPR_NOACCESS, 5478 &spr_read_generic, &spr_write_generic, 5479 0x00000000); 5480 /* MSSSR0 */ 5481 /* XXX : not implemented */ 5482 spr_register(env, SPR_MSSSR0, "MSSSR0", 5483 SPR_NOACCESS, SPR_NOACCESS, 5484 &spr_read_generic, &spr_write_generic, 5485 0x00000000); 5486 /* PMC */ 5487 /* XXX : not implemented */ 5488 spr_register(env, SPR_7XX_PMC5, "PMC5", 5489 SPR_NOACCESS, SPR_NOACCESS, 5490 &spr_read_generic, &spr_write_generic, 5491 0x00000000); 5492 /* XXX : not implemented */ 5493 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5494 &spr_read_ureg, SPR_NOACCESS, 5495 &spr_read_ureg, SPR_NOACCESS, 5496 0x00000000); 5497 /* XXX : not implemented */ 5498 spr_register(env, SPR_7XX_PMC6, "PMC6", 5499 SPR_NOACCESS, SPR_NOACCESS, 5500 &spr_read_generic, &spr_write_generic, 5501 0x00000000); 5502 /* XXX : not implemented */ 5503 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5504 &spr_read_ureg, SPR_NOACCESS, 5505 &spr_read_ureg, SPR_NOACCESS, 5506 0x00000000); 5507 /* Memory management */ 5508 register_low_BATs(env); 5509 init_excp_7450(env); 5510 env->dcache_line_size = 32; 5511 env->icache_line_size = 32; 5512 /* Allocate hardware IRQ controller */ 5513 ppc6xx_irq_init(env_archcpu(env)); 5514 } 5515 5516 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 5517 { 5518 DeviceClass *dc = DEVICE_CLASS(oc); 5519 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5520 5521 dc->desc = "PowerPC 7450 (aka G4)"; 5522 pcc->init_proc = init_proc_7450; 5523 pcc->check_pow = check_pow_hid0_74xx; 5524 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5525 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5526 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5527 PPC_FLOAT_STFIWX | 5528 PPC_CACHE | PPC_CACHE_ICBI | 5529 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5530 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5531 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5532 PPC_MEM_TLBIA | 5533 PPC_SEGMENT | PPC_EXTERN | 5534 PPC_ALTIVEC; 5535 pcc->msr_mask = (1ull << MSR_VR) | 5536 (1ull << MSR_POW) | 5537 (1ull << MSR_ILE) | 5538 (1ull << MSR_EE) | 5539 (1ull << MSR_PR) | 5540 (1ull << MSR_FP) | 5541 (1ull << MSR_ME) | 5542 (1ull << MSR_FE0) | 5543 (1ull << MSR_SE) | 5544 (1ull << MSR_DE) | 5545 (1ull << MSR_FE1) | 5546 (1ull << MSR_EP) | 5547 (1ull << MSR_IR) | 5548 (1ull << MSR_DR) | 5549 (1ull << MSR_PMM) | 5550 (1ull << MSR_RI) | 5551 (1ull << MSR_LE); 5552 pcc->mmu_model = POWERPC_MMU_32B; 5553 pcc->excp_model = POWERPC_EXCP_74xx; 5554 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5555 pcc->bfd_mach = bfd_mach_ppc_7400; 5556 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5557 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5558 POWERPC_FLAG_BUS_CLK; 5559 } 5560 5561 static void init_proc_7445(CPUPPCState *env) 5562 { 5563 register_ne_601_sprs(env); 5564 register_sdr1_sprs(env); 5565 register_7xx_sprs(env); 5566 /* Time base */ 5567 register_tbl(env); 5568 /* 74xx specific SPR */ 5569 register_74xx_sprs(env); 5570 vscr_init(env, 0x00010000); 5571 /* LDSTCR */ 5572 /* XXX : not implemented */ 5573 spr_register(env, SPR_LDSTCR, "LDSTCR", 5574 SPR_NOACCESS, SPR_NOACCESS, 5575 &spr_read_generic, &spr_write_generic, 5576 0x00000000); 5577 /* ICTRL */ 5578 /* XXX : not implemented */ 5579 spr_register(env, SPR_ICTRL, "ICTRL", 5580 SPR_NOACCESS, SPR_NOACCESS, 5581 &spr_read_generic, &spr_write_generic, 5582 0x00000000); 5583 /* MSSSR0 */ 5584 /* XXX : not implemented */ 5585 spr_register(env, SPR_MSSSR0, "MSSSR0", 5586 SPR_NOACCESS, SPR_NOACCESS, 5587 &spr_read_generic, &spr_write_generic, 5588 0x00000000); 5589 /* PMC */ 5590 /* XXX : not implemented */ 5591 spr_register(env, SPR_7XX_PMC5, "PMC5", 5592 SPR_NOACCESS, SPR_NOACCESS, 5593 &spr_read_generic, &spr_write_generic, 5594 0x00000000); 5595 /* XXX : not implemented */ 5596 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5597 &spr_read_ureg, SPR_NOACCESS, 5598 &spr_read_ureg, SPR_NOACCESS, 5599 0x00000000); 5600 /* XXX : not implemented */ 5601 spr_register(env, SPR_7XX_PMC6, "PMC6", 5602 SPR_NOACCESS, SPR_NOACCESS, 5603 &spr_read_generic, &spr_write_generic, 5604 0x00000000); 5605 /* XXX : not implemented */ 5606 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5607 &spr_read_ureg, SPR_NOACCESS, 5608 &spr_read_ureg, SPR_NOACCESS, 5609 0x00000000); 5610 /* SPRGs */ 5611 spr_register(env, SPR_SPRG4, "SPRG4", 5612 SPR_NOACCESS, SPR_NOACCESS, 5613 &spr_read_generic, &spr_write_generic, 5614 0x00000000); 5615 spr_register(env, SPR_USPRG4, "USPRG4", 5616 &spr_read_ureg, SPR_NOACCESS, 5617 &spr_read_ureg, SPR_NOACCESS, 5618 0x00000000); 5619 spr_register(env, SPR_SPRG5, "SPRG5", 5620 SPR_NOACCESS, SPR_NOACCESS, 5621 &spr_read_generic, &spr_write_generic, 5622 0x00000000); 5623 spr_register(env, SPR_USPRG5, "USPRG5", 5624 &spr_read_ureg, SPR_NOACCESS, 5625 &spr_read_ureg, SPR_NOACCESS, 5626 0x00000000); 5627 spr_register(env, SPR_SPRG6, "SPRG6", 5628 SPR_NOACCESS, SPR_NOACCESS, 5629 &spr_read_generic, &spr_write_generic, 5630 0x00000000); 5631 spr_register(env, SPR_USPRG6, "USPRG6", 5632 &spr_read_ureg, SPR_NOACCESS, 5633 &spr_read_ureg, SPR_NOACCESS, 5634 0x00000000); 5635 spr_register(env, SPR_SPRG7, "SPRG7", 5636 SPR_NOACCESS, SPR_NOACCESS, 5637 &spr_read_generic, &spr_write_generic, 5638 0x00000000); 5639 spr_register(env, SPR_USPRG7, "USPRG7", 5640 &spr_read_ureg, SPR_NOACCESS, 5641 &spr_read_ureg, SPR_NOACCESS, 5642 0x00000000); 5643 /* Memory management */ 5644 register_low_BATs(env); 5645 register_high_BATs(env); 5646 init_excp_7450(env); 5647 env->dcache_line_size = 32; 5648 env->icache_line_size = 32; 5649 /* Allocate hardware IRQ controller */ 5650 ppc6xx_irq_init(env_archcpu(env)); 5651 } 5652 5653 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 5654 { 5655 DeviceClass *dc = DEVICE_CLASS(oc); 5656 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5657 5658 dc->desc = "PowerPC 7445 (aka G4)"; 5659 pcc->init_proc = init_proc_7445; 5660 pcc->check_pow = check_pow_hid0_74xx; 5661 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5662 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5663 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5664 PPC_FLOAT_STFIWX | 5665 PPC_CACHE | PPC_CACHE_ICBI | 5666 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5667 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5668 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5669 PPC_MEM_TLBIA | 5670 PPC_SEGMENT | PPC_EXTERN | 5671 PPC_ALTIVEC; 5672 pcc->msr_mask = (1ull << MSR_VR) | 5673 (1ull << MSR_POW) | 5674 (1ull << MSR_ILE) | 5675 (1ull << MSR_EE) | 5676 (1ull << MSR_PR) | 5677 (1ull << MSR_FP) | 5678 (1ull << MSR_ME) | 5679 (1ull << MSR_FE0) | 5680 (1ull << MSR_SE) | 5681 (1ull << MSR_DE) | 5682 (1ull << MSR_FE1) | 5683 (1ull << MSR_EP) | 5684 (1ull << MSR_IR) | 5685 (1ull << MSR_DR) | 5686 (1ull << MSR_PMM) | 5687 (1ull << MSR_RI) | 5688 (1ull << MSR_LE); 5689 pcc->mmu_model = POWERPC_MMU_32B; 5690 pcc->excp_model = POWERPC_EXCP_74xx; 5691 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5692 pcc->bfd_mach = bfd_mach_ppc_7400; 5693 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5694 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5695 POWERPC_FLAG_BUS_CLK; 5696 } 5697 5698 static void init_proc_7455(CPUPPCState *env) 5699 { 5700 register_ne_601_sprs(env); 5701 register_sdr1_sprs(env); 5702 register_7xx_sprs(env); 5703 /* Time base */ 5704 register_tbl(env); 5705 /* 74xx specific SPR */ 5706 register_74xx_sprs(env); 5707 vscr_init(env, 0x00010000); 5708 /* Level 3 cache control */ 5709 register_l3_ctrl(env); 5710 /* LDSTCR */ 5711 /* XXX : not implemented */ 5712 spr_register(env, SPR_LDSTCR, "LDSTCR", 5713 SPR_NOACCESS, SPR_NOACCESS, 5714 &spr_read_generic, &spr_write_generic, 5715 0x00000000); 5716 /* ICTRL */ 5717 /* XXX : not implemented */ 5718 spr_register(env, SPR_ICTRL, "ICTRL", 5719 SPR_NOACCESS, SPR_NOACCESS, 5720 &spr_read_generic, &spr_write_generic, 5721 0x00000000); 5722 /* MSSSR0 */ 5723 /* XXX : not implemented */ 5724 spr_register(env, SPR_MSSSR0, "MSSSR0", 5725 SPR_NOACCESS, SPR_NOACCESS, 5726 &spr_read_generic, &spr_write_generic, 5727 0x00000000); 5728 /* PMC */ 5729 /* XXX : not implemented */ 5730 spr_register(env, SPR_7XX_PMC5, "PMC5", 5731 SPR_NOACCESS, SPR_NOACCESS, 5732 &spr_read_generic, &spr_write_generic, 5733 0x00000000); 5734 /* XXX : not implemented */ 5735 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5736 &spr_read_ureg, SPR_NOACCESS, 5737 &spr_read_ureg, SPR_NOACCESS, 5738 0x00000000); 5739 /* XXX : not implemented */ 5740 spr_register(env, SPR_7XX_PMC6, "PMC6", 5741 SPR_NOACCESS, SPR_NOACCESS, 5742 &spr_read_generic, &spr_write_generic, 5743 0x00000000); 5744 /* XXX : not implemented */ 5745 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5746 &spr_read_ureg, SPR_NOACCESS, 5747 &spr_read_ureg, SPR_NOACCESS, 5748 0x00000000); 5749 /* SPRGs */ 5750 spr_register(env, SPR_SPRG4, "SPRG4", 5751 SPR_NOACCESS, SPR_NOACCESS, 5752 &spr_read_generic, &spr_write_generic, 5753 0x00000000); 5754 spr_register(env, SPR_USPRG4, "USPRG4", 5755 &spr_read_ureg, SPR_NOACCESS, 5756 &spr_read_ureg, SPR_NOACCESS, 5757 0x00000000); 5758 spr_register(env, SPR_SPRG5, "SPRG5", 5759 SPR_NOACCESS, SPR_NOACCESS, 5760 &spr_read_generic, &spr_write_generic, 5761 0x00000000); 5762 spr_register(env, SPR_USPRG5, "USPRG5", 5763 &spr_read_ureg, SPR_NOACCESS, 5764 &spr_read_ureg, SPR_NOACCESS, 5765 0x00000000); 5766 spr_register(env, SPR_SPRG6, "SPRG6", 5767 SPR_NOACCESS, SPR_NOACCESS, 5768 &spr_read_generic, &spr_write_generic, 5769 0x00000000); 5770 spr_register(env, SPR_USPRG6, "USPRG6", 5771 &spr_read_ureg, SPR_NOACCESS, 5772 &spr_read_ureg, SPR_NOACCESS, 5773 0x00000000); 5774 spr_register(env, SPR_SPRG7, "SPRG7", 5775 SPR_NOACCESS, SPR_NOACCESS, 5776 &spr_read_generic, &spr_write_generic, 5777 0x00000000); 5778 spr_register(env, SPR_USPRG7, "USPRG7", 5779 &spr_read_ureg, SPR_NOACCESS, 5780 &spr_read_ureg, SPR_NOACCESS, 5781 0x00000000); 5782 /* Memory management */ 5783 register_low_BATs(env); 5784 register_high_BATs(env); 5785 init_excp_7450(env); 5786 env->dcache_line_size = 32; 5787 env->icache_line_size = 32; 5788 /* Allocate hardware IRQ controller */ 5789 ppc6xx_irq_init(env_archcpu(env)); 5790 } 5791 5792 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5793 { 5794 DeviceClass *dc = DEVICE_CLASS(oc); 5795 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5796 5797 dc->desc = "PowerPC 7455 (aka G4)"; 5798 pcc->init_proc = init_proc_7455; 5799 pcc->check_pow = check_pow_hid0_74xx; 5800 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5801 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5802 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5803 PPC_FLOAT_STFIWX | 5804 PPC_CACHE | PPC_CACHE_ICBI | 5805 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5806 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5807 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5808 PPC_MEM_TLBIA | 5809 PPC_SEGMENT | PPC_EXTERN | 5810 PPC_ALTIVEC; 5811 pcc->msr_mask = (1ull << MSR_VR) | 5812 (1ull << MSR_POW) | 5813 (1ull << MSR_ILE) | 5814 (1ull << MSR_EE) | 5815 (1ull << MSR_PR) | 5816 (1ull << MSR_FP) | 5817 (1ull << MSR_ME) | 5818 (1ull << MSR_FE0) | 5819 (1ull << MSR_SE) | 5820 (1ull << MSR_DE) | 5821 (1ull << MSR_FE1) | 5822 (1ull << MSR_EP) | 5823 (1ull << MSR_IR) | 5824 (1ull << MSR_DR) | 5825 (1ull << MSR_PMM) | 5826 (1ull << MSR_RI) | 5827 (1ull << MSR_LE); 5828 pcc->mmu_model = POWERPC_MMU_32B; 5829 pcc->excp_model = POWERPC_EXCP_74xx; 5830 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5831 pcc->bfd_mach = bfd_mach_ppc_7400; 5832 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5833 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5834 POWERPC_FLAG_BUS_CLK; 5835 } 5836 5837 static void init_proc_7457(CPUPPCState *env) 5838 { 5839 register_ne_601_sprs(env); 5840 register_sdr1_sprs(env); 5841 register_7xx_sprs(env); 5842 /* Time base */ 5843 register_tbl(env); 5844 /* 74xx specific SPR */ 5845 register_74xx_sprs(env); 5846 vscr_init(env, 0x00010000); 5847 /* Level 3 cache control */ 5848 register_l3_ctrl(env); 5849 /* L3ITCR1 */ 5850 /* XXX : not implemented */ 5851 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5852 SPR_NOACCESS, SPR_NOACCESS, 5853 &spr_read_generic, &spr_write_generic, 5854 0x00000000); 5855 /* L3ITCR2 */ 5856 /* XXX : not implemented */ 5857 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5858 SPR_NOACCESS, SPR_NOACCESS, 5859 &spr_read_generic, &spr_write_generic, 5860 0x00000000); 5861 /* L3ITCR3 */ 5862 /* XXX : not implemented */ 5863 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5864 SPR_NOACCESS, SPR_NOACCESS, 5865 &spr_read_generic, &spr_write_generic, 5866 0x00000000); 5867 /* L3OHCR */ 5868 /* XXX : not implemented */ 5869 spr_register(env, SPR_L3OHCR, "L3OHCR", 5870 SPR_NOACCESS, SPR_NOACCESS, 5871 &spr_read_generic, &spr_write_generic, 5872 0x00000000); 5873 /* LDSTCR */ 5874 /* XXX : not implemented */ 5875 spr_register(env, SPR_LDSTCR, "LDSTCR", 5876 SPR_NOACCESS, SPR_NOACCESS, 5877 &spr_read_generic, &spr_write_generic, 5878 0x00000000); 5879 /* ICTRL */ 5880 /* XXX : not implemented */ 5881 spr_register(env, SPR_ICTRL, "ICTRL", 5882 SPR_NOACCESS, SPR_NOACCESS, 5883 &spr_read_generic, &spr_write_generic, 5884 0x00000000); 5885 /* MSSSR0 */ 5886 /* XXX : not implemented */ 5887 spr_register(env, SPR_MSSSR0, "MSSSR0", 5888 SPR_NOACCESS, SPR_NOACCESS, 5889 &spr_read_generic, &spr_write_generic, 5890 0x00000000); 5891 /* PMC */ 5892 /* XXX : not implemented */ 5893 spr_register(env, SPR_7XX_PMC5, "PMC5", 5894 SPR_NOACCESS, SPR_NOACCESS, 5895 &spr_read_generic, &spr_write_generic, 5896 0x00000000); 5897 /* XXX : not implemented */ 5898 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5899 &spr_read_ureg, SPR_NOACCESS, 5900 &spr_read_ureg, SPR_NOACCESS, 5901 0x00000000); 5902 /* XXX : not implemented */ 5903 spr_register(env, SPR_7XX_PMC6, "PMC6", 5904 SPR_NOACCESS, SPR_NOACCESS, 5905 &spr_read_generic, &spr_write_generic, 5906 0x00000000); 5907 /* XXX : not implemented */ 5908 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5909 &spr_read_ureg, SPR_NOACCESS, 5910 &spr_read_ureg, SPR_NOACCESS, 5911 0x00000000); 5912 /* SPRGs */ 5913 spr_register(env, SPR_SPRG4, "SPRG4", 5914 SPR_NOACCESS, SPR_NOACCESS, 5915 &spr_read_generic, &spr_write_generic, 5916 0x00000000); 5917 spr_register(env, SPR_USPRG4, "USPRG4", 5918 &spr_read_ureg, SPR_NOACCESS, 5919 &spr_read_ureg, SPR_NOACCESS, 5920 0x00000000); 5921 spr_register(env, SPR_SPRG5, "SPRG5", 5922 SPR_NOACCESS, SPR_NOACCESS, 5923 &spr_read_generic, &spr_write_generic, 5924 0x00000000); 5925 spr_register(env, SPR_USPRG5, "USPRG5", 5926 &spr_read_ureg, SPR_NOACCESS, 5927 &spr_read_ureg, SPR_NOACCESS, 5928 0x00000000); 5929 spr_register(env, SPR_SPRG6, "SPRG6", 5930 SPR_NOACCESS, SPR_NOACCESS, 5931 &spr_read_generic, &spr_write_generic, 5932 0x00000000); 5933 spr_register(env, SPR_USPRG6, "USPRG6", 5934 &spr_read_ureg, SPR_NOACCESS, 5935 &spr_read_ureg, SPR_NOACCESS, 5936 0x00000000); 5937 spr_register(env, SPR_SPRG7, "SPRG7", 5938 SPR_NOACCESS, SPR_NOACCESS, 5939 &spr_read_generic, &spr_write_generic, 5940 0x00000000); 5941 spr_register(env, SPR_USPRG7, "USPRG7", 5942 &spr_read_ureg, SPR_NOACCESS, 5943 &spr_read_ureg, SPR_NOACCESS, 5944 0x00000000); 5945 /* Memory management */ 5946 register_low_BATs(env); 5947 register_high_BATs(env); 5948 init_excp_7450(env); 5949 env->dcache_line_size = 32; 5950 env->icache_line_size = 32; 5951 /* Allocate hardware IRQ controller */ 5952 ppc6xx_irq_init(env_archcpu(env)); 5953 } 5954 5955 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5956 { 5957 DeviceClass *dc = DEVICE_CLASS(oc); 5958 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5959 5960 dc->desc = "PowerPC 7457 (aka G4)"; 5961 pcc->init_proc = init_proc_7457; 5962 pcc->check_pow = check_pow_hid0_74xx; 5963 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5964 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5965 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5966 PPC_FLOAT_STFIWX | 5967 PPC_CACHE | PPC_CACHE_ICBI | 5968 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5969 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5970 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5971 PPC_MEM_TLBIA | 5972 PPC_SEGMENT | PPC_EXTERN | 5973 PPC_ALTIVEC; 5974 pcc->msr_mask = (1ull << MSR_VR) | 5975 (1ull << MSR_POW) | 5976 (1ull << MSR_ILE) | 5977 (1ull << MSR_EE) | 5978 (1ull << MSR_PR) | 5979 (1ull << MSR_FP) | 5980 (1ull << MSR_ME) | 5981 (1ull << MSR_FE0) | 5982 (1ull << MSR_SE) | 5983 (1ull << MSR_DE) | 5984 (1ull << MSR_FE1) | 5985 (1ull << MSR_EP) | 5986 (1ull << MSR_IR) | 5987 (1ull << MSR_DR) | 5988 (1ull << MSR_PMM) | 5989 (1ull << MSR_RI) | 5990 (1ull << MSR_LE); 5991 pcc->mmu_model = POWERPC_MMU_32B; 5992 pcc->excp_model = POWERPC_EXCP_74xx; 5993 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5994 pcc->bfd_mach = bfd_mach_ppc_7400; 5995 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5996 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5997 POWERPC_FLAG_BUS_CLK; 5998 } 5999 6000 static void init_proc_e600(CPUPPCState *env) 6001 { 6002 register_ne_601_sprs(env); 6003 register_sdr1_sprs(env); 6004 register_7xx_sprs(env); 6005 /* Time base */ 6006 register_tbl(env); 6007 /* 74xx specific SPR */ 6008 register_74xx_sprs(env); 6009 vscr_init(env, 0x00010000); 6010 /* XXX : not implemented */ 6011 spr_register(env, SPR_UBAMR, "UBAMR", 6012 &spr_read_ureg, SPR_NOACCESS, 6013 &spr_read_ureg, SPR_NOACCESS, 6014 0x00000000); 6015 /* XXX : not implemented */ 6016 spr_register(env, SPR_LDSTCR, "LDSTCR", 6017 SPR_NOACCESS, SPR_NOACCESS, 6018 &spr_read_generic, &spr_write_generic, 6019 0x00000000); 6020 /* XXX : not implemented */ 6021 spr_register(env, SPR_ICTRL, "ICTRL", 6022 SPR_NOACCESS, SPR_NOACCESS, 6023 &spr_read_generic, &spr_write_generic, 6024 0x00000000); 6025 /* XXX : not implemented */ 6026 spr_register(env, SPR_MSSSR0, "MSSSR0", 6027 SPR_NOACCESS, SPR_NOACCESS, 6028 &spr_read_generic, &spr_write_generic, 6029 0x00000000); 6030 /* XXX : not implemented */ 6031 spr_register(env, SPR_7XX_PMC5, "PMC5", 6032 SPR_NOACCESS, SPR_NOACCESS, 6033 &spr_read_generic, &spr_write_generic, 6034 0x00000000); 6035 /* XXX : not implemented */ 6036 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6037 &spr_read_ureg, SPR_NOACCESS, 6038 &spr_read_ureg, SPR_NOACCESS, 6039 0x00000000); 6040 /* XXX : not implemented */ 6041 spr_register(env, SPR_7XX_PMC6, "PMC6", 6042 SPR_NOACCESS, SPR_NOACCESS, 6043 &spr_read_generic, &spr_write_generic, 6044 0x00000000); 6045 /* XXX : not implemented */ 6046 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6047 &spr_read_ureg, SPR_NOACCESS, 6048 &spr_read_ureg, SPR_NOACCESS, 6049 0x00000000); 6050 /* SPRGs */ 6051 spr_register(env, SPR_SPRG4, "SPRG4", 6052 SPR_NOACCESS, SPR_NOACCESS, 6053 &spr_read_generic, &spr_write_generic, 6054 0x00000000); 6055 spr_register(env, SPR_USPRG4, "USPRG4", 6056 &spr_read_ureg, SPR_NOACCESS, 6057 &spr_read_ureg, SPR_NOACCESS, 6058 0x00000000); 6059 spr_register(env, SPR_SPRG5, "SPRG5", 6060 SPR_NOACCESS, SPR_NOACCESS, 6061 &spr_read_generic, &spr_write_generic, 6062 0x00000000); 6063 spr_register(env, SPR_USPRG5, "USPRG5", 6064 &spr_read_ureg, SPR_NOACCESS, 6065 &spr_read_ureg, SPR_NOACCESS, 6066 0x00000000); 6067 spr_register(env, SPR_SPRG6, "SPRG6", 6068 SPR_NOACCESS, SPR_NOACCESS, 6069 &spr_read_generic, &spr_write_generic, 6070 0x00000000); 6071 spr_register(env, SPR_USPRG6, "USPRG6", 6072 &spr_read_ureg, SPR_NOACCESS, 6073 &spr_read_ureg, SPR_NOACCESS, 6074 0x00000000); 6075 spr_register(env, SPR_SPRG7, "SPRG7", 6076 SPR_NOACCESS, SPR_NOACCESS, 6077 &spr_read_generic, &spr_write_generic, 6078 0x00000000); 6079 spr_register(env, SPR_USPRG7, "USPRG7", 6080 &spr_read_ureg, SPR_NOACCESS, 6081 &spr_read_ureg, SPR_NOACCESS, 6082 0x00000000); 6083 /* Memory management */ 6084 register_low_BATs(env); 6085 register_high_BATs(env); 6086 init_excp_7450(env); 6087 env->dcache_line_size = 32; 6088 env->icache_line_size = 32; 6089 /* Allocate hardware IRQ controller */ 6090 ppc6xx_irq_init(env_archcpu(env)); 6091 } 6092 6093 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 6094 { 6095 DeviceClass *dc = DEVICE_CLASS(oc); 6096 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6097 6098 dc->desc = "PowerPC e600"; 6099 pcc->init_proc = init_proc_e600; 6100 pcc->check_pow = check_pow_hid0_74xx; 6101 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6102 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6103 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6104 PPC_FLOAT_STFIWX | 6105 PPC_CACHE | PPC_CACHE_ICBI | 6106 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6107 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6108 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6109 PPC_MEM_TLBIA | 6110 PPC_SEGMENT | PPC_EXTERN | 6111 PPC_ALTIVEC; 6112 pcc->insns_flags2 = PPC_NONE; 6113 pcc->msr_mask = (1ull << MSR_VR) | 6114 (1ull << MSR_POW) | 6115 (1ull << MSR_ILE) | 6116 (1ull << MSR_EE) | 6117 (1ull << MSR_PR) | 6118 (1ull << MSR_FP) | 6119 (1ull << MSR_ME) | 6120 (1ull << MSR_FE0) | 6121 (1ull << MSR_SE) | 6122 (1ull << MSR_DE) | 6123 (1ull << MSR_FE1) | 6124 (1ull << MSR_EP) | 6125 (1ull << MSR_IR) | 6126 (1ull << MSR_DR) | 6127 (1ull << MSR_PMM) | 6128 (1ull << MSR_RI) | 6129 (1ull << MSR_LE); 6130 pcc->mmu_model = POWERPC_MMU_32B; 6131 pcc->excp_model = POWERPC_EXCP_74xx; 6132 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6133 pcc->bfd_mach = bfd_mach_ppc_7400; 6134 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6135 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6136 POWERPC_FLAG_BUS_CLK; 6137 } 6138 6139 #if defined(TARGET_PPC64) 6140 #if defined(CONFIG_USER_ONLY) 6141 #define POWERPC970_HID5_INIT 0x00000080 6142 #else 6143 #define POWERPC970_HID5_INIT 0x00000000 6144 #endif 6145 6146 static int check_pow_970(CPUPPCState *env) 6147 { 6148 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 6149 return 1; 6150 } 6151 6152 return 0; 6153 } 6154 6155 static void register_970_hid_sprs(CPUPPCState *env) 6156 { 6157 /* Hardware implementation registers */ 6158 /* XXX : not implemented */ 6159 spr_register(env, SPR_HID0, "HID0", 6160 SPR_NOACCESS, SPR_NOACCESS, 6161 &spr_read_generic, &spr_write_clear, 6162 0x60000000); 6163 spr_register(env, SPR_HID1, "HID1", 6164 SPR_NOACCESS, SPR_NOACCESS, 6165 &spr_read_generic, &spr_write_generic, 6166 0x00000000); 6167 spr_register(env, SPR_970_HID5, "HID5", 6168 SPR_NOACCESS, SPR_NOACCESS, 6169 &spr_read_generic, &spr_write_generic, 6170 POWERPC970_HID5_INIT); 6171 } 6172 6173 static void register_970_hior_sprs(CPUPPCState *env) 6174 { 6175 spr_register(env, SPR_HIOR, "SPR_HIOR", 6176 SPR_NOACCESS, SPR_NOACCESS, 6177 &spr_read_hior, &spr_write_hior, 6178 0x00000000); 6179 } 6180 6181 static void register_book3s_ctrl_sprs(CPUPPCState *env) 6182 { 6183 spr_register(env, SPR_CTRL, "SPR_CTRL", 6184 SPR_NOACCESS, SPR_NOACCESS, 6185 SPR_NOACCESS, &spr_write_CTRL, 6186 0x00000000); 6187 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 6188 &spr_read_ureg, SPR_NOACCESS, 6189 &spr_read_ureg, SPR_NOACCESS, 6190 0x00000000); 6191 } 6192 6193 static void register_book3s_altivec_sprs(CPUPPCState *env) 6194 { 6195 if (!(env->insns_flags & PPC_ALTIVEC)) { 6196 return; 6197 } 6198 6199 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 6200 &spr_read_generic, &spr_write_generic, 6201 &spr_read_generic, &spr_write_generic, 6202 KVM_REG_PPC_VRSAVE, 0x00000000); 6203 6204 } 6205 6206 static void register_book3s_dbg_sprs(CPUPPCState *env) 6207 { 6208 /* 6209 * TODO: different specs define different scopes for these, 6210 * will have to address this: 6211 * 970: super/write and super/read 6212 * powerisa 2.03..2.04: hypv/write and super/read. 6213 * powerisa 2.05 and newer: hypv/write and hypv/read. 6214 */ 6215 spr_register_kvm(env, SPR_DABR, "DABR", 6216 SPR_NOACCESS, SPR_NOACCESS, 6217 &spr_read_generic, &spr_write_generic, 6218 KVM_REG_PPC_DABR, 0x00000000); 6219 spr_register_kvm(env, SPR_DABRX, "DABRX", 6220 SPR_NOACCESS, SPR_NOACCESS, 6221 &spr_read_generic, &spr_write_generic, 6222 KVM_REG_PPC_DABRX, 0x00000000); 6223 } 6224 6225 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 6226 { 6227 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 6228 SPR_NOACCESS, SPR_NOACCESS, 6229 SPR_NOACCESS, SPR_NOACCESS, 6230 &spr_read_generic, &spr_write_generic, 6231 KVM_REG_PPC_DAWR, 0x00000000); 6232 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 6233 SPR_NOACCESS, SPR_NOACCESS, 6234 SPR_NOACCESS, SPR_NOACCESS, 6235 &spr_read_generic, &spr_write_generic, 6236 KVM_REG_PPC_DAWRX, 0x00000000); 6237 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 6238 SPR_NOACCESS, SPR_NOACCESS, 6239 SPR_NOACCESS, SPR_NOACCESS, 6240 &spr_read_generic, &spr_write_generic, 6241 KVM_REG_PPC_CIABR, 0x00000000); 6242 } 6243 6244 static void register_970_dbg_sprs(CPUPPCState *env) 6245 { 6246 /* Breakpoints */ 6247 spr_register(env, SPR_IABR, "IABR", 6248 SPR_NOACCESS, SPR_NOACCESS, 6249 &spr_read_generic, &spr_write_generic, 6250 0x00000000); 6251 } 6252 6253 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 6254 { 6255 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 6256 SPR_NOACCESS, SPR_NOACCESS, 6257 &spr_read_generic, &spr_write_MMCR0, 6258 KVM_REG_PPC_MMCR0, 0x80000000); 6259 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 6260 SPR_NOACCESS, SPR_NOACCESS, 6261 &spr_read_generic, &spr_write_MMCR1, 6262 KVM_REG_PPC_MMCR1, 0x00000000); 6263 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 6264 SPR_NOACCESS, SPR_NOACCESS, 6265 &spr_read_generic, &spr_write_generic, 6266 KVM_REG_PPC_MMCRA, 0x00000000); 6267 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 6268 SPR_NOACCESS, SPR_NOACCESS, 6269 &spr_read_PMC, &spr_write_PMC, 6270 KVM_REG_PPC_PMC1, 0x00000000); 6271 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 6272 SPR_NOACCESS, SPR_NOACCESS, 6273 &spr_read_PMC, &spr_write_PMC, 6274 KVM_REG_PPC_PMC2, 0x00000000); 6275 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 6276 SPR_NOACCESS, SPR_NOACCESS, 6277 &spr_read_PMC, &spr_write_PMC, 6278 KVM_REG_PPC_PMC3, 0x00000000); 6279 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 6280 SPR_NOACCESS, SPR_NOACCESS, 6281 &spr_read_PMC, &spr_write_PMC, 6282 KVM_REG_PPC_PMC4, 0x00000000); 6283 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 6284 SPR_NOACCESS, SPR_NOACCESS, 6285 &spr_read_PMC, &spr_write_PMC, 6286 KVM_REG_PPC_PMC5, 0x00000000); 6287 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 6288 SPR_NOACCESS, SPR_NOACCESS, 6289 &spr_read_PMC, &spr_write_PMC, 6290 KVM_REG_PPC_PMC6, 0x00000000); 6291 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 6292 SPR_NOACCESS, SPR_NOACCESS, 6293 &spr_read_generic, &spr_write_generic, 6294 KVM_REG_PPC_SIAR, 0x00000000); 6295 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 6296 SPR_NOACCESS, SPR_NOACCESS, 6297 &spr_read_generic, &spr_write_generic, 6298 KVM_REG_PPC_SDAR, 0x00000000); 6299 } 6300 6301 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 6302 { 6303 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 6304 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 6305 &spr_read_ureg, &spr_write_ureg, 6306 0x80000000); 6307 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 6308 &spr_read_ureg, SPR_NOACCESS, 6309 &spr_read_ureg, &spr_write_ureg, 6310 0x00000000); 6311 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 6312 &spr_read_ureg, SPR_NOACCESS, 6313 &spr_read_ureg, &spr_write_ureg, 6314 0x00000000); 6315 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 6316 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6317 &spr_read_ureg, &spr_write_ureg, 6318 0x00000000); 6319 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 6320 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6321 &spr_read_ureg, &spr_write_ureg, 6322 0x00000000); 6323 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 6324 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6325 &spr_read_ureg, &spr_write_ureg, 6326 0x00000000); 6327 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 6328 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6329 &spr_read_ureg, &spr_write_ureg, 6330 0x00000000); 6331 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 6332 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 6333 &spr_read_ureg, &spr_write_ureg, 6334 0x00000000); 6335 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 6336 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 6337 &spr_read_ureg, &spr_write_ureg, 6338 0x00000000); 6339 spr_register(env, SPR_POWER_USIAR, "USIAR", 6340 &spr_read_ureg, SPR_NOACCESS, 6341 &spr_read_ureg, &spr_write_ureg, 6342 0x00000000); 6343 spr_register(env, SPR_POWER_USDAR, "USDAR", 6344 &spr_read_ureg, SPR_NOACCESS, 6345 &spr_read_ureg, &spr_write_ureg, 6346 0x00000000); 6347 } 6348 6349 static void register_970_pmu_sup_sprs(CPUPPCState *env) 6350 { 6351 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 6352 SPR_NOACCESS, SPR_NOACCESS, 6353 &spr_read_generic, &spr_write_generic, 6354 KVM_REG_PPC_PMC7, 0x00000000); 6355 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 6356 SPR_NOACCESS, SPR_NOACCESS, 6357 &spr_read_generic, &spr_write_generic, 6358 KVM_REG_PPC_PMC8, 0x00000000); 6359 } 6360 6361 static void register_970_pmu_user_sprs(CPUPPCState *env) 6362 { 6363 spr_register(env, SPR_970_UPMC7, "UPMC7", 6364 &spr_read_ureg, SPR_NOACCESS, 6365 &spr_read_ureg, &spr_write_ureg, 6366 0x00000000); 6367 spr_register(env, SPR_970_UPMC8, "UPMC8", 6368 &spr_read_ureg, SPR_NOACCESS, 6369 &spr_read_ureg, &spr_write_ureg, 6370 0x00000000); 6371 } 6372 6373 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 6374 { 6375 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 6376 SPR_NOACCESS, SPR_NOACCESS, 6377 &spr_read_generic, &spr_write_generic, 6378 KVM_REG_PPC_MMCR2, 0x00000000); 6379 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 6380 SPR_NOACCESS, SPR_NOACCESS, 6381 &spr_read_generic, &spr_write_generic, 6382 KVM_REG_PPC_MMCRS, 0x00000000); 6383 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 6384 SPR_NOACCESS, SPR_NOACCESS, 6385 &spr_read_generic, &spr_write_generic, 6386 KVM_REG_PPC_SIER, 0x00000000); 6387 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 6388 SPR_NOACCESS, SPR_NOACCESS, 6389 &spr_read_generic, &spr_write_generic, 6390 KVM_REG_PPC_SPMC1, 0x00000000); 6391 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 6392 SPR_NOACCESS, SPR_NOACCESS, 6393 &spr_read_generic, &spr_write_generic, 6394 KVM_REG_PPC_SPMC2, 0x00000000); 6395 spr_register_kvm(env, SPR_TACR, "TACR", 6396 SPR_NOACCESS, SPR_NOACCESS, 6397 &spr_read_generic, &spr_write_generic, 6398 KVM_REG_PPC_TACR, 0x00000000); 6399 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 6400 SPR_NOACCESS, SPR_NOACCESS, 6401 &spr_read_generic, &spr_write_generic, 6402 KVM_REG_PPC_TCSCR, 0x00000000); 6403 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 6404 SPR_NOACCESS, SPR_NOACCESS, 6405 &spr_read_generic, &spr_write_generic, 6406 KVM_REG_PPC_CSIGR, 0x00000000); 6407 } 6408 6409 static void register_power8_pmu_user_sprs(CPUPPCState *env) 6410 { 6411 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 6412 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 6413 &spr_read_ureg, &spr_write_ureg, 6414 0x00000000); 6415 spr_register(env, SPR_POWER_USIER, "USIER", 6416 &spr_read_generic, SPR_NOACCESS, 6417 &spr_read_generic, &spr_write_generic, 6418 0x00000000); 6419 } 6420 6421 static void register_power5p_ear_sprs(CPUPPCState *env) 6422 { 6423 /* External access control */ 6424 spr_register(env, SPR_EAR, "EAR", 6425 SPR_NOACCESS, SPR_NOACCESS, 6426 &spr_read_generic, &spr_write_generic, 6427 0x00000000); 6428 } 6429 6430 static void register_power5p_tb_sprs(CPUPPCState *env) 6431 { 6432 /* TBU40 (High 40 bits of the Timebase register */ 6433 spr_register_hv(env, SPR_TBU40, "TBU40", 6434 SPR_NOACCESS, SPR_NOACCESS, 6435 SPR_NOACCESS, SPR_NOACCESS, 6436 SPR_NOACCESS, &spr_write_tbu40, 6437 0x00000000); 6438 } 6439 6440 static void register_970_lpar_sprs(CPUPPCState *env) 6441 { 6442 #if !defined(CONFIG_USER_ONLY) 6443 /* 6444 * PPC970: HID4 covers things later controlled by the LPCR and 6445 * RMOR in later CPUs, but with a different encoding. We only 6446 * support the 970 in "Apple mode" which has all hypervisor 6447 * facilities disabled by strapping, so we can basically just 6448 * ignore it 6449 */ 6450 spr_register(env, SPR_970_HID4, "HID4", 6451 SPR_NOACCESS, SPR_NOACCESS, 6452 &spr_read_generic, &spr_write_generic, 6453 0x00000000); 6454 #endif 6455 } 6456 6457 static void register_power5p_lpar_sprs(CPUPPCState *env) 6458 { 6459 #if !defined(CONFIG_USER_ONLY) 6460 /* Logical partitionning */ 6461 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 6462 SPR_NOACCESS, SPR_NOACCESS, 6463 SPR_NOACCESS, SPR_NOACCESS, 6464 &spr_read_generic, &spr_write_lpcr, 6465 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 6466 spr_register_hv(env, SPR_HDEC, "HDEC", 6467 SPR_NOACCESS, SPR_NOACCESS, 6468 SPR_NOACCESS, SPR_NOACCESS, 6469 &spr_read_hdecr, &spr_write_hdecr, 0); 6470 #endif 6471 } 6472 6473 static void register_book3s_ids_sprs(CPUPPCState *env) 6474 { 6475 /* FIXME: Will need to deal with thread vs core only SPRs */ 6476 6477 /* Processor identification */ 6478 spr_register_hv(env, SPR_PIR, "PIR", 6479 SPR_NOACCESS, SPR_NOACCESS, 6480 &spr_read_generic, SPR_NOACCESS, 6481 &spr_read_generic, NULL, 6482 0x00000000); 6483 spr_register_hv(env, SPR_HID0, "HID0", 6484 SPR_NOACCESS, SPR_NOACCESS, 6485 SPR_NOACCESS, SPR_NOACCESS, 6486 &spr_read_generic, &spr_write_generic, 6487 0x00000000); 6488 spr_register_hv(env, SPR_TSCR, "TSCR", 6489 SPR_NOACCESS, SPR_NOACCESS, 6490 SPR_NOACCESS, SPR_NOACCESS, 6491 &spr_read_generic, &spr_write_generic, 6492 0x00000000); 6493 spr_register_hv(env, SPR_HMER, "HMER", 6494 SPR_NOACCESS, SPR_NOACCESS, 6495 SPR_NOACCESS, SPR_NOACCESS, 6496 &spr_read_generic, &spr_write_hmer, 6497 0x00000000); 6498 spr_register_hv(env, SPR_HMEER, "HMEER", 6499 SPR_NOACCESS, SPR_NOACCESS, 6500 SPR_NOACCESS, SPR_NOACCESS, 6501 &spr_read_generic, &spr_write_generic, 6502 0x00000000); 6503 spr_register_hv(env, SPR_TFMR, "TFMR", 6504 SPR_NOACCESS, SPR_NOACCESS, 6505 SPR_NOACCESS, SPR_NOACCESS, 6506 &spr_read_generic, &spr_write_generic, 6507 0x00000000); 6508 spr_register_hv(env, SPR_LPIDR, "LPIDR", 6509 SPR_NOACCESS, SPR_NOACCESS, 6510 SPR_NOACCESS, SPR_NOACCESS, 6511 &spr_read_generic, &spr_write_lpidr, 6512 0x00000000); 6513 spr_register_hv(env, SPR_HFSCR, "HFSCR", 6514 SPR_NOACCESS, SPR_NOACCESS, 6515 SPR_NOACCESS, SPR_NOACCESS, 6516 &spr_read_generic, &spr_write_generic, 6517 0x00000000); 6518 spr_register_hv(env, SPR_MMCRC, "MMCRC", 6519 SPR_NOACCESS, SPR_NOACCESS, 6520 SPR_NOACCESS, SPR_NOACCESS, 6521 &spr_read_generic, &spr_write_generic, 6522 0x00000000); 6523 spr_register_hv(env, SPR_MMCRH, "MMCRH", 6524 SPR_NOACCESS, SPR_NOACCESS, 6525 SPR_NOACCESS, SPR_NOACCESS, 6526 &spr_read_generic, &spr_write_generic, 6527 0x00000000); 6528 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 6529 SPR_NOACCESS, SPR_NOACCESS, 6530 SPR_NOACCESS, SPR_NOACCESS, 6531 &spr_read_generic, &spr_write_generic, 6532 0x00000000); 6533 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 6534 SPR_NOACCESS, SPR_NOACCESS, 6535 SPR_NOACCESS, SPR_NOACCESS, 6536 &spr_read_generic, &spr_write_generic, 6537 0x00000000); 6538 spr_register_hv(env, SPR_HSRR0, "HSRR0", 6539 SPR_NOACCESS, SPR_NOACCESS, 6540 SPR_NOACCESS, SPR_NOACCESS, 6541 &spr_read_generic, &spr_write_generic, 6542 0x00000000); 6543 spr_register_hv(env, SPR_HSRR1, "HSRR1", 6544 SPR_NOACCESS, SPR_NOACCESS, 6545 SPR_NOACCESS, SPR_NOACCESS, 6546 &spr_read_generic, &spr_write_generic, 6547 0x00000000); 6548 spr_register_hv(env, SPR_HDAR, "HDAR", 6549 SPR_NOACCESS, SPR_NOACCESS, 6550 SPR_NOACCESS, SPR_NOACCESS, 6551 &spr_read_generic, &spr_write_generic, 6552 0x00000000); 6553 spr_register_hv(env, SPR_HDSISR, "HDSISR", 6554 SPR_NOACCESS, SPR_NOACCESS, 6555 SPR_NOACCESS, SPR_NOACCESS, 6556 &spr_read_generic, &spr_write_generic, 6557 0x00000000); 6558 spr_register_hv(env, SPR_HRMOR, "HRMOR", 6559 SPR_NOACCESS, SPR_NOACCESS, 6560 SPR_NOACCESS, SPR_NOACCESS, 6561 &spr_read_generic, &spr_write_generic, 6562 0x00000000); 6563 } 6564 6565 static void register_rmor_sprs(CPUPPCState *env) 6566 { 6567 spr_register_hv(env, SPR_RMOR, "RMOR", 6568 SPR_NOACCESS, SPR_NOACCESS, 6569 SPR_NOACCESS, SPR_NOACCESS, 6570 &spr_read_generic, &spr_write_generic, 6571 0x00000000); 6572 } 6573 6574 static void register_power8_ids_sprs(CPUPPCState *env) 6575 { 6576 /* Thread identification */ 6577 spr_register(env, SPR_TIR, "TIR", 6578 SPR_NOACCESS, SPR_NOACCESS, 6579 &spr_read_generic, SPR_NOACCESS, 6580 0x00000000); 6581 } 6582 6583 static void register_book3s_purr_sprs(CPUPPCState *env) 6584 { 6585 #if !defined(CONFIG_USER_ONLY) 6586 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 6587 spr_register_kvm_hv(env, SPR_PURR, "PURR", 6588 &spr_read_purr, SPR_NOACCESS, 6589 &spr_read_purr, SPR_NOACCESS, 6590 &spr_read_purr, &spr_write_purr, 6591 KVM_REG_PPC_PURR, 0x00000000); 6592 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 6593 &spr_read_purr, SPR_NOACCESS, 6594 &spr_read_purr, SPR_NOACCESS, 6595 &spr_read_purr, &spr_write_purr, 6596 KVM_REG_PPC_SPURR, 0x00000000); 6597 #endif 6598 } 6599 6600 static void register_power6_dbg_sprs(CPUPPCState *env) 6601 { 6602 #if !defined(CONFIG_USER_ONLY) 6603 spr_register(env, SPR_CFAR, "SPR_CFAR", 6604 SPR_NOACCESS, SPR_NOACCESS, 6605 &spr_read_cfar, &spr_write_cfar, 6606 0x00000000); 6607 #endif 6608 } 6609 6610 static void register_power5p_common_sprs(CPUPPCState *env) 6611 { 6612 spr_register_kvm(env, SPR_PPR, "PPR", 6613 &spr_read_generic, &spr_write_generic, 6614 &spr_read_generic, &spr_write_generic, 6615 KVM_REG_PPC_PPR, 0x00000000); 6616 } 6617 6618 static void register_power6_common_sprs(CPUPPCState *env) 6619 { 6620 #if !defined(CONFIG_USER_ONLY) 6621 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 6622 SPR_NOACCESS, SPR_NOACCESS, 6623 &spr_read_generic, &spr_write_generic, 6624 KVM_REG_PPC_DSCR, 0x00000000); 6625 #endif 6626 /* 6627 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 6628 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 6629 */ 6630 spr_register_hv(env, SPR_PCR, "PCR", 6631 SPR_NOACCESS, SPR_NOACCESS, 6632 SPR_NOACCESS, SPR_NOACCESS, 6633 &spr_read_generic, &spr_write_pcr, 6634 0x00000000); 6635 } 6636 6637 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 6638 { 6639 spr_register_kvm(env, SPR_TAR, "TAR", 6640 &spr_read_tar, &spr_write_tar, 6641 &spr_read_generic, &spr_write_generic, 6642 KVM_REG_PPC_TAR, 0x00000000); 6643 } 6644 6645 static void register_power8_tm_sprs(CPUPPCState *env) 6646 { 6647 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 6648 &spr_read_tm, &spr_write_tm, 6649 &spr_read_tm, &spr_write_tm, 6650 KVM_REG_PPC_TFHAR, 0x00000000); 6651 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 6652 &spr_read_tm, &spr_write_tm, 6653 &spr_read_tm, &spr_write_tm, 6654 KVM_REG_PPC_TFIAR, 0x00000000); 6655 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 6656 &spr_read_tm, &spr_write_tm, 6657 &spr_read_tm, &spr_write_tm, 6658 KVM_REG_PPC_TEXASR, 0x00000000); 6659 spr_register(env, SPR_TEXASRU, "TEXASRU", 6660 &spr_read_tm_upper32, &spr_write_tm_upper32, 6661 &spr_read_tm_upper32, &spr_write_tm_upper32, 6662 0x00000000); 6663 } 6664 6665 static void register_power8_ebb_sprs(CPUPPCState *env) 6666 { 6667 spr_register(env, SPR_BESCRS, "BESCRS", 6668 &spr_read_ebb, &spr_write_ebb, 6669 &spr_read_generic, &spr_write_generic, 6670 0x00000000); 6671 spr_register(env, SPR_BESCRSU, "BESCRSU", 6672 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6673 &spr_read_prev_upper32, &spr_write_prev_upper32, 6674 0x00000000); 6675 spr_register(env, SPR_BESCRR, "BESCRR", 6676 &spr_read_ebb, &spr_write_ebb, 6677 &spr_read_generic, &spr_write_generic, 6678 0x00000000); 6679 spr_register(env, SPR_BESCRRU, "BESCRRU", 6680 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6681 &spr_read_prev_upper32, &spr_write_prev_upper32, 6682 0x00000000); 6683 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 6684 &spr_read_ebb, &spr_write_ebb, 6685 &spr_read_generic, &spr_write_generic, 6686 KVM_REG_PPC_EBBHR, 0x00000000); 6687 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 6688 &spr_read_ebb, &spr_write_ebb, 6689 &spr_read_generic, &spr_write_generic, 6690 KVM_REG_PPC_EBBRR, 0x00000000); 6691 spr_register_kvm(env, SPR_BESCR, "BESCR", 6692 &spr_read_ebb, &spr_write_ebb, 6693 &spr_read_generic, &spr_write_generic, 6694 KVM_REG_PPC_BESCR, 0x00000000); 6695 } 6696 6697 /* Virtual Time Base */ 6698 static void register_vtb_sprs(CPUPPCState *env) 6699 { 6700 spr_register_kvm_hv(env, SPR_VTB, "VTB", 6701 SPR_NOACCESS, SPR_NOACCESS, 6702 &spr_read_vtb, SPR_NOACCESS, 6703 &spr_read_vtb, &spr_write_vtb, 6704 KVM_REG_PPC_VTB, 0x00000000); 6705 } 6706 6707 static void register_power8_fscr_sprs(CPUPPCState *env) 6708 { 6709 #if defined(CONFIG_USER_ONLY) 6710 target_ulong initval = 1ULL << FSCR_TAR; 6711 #else 6712 target_ulong initval = 0; 6713 #endif 6714 spr_register_kvm(env, SPR_FSCR, "FSCR", 6715 SPR_NOACCESS, SPR_NOACCESS, 6716 &spr_read_generic, &spr_write_generic, 6717 KVM_REG_PPC_FSCR, initval); 6718 } 6719 6720 static void register_power8_pspb_sprs(CPUPPCState *env) 6721 { 6722 spr_register_kvm(env, SPR_PSPB, "PSPB", 6723 SPR_NOACCESS, SPR_NOACCESS, 6724 &spr_read_generic, &spr_write_generic32, 6725 KVM_REG_PPC_PSPB, 0); 6726 } 6727 6728 static void register_power8_dpdes_sprs(CPUPPCState *env) 6729 { 6730 #if !defined(CONFIG_USER_ONLY) 6731 /* Directed Privileged Door-bell Exception State, used for IPI */ 6732 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6733 SPR_NOACCESS, SPR_NOACCESS, 6734 &spr_read_dpdes, SPR_NOACCESS, 6735 &spr_read_dpdes, &spr_write_dpdes, 6736 KVM_REG_PPC_DPDES, 0x00000000); 6737 #endif 6738 } 6739 6740 static void register_power8_ic_sprs(CPUPPCState *env) 6741 { 6742 #if !defined(CONFIG_USER_ONLY) 6743 spr_register_hv(env, SPR_IC, "IC", 6744 SPR_NOACCESS, SPR_NOACCESS, 6745 &spr_read_generic, SPR_NOACCESS, 6746 &spr_read_generic, &spr_write_generic, 6747 0); 6748 #endif 6749 } 6750 6751 static void register_power8_book4_sprs(CPUPPCState *env) 6752 { 6753 /* Add a number of P8 book4 registers */ 6754 #if !defined(CONFIG_USER_ONLY) 6755 spr_register_kvm(env, SPR_ACOP, "ACOP", 6756 SPR_NOACCESS, SPR_NOACCESS, 6757 &spr_read_generic, &spr_write_generic, 6758 KVM_REG_PPC_ACOP, 0); 6759 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6760 SPR_NOACCESS, SPR_NOACCESS, 6761 &spr_read_generic, &spr_write_pidr, 6762 KVM_REG_PPC_PID, 0); 6763 spr_register_kvm(env, SPR_WORT, "WORT", 6764 SPR_NOACCESS, SPR_NOACCESS, 6765 &spr_read_generic, &spr_write_generic, 6766 KVM_REG_PPC_WORT, 0); 6767 #endif 6768 } 6769 6770 static void register_power7_book4_sprs(CPUPPCState *env) 6771 { 6772 /* Add a number of P7 book4 registers */ 6773 #if !defined(CONFIG_USER_ONLY) 6774 spr_register_kvm(env, SPR_ACOP, "ACOP", 6775 SPR_NOACCESS, SPR_NOACCESS, 6776 &spr_read_generic, &spr_write_generic, 6777 KVM_REG_PPC_ACOP, 0); 6778 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6779 SPR_NOACCESS, SPR_NOACCESS, 6780 &spr_read_generic, &spr_write_generic, 6781 KVM_REG_PPC_PID, 0); 6782 #endif 6783 } 6784 6785 static void register_power8_rpr_sprs(CPUPPCState *env) 6786 { 6787 #if !defined(CONFIG_USER_ONLY) 6788 spr_register_hv(env, SPR_RPR, "RPR", 6789 SPR_NOACCESS, SPR_NOACCESS, 6790 SPR_NOACCESS, SPR_NOACCESS, 6791 &spr_read_generic, &spr_write_generic, 6792 0x00000103070F1F3F); 6793 #endif 6794 } 6795 6796 static void register_power9_mmu_sprs(CPUPPCState *env) 6797 { 6798 #if !defined(CONFIG_USER_ONLY) 6799 /* Partition Table Control */ 6800 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6801 SPR_NOACCESS, SPR_NOACCESS, 6802 SPR_NOACCESS, SPR_NOACCESS, 6803 &spr_read_generic, &spr_write_ptcr, 6804 KVM_REG_PPC_PTCR, 0x00000000); 6805 /* Address Segment Descriptor Register */ 6806 spr_register_hv(env, SPR_ASDR, "ASDR", 6807 SPR_NOACCESS, SPR_NOACCESS, 6808 SPR_NOACCESS, SPR_NOACCESS, 6809 &spr_read_generic, &spr_write_generic, 6810 0x0000000000000000); 6811 #endif 6812 } 6813 6814 /* 6815 * Initialize PMU counter overflow timers for Power8 and 6816 * newer Power chips when using TCG. 6817 */ 6818 static void init_tcg_pmu_power8(CPUPPCState *env) 6819 { 6820 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6821 /* Init PMU overflow timers */ 6822 if (!kvm_enabled()) { 6823 cpu_ppc_pmu_init(env); 6824 } 6825 #endif 6826 } 6827 6828 static void init_proc_book3s_common(CPUPPCState *env) 6829 { 6830 register_ne_601_sprs(env); 6831 register_tbl(env); 6832 register_usprg3_sprs(env); 6833 register_book3s_altivec_sprs(env); 6834 register_book3s_pmu_sup_sprs(env); 6835 register_book3s_pmu_user_sprs(env); 6836 register_book3s_ctrl_sprs(env); 6837 /* 6838 * Can't find information on what this should be on reset. This 6839 * value is the one used by 74xx processors. 6840 */ 6841 vscr_init(env, 0x00010000); 6842 } 6843 6844 static void init_proc_970(CPUPPCState *env) 6845 { 6846 /* Common Registers */ 6847 init_proc_book3s_common(env); 6848 register_sdr1_sprs(env); 6849 register_book3s_dbg_sprs(env); 6850 6851 /* 970 Specific Registers */ 6852 register_970_hid_sprs(env); 6853 register_970_hior_sprs(env); 6854 register_low_BATs(env); 6855 register_970_pmu_sup_sprs(env); 6856 register_970_pmu_user_sprs(env); 6857 register_970_lpar_sprs(env); 6858 register_970_dbg_sprs(env); 6859 6860 /* env variables */ 6861 env->dcache_line_size = 128; 6862 env->icache_line_size = 128; 6863 6864 /* Allocate hardware IRQ controller */ 6865 init_excp_970(env); 6866 ppc970_irq_init(env_archcpu(env)); 6867 } 6868 6869 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6870 { 6871 DeviceClass *dc = DEVICE_CLASS(oc); 6872 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6873 6874 dc->desc = "PowerPC 970"; 6875 pcc->init_proc = init_proc_970; 6876 pcc->check_pow = check_pow_970; 6877 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6878 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6879 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6880 PPC_FLOAT_STFIWX | 6881 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6882 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6883 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6884 PPC_64B | PPC_ALTIVEC | 6885 PPC_SEGMENT_64B | PPC_SLBI; 6886 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6887 pcc->msr_mask = (1ull << MSR_SF) | 6888 (1ull << MSR_VR) | 6889 (1ull << MSR_POW) | 6890 (1ull << MSR_EE) | 6891 (1ull << MSR_PR) | 6892 (1ull << MSR_FP) | 6893 (1ull << MSR_ME) | 6894 (1ull << MSR_FE0) | 6895 (1ull << MSR_SE) | 6896 (1ull << MSR_DE) | 6897 (1ull << MSR_FE1) | 6898 (1ull << MSR_IR) | 6899 (1ull << MSR_DR) | 6900 (1ull << MSR_PMM) | 6901 (1ull << MSR_RI); 6902 pcc->mmu_model = POWERPC_MMU_64B; 6903 #if defined(CONFIG_SOFTMMU) 6904 pcc->hash64_opts = &ppc_hash64_opts_basic; 6905 #endif 6906 pcc->excp_model = POWERPC_EXCP_970; 6907 pcc->bus_model = PPC_FLAGS_INPUT_970; 6908 pcc->bfd_mach = bfd_mach_ppc64; 6909 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6910 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6911 POWERPC_FLAG_BUS_CLK; 6912 pcc->l1_dcache_size = 0x8000; 6913 pcc->l1_icache_size = 0x10000; 6914 } 6915 6916 static void init_proc_power5plus(CPUPPCState *env) 6917 { 6918 /* Common Registers */ 6919 init_proc_book3s_common(env); 6920 register_sdr1_sprs(env); 6921 register_book3s_dbg_sprs(env); 6922 6923 /* POWER5+ Specific Registers */ 6924 register_970_hid_sprs(env); 6925 register_970_hior_sprs(env); 6926 register_low_BATs(env); 6927 register_970_pmu_sup_sprs(env); 6928 register_970_pmu_user_sprs(env); 6929 register_power5p_common_sprs(env); 6930 register_power5p_lpar_sprs(env); 6931 register_power5p_ear_sprs(env); 6932 register_power5p_tb_sprs(env); 6933 6934 /* env variables */ 6935 env->dcache_line_size = 128; 6936 env->icache_line_size = 128; 6937 6938 /* Allocate hardware IRQ controller */ 6939 init_excp_970(env); 6940 ppc970_irq_init(env_archcpu(env)); 6941 } 6942 6943 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6944 { 6945 DeviceClass *dc = DEVICE_CLASS(oc); 6946 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6947 6948 dc->fw_name = "PowerPC,POWER5"; 6949 dc->desc = "POWER5+"; 6950 pcc->init_proc = init_proc_power5plus; 6951 pcc->check_pow = check_pow_970; 6952 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6953 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6954 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6955 PPC_FLOAT_STFIWX | 6956 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6957 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6958 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6959 PPC_64B | 6960 PPC_SEGMENT_64B | PPC_SLBI; 6961 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6962 pcc->msr_mask = (1ull << MSR_SF) | 6963 (1ull << MSR_VR) | 6964 (1ull << MSR_POW) | 6965 (1ull << MSR_EE) | 6966 (1ull << MSR_PR) | 6967 (1ull << MSR_FP) | 6968 (1ull << MSR_ME) | 6969 (1ull << MSR_FE0) | 6970 (1ull << MSR_SE) | 6971 (1ull << MSR_DE) | 6972 (1ull << MSR_FE1) | 6973 (1ull << MSR_IR) | 6974 (1ull << MSR_DR) | 6975 (1ull << MSR_PMM) | 6976 (1ull << MSR_RI); 6977 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6978 LPCR_RMI | LPCR_HDICE; 6979 pcc->mmu_model = POWERPC_MMU_2_03; 6980 #if defined(CONFIG_SOFTMMU) 6981 pcc->hash64_opts = &ppc_hash64_opts_basic; 6982 pcc->lrg_decr_bits = 32; 6983 #endif 6984 pcc->excp_model = POWERPC_EXCP_970; 6985 pcc->bus_model = PPC_FLAGS_INPUT_970; 6986 pcc->bfd_mach = bfd_mach_ppc64; 6987 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6988 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6989 POWERPC_FLAG_BUS_CLK; 6990 pcc->l1_dcache_size = 0x8000; 6991 pcc->l1_icache_size = 0x10000; 6992 } 6993 6994 static void init_proc_POWER7(CPUPPCState *env) 6995 { 6996 /* Common Registers */ 6997 init_proc_book3s_common(env); 6998 register_sdr1_sprs(env); 6999 register_book3s_dbg_sprs(env); 7000 7001 /* POWER7 Specific Registers */ 7002 register_book3s_ids_sprs(env); 7003 register_rmor_sprs(env); 7004 register_amr_sprs(env); 7005 register_book3s_purr_sprs(env); 7006 register_power5p_common_sprs(env); 7007 register_power5p_lpar_sprs(env); 7008 register_power5p_ear_sprs(env); 7009 register_power5p_tb_sprs(env); 7010 register_power6_common_sprs(env); 7011 register_power6_dbg_sprs(env); 7012 register_power7_book4_sprs(env); 7013 7014 /* env variables */ 7015 env->dcache_line_size = 128; 7016 env->icache_line_size = 128; 7017 7018 /* Allocate hardware IRQ controller */ 7019 init_excp_POWER7(env); 7020 ppcPOWER7_irq_init(env_archcpu(env)); 7021 } 7022 7023 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 7024 { 7025 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 7026 return true; 7027 } 7028 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 7029 return true; 7030 } 7031 return false; 7032 } 7033 7034 static bool cpu_has_work_POWER7(CPUState *cs) 7035 { 7036 PowerPCCPU *cpu = POWERPC_CPU(cs); 7037 CPUPPCState *env = &cpu->env; 7038 7039 if (cs->halted) { 7040 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7041 return false; 7042 } 7043 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7044 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 7045 return true; 7046 } 7047 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7048 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 7049 return true; 7050 } 7051 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 7052 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 7053 return true; 7054 } 7055 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 7056 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 7057 return true; 7058 } 7059 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7060 return true; 7061 } 7062 return false; 7063 } else { 7064 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7065 } 7066 } 7067 7068 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 7069 { 7070 DeviceClass *dc = DEVICE_CLASS(oc); 7071 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7072 CPUClass *cc = CPU_CLASS(oc); 7073 7074 dc->fw_name = "PowerPC,POWER7"; 7075 dc->desc = "POWER7"; 7076 pcc->pvr_match = ppc_pvr_match_power7; 7077 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 7078 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7079 pcc->init_proc = init_proc_POWER7; 7080 pcc->check_pow = check_pow_nocheck; 7081 cc->has_work = cpu_has_work_POWER7; 7082 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7083 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7084 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7085 PPC_FLOAT_FRSQRTES | 7086 PPC_FLOAT_STFIWX | 7087 PPC_FLOAT_EXT | 7088 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7089 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7090 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7091 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7092 PPC_SEGMENT_64B | PPC_SLBI | 7093 PPC_POPCNTB | PPC_POPCNTWD | 7094 PPC_CILDST; 7095 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 7096 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7097 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7098 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 7099 PPC2_PM_ISA206; 7100 pcc->msr_mask = (1ull << MSR_SF) | 7101 (1ull << MSR_VR) | 7102 (1ull << MSR_VSX) | 7103 (1ull << MSR_EE) | 7104 (1ull << MSR_PR) | 7105 (1ull << MSR_FP) | 7106 (1ull << MSR_ME) | 7107 (1ull << MSR_FE0) | 7108 (1ull << MSR_SE) | 7109 (1ull << MSR_DE) | 7110 (1ull << MSR_FE1) | 7111 (1ull << MSR_IR) | 7112 (1ull << MSR_DR) | 7113 (1ull << MSR_PMM) | 7114 (1ull << MSR_RI) | 7115 (1ull << MSR_LE); 7116 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 7117 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 7118 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 7119 LPCR_MER | LPCR_TC | 7120 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 7121 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 7122 pcc->mmu_model = POWERPC_MMU_2_06; 7123 #if defined(CONFIG_SOFTMMU) 7124 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7125 pcc->lrg_decr_bits = 32; 7126 #endif 7127 pcc->excp_model = POWERPC_EXCP_POWER7; 7128 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 7129 pcc->bfd_mach = bfd_mach_ppc64; 7130 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7131 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7132 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7133 POWERPC_FLAG_VSX; 7134 pcc->l1_dcache_size = 0x8000; 7135 pcc->l1_icache_size = 0x8000; 7136 } 7137 7138 static void init_proc_POWER8(CPUPPCState *env) 7139 { 7140 /* Common Registers */ 7141 init_proc_book3s_common(env); 7142 register_sdr1_sprs(env); 7143 register_book3s_207_dbg_sprs(env); 7144 7145 /* Common TCG PMU */ 7146 init_tcg_pmu_power8(env); 7147 7148 /* POWER8 Specific Registers */ 7149 register_book3s_ids_sprs(env); 7150 register_rmor_sprs(env); 7151 register_amr_sprs(env); 7152 register_iamr_sprs(env); 7153 register_book3s_purr_sprs(env); 7154 register_power5p_common_sprs(env); 7155 register_power5p_lpar_sprs(env); 7156 register_power5p_ear_sprs(env); 7157 register_power5p_tb_sprs(env); 7158 register_power6_common_sprs(env); 7159 register_power6_dbg_sprs(env); 7160 register_power8_tce_address_control_sprs(env); 7161 register_power8_ids_sprs(env); 7162 register_power8_ebb_sprs(env); 7163 register_power8_fscr_sprs(env); 7164 register_power8_pmu_sup_sprs(env); 7165 register_power8_pmu_user_sprs(env); 7166 register_power8_tm_sprs(env); 7167 register_power8_pspb_sprs(env); 7168 register_power8_dpdes_sprs(env); 7169 register_vtb_sprs(env); 7170 register_power8_ic_sprs(env); 7171 register_power8_book4_sprs(env); 7172 register_power8_rpr_sprs(env); 7173 7174 /* env variables */ 7175 env->dcache_line_size = 128; 7176 env->icache_line_size = 128; 7177 7178 /* Allocate hardware IRQ controller */ 7179 init_excp_POWER8(env); 7180 ppcPOWER7_irq_init(env_archcpu(env)); 7181 } 7182 7183 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 7184 { 7185 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 7186 return true; 7187 } 7188 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 7189 return true; 7190 } 7191 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 7192 return true; 7193 } 7194 return false; 7195 } 7196 7197 static bool cpu_has_work_POWER8(CPUState *cs) 7198 { 7199 PowerPCCPU *cpu = POWERPC_CPU(cs); 7200 CPUPPCState *env = &cpu->env; 7201 7202 if (cs->halted) { 7203 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7204 return false; 7205 } 7206 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7207 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 7208 return true; 7209 } 7210 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7211 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 7212 return true; 7213 } 7214 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 7215 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 7216 return true; 7217 } 7218 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 7219 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 7220 return true; 7221 } 7222 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7223 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 7224 return true; 7225 } 7226 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7227 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 7228 return true; 7229 } 7230 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7231 return true; 7232 } 7233 return false; 7234 } else { 7235 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7236 } 7237 } 7238 7239 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 7240 { 7241 DeviceClass *dc = DEVICE_CLASS(oc); 7242 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7243 CPUClass *cc = CPU_CLASS(oc); 7244 7245 dc->fw_name = "PowerPC,POWER8"; 7246 dc->desc = "POWER8"; 7247 pcc->pvr_match = ppc_pvr_match_power8; 7248 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7249 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7250 pcc->init_proc = init_proc_POWER8; 7251 pcc->check_pow = check_pow_nocheck; 7252 cc->has_work = cpu_has_work_POWER8; 7253 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7254 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7255 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7256 PPC_FLOAT_FRSQRTES | 7257 PPC_FLOAT_STFIWX | 7258 PPC_FLOAT_EXT | 7259 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7260 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7261 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7262 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7263 PPC_SEGMENT_64B | PPC_SLBI | 7264 PPC_POPCNTB | PPC_POPCNTWD | 7265 PPC_CILDST; 7266 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7267 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7268 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7269 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7270 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7271 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7272 PPC2_TM | PPC2_PM_ISA206; 7273 pcc->msr_mask = (1ull << MSR_SF) | 7274 (1ull << MSR_HV) | 7275 (1ull << MSR_TM) | 7276 (1ull << MSR_VR) | 7277 (1ull << MSR_VSX) | 7278 (1ull << MSR_EE) | 7279 (1ull << MSR_PR) | 7280 (1ull << MSR_FP) | 7281 (1ull << MSR_ME) | 7282 (1ull << MSR_FE0) | 7283 (1ull << MSR_SE) | 7284 (1ull << MSR_DE) | 7285 (1ull << MSR_FE1) | 7286 (1ull << MSR_IR) | 7287 (1ull << MSR_DR) | 7288 (1ull << MSR_PMM) | 7289 (1ull << MSR_RI) | 7290 (1ull << MSR_TS0) | 7291 (1ull << MSR_TS1) | 7292 (1ull << MSR_LE); 7293 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 7294 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 7295 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 7296 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 7297 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 7298 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 7299 LPCR_P8_PECE3 | LPCR_P8_PECE4; 7300 pcc->mmu_model = POWERPC_MMU_2_07; 7301 #if defined(CONFIG_SOFTMMU) 7302 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7303 pcc->lrg_decr_bits = 32; 7304 pcc->n_host_threads = 8; 7305 #endif 7306 pcc->excp_model = POWERPC_EXCP_POWER8; 7307 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 7308 pcc->bfd_mach = bfd_mach_ppc64; 7309 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7310 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7311 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7312 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 7313 pcc->l1_dcache_size = 0x8000; 7314 pcc->l1_icache_size = 0x8000; 7315 } 7316 7317 #ifdef CONFIG_SOFTMMU 7318 /* 7319 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 7320 * Encoded as array of int_32s in the form: 7321 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 7322 * x -> AP encoding 7323 * y -> radix mode supported page size (encoded as a shift) 7324 */ 7325 static struct ppc_radix_page_info POWER9_radix_page_info = { 7326 .count = 4, 7327 .entries = { 7328 0x0000000c, /* 4K - enc: 0x0 */ 7329 0xa0000010, /* 64K - enc: 0x5 */ 7330 0x20000015, /* 2M - enc: 0x1 */ 7331 0x4000001e /* 1G - enc: 0x2 */ 7332 } 7333 }; 7334 #endif /* CONFIG_SOFTMMU */ 7335 7336 static void init_proc_POWER9(CPUPPCState *env) 7337 { 7338 /* Common Registers */ 7339 init_proc_book3s_common(env); 7340 register_book3s_207_dbg_sprs(env); 7341 7342 /* Common TCG PMU */ 7343 init_tcg_pmu_power8(env); 7344 7345 /* POWER8 Specific Registers */ 7346 register_book3s_ids_sprs(env); 7347 register_amr_sprs(env); 7348 register_iamr_sprs(env); 7349 register_book3s_purr_sprs(env); 7350 register_power5p_common_sprs(env); 7351 register_power5p_lpar_sprs(env); 7352 register_power5p_ear_sprs(env); 7353 register_power5p_tb_sprs(env); 7354 register_power6_common_sprs(env); 7355 register_power6_dbg_sprs(env); 7356 register_power8_tce_address_control_sprs(env); 7357 register_power8_ids_sprs(env); 7358 register_power8_ebb_sprs(env); 7359 register_power8_fscr_sprs(env); 7360 register_power8_pmu_sup_sprs(env); 7361 register_power8_pmu_user_sprs(env); 7362 register_power8_tm_sprs(env); 7363 register_power8_pspb_sprs(env); 7364 register_power8_dpdes_sprs(env); 7365 register_vtb_sprs(env); 7366 register_power8_ic_sprs(env); 7367 register_power8_book4_sprs(env); 7368 register_power8_rpr_sprs(env); 7369 register_power9_mmu_sprs(env); 7370 7371 /* POWER9 Specific registers */ 7372 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 7373 spr_read_generic, spr_write_generic, 7374 KVM_REG_PPC_TIDR, 0); 7375 7376 /* FIXME: Filter fields properly based on privilege level */ 7377 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7378 spr_read_generic, spr_write_generic, 7379 KVM_REG_PPC_PSSCR, 0); 7380 7381 /* env variables */ 7382 env->dcache_line_size = 128; 7383 env->icache_line_size = 128; 7384 7385 /* Allocate hardware IRQ controller */ 7386 init_excp_POWER9(env); 7387 ppcPOWER9_irq_init(env_archcpu(env)); 7388 } 7389 7390 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 7391 { 7392 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 7393 return true; 7394 } 7395 return false; 7396 } 7397 7398 static bool cpu_has_work_POWER9(CPUState *cs) 7399 { 7400 PowerPCCPU *cpu = POWERPC_CPU(cs); 7401 CPUPPCState *env = &cpu->env; 7402 7403 if (cs->halted) { 7404 uint64_t psscr = env->spr[SPR_PSSCR]; 7405 7406 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7407 return false; 7408 } 7409 7410 /* If EC is clear, just return true on any pending interrupt */ 7411 if (!(psscr & PSSCR_EC)) { 7412 return true; 7413 } 7414 /* External Exception */ 7415 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7416 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7417 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7418 if (heic == 0 || !msr_hv || msr_pr) { 7419 return true; 7420 } 7421 } 7422 /* Decrementer Exception */ 7423 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7424 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7425 return true; 7426 } 7427 /* Machine Check or Hypervisor Maintenance Exception */ 7428 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7429 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7430 return true; 7431 } 7432 /* Privileged Doorbell Exception */ 7433 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7434 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7435 return true; 7436 } 7437 /* Hypervisor Doorbell Exception */ 7438 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7439 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7440 return true; 7441 } 7442 /* Hypervisor virtualization exception */ 7443 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7444 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7445 return true; 7446 } 7447 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7448 return true; 7449 } 7450 return false; 7451 } else { 7452 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7453 } 7454 } 7455 7456 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 7457 { 7458 DeviceClass *dc = DEVICE_CLASS(oc); 7459 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7460 CPUClass *cc = CPU_CLASS(oc); 7461 7462 dc->fw_name = "PowerPC,POWER9"; 7463 dc->desc = "POWER9"; 7464 pcc->pvr_match = ppc_pvr_match_power9; 7465 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 7466 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 7467 PCR_COMPAT_2_05; 7468 pcc->init_proc = init_proc_POWER9; 7469 pcc->check_pow = check_pow_nocheck; 7470 cc->has_work = cpu_has_work_POWER9; 7471 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7472 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7473 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7474 PPC_FLOAT_FRSQRTES | 7475 PPC_FLOAT_STFIWX | 7476 PPC_FLOAT_EXT | 7477 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7478 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7479 PPC_MEM_TLBSYNC | 7480 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7481 PPC_SEGMENT_64B | PPC_SLBI | 7482 PPC_POPCNTB | PPC_POPCNTWD | 7483 PPC_CILDST; 7484 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7485 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7486 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7487 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7488 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7489 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7490 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 7491 pcc->msr_mask = (1ull << MSR_SF) | 7492 (1ull << MSR_HV) | 7493 (1ull << MSR_TM) | 7494 (1ull << MSR_VR) | 7495 (1ull << MSR_VSX) | 7496 (1ull << MSR_EE) | 7497 (1ull << MSR_PR) | 7498 (1ull << MSR_FP) | 7499 (1ull << MSR_ME) | 7500 (1ull << MSR_FE0) | 7501 (1ull << MSR_SE) | 7502 (1ull << MSR_DE) | 7503 (1ull << MSR_FE1) | 7504 (1ull << MSR_IR) | 7505 (1ull << MSR_DR) | 7506 (1ull << MSR_PMM) | 7507 (1ull << MSR_RI) | 7508 (1ull << MSR_LE); 7509 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7510 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7511 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7512 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7513 LPCR_DEE | LPCR_OEE)) 7514 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7515 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7516 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7517 pcc->mmu_model = POWERPC_MMU_3_00; 7518 #if defined(CONFIG_SOFTMMU) 7519 /* segment page size remain the same */ 7520 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7521 pcc->radix_page_info = &POWER9_radix_page_info; 7522 pcc->lrg_decr_bits = 56; 7523 pcc->n_host_threads = 4; 7524 #endif 7525 pcc->excp_model = POWERPC_EXCP_POWER9; 7526 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7527 pcc->bfd_mach = bfd_mach_ppc64; 7528 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7529 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7530 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7531 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7532 pcc->l1_dcache_size = 0x8000; 7533 pcc->l1_icache_size = 0x8000; 7534 } 7535 7536 #ifdef CONFIG_SOFTMMU 7537 /* 7538 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 7539 * Encoded as array of int_32s in the form: 7540 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 7541 * x -> AP encoding 7542 * y -> radix mode supported page size (encoded as a shift) 7543 */ 7544 static struct ppc_radix_page_info POWER10_radix_page_info = { 7545 .count = 4, 7546 .entries = { 7547 0x0000000c, /* 4K - enc: 0x0 */ 7548 0xa0000010, /* 64K - enc: 0x5 */ 7549 0x20000015, /* 2M - enc: 0x1 */ 7550 0x4000001e /* 1G - enc: 0x2 */ 7551 } 7552 }; 7553 #endif /* CONFIG_SOFTMMU */ 7554 7555 static void init_proc_POWER10(CPUPPCState *env) 7556 { 7557 /* Common Registers */ 7558 init_proc_book3s_common(env); 7559 register_book3s_207_dbg_sprs(env); 7560 7561 /* Common TCG PMU */ 7562 init_tcg_pmu_power8(env); 7563 7564 /* POWER8 Specific Registers */ 7565 register_book3s_ids_sprs(env); 7566 register_amr_sprs(env); 7567 register_iamr_sprs(env); 7568 register_book3s_purr_sprs(env); 7569 register_power5p_common_sprs(env); 7570 register_power5p_lpar_sprs(env); 7571 register_power5p_ear_sprs(env); 7572 register_power6_common_sprs(env); 7573 register_power6_dbg_sprs(env); 7574 register_power8_tce_address_control_sprs(env); 7575 register_power8_ids_sprs(env); 7576 register_power8_ebb_sprs(env); 7577 register_power8_fscr_sprs(env); 7578 register_power8_pmu_sup_sprs(env); 7579 register_power8_pmu_user_sprs(env); 7580 register_power8_tm_sprs(env); 7581 register_power8_pspb_sprs(env); 7582 register_vtb_sprs(env); 7583 register_power8_ic_sprs(env); 7584 register_power8_book4_sprs(env); 7585 register_power8_rpr_sprs(env); 7586 register_power9_mmu_sprs(env); 7587 7588 /* FIXME: Filter fields properly based on privilege level */ 7589 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7590 spr_read_generic, spr_write_generic, 7591 KVM_REG_PPC_PSSCR, 0); 7592 7593 /* env variables */ 7594 env->dcache_line_size = 128; 7595 env->icache_line_size = 128; 7596 7597 /* Allocate hardware IRQ controller */ 7598 init_excp_POWER10(env); 7599 ppcPOWER9_irq_init(env_archcpu(env)); 7600 } 7601 7602 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 7603 { 7604 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 7605 return true; 7606 } 7607 return false; 7608 } 7609 7610 static bool cpu_has_work_POWER10(CPUState *cs) 7611 { 7612 PowerPCCPU *cpu = POWERPC_CPU(cs); 7613 CPUPPCState *env = &cpu->env; 7614 7615 if (cs->halted) { 7616 uint64_t psscr = env->spr[SPR_PSSCR]; 7617 7618 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7619 return false; 7620 } 7621 7622 /* If EC is clear, just return true on any pending interrupt */ 7623 if (!(psscr & PSSCR_EC)) { 7624 return true; 7625 } 7626 /* External Exception */ 7627 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7628 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7629 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7630 if (heic == 0 || !msr_hv || msr_pr) { 7631 return true; 7632 } 7633 } 7634 /* Decrementer Exception */ 7635 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7636 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7637 return true; 7638 } 7639 /* Machine Check or Hypervisor Maintenance Exception */ 7640 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7641 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7642 return true; 7643 } 7644 /* Privileged Doorbell Exception */ 7645 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7646 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7647 return true; 7648 } 7649 /* Hypervisor Doorbell Exception */ 7650 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7651 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7652 return true; 7653 } 7654 /* Hypervisor virtualization exception */ 7655 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7656 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7657 return true; 7658 } 7659 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7660 return true; 7661 } 7662 return false; 7663 } else { 7664 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7665 } 7666 } 7667 7668 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 7669 { 7670 DeviceClass *dc = DEVICE_CLASS(oc); 7671 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7672 CPUClass *cc = CPU_CLASS(oc); 7673 7674 dc->fw_name = "PowerPC,POWER10"; 7675 dc->desc = "POWER10"; 7676 pcc->pvr_match = ppc_pvr_match_power10; 7677 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 7678 PCR_COMPAT_3_00; 7679 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 7680 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7681 pcc->init_proc = init_proc_POWER10; 7682 pcc->check_pow = check_pow_nocheck; 7683 cc->has_work = cpu_has_work_POWER10; 7684 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7685 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7686 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7687 PPC_FLOAT_FRSQRTES | 7688 PPC_FLOAT_STFIWX | 7689 PPC_FLOAT_EXT | 7690 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7691 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7692 PPC_MEM_TLBSYNC | 7693 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7694 PPC_SEGMENT_64B | PPC_SLBI | 7695 PPC_POPCNTB | PPC_POPCNTWD | 7696 PPC_CILDST; 7697 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7698 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7699 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7700 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7701 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7702 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7703 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 7704 pcc->msr_mask = (1ull << MSR_SF) | 7705 (1ull << MSR_HV) | 7706 (1ull << MSR_TM) | 7707 (1ull << MSR_VR) | 7708 (1ull << MSR_VSX) | 7709 (1ull << MSR_EE) | 7710 (1ull << MSR_PR) | 7711 (1ull << MSR_FP) | 7712 (1ull << MSR_ME) | 7713 (1ull << MSR_FE0) | 7714 (1ull << MSR_SE) | 7715 (1ull << MSR_DE) | 7716 (1ull << MSR_FE1) | 7717 (1ull << MSR_IR) | 7718 (1ull << MSR_DR) | 7719 (1ull << MSR_PMM) | 7720 (1ull << MSR_RI) | 7721 (1ull << MSR_LE); 7722 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7723 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7724 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7725 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7726 LPCR_DEE | LPCR_OEE)) 7727 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7728 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7729 /* DD2 adds an extra HAIL bit */ 7730 pcc->lpcr_mask |= LPCR_HAIL; 7731 7732 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7733 pcc->mmu_model = POWERPC_MMU_3_00; 7734 #if defined(CONFIG_SOFTMMU) 7735 /* segment page size remain the same */ 7736 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7737 pcc->radix_page_info = &POWER10_radix_page_info; 7738 pcc->lrg_decr_bits = 56; 7739 #endif 7740 pcc->excp_model = POWERPC_EXCP_POWER10; 7741 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7742 pcc->bfd_mach = bfd_mach_ppc64; 7743 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7744 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7745 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7746 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7747 pcc->l1_dcache_size = 0x8000; 7748 pcc->l1_icache_size = 0x8000; 7749 } 7750 7751 #if !defined(CONFIG_USER_ONLY) 7752 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7753 { 7754 CPUPPCState *env = &cpu->env; 7755 7756 cpu->vhyp = vhyp; 7757 7758 /* 7759 * With a virtual hypervisor mode we never allow the CPU to go 7760 * hypervisor mode itself 7761 */ 7762 env->msr_mask &= ~MSR_HVB; 7763 } 7764 7765 #endif /* !defined(CONFIG_USER_ONLY) */ 7766 7767 #endif /* defined(TARGET_PPC64) */ 7768 7769 /*****************************************************************************/ 7770 /* Generic CPU instantiation routine */ 7771 static void init_ppc_proc(PowerPCCPU *cpu) 7772 { 7773 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7774 CPUPPCState *env = &cpu->env; 7775 #if !defined(CONFIG_USER_ONLY) 7776 int i; 7777 7778 env->irq_inputs = NULL; 7779 /* Set all exception vectors to an invalid address */ 7780 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7781 env->excp_vectors[i] = (target_ulong)(-1ULL); 7782 } 7783 env->ivor_mask = 0x00000000; 7784 env->ivpr_mask = 0x00000000; 7785 /* Default MMU definitions */ 7786 env->nb_BATs = 0; 7787 env->nb_tlb = 0; 7788 env->nb_ways = 0; 7789 env->tlb_type = TLB_NONE; 7790 #endif 7791 /* Register SPR common to all PowerPC implementations */ 7792 register_generic_sprs(env); 7793 spr_register(env, SPR_PVR, "PVR", 7794 /* Linux permits userspace to read PVR */ 7795 #if defined(CONFIG_LINUX_USER) 7796 &spr_read_generic, 7797 #else 7798 SPR_NOACCESS, 7799 #endif 7800 SPR_NOACCESS, 7801 &spr_read_generic, SPR_NOACCESS, 7802 pcc->pvr); 7803 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 7804 if (pcc->svr != POWERPC_SVR_NONE) { 7805 if (pcc->svr & POWERPC_SVR_E500) { 7806 spr_register(env, SPR_E500_SVR, "SVR", 7807 SPR_NOACCESS, SPR_NOACCESS, 7808 &spr_read_generic, SPR_NOACCESS, 7809 pcc->svr & ~POWERPC_SVR_E500); 7810 } else { 7811 spr_register(env, SPR_SVR, "SVR", 7812 SPR_NOACCESS, SPR_NOACCESS, 7813 &spr_read_generic, SPR_NOACCESS, 7814 pcc->svr); 7815 } 7816 } 7817 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7818 (*pcc->init_proc)(env); 7819 7820 #if !defined(CONFIG_USER_ONLY) 7821 ppc_gdb_gen_spr_xml(cpu); 7822 #endif 7823 7824 /* MSR bits & flags consistency checks */ 7825 if (env->msr_mask & (1 << 25)) { 7826 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7827 case POWERPC_FLAG_SPE: 7828 case POWERPC_FLAG_VRE: 7829 break; 7830 default: 7831 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7832 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7833 exit(1); 7834 } 7835 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7836 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7837 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7838 exit(1); 7839 } 7840 if (env->msr_mask & (1 << 17)) { 7841 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7842 case POWERPC_FLAG_TGPR: 7843 case POWERPC_FLAG_CE: 7844 break; 7845 default: 7846 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7847 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7848 exit(1); 7849 } 7850 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7851 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7852 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7853 exit(1); 7854 } 7855 if (env->msr_mask & (1 << 10)) { 7856 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7857 POWERPC_FLAG_UBLE)) { 7858 case POWERPC_FLAG_SE: 7859 case POWERPC_FLAG_DWE: 7860 case POWERPC_FLAG_UBLE: 7861 break; 7862 default: 7863 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7864 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7865 "POWERPC_FLAG_UBLE\n"); 7866 exit(1); 7867 } 7868 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7869 POWERPC_FLAG_UBLE)) { 7870 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7871 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7872 "POWERPC_FLAG_UBLE\n"); 7873 exit(1); 7874 } 7875 if (env->msr_mask & (1 << 9)) { 7876 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7877 case POWERPC_FLAG_BE: 7878 case POWERPC_FLAG_DE: 7879 break; 7880 default: 7881 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7882 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7883 exit(1); 7884 } 7885 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7886 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7887 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7888 exit(1); 7889 } 7890 if (env->msr_mask & (1 << 2)) { 7891 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7892 case POWERPC_FLAG_PX: 7893 case POWERPC_FLAG_PMM: 7894 break; 7895 default: 7896 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7897 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7898 exit(1); 7899 } 7900 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7901 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7902 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7903 exit(1); 7904 } 7905 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { 7906 fprintf(stderr, "PowerPC flags inconsistency\n" 7907 "Should define the time-base and decrementer clock source\n"); 7908 exit(1); 7909 } 7910 /* Allocate TLBs buffer when needed */ 7911 #if !defined(CONFIG_USER_ONLY) 7912 if (env->nb_tlb != 0) { 7913 int nb_tlb = env->nb_tlb; 7914 if (env->id_tlbs != 0) { 7915 nb_tlb *= 2; 7916 } 7917 switch (env->tlb_type) { 7918 case TLB_6XX: 7919 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7920 break; 7921 case TLB_EMB: 7922 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7923 break; 7924 case TLB_MAS: 7925 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7926 break; 7927 } 7928 /* Pre-compute some useful values */ 7929 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7930 } 7931 if (env->irq_inputs == NULL) { 7932 warn_report("no internal IRQ controller registered." 7933 " Attempt QEMU to crash very soon !"); 7934 } 7935 #endif 7936 if (env->check_pow == NULL) { 7937 warn_report("no power management check handler registered." 7938 " Attempt QEMU to crash very soon !"); 7939 } 7940 } 7941 7942 7943 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7944 { 7945 CPUState *cs = CPU(dev); 7946 PowerPCCPU *cpu = POWERPC_CPU(dev); 7947 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7948 Error *local_err = NULL; 7949 7950 cpu_exec_realizefn(cs, &local_err); 7951 if (local_err != NULL) { 7952 error_propagate(errp, local_err); 7953 return; 7954 } 7955 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7956 cpu->vcpu_id = cs->cpu_index; 7957 } 7958 7959 if (tcg_enabled()) { 7960 if (ppc_fixup_cpu(cpu) != 0) { 7961 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7962 goto unrealize; 7963 } 7964 } 7965 7966 create_ppc_opcodes(cpu, &local_err); 7967 if (local_err != NULL) { 7968 error_propagate(errp, local_err); 7969 goto unrealize; 7970 } 7971 init_ppc_proc(cpu); 7972 7973 ppc_gdb_init(cs, pcc); 7974 qemu_init_vcpu(cs); 7975 7976 pcc->parent_realize(dev, errp); 7977 7978 return; 7979 7980 unrealize: 7981 cpu_exec_unrealizefn(cs); 7982 } 7983 7984 static void ppc_cpu_unrealize(DeviceState *dev) 7985 { 7986 PowerPCCPU *cpu = POWERPC_CPU(dev); 7987 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7988 7989 pcc->parent_unrealize(dev); 7990 7991 cpu_remove_sync(CPU(cpu)); 7992 7993 destroy_ppc_opcodes(cpu); 7994 } 7995 7996 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7997 { 7998 ObjectClass *oc = (ObjectClass *)a; 7999 uint32_t pvr = *(uint32_t *)b; 8000 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 8001 8002 /* -cpu host does a PVR lookup during construction */ 8003 if (unlikely(strcmp(object_class_get_name(oc), 8004 TYPE_HOST_POWERPC_CPU) == 0)) { 8005 return -1; 8006 } 8007 8008 return pcc->pvr == pvr ? 0 : -1; 8009 } 8010 8011 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 8012 { 8013 GSList *list, *item; 8014 PowerPCCPUClass *pcc = NULL; 8015 8016 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8017 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 8018 if (item != NULL) { 8019 pcc = POWERPC_CPU_CLASS(item->data); 8020 } 8021 g_slist_free(list); 8022 8023 return pcc; 8024 } 8025 8026 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 8027 { 8028 ObjectClass *oc = (ObjectClass *)a; 8029 uint32_t pvr = *(uint32_t *)b; 8030 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 8031 8032 /* -cpu host does a PVR lookup during construction */ 8033 if (unlikely(strcmp(object_class_get_name(oc), 8034 TYPE_HOST_POWERPC_CPU) == 0)) { 8035 return -1; 8036 } 8037 8038 if (pcc->pvr_match(pcc, pvr)) { 8039 return 0; 8040 } 8041 8042 return -1; 8043 } 8044 8045 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 8046 { 8047 GSList *list, *item; 8048 PowerPCCPUClass *pcc = NULL; 8049 8050 list = object_class_get_list(TYPE_POWERPC_CPU, true); 8051 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 8052 if (item != NULL) { 8053 pcc = POWERPC_CPU_CLASS(item->data); 8054 } 8055 g_slist_free(list); 8056 8057 return pcc; 8058 } 8059 8060 static const char *ppc_cpu_lookup_alias(const char *alias) 8061 { 8062 int ai; 8063 8064 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 8065 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 8066 return ppc_cpu_aliases[ai].model; 8067 } 8068 } 8069 8070 return NULL; 8071 } 8072 8073 static ObjectClass *ppc_cpu_class_by_name(const char *name) 8074 { 8075 char *cpu_model, *typename; 8076 ObjectClass *oc; 8077 const char *p; 8078 unsigned long pvr; 8079 8080 /* 8081 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 8082 * 0x prefix if present) 8083 */ 8084 if (!qemu_strtoul(name, &p, 16, &pvr)) { 8085 int len = p - name; 8086 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 8087 if ((len == 8) && (*p == '\0')) { 8088 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 8089 } 8090 } 8091 8092 cpu_model = g_ascii_strdown(name, -1); 8093 p = ppc_cpu_lookup_alias(cpu_model); 8094 if (p) { 8095 g_free(cpu_model); 8096 cpu_model = g_strdup(p); 8097 } 8098 8099 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 8100 oc = object_class_by_name(typename); 8101 g_free(typename); 8102 g_free(cpu_model); 8103 8104 return oc; 8105 } 8106 8107 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 8108 { 8109 ObjectClass *oc = OBJECT_CLASS(pcc); 8110 8111 while (oc && !object_class_is_abstract(oc)) { 8112 oc = object_class_get_parent(oc); 8113 } 8114 assert(oc); 8115 8116 return POWERPC_CPU_CLASS(oc); 8117 } 8118 8119 /* Sort by PVR, ordering special case "host" last. */ 8120 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 8121 { 8122 ObjectClass *oc_a = (ObjectClass *)a; 8123 ObjectClass *oc_b = (ObjectClass *)b; 8124 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 8125 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 8126 const char *name_a = object_class_get_name(oc_a); 8127 const char *name_b = object_class_get_name(oc_b); 8128 8129 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 8130 return 1; 8131 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 8132 return -1; 8133 } else { 8134 /* Avoid an integer overflow during subtraction */ 8135 if (pcc_a->pvr < pcc_b->pvr) { 8136 return -1; 8137 } else if (pcc_a->pvr > pcc_b->pvr) { 8138 return 1; 8139 } else { 8140 return 0; 8141 } 8142 } 8143 } 8144 8145 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 8146 { 8147 ObjectClass *oc = data; 8148 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8149 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 8150 const char *typename = object_class_get_name(oc); 8151 char *name; 8152 int i; 8153 8154 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 8155 return; 8156 } 8157 8158 name = g_strndup(typename, 8159 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 8160 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 8161 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 8162 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 8163 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 8164 8165 if (alias_oc != oc) { 8166 continue; 8167 } 8168 /* 8169 * If running with KVM, we might update the family alias later, so 8170 * avoid printing the wrong alias here and use "preferred" instead 8171 */ 8172 if (strcmp(alias->alias, family->desc) == 0) { 8173 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 8174 alias->alias, family->desc); 8175 } else { 8176 qemu_printf("PowerPC %-16s (alias for %s)\n", 8177 alias->alias, name); 8178 } 8179 } 8180 g_free(name); 8181 } 8182 8183 void ppc_cpu_list(void) 8184 { 8185 GSList *list; 8186 8187 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8188 list = g_slist_sort(list, ppc_cpu_list_compare); 8189 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 8190 g_slist_free(list); 8191 8192 #ifdef CONFIG_KVM 8193 qemu_printf("\n"); 8194 qemu_printf("PowerPC %s\n", "host"); 8195 #endif 8196 } 8197 8198 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 8199 { 8200 ObjectClass *oc = data; 8201 CpuDefinitionInfoList **first = user_data; 8202 const char *typename; 8203 CpuDefinitionInfo *info; 8204 8205 typename = object_class_get_name(oc); 8206 info = g_malloc0(sizeof(*info)); 8207 info->name = g_strndup(typename, 8208 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 8209 8210 QAPI_LIST_PREPEND(*first, info); 8211 } 8212 8213 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 8214 { 8215 CpuDefinitionInfoList *cpu_list = NULL; 8216 GSList *list; 8217 int i; 8218 8219 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8220 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 8221 g_slist_free(list); 8222 8223 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 8224 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 8225 ObjectClass *oc; 8226 CpuDefinitionInfo *info; 8227 8228 oc = ppc_cpu_class_by_name(alias->model); 8229 if (oc == NULL) { 8230 continue; 8231 } 8232 8233 info = g_malloc0(sizeof(*info)); 8234 info->name = g_strdup(alias->alias); 8235 info->q_typename = g_strdup(object_class_get_name(oc)); 8236 8237 QAPI_LIST_PREPEND(cpu_list, info); 8238 } 8239 8240 return cpu_list; 8241 } 8242 8243 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 8244 { 8245 PowerPCCPU *cpu = POWERPC_CPU(cs); 8246 8247 cpu->env.nip = value; 8248 } 8249 8250 static bool ppc_cpu_has_work(CPUState *cs) 8251 { 8252 PowerPCCPU *cpu = POWERPC_CPU(cs); 8253 CPUPPCState *env = &cpu->env; 8254 8255 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8256 } 8257 8258 static void ppc_cpu_reset(DeviceState *dev) 8259 { 8260 CPUState *s = CPU(dev); 8261 PowerPCCPU *cpu = POWERPC_CPU(s); 8262 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8263 CPUPPCState *env = &cpu->env; 8264 target_ulong msr; 8265 int i; 8266 8267 pcc->parent_reset(dev); 8268 8269 msr = (target_ulong)0; 8270 msr |= (target_ulong)MSR_HVB; 8271 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ 8272 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ 8273 msr |= (target_ulong)1 << MSR_EP; 8274 #if defined(DO_SINGLE_STEP) && 0 8275 /* Single step trace mode */ 8276 msr |= (target_ulong)1 << MSR_SE; 8277 msr |= (target_ulong)1 << MSR_BE; 8278 #endif 8279 #if defined(CONFIG_USER_ONLY) 8280 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 8281 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 8282 msr |= (target_ulong)1 << MSR_FE1; 8283 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 8284 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 8285 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 8286 msr |= (target_ulong)1 << MSR_PR; 8287 #if defined(TARGET_PPC64) 8288 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 8289 #endif 8290 #if !defined(TARGET_WORDS_BIGENDIAN) 8291 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 8292 if (!((env->msr_mask >> MSR_LE) & 1)) { 8293 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 8294 exit(1); 8295 } 8296 #endif 8297 #endif 8298 8299 #if defined(TARGET_PPC64) 8300 if (mmu_is_64bit(env->mmu_model)) { 8301 msr |= (1ULL << MSR_SF); 8302 } 8303 #endif 8304 8305 hreg_store_msr(env, msr, 1); 8306 8307 #if !defined(CONFIG_USER_ONLY) 8308 env->nip = env->hreset_vector | env->excp_prefix; 8309 #if defined(CONFIG_TCG) 8310 if (env->mmu_model != POWERPC_MMU_REAL) { 8311 ppc_tlb_invalidate_all(env); 8312 } 8313 #endif /* CONFIG_TCG */ 8314 #endif 8315 8316 hreg_compute_hflags(env); 8317 env->reserve_addr = (target_ulong)-1ULL; 8318 /* Be sure no exception or interrupt is pending */ 8319 env->pending_interrupts = 0; 8320 s->exception_index = POWERPC_EXCP_NONE; 8321 env->error_code = 0; 8322 ppc_irq_reset(cpu); 8323 8324 /* tininess for underflow is detected before rounding */ 8325 set_float_detect_tininess(float_tininess_before_rounding, 8326 &env->fp_status); 8327 8328 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 8329 ppc_spr_t *spr = &env->spr_cb[i]; 8330 8331 if (!spr->name) { 8332 continue; 8333 } 8334 env->spr[i] = spr->default_value; 8335 } 8336 } 8337 8338 #ifndef CONFIG_USER_ONLY 8339 8340 static bool ppc_cpu_is_big_endian(CPUState *cs) 8341 { 8342 PowerPCCPU *cpu = POWERPC_CPU(cs); 8343 CPUPPCState *env = &cpu->env; 8344 8345 cpu_synchronize_state(cs); 8346 8347 return !msr_le; 8348 } 8349 8350 #ifdef CONFIG_TCG 8351 static void ppc_cpu_exec_enter(CPUState *cs) 8352 { 8353 PowerPCCPU *cpu = POWERPC_CPU(cs); 8354 8355 if (cpu->vhyp) { 8356 PPCVirtualHypervisorClass *vhc = 8357 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 8358 vhc->cpu_exec_enter(cpu->vhyp, cpu); 8359 } 8360 } 8361 8362 static void ppc_cpu_exec_exit(CPUState *cs) 8363 { 8364 PowerPCCPU *cpu = POWERPC_CPU(cs); 8365 8366 if (cpu->vhyp) { 8367 PPCVirtualHypervisorClass *vhc = 8368 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 8369 vhc->cpu_exec_exit(cpu->vhyp, cpu); 8370 } 8371 } 8372 #endif /* CONFIG_TCG */ 8373 8374 #endif /* !CONFIG_USER_ONLY */ 8375 8376 static void ppc_cpu_instance_init(Object *obj) 8377 { 8378 PowerPCCPU *cpu = POWERPC_CPU(obj); 8379 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8380 CPUPPCState *env = &cpu->env; 8381 8382 cpu_set_cpustate_pointers(cpu); 8383 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 8384 8385 env->msr_mask = pcc->msr_mask; 8386 env->mmu_model = pcc->mmu_model; 8387 env->excp_model = pcc->excp_model; 8388 env->bus_model = pcc->bus_model; 8389 env->insns_flags = pcc->insns_flags; 8390 env->insns_flags2 = pcc->insns_flags2; 8391 env->flags = pcc->flags; 8392 env->bfd_mach = pcc->bfd_mach; 8393 env->check_pow = pcc->check_pow; 8394 8395 /* 8396 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 8397 * msr_mask. The mask can later be cleared by PAPR mode but the hv 8398 * mode support will remain, thus enforcing that we cannot use 8399 * priv. instructions in guest in PAPR mode. For 970 we currently 8400 * simply don't set HV in msr_mask thus simulating an "Apple mode" 8401 * 970. If we ever want to support 970 HV mode, we'll have to add 8402 * a processor attribute of some sort. 8403 */ 8404 #if !defined(CONFIG_USER_ONLY) 8405 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 8406 #endif 8407 8408 ppc_hash64_init(cpu); 8409 } 8410 8411 static void ppc_cpu_instance_finalize(Object *obj) 8412 { 8413 PowerPCCPU *cpu = POWERPC_CPU(obj); 8414 8415 ppc_hash64_finalize(cpu); 8416 } 8417 8418 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 8419 { 8420 return pcc->pvr == pvr; 8421 } 8422 8423 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 8424 { 8425 PowerPCCPU *cpu = POWERPC_CPU(cs); 8426 CPUPPCState *env = &cpu->env; 8427 8428 if ((env->hflags >> MSR_LE) & 1) { 8429 info->endian = BFD_ENDIAN_LITTLE; 8430 } 8431 info->mach = env->bfd_mach; 8432 if (!env->bfd_mach) { 8433 #ifdef TARGET_PPC64 8434 info->mach = bfd_mach_ppc64; 8435 #else 8436 info->mach = bfd_mach_ppc; 8437 #endif 8438 } 8439 info->disassembler_options = (char *)"any"; 8440 info->print_insn = print_insn_ppc; 8441 8442 info->cap_arch = CS_ARCH_PPC; 8443 #ifdef TARGET_PPC64 8444 info->cap_mode = CS_MODE_64; 8445 #endif 8446 } 8447 8448 static Property ppc_cpu_properties[] = { 8449 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 8450 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 8451 false), 8452 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 8453 false), 8454 DEFINE_PROP_END_OF_LIST(), 8455 }; 8456 8457 #ifndef CONFIG_USER_ONLY 8458 #include "hw/core/sysemu-cpu-ops.h" 8459 8460 static const struct SysemuCPUOps ppc_sysemu_ops = { 8461 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 8462 .write_elf32_note = ppc32_cpu_write_elf32_note, 8463 .write_elf64_note = ppc64_cpu_write_elf64_note, 8464 .virtio_is_big_endian = ppc_cpu_is_big_endian, 8465 .legacy_vmsd = &vmstate_ppc_cpu, 8466 }; 8467 #endif 8468 8469 #ifdef CONFIG_TCG 8470 #include "hw/core/tcg-cpu-ops.h" 8471 8472 static const struct TCGCPUOps ppc_tcg_ops = { 8473 .initialize = ppc_translate_init, 8474 8475 #ifdef CONFIG_USER_ONLY 8476 .record_sigsegv = ppc_cpu_record_sigsegv, 8477 #else 8478 .tlb_fill = ppc_cpu_tlb_fill, 8479 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 8480 .do_interrupt = ppc_cpu_do_interrupt, 8481 .cpu_exec_enter = ppc_cpu_exec_enter, 8482 .cpu_exec_exit = ppc_cpu_exec_exit, 8483 .do_unaligned_access = ppc_cpu_do_unaligned_access, 8484 #endif /* !CONFIG_USER_ONLY */ 8485 }; 8486 #endif /* CONFIG_TCG */ 8487 8488 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 8489 { 8490 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8491 CPUClass *cc = CPU_CLASS(oc); 8492 DeviceClass *dc = DEVICE_CLASS(oc); 8493 8494 device_class_set_parent_realize(dc, ppc_cpu_realize, 8495 &pcc->parent_realize); 8496 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 8497 &pcc->parent_unrealize); 8498 pcc->pvr_match = ppc_pvr_match_default; 8499 device_class_set_props(dc, ppc_cpu_properties); 8500 8501 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 8502 8503 cc->class_by_name = ppc_cpu_class_by_name; 8504 cc->has_work = ppc_cpu_has_work; 8505 cc->dump_state = ppc_cpu_dump_state; 8506 cc->set_pc = ppc_cpu_set_pc; 8507 cc->gdb_read_register = ppc_cpu_gdb_read_register; 8508 cc->gdb_write_register = ppc_cpu_gdb_write_register; 8509 #ifndef CONFIG_USER_ONLY 8510 cc->sysemu_ops = &ppc_sysemu_ops; 8511 #endif 8512 8513 cc->gdb_num_core_regs = 71; 8514 #ifndef CONFIG_USER_ONLY 8515 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 8516 #endif 8517 #ifdef USE_APPLE_GDB 8518 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 8519 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 8520 cc->gdb_num_core_regs = 71 + 32; 8521 #endif 8522 8523 cc->gdb_arch_name = ppc_gdb_arch_name; 8524 #if defined(TARGET_PPC64) 8525 cc->gdb_core_xml_file = "power64-core.xml"; 8526 #else 8527 cc->gdb_core_xml_file = "power-core.xml"; 8528 #endif 8529 cc->disas_set_info = ppc_disas_set_info; 8530 8531 dc->fw_name = "PowerPC,UNKNOWN"; 8532 8533 #ifdef CONFIG_TCG 8534 cc->tcg_ops = &ppc_tcg_ops; 8535 #endif /* CONFIG_TCG */ 8536 } 8537 8538 static const TypeInfo ppc_cpu_type_info = { 8539 .name = TYPE_POWERPC_CPU, 8540 .parent = TYPE_CPU, 8541 .instance_size = sizeof(PowerPCCPU), 8542 .instance_align = __alignof__(PowerPCCPU), 8543 .instance_init = ppc_cpu_instance_init, 8544 .instance_finalize = ppc_cpu_instance_finalize, 8545 .abstract = true, 8546 .class_size = sizeof(PowerPCCPUClass), 8547 .class_init = ppc_cpu_class_init, 8548 }; 8549 8550 #ifndef CONFIG_USER_ONLY 8551 static const TypeInfo ppc_vhyp_type_info = { 8552 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 8553 .parent = TYPE_INTERFACE, 8554 .class_size = sizeof(PPCVirtualHypervisorClass), 8555 }; 8556 #endif 8557 8558 static void ppc_cpu_register_types(void) 8559 { 8560 type_register_static(&ppc_cpu_type_info); 8561 #ifndef CONFIG_USER_ONLY 8562 type_register_static(&ppc_vhyp_type_info); 8563 #endif 8564 } 8565 8566 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 8567 { 8568 #define RGPL 4 8569 #define RFPL 4 8570 8571 PowerPCCPU *cpu = POWERPC_CPU(cs); 8572 CPUPPCState *env = &cpu->env; 8573 int i; 8574 8575 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 8576 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 8577 env->nip, env->lr, env->ctr, cpu_read_xer(env), 8578 cs->cpu_index); 8579 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 8580 "%08x iidx %d didx %d\n", 8581 env->msr, env->spr[SPR_HID0], env->hflags, 8582 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 8583 #if !defined(NO_TIMER_DUMP) 8584 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 8585 #if !defined(CONFIG_USER_ONLY) 8586 " DECR " TARGET_FMT_lu 8587 #endif 8588 "\n", 8589 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 8590 #if !defined(CONFIG_USER_ONLY) 8591 , cpu_ppc_load_decr(env) 8592 #endif 8593 ); 8594 #endif 8595 for (i = 0; i < 32; i++) { 8596 if ((i & (RGPL - 1)) == 0) { 8597 qemu_fprintf(f, "GPR%02d", i); 8598 } 8599 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 8600 if ((i & (RGPL - 1)) == (RGPL - 1)) { 8601 qemu_fprintf(f, "\n"); 8602 } 8603 } 8604 qemu_fprintf(f, "CR "); 8605 for (i = 0; i < 8; i++) 8606 qemu_fprintf(f, "%01x", env->crf[i]); 8607 qemu_fprintf(f, " ["); 8608 for (i = 0; i < 8; i++) { 8609 char a = '-'; 8610 if (env->crf[i] & 0x08) { 8611 a = 'L'; 8612 } else if (env->crf[i] & 0x04) { 8613 a = 'G'; 8614 } else if (env->crf[i] & 0x02) { 8615 a = 'E'; 8616 } 8617 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 8618 } 8619 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 8620 env->reserve_addr); 8621 8622 if (flags & CPU_DUMP_FPU) { 8623 for (i = 0; i < 32; i++) { 8624 if ((i & (RFPL - 1)) == 0) { 8625 qemu_fprintf(f, "FPR%02d", i); 8626 } 8627 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 8628 if ((i & (RFPL - 1)) == (RFPL - 1)) { 8629 qemu_fprintf(f, "\n"); 8630 } 8631 } 8632 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 8633 } 8634 8635 #if !defined(CONFIG_USER_ONLY) 8636 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 8637 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 8638 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 8639 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 8640 8641 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 8642 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 8643 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 8644 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 8645 8646 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 8647 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 8648 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 8649 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 8650 8651 #if defined(TARGET_PPC64) 8652 if (env->excp_model == POWERPC_EXCP_POWER7 || 8653 env->excp_model == POWERPC_EXCP_POWER8 || 8654 env->excp_model == POWERPC_EXCP_POWER9 || 8655 env->excp_model == POWERPC_EXCP_POWER10) { 8656 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 8657 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 8658 } 8659 #endif 8660 if (env->excp_model == POWERPC_EXCP_BOOKE) { 8661 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 8662 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 8663 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 8664 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 8665 8666 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8667 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8668 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 8669 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 8670 8671 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 8672 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 8673 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 8674 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 8675 8676 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 8677 " EPR " TARGET_FMT_lx "\n", 8678 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 8679 env->spr[SPR_BOOKE_EPR]); 8680 8681 /* FSL-specific */ 8682 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 8683 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 8684 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 8685 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 8686 8687 /* 8688 * IVORs are left out as they are large and do not change often -- 8689 * they can be read with "p $ivor0", "p $ivor1", etc. 8690 */ 8691 } 8692 8693 #if defined(TARGET_PPC64) 8694 if (env->flags & POWERPC_FLAG_CFAR) { 8695 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8696 } 8697 #endif 8698 8699 if (env->spr_cb[SPR_LPCR].name) { 8700 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8701 } 8702 8703 switch (env->mmu_model) { 8704 case POWERPC_MMU_32B: 8705 case POWERPC_MMU_601: 8706 case POWERPC_MMU_SOFT_6xx: 8707 #if defined(TARGET_PPC64) 8708 case POWERPC_MMU_64B: 8709 case POWERPC_MMU_2_03: 8710 case POWERPC_MMU_2_06: 8711 case POWERPC_MMU_2_07: 8712 case POWERPC_MMU_3_00: 8713 #endif 8714 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 8715 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 8716 } 8717 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 8718 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 8719 } 8720 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8721 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8722 break; 8723 case POWERPC_MMU_BOOKE206: 8724 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8725 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8726 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8727 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8728 8729 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8730 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8731 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8732 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8733 8734 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8735 " TLB1CFG " TARGET_FMT_lx "\n", 8736 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8737 env->spr[SPR_BOOKE_TLB1CFG]); 8738 break; 8739 default: 8740 break; 8741 } 8742 #endif 8743 8744 #undef RGPL 8745 #undef RFPL 8746 } 8747 type_init(ppc_cpu_register_types) 8748