1 /* 2 * PowerPC implementation of KVM hooks 3 * 4 * Copyright IBM Corp. 2007 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * Authors: 8 * Jerone Young <jyoung5@us.ibm.com> 9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 10 * Hollis Blanchard <hollisb@us.ibm.com> 11 * 12 * This work is licensed under the terms of the GNU GPL, version 2 or later. 13 * See the COPYING file in the top-level directory. 14 * 15 */ 16 17 #include "qemu/osdep.h" 18 #include <dirent.h> 19 #include <sys/ioctl.h> 20 #include <sys/vfs.h> 21 22 #include <linux/kvm.h> 23 24 #include "qapi/error.h" 25 #include "qemu/error-report.h" 26 #include "cpu.h" 27 #include "cpu-models.h" 28 #include "qemu/timer.h" 29 #include "sysemu/hw_accel.h" 30 #include "kvm_ppc.h" 31 #include "sysemu/cpus.h" 32 #include "sysemu/device_tree.h" 33 #include "mmu-hash64.h" 34 35 #include "hw/ppc/spapr.h" 36 #include "hw/ppc/spapr_cpu_core.h" 37 #include "hw/hw.h" 38 #include "hw/ppc/ppc.h" 39 #include "migration/qemu-file-types.h" 40 #include "sysemu/watchdog.h" 41 #include "trace.h" 42 #include "exec/gdbstub.h" 43 #include "exec/memattrs.h" 44 #include "exec/ram_addr.h" 45 #include "sysemu/hostmem.h" 46 #include "qemu/cutils.h" 47 #include "qemu/main-loop.h" 48 #include "qemu/mmap-alloc.h" 49 #include "elf.h" 50 #include "sysemu/kvm_int.h" 51 52 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/" 53 54 #define DEBUG_RETURN_GUEST 0 55 #define DEBUG_RETURN_GDB 1 56 57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 58 KVM_CAP_LAST_INFO 59 }; 60 61 static int cap_interrupt_unset; 62 static int cap_segstate; 63 static int cap_booke_sregs; 64 static int cap_ppc_smt; 65 static int cap_ppc_smt_possible; 66 static int cap_spapr_tce; 67 static int cap_spapr_tce_64; 68 static int cap_spapr_multitce; 69 static int cap_spapr_vfio; 70 static int cap_hior; 71 static int cap_one_reg; 72 static int cap_epr; 73 static int cap_ppc_watchdog; 74 static int cap_papr; 75 static int cap_htab_fd; 76 static int cap_fixup_hcalls; 77 static int cap_htm; /* Hardware transactional memory support */ 78 static int cap_mmu_radix; 79 static int cap_mmu_hash_v3; 80 static int cap_xive; 81 static int cap_resize_hpt; 82 static int cap_ppc_pvr_compat; 83 static int cap_ppc_safe_cache; 84 static int cap_ppc_safe_bounds_check; 85 static int cap_ppc_safe_indirect_branch; 86 static int cap_ppc_count_cache_flush_assist; 87 static int cap_ppc_nested_kvm_hv; 88 static int cap_large_decr; 89 static int cap_fwnmi; 90 static int cap_rpt_invalidate; 91 92 static uint32_t debug_inst_opcode; 93 94 /* 95 * Check whether we are running with KVM-PR (instead of KVM-HV). This 96 * should only be used for fallback tests - generally we should use 97 * explicit capabilities for the features we want, rather than 98 * assuming what is/isn't available depending on the KVM variant. 99 */ 100 static bool kvmppc_is_pr(KVMState *ks) 101 { 102 /* Assume KVM-PR if the GET_PVINFO capability is available */ 103 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0; 104 } 105 106 static int kvm_ppc_register_host_cpu_type(void); 107 static void kvmppc_get_cpu_characteristics(KVMState *s); 108 static int kvmppc_get_dec_bits(void); 109 110 int kvm_arch_init(MachineState *ms, KVMState *s) 111 { 112 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); 113 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); 114 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); 115 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE); 116 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE); 117 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64); 118 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE); 119 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO); 120 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG); 121 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR); 122 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR); 123 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG); 124 /* 125 * Note: we don't set cap_papr here, because this capability is 126 * only activated after this by kvmppc_set_papr() 127 */ 128 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD); 129 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL); 130 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT); 131 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM); 132 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX); 133 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3); 134 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE); 135 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT); 136 kvmppc_get_cpu_characteristics(s); 137 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV); 138 cap_large_decr = kvmppc_get_dec_bits(); 139 cap_fwnmi = kvm_vm_check_extension(s, KVM_CAP_PPC_FWNMI); 140 /* 141 * Note: setting it to false because there is not such capability 142 * in KVM at this moment. 143 * 144 * TODO: call kvm_vm_check_extension() with the right capability 145 * after the kernel starts implementing it. 146 */ 147 cap_ppc_pvr_compat = false; 148 149 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) { 150 error_report("KVM: Host kernel doesn't have level irq capability"); 151 exit(1); 152 } 153 154 cap_rpt_invalidate = kvm_vm_check_extension(s, KVM_CAP_PPC_RPT_INVALIDATE); 155 kvm_ppc_register_host_cpu_type(); 156 157 return 0; 158 } 159 160 int kvm_arch_irqchip_create(KVMState *s) 161 { 162 return 0; 163 } 164 165 static int kvm_arch_sync_sregs(PowerPCCPU *cpu) 166 { 167 CPUPPCState *cenv = &cpu->env; 168 CPUState *cs = CPU(cpu); 169 struct kvm_sregs sregs; 170 int ret; 171 172 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 173 /* 174 * What we're really trying to say is "if we're on BookE, we 175 * use the native PVR for now". This is the only sane way to 176 * check it though, so we potentially confuse users that they 177 * can run BookE guests on BookS. Let's hope nobody dares 178 * enough :) 179 */ 180 return 0; 181 } else { 182 if (!cap_segstate) { 183 fprintf(stderr, "kvm error: missing PVR setting capability\n"); 184 return -ENOSYS; 185 } 186 } 187 188 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); 189 if (ret) { 190 return ret; 191 } 192 193 sregs.pvr = cenv->spr[SPR_PVR]; 194 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); 195 } 196 197 /* Set up a shared TLB array with KVM */ 198 static int kvm_booke206_tlb_init(PowerPCCPU *cpu) 199 { 200 CPUPPCState *env = &cpu->env; 201 CPUState *cs = CPU(cpu); 202 struct kvm_book3e_206_tlb_params params = {}; 203 struct kvm_config_tlb cfg = {}; 204 unsigned int entries = 0; 205 int ret, i; 206 207 if (!kvm_enabled() || 208 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) { 209 return 0; 210 } 211 212 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN); 213 214 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 215 params.tlb_sizes[i] = booke206_tlb_size(env, i); 216 params.tlb_ways[i] = booke206_tlb_ways(env, i); 217 entries += params.tlb_sizes[i]; 218 } 219 220 assert(entries == env->nb_tlb); 221 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t)); 222 223 env->tlb_dirty = true; 224 225 cfg.array = (uintptr_t)env->tlb.tlbm; 226 cfg.array_len = sizeof(ppcmas_tlb_t) * entries; 227 cfg.params = (uintptr_t)¶ms; 228 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV; 229 230 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg); 231 if (ret < 0) { 232 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n", 233 __func__, strerror(-ret)); 234 return ret; 235 } 236 237 env->kvm_sw_tlb = true; 238 return 0; 239 } 240 241 242 #if defined(TARGET_PPC64) 243 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp) 244 { 245 int ret; 246 247 assert(kvm_state != NULL); 248 249 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) { 250 error_setg(errp, "KVM doesn't expose the MMU features it supports"); 251 error_append_hint(errp, "Consider switching to a newer KVM\n"); 252 return; 253 } 254 255 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info); 256 if (ret == 0) { 257 return; 258 } 259 260 error_setg_errno(errp, -ret, 261 "KVM failed to provide the MMU features it supports"); 262 } 263 264 struct ppc_radix_page_info *kvm_get_radix_page_info(void) 265 { 266 KVMState *s = KVM_STATE(current_accel()); 267 struct ppc_radix_page_info *radix_page_info; 268 struct kvm_ppc_rmmu_info rmmu_info = { }; 269 int i; 270 271 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) { 272 return NULL; 273 } 274 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) { 275 return NULL; 276 } 277 radix_page_info = g_malloc0(sizeof(*radix_page_info)); 278 radix_page_info->count = 0; 279 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 280 if (rmmu_info.ap_encodings[i]) { 281 radix_page_info->entries[i] = rmmu_info.ap_encodings[i]; 282 radix_page_info->count++; 283 } 284 } 285 return radix_page_info; 286 } 287 288 target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu, 289 bool radix, bool gtse, 290 uint64_t proc_tbl) 291 { 292 CPUState *cs = CPU(cpu); 293 int ret; 294 uint64_t flags = 0; 295 struct kvm_ppc_mmuv3_cfg cfg = { 296 .process_table = proc_tbl, 297 }; 298 299 if (radix) { 300 flags |= KVM_PPC_MMUV3_RADIX; 301 } 302 if (gtse) { 303 flags |= KVM_PPC_MMUV3_GTSE; 304 } 305 cfg.flags = flags; 306 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg); 307 switch (ret) { 308 case 0: 309 return H_SUCCESS; 310 case -EINVAL: 311 return H_PARAMETER; 312 case -ENODEV: 313 return H_NOT_AVAILABLE; 314 default: 315 return H_HARDWARE; 316 } 317 } 318 319 bool kvmppc_hpt_needs_host_contiguous_pages(void) 320 { 321 static struct kvm_ppc_smmu_info smmu_info; 322 323 if (!kvm_enabled()) { 324 return false; 325 } 326 327 kvm_get_smmu_info(&smmu_info, &error_fatal); 328 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL); 329 } 330 331 void kvm_check_mmu(PowerPCCPU *cpu, Error **errp) 332 { 333 struct kvm_ppc_smmu_info smmu_info; 334 int iq, ik, jq, jk; 335 Error *local_err = NULL; 336 337 /* For now, we only have anything to check on hash64 MMUs */ 338 if (!cpu->hash64_opts || !kvm_enabled()) { 339 return; 340 } 341 342 kvm_get_smmu_info(&smmu_info, &local_err); 343 if (local_err) { 344 error_propagate(errp, local_err); 345 return; 346 } 347 348 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG) 349 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { 350 error_setg(errp, 351 "KVM does not support 1TiB segments which guest expects"); 352 return; 353 } 354 355 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) { 356 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u", 357 smmu_info.slb_size, cpu->hash64_opts->slb_size); 358 return; 359 } 360 361 /* 362 * Verify that every pagesize supported by the cpu model is 363 * supported by KVM with the same encodings 364 */ 365 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) { 366 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq]; 367 struct kvm_ppc_one_seg_page_size *ksps; 368 369 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) { 370 if (qsps->page_shift == smmu_info.sps[ik].page_shift) { 371 break; 372 } 373 } 374 if (ik >= ARRAY_SIZE(smmu_info.sps)) { 375 error_setg(errp, "KVM doesn't support for base page shift %u", 376 qsps->page_shift); 377 return; 378 } 379 380 ksps = &smmu_info.sps[ik]; 381 if (ksps->slb_enc != qsps->slb_enc) { 382 error_setg(errp, 383 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x", 384 ksps->slb_enc, ksps->page_shift, qsps->slb_enc); 385 return; 386 } 387 388 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) { 389 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) { 390 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) { 391 break; 392 } 393 } 394 395 if (jk >= ARRAY_SIZE(ksps->enc)) { 396 error_setg(errp, "KVM doesn't support page shift %u/%u", 397 qsps->enc[jq].page_shift, qsps->page_shift); 398 return; 399 } 400 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) { 401 error_setg(errp, 402 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x", 403 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift, 404 qsps->page_shift, qsps->enc[jq].pte_enc); 405 return; 406 } 407 } 408 } 409 410 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 411 /* 412 * Mostly what guest pagesizes we can use are related to the 413 * host pages used to map guest RAM, which is handled in the 414 * platform code. Cache-Inhibited largepages (64k) however are 415 * used for I/O, so if they're mapped to the host at all it 416 * will be a normal mapping, not a special hugepage one used 417 * for RAM. 418 */ 419 if (qemu_real_host_page_size() < 0x10000) { 420 error_setg(errp, 421 "KVM can't supply 64kiB CI pages, which guest expects"); 422 } 423 } 424 } 425 #endif /* !defined (TARGET_PPC64) */ 426 427 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 428 { 429 return POWERPC_CPU(cpu)->vcpu_id; 430 } 431 432 /* 433 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports 434 * only 1 watchpoint, so array size of 4 is sufficient for now. 435 */ 436 #define MAX_HW_BKPTS 4 437 438 static struct HWBreakpoint { 439 target_ulong addr; 440 int type; 441 } hw_debug_points[MAX_HW_BKPTS]; 442 443 static CPUWatchpoint hw_watchpoint; 444 445 /* Default there is no breakpoint and watchpoint supported */ 446 static int max_hw_breakpoint; 447 static int max_hw_watchpoint; 448 static int nb_hw_breakpoint; 449 static int nb_hw_watchpoint; 450 451 static void kvmppc_hw_debug_points_init(CPUPPCState *cenv) 452 { 453 if (cenv->excp_model == POWERPC_EXCP_BOOKE) { 454 max_hw_breakpoint = 2; 455 max_hw_watchpoint = 2; 456 } 457 458 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) { 459 fprintf(stderr, "Error initializing h/w breakpoints\n"); 460 return; 461 } 462 } 463 464 int kvm_arch_init_vcpu(CPUState *cs) 465 { 466 PowerPCCPU *cpu = POWERPC_CPU(cs); 467 CPUPPCState *cenv = &cpu->env; 468 int ret; 469 470 /* Synchronize sregs with kvm */ 471 ret = kvm_arch_sync_sregs(cpu); 472 if (ret) { 473 if (ret == -EINVAL) { 474 error_report("Register sync failed... If you're using kvm-hv.ko," 475 " only \"-cpu host\" is possible"); 476 } 477 return ret; 478 } 479 480 switch (cenv->mmu_model) { 481 case POWERPC_MMU_BOOKE206: 482 /* This target supports access to KVM's guest TLB */ 483 ret = kvm_booke206_tlb_init(cpu); 484 break; 485 case POWERPC_MMU_2_07: 486 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) { 487 /* 488 * KVM-HV has transactional memory on POWER8 also without 489 * the KVM_CAP_PPC_HTM extension, so enable it here 490 * instead as long as it's available to userspace on the 491 * host. 492 */ 493 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) { 494 cap_htm = true; 495 } 496 } 497 break; 498 default: 499 break; 500 } 501 502 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode); 503 kvmppc_hw_debug_points_init(cenv); 504 505 return ret; 506 } 507 508 int kvm_arch_destroy_vcpu(CPUState *cs) 509 { 510 return 0; 511 } 512 513 static void kvm_sw_tlb_put(PowerPCCPU *cpu) 514 { 515 CPUPPCState *env = &cpu->env; 516 CPUState *cs = CPU(cpu); 517 struct kvm_dirty_tlb dirty_tlb; 518 unsigned char *bitmap; 519 int ret; 520 521 if (!env->kvm_sw_tlb) { 522 return; 523 } 524 525 bitmap = g_malloc((env->nb_tlb + 7) / 8); 526 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8); 527 528 dirty_tlb.bitmap = (uintptr_t)bitmap; 529 dirty_tlb.num_dirty = env->nb_tlb; 530 531 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb); 532 if (ret) { 533 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n", 534 __func__, strerror(-ret)); 535 } 536 537 g_free(bitmap); 538 } 539 540 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) 541 { 542 PowerPCCPU *cpu = POWERPC_CPU(cs); 543 CPUPPCState *env = &cpu->env; 544 /* Init 'val' to avoid "uninitialised value" Valgrind warnings */ 545 union { 546 uint32_t u32; 547 uint64_t u64; 548 } val = { }; 549 struct kvm_one_reg reg = { 550 .id = id, 551 .addr = (uintptr_t) &val, 552 }; 553 int ret; 554 555 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 556 if (ret != 0) { 557 trace_kvm_failed_spr_get(spr, strerror(errno)); 558 } else { 559 switch (id & KVM_REG_SIZE_MASK) { 560 case KVM_REG_SIZE_U32: 561 env->spr[spr] = val.u32; 562 break; 563 564 case KVM_REG_SIZE_U64: 565 env->spr[spr] = val.u64; 566 break; 567 568 default: 569 /* Don't handle this size yet */ 570 abort(); 571 } 572 } 573 } 574 575 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) 576 { 577 PowerPCCPU *cpu = POWERPC_CPU(cs); 578 CPUPPCState *env = &cpu->env; 579 union { 580 uint32_t u32; 581 uint64_t u64; 582 } val; 583 struct kvm_one_reg reg = { 584 .id = id, 585 .addr = (uintptr_t) &val, 586 }; 587 int ret; 588 589 switch (id & KVM_REG_SIZE_MASK) { 590 case KVM_REG_SIZE_U32: 591 val.u32 = env->spr[spr]; 592 break; 593 594 case KVM_REG_SIZE_U64: 595 val.u64 = env->spr[spr]; 596 break; 597 598 default: 599 /* Don't handle this size yet */ 600 abort(); 601 } 602 603 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 604 if (ret != 0) { 605 trace_kvm_failed_spr_set(spr, strerror(errno)); 606 } 607 } 608 609 static int kvm_put_fp(CPUState *cs) 610 { 611 PowerPCCPU *cpu = POWERPC_CPU(cs); 612 CPUPPCState *env = &cpu->env; 613 struct kvm_one_reg reg; 614 int i; 615 int ret; 616 617 if (env->insns_flags & PPC_FLOAT) { 618 uint64_t fpscr = env->fpscr; 619 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 620 621 reg.id = KVM_REG_PPC_FPSCR; 622 reg.addr = (uintptr_t)&fpscr; 623 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 624 if (ret < 0) { 625 trace_kvm_failed_fpscr_set(strerror(errno)); 626 return ret; 627 } 628 629 for (i = 0; i < 32; i++) { 630 uint64_t vsr[2]; 631 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); 632 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); 633 634 #if HOST_BIG_ENDIAN 635 vsr[0] = float64_val(*fpr); 636 vsr[1] = *vsrl; 637 #else 638 vsr[0] = *vsrl; 639 vsr[1] = float64_val(*fpr); 640 #endif 641 reg.addr = (uintptr_t) &vsr; 642 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 643 644 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 645 if (ret < 0) { 646 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i, 647 strerror(errno)); 648 return ret; 649 } 650 } 651 } 652 653 if (env->insns_flags & PPC_ALTIVEC) { 654 reg.id = KVM_REG_PPC_VSCR; 655 reg.addr = (uintptr_t)&env->vscr; 656 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 657 if (ret < 0) { 658 trace_kvm_failed_vscr_set(strerror(errno)); 659 return ret; 660 } 661 662 for (i = 0; i < 32; i++) { 663 reg.id = KVM_REG_PPC_VR(i); 664 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 665 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 666 if (ret < 0) { 667 trace_kvm_failed_vr_set(i, strerror(errno)); 668 return ret; 669 } 670 } 671 } 672 673 return 0; 674 } 675 676 static int kvm_get_fp(CPUState *cs) 677 { 678 PowerPCCPU *cpu = POWERPC_CPU(cs); 679 CPUPPCState *env = &cpu->env; 680 struct kvm_one_reg reg; 681 int i; 682 int ret; 683 684 if (env->insns_flags & PPC_FLOAT) { 685 uint64_t fpscr; 686 bool vsx = !!(env->insns_flags2 & PPC2_VSX); 687 688 reg.id = KVM_REG_PPC_FPSCR; 689 reg.addr = (uintptr_t)&fpscr; 690 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 691 if (ret < 0) { 692 trace_kvm_failed_fpscr_get(strerror(errno)); 693 return ret; 694 } else { 695 env->fpscr = fpscr; 696 } 697 698 for (i = 0; i < 32; i++) { 699 uint64_t vsr[2]; 700 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); 701 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); 702 703 reg.addr = (uintptr_t) &vsr; 704 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); 705 706 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 707 if (ret < 0) { 708 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i, 709 strerror(errno)); 710 return ret; 711 } else { 712 #if HOST_BIG_ENDIAN 713 *fpr = vsr[0]; 714 if (vsx) { 715 *vsrl = vsr[1]; 716 } 717 #else 718 *fpr = vsr[1]; 719 if (vsx) { 720 *vsrl = vsr[0]; 721 } 722 #endif 723 } 724 } 725 } 726 727 if (env->insns_flags & PPC_ALTIVEC) { 728 reg.id = KVM_REG_PPC_VSCR; 729 reg.addr = (uintptr_t)&env->vscr; 730 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 731 if (ret < 0) { 732 trace_kvm_failed_vscr_get(strerror(errno)); 733 return ret; 734 } 735 736 for (i = 0; i < 32; i++) { 737 reg.id = KVM_REG_PPC_VR(i); 738 reg.addr = (uintptr_t)cpu_avr_ptr(env, i); 739 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 740 if (ret < 0) { 741 trace_kvm_failed_vr_get(i, strerror(errno)); 742 return ret; 743 } 744 } 745 } 746 747 return 0; 748 } 749 750 #if defined(TARGET_PPC64) 751 static int kvm_get_vpa(CPUState *cs) 752 { 753 PowerPCCPU *cpu = POWERPC_CPU(cs); 754 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 755 struct kvm_one_reg reg; 756 int ret; 757 758 reg.id = KVM_REG_PPC_VPA_ADDR; 759 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 760 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 761 if (ret < 0) { 762 trace_kvm_failed_vpa_addr_get(strerror(errno)); 763 return ret; 764 } 765 766 assert((uintptr_t)&spapr_cpu->slb_shadow_size 767 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 768 reg.id = KVM_REG_PPC_VPA_SLB; 769 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 770 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 771 if (ret < 0) { 772 trace_kvm_failed_slb_get(strerror(errno)); 773 return ret; 774 } 775 776 assert((uintptr_t)&spapr_cpu->dtl_size 777 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 778 reg.id = KVM_REG_PPC_VPA_DTL; 779 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 780 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); 781 if (ret < 0) { 782 trace_kvm_failed_dtl_get(strerror(errno)); 783 return ret; 784 } 785 786 return 0; 787 } 788 789 static int kvm_put_vpa(CPUState *cs) 790 { 791 PowerPCCPU *cpu = POWERPC_CPU(cs); 792 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 793 struct kvm_one_reg reg; 794 int ret; 795 796 /* 797 * SLB shadow or DTL can't be registered unless a master VPA is 798 * registered. That means when restoring state, if a VPA *is* 799 * registered, we need to set that up first. If not, we need to 800 * deregister the others before deregistering the master VPA 801 */ 802 assert(spapr_cpu->vpa_addr 803 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr)); 804 805 if (spapr_cpu->vpa_addr) { 806 reg.id = KVM_REG_PPC_VPA_ADDR; 807 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 808 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 809 if (ret < 0) { 810 trace_kvm_failed_vpa_addr_set(strerror(errno)); 811 return ret; 812 } 813 } 814 815 assert((uintptr_t)&spapr_cpu->slb_shadow_size 816 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8)); 817 reg.id = KVM_REG_PPC_VPA_SLB; 818 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr; 819 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 820 if (ret < 0) { 821 trace_kvm_failed_slb_set(strerror(errno)); 822 return ret; 823 } 824 825 assert((uintptr_t)&spapr_cpu->dtl_size 826 == ((uintptr_t)&spapr_cpu->dtl_addr + 8)); 827 reg.id = KVM_REG_PPC_VPA_DTL; 828 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr; 829 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 830 if (ret < 0) { 831 trace_kvm_failed_dtl_set(strerror(errno)); 832 return ret; 833 } 834 835 if (!spapr_cpu->vpa_addr) { 836 reg.id = KVM_REG_PPC_VPA_ADDR; 837 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr; 838 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 839 if (ret < 0) { 840 trace_kvm_failed_null_vpa_addr_set(strerror(errno)); 841 return ret; 842 } 843 } 844 845 return 0; 846 } 847 #endif /* TARGET_PPC64 */ 848 849 int kvmppc_put_books_sregs(PowerPCCPU *cpu) 850 { 851 CPUPPCState *env = &cpu->env; 852 struct kvm_sregs sregs = { }; 853 int i; 854 855 sregs.pvr = env->spr[SPR_PVR]; 856 857 if (cpu->vhyp) { 858 PPCVirtualHypervisorClass *vhc = 859 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 860 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp); 861 } else { 862 sregs.u.s.sdr1 = env->spr[SPR_SDR1]; 863 } 864 865 /* Sync SLB */ 866 #ifdef TARGET_PPC64 867 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 868 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid; 869 if (env->slb[i].esid & SLB_ESID_V) { 870 sregs.u.s.ppc64.slb[i].slbe |= i; 871 } 872 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid; 873 } 874 #endif 875 876 /* Sync SRs */ 877 for (i = 0; i < 16; i++) { 878 sregs.u.s.ppc32.sr[i] = env->sr[i]; 879 } 880 881 /* Sync BATs */ 882 for (i = 0; i < 8; i++) { 883 /* Beware. We have to swap upper and lower bits here */ 884 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32) 885 | env->DBAT[1][i]; 886 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32) 887 | env->IBAT[1][i]; 888 } 889 890 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); 891 } 892 893 int kvm_arch_put_registers(CPUState *cs, int level) 894 { 895 PowerPCCPU *cpu = POWERPC_CPU(cs); 896 CPUPPCState *env = &cpu->env; 897 struct kvm_regs regs; 898 int ret; 899 int i; 900 901 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 902 if (ret < 0) { 903 return ret; 904 } 905 906 regs.ctr = env->ctr; 907 regs.lr = env->lr; 908 regs.xer = cpu_read_xer(env); 909 regs.msr = env->msr; 910 regs.pc = env->nip; 911 912 regs.srr0 = env->spr[SPR_SRR0]; 913 regs.srr1 = env->spr[SPR_SRR1]; 914 915 regs.sprg0 = env->spr[SPR_SPRG0]; 916 regs.sprg1 = env->spr[SPR_SPRG1]; 917 regs.sprg2 = env->spr[SPR_SPRG2]; 918 regs.sprg3 = env->spr[SPR_SPRG3]; 919 regs.sprg4 = env->spr[SPR_SPRG4]; 920 regs.sprg5 = env->spr[SPR_SPRG5]; 921 regs.sprg6 = env->spr[SPR_SPRG6]; 922 regs.sprg7 = env->spr[SPR_SPRG7]; 923 924 regs.pid = env->spr[SPR_BOOKE_PID]; 925 926 for (i = 0; i < 32; i++) { 927 regs.gpr[i] = env->gpr[i]; 928 } 929 930 regs.cr = 0; 931 for (i = 0; i < 8; i++) { 932 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i)); 933 } 934 935 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); 936 if (ret < 0) { 937 return ret; 938 } 939 940 kvm_put_fp(cs); 941 942 if (env->tlb_dirty) { 943 kvm_sw_tlb_put(cpu); 944 env->tlb_dirty = false; 945 } 946 947 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) { 948 ret = kvmppc_put_books_sregs(cpu); 949 if (ret < 0) { 950 return ret; 951 } 952 } 953 954 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) { 955 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 956 } 957 958 if (cap_one_reg) { 959 int i; 960 961 /* 962 * We deliberately ignore errors here, for kernels which have 963 * the ONE_REG calls, but don't support the specific 964 * registers, there's a reasonable chance things will still 965 * work, at least until we try to migrate. 966 */ 967 for (i = 0; i < 1024; i++) { 968 uint64_t id = env->spr_cb[i].one_reg_id; 969 970 if (id != 0) { 971 kvm_put_one_spr(cs, id, i); 972 } 973 } 974 975 #ifdef TARGET_PPC64 976 if (FIELD_EX64(env->msr, MSR, TS)) { 977 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 978 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 979 } 980 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 981 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 982 } 983 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 984 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 986 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 987 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 988 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 989 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 990 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 991 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 992 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 993 } 994 995 if (cap_papr) { 996 if (kvm_put_vpa(cs) < 0) { 997 trace_kvm_failed_put_vpa(); 998 } 999 } 1000 1001 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 1002 1003 if (level > KVM_PUT_RUNTIME_STATE) { 1004 kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES); 1005 } 1006 #endif /* TARGET_PPC64 */ 1007 } 1008 1009 return ret; 1010 } 1011 1012 static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor) 1013 { 1014 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR]; 1015 } 1016 1017 static int kvmppc_get_booke_sregs(PowerPCCPU *cpu) 1018 { 1019 CPUPPCState *env = &cpu->env; 1020 struct kvm_sregs sregs; 1021 int ret; 1022 1023 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1024 if (ret < 0) { 1025 return ret; 1026 } 1027 1028 if (sregs.u.e.features & KVM_SREGS_E_BASE) { 1029 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; 1030 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; 1031 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; 1032 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; 1033 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; 1034 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; 1035 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; 1036 env->spr[SPR_DECR] = sregs.u.e.dec; 1037 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff; 1038 env->spr[SPR_TBU] = sregs.u.e.tb >> 32; 1039 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; 1040 } 1041 1042 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { 1043 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; 1044 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; 1045 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; 1046 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; 1047 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; 1048 } 1049 1050 if (sregs.u.e.features & KVM_SREGS_E_64) { 1051 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; 1052 } 1053 1054 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { 1055 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; 1056 } 1057 1058 if (sregs.u.e.features & KVM_SREGS_E_IVOR) { 1059 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0]; 1060 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0); 1061 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1]; 1062 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1); 1063 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2]; 1064 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2); 1065 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3]; 1066 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3); 1067 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4]; 1068 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4); 1069 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5]; 1070 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5); 1071 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6]; 1072 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6); 1073 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7]; 1074 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7); 1075 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8]; 1076 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8); 1077 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9]; 1078 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9); 1079 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10]; 1080 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10); 1081 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11]; 1082 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11); 1083 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12]; 1084 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12); 1085 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13]; 1086 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13); 1087 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14]; 1088 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14); 1089 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15]; 1090 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15); 1091 1092 if (sregs.u.e.features & KVM_SREGS_E_SPE) { 1093 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0]; 1094 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32); 1095 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1]; 1096 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33); 1097 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2]; 1098 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34); 1099 } 1100 1101 if (sregs.u.e.features & KVM_SREGS_E_PM) { 1102 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3]; 1103 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35); 1104 } 1105 1106 if (sregs.u.e.features & KVM_SREGS_E_PC) { 1107 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4]; 1108 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36); 1109 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5]; 1110 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37); 1111 } 1112 } 1113 1114 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { 1115 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; 1116 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; 1117 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; 1118 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff; 1119 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; 1120 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; 1121 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32; 1122 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; 1123 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0]; 1124 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1]; 1125 } 1126 1127 if (sregs.u.e.features & KVM_SREGS_EXP) { 1128 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; 1129 } 1130 1131 if (sregs.u.e.features & KVM_SREGS_E_PD) { 1132 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; 1133 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; 1134 } 1135 1136 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) { 1137 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; 1138 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; 1139 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; 1140 1141 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { 1142 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; 1143 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; 1144 } 1145 } 1146 1147 return 0; 1148 } 1149 1150 static int kvmppc_get_books_sregs(PowerPCCPU *cpu) 1151 { 1152 CPUPPCState *env = &cpu->env; 1153 struct kvm_sregs sregs; 1154 int ret; 1155 int i; 1156 1157 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); 1158 if (ret < 0) { 1159 return ret; 1160 } 1161 1162 if (!cpu->vhyp) { 1163 ppc_store_sdr1(env, sregs.u.s.sdr1); 1164 } 1165 1166 /* Sync SLB */ 1167 #ifdef TARGET_PPC64 1168 /* 1169 * The packed SLB array we get from KVM_GET_SREGS only contains 1170 * information about valid entries. So we flush our internal copy 1171 * to get rid of stale ones, then put all valid SLB entries back 1172 * in. 1173 */ 1174 memset(env->slb, 0, sizeof(env->slb)); 1175 for (i = 0; i < ARRAY_SIZE(env->slb); i++) { 1176 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe; 1177 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv; 1178 /* 1179 * Only restore valid entries 1180 */ 1181 if (rb & SLB_ESID_V) { 1182 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs); 1183 } 1184 } 1185 #endif 1186 1187 /* Sync SRs */ 1188 for (i = 0; i < 16; i++) { 1189 env->sr[i] = sregs.u.s.ppc32.sr[i]; 1190 } 1191 1192 /* Sync BATs */ 1193 for (i = 0; i < 8; i++) { 1194 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; 1195 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; 1196 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; 1197 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; 1198 } 1199 1200 return 0; 1201 } 1202 1203 int kvm_arch_get_registers(CPUState *cs) 1204 { 1205 PowerPCCPU *cpu = POWERPC_CPU(cs); 1206 CPUPPCState *env = &cpu->env; 1207 struct kvm_regs regs; 1208 uint32_t cr; 1209 int i, ret; 1210 1211 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); 1212 if (ret < 0) { 1213 return ret; 1214 } 1215 1216 cr = regs.cr; 1217 for (i = 7; i >= 0; i--) { 1218 env->crf[i] = cr & 15; 1219 cr >>= 4; 1220 } 1221 1222 env->ctr = regs.ctr; 1223 env->lr = regs.lr; 1224 cpu_write_xer(env, regs.xer); 1225 env->msr = regs.msr; 1226 env->nip = regs.pc; 1227 1228 env->spr[SPR_SRR0] = regs.srr0; 1229 env->spr[SPR_SRR1] = regs.srr1; 1230 1231 env->spr[SPR_SPRG0] = regs.sprg0; 1232 env->spr[SPR_SPRG1] = regs.sprg1; 1233 env->spr[SPR_SPRG2] = regs.sprg2; 1234 env->spr[SPR_SPRG3] = regs.sprg3; 1235 env->spr[SPR_SPRG4] = regs.sprg4; 1236 env->spr[SPR_SPRG5] = regs.sprg5; 1237 env->spr[SPR_SPRG6] = regs.sprg6; 1238 env->spr[SPR_SPRG7] = regs.sprg7; 1239 1240 env->spr[SPR_BOOKE_PID] = regs.pid; 1241 1242 for (i = 0; i < 32; i++) { 1243 env->gpr[i] = regs.gpr[i]; 1244 } 1245 1246 kvm_get_fp(cs); 1247 1248 if (cap_booke_sregs) { 1249 ret = kvmppc_get_booke_sregs(cpu); 1250 if (ret < 0) { 1251 return ret; 1252 } 1253 } 1254 1255 if (cap_segstate) { 1256 ret = kvmppc_get_books_sregs(cpu); 1257 if (ret < 0) { 1258 return ret; 1259 } 1260 } 1261 1262 if (cap_hior) { 1263 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); 1264 } 1265 1266 if (cap_one_reg) { 1267 int i; 1268 1269 /* 1270 * We deliberately ignore errors here, for kernels which have 1271 * the ONE_REG calls, but don't support the specific 1272 * registers, there's a reasonable chance things will still 1273 * work, at least until we try to migrate. 1274 */ 1275 for (i = 0; i < 1024; i++) { 1276 uint64_t id = env->spr_cb[i].one_reg_id; 1277 1278 if (id != 0) { 1279 kvm_get_one_spr(cs, id, i); 1280 } 1281 } 1282 1283 #ifdef TARGET_PPC64 1284 if (FIELD_EX64(env->msr, MSR, TS)) { 1285 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { 1286 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); 1287 } 1288 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { 1289 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); 1290 } 1291 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); 1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); 1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); 1294 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); 1295 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); 1296 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); 1297 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); 1298 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); 1299 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); 1300 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); 1301 } 1302 1303 if (cap_papr) { 1304 if (kvm_get_vpa(cs) < 0) { 1305 trace_kvm_failed_get_vpa(); 1306 } 1307 } 1308 1309 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); 1310 kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES); 1311 #endif 1312 } 1313 1314 return 0; 1315 } 1316 1317 int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) 1318 { 1319 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; 1320 1321 if (irq != PPC_INTERRUPT_EXT) { 1322 return 0; 1323 } 1324 1325 if (!kvm_enabled() || !cap_interrupt_unset) { 1326 return 0; 1327 } 1328 1329 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1330 1331 return 0; 1332 } 1333 1334 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1335 { 1336 return; 1337 } 1338 1339 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1340 { 1341 return MEMTXATTRS_UNSPECIFIED; 1342 } 1343 1344 int kvm_arch_process_async_events(CPUState *cs) 1345 { 1346 return cs->halted; 1347 } 1348 1349 static int kvmppc_handle_halt(PowerPCCPU *cpu) 1350 { 1351 CPUState *cs = CPU(cpu); 1352 CPUPPCState *env = &cpu->env; 1353 1354 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && 1355 FIELD_EX64(env->msr, MSR, EE)) { 1356 cs->halted = 1; 1357 cs->exception_index = EXCP_HLT; 1358 } 1359 1360 return 0; 1361 } 1362 1363 /* map dcr access to existing qemu dcr emulation */ 1364 static int kvmppc_handle_dcr_read(CPUPPCState *env, 1365 uint32_t dcrn, uint32_t *data) 1366 { 1367 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) { 1368 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); 1369 } 1370 1371 return 0; 1372 } 1373 1374 static int kvmppc_handle_dcr_write(CPUPPCState *env, 1375 uint32_t dcrn, uint32_t data) 1376 { 1377 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) { 1378 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); 1379 } 1380 1381 return 0; 1382 } 1383 1384 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1385 { 1386 /* Mixed endian case is not handled */ 1387 uint32_t sc = debug_inst_opcode; 1388 1389 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1390 sizeof(sc), 0) || 1391 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) { 1392 return -EINVAL; 1393 } 1394 1395 return 0; 1396 } 1397 1398 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) 1399 { 1400 uint32_t sc; 1401 1402 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) || 1403 sc != debug_inst_opcode || 1404 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1405 sizeof(sc), 1)) { 1406 return -EINVAL; 1407 } 1408 1409 return 0; 1410 } 1411 1412 static int find_hw_breakpoint(target_ulong addr, int type) 1413 { 1414 int n; 1415 1416 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1417 <= ARRAY_SIZE(hw_debug_points)); 1418 1419 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1420 if (hw_debug_points[n].addr == addr && 1421 hw_debug_points[n].type == type) { 1422 return n; 1423 } 1424 } 1425 1426 return -1; 1427 } 1428 1429 static int find_hw_watchpoint(target_ulong addr, int *flag) 1430 { 1431 int n; 1432 1433 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS); 1434 if (n >= 0) { 1435 *flag = BP_MEM_ACCESS; 1436 return n; 1437 } 1438 1439 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE); 1440 if (n >= 0) { 1441 *flag = BP_MEM_WRITE; 1442 return n; 1443 } 1444 1445 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ); 1446 if (n >= 0) { 1447 *flag = BP_MEM_READ; 1448 return n; 1449 } 1450 1451 return -1; 1452 } 1453 1454 int kvm_arch_insert_hw_breakpoint(target_ulong addr, 1455 target_ulong len, int type) 1456 { 1457 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) { 1458 return -ENOBUFS; 1459 } 1460 1461 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr; 1462 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type; 1463 1464 switch (type) { 1465 case GDB_BREAKPOINT_HW: 1466 if (nb_hw_breakpoint >= max_hw_breakpoint) { 1467 return -ENOBUFS; 1468 } 1469 1470 if (find_hw_breakpoint(addr, type) >= 0) { 1471 return -EEXIST; 1472 } 1473 1474 nb_hw_breakpoint++; 1475 break; 1476 1477 case GDB_WATCHPOINT_WRITE: 1478 case GDB_WATCHPOINT_READ: 1479 case GDB_WATCHPOINT_ACCESS: 1480 if (nb_hw_watchpoint >= max_hw_watchpoint) { 1481 return -ENOBUFS; 1482 } 1483 1484 if (find_hw_breakpoint(addr, type) >= 0) { 1485 return -EEXIST; 1486 } 1487 1488 nb_hw_watchpoint++; 1489 break; 1490 1491 default: 1492 return -ENOSYS; 1493 } 1494 1495 return 0; 1496 } 1497 1498 int kvm_arch_remove_hw_breakpoint(target_ulong addr, 1499 target_ulong len, int type) 1500 { 1501 int n; 1502 1503 n = find_hw_breakpoint(addr, type); 1504 if (n < 0) { 1505 return -ENOENT; 1506 } 1507 1508 switch (type) { 1509 case GDB_BREAKPOINT_HW: 1510 nb_hw_breakpoint--; 1511 break; 1512 1513 case GDB_WATCHPOINT_WRITE: 1514 case GDB_WATCHPOINT_READ: 1515 case GDB_WATCHPOINT_ACCESS: 1516 nb_hw_watchpoint--; 1517 break; 1518 1519 default: 1520 return -ENOSYS; 1521 } 1522 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint]; 1523 1524 return 0; 1525 } 1526 1527 void kvm_arch_remove_all_hw_breakpoints(void) 1528 { 1529 nb_hw_breakpoint = nb_hw_watchpoint = 0; 1530 } 1531 1532 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) 1533 { 1534 int n; 1535 1536 /* Software Breakpoint updates */ 1537 if (kvm_sw_breakpoints_active(cs)) { 1538 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; 1539 } 1540 1541 assert((nb_hw_breakpoint + nb_hw_watchpoint) 1542 <= ARRAY_SIZE(hw_debug_points)); 1543 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp)); 1544 1545 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1546 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; 1547 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp)); 1548 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { 1549 switch (hw_debug_points[n].type) { 1550 case GDB_BREAKPOINT_HW: 1551 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT; 1552 break; 1553 case GDB_WATCHPOINT_WRITE: 1554 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE; 1555 break; 1556 case GDB_WATCHPOINT_READ: 1557 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ; 1558 break; 1559 case GDB_WATCHPOINT_ACCESS: 1560 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE | 1561 KVMPPC_DEBUG_WATCH_READ; 1562 break; 1563 default: 1564 cpu_abort(cs, "Unsupported breakpoint type\n"); 1565 } 1566 dbg->arch.bp[n].addr = hw_debug_points[n].addr; 1567 } 1568 } 1569 } 1570 1571 static int kvm_handle_hw_breakpoint(CPUState *cs, 1572 struct kvm_debug_exit_arch *arch_info) 1573 { 1574 int handle = DEBUG_RETURN_GUEST; 1575 int n; 1576 int flag = 0; 1577 1578 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { 1579 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) { 1580 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW); 1581 if (n >= 0) { 1582 handle = DEBUG_RETURN_GDB; 1583 } 1584 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ | 1585 KVMPPC_DEBUG_WATCH_WRITE)) { 1586 n = find_hw_watchpoint(arch_info->address, &flag); 1587 if (n >= 0) { 1588 handle = DEBUG_RETURN_GDB; 1589 cs->watchpoint_hit = &hw_watchpoint; 1590 hw_watchpoint.vaddr = hw_debug_points[n].addr; 1591 hw_watchpoint.flags = flag; 1592 } 1593 } 1594 } 1595 return handle; 1596 } 1597 1598 static int kvm_handle_singlestep(void) 1599 { 1600 return DEBUG_RETURN_GDB; 1601 } 1602 1603 static int kvm_handle_sw_breakpoint(void) 1604 { 1605 return DEBUG_RETURN_GDB; 1606 } 1607 1608 static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run) 1609 { 1610 CPUState *cs = CPU(cpu); 1611 CPUPPCState *env = &cpu->env; 1612 struct kvm_debug_exit_arch *arch_info = &run->debug.arch; 1613 1614 if (cs->singlestep_enabled) { 1615 return kvm_handle_singlestep(); 1616 } 1617 1618 if (arch_info->status) { 1619 return kvm_handle_hw_breakpoint(cs, arch_info); 1620 } 1621 1622 if (kvm_find_sw_breakpoint(cs, arch_info->address)) { 1623 return kvm_handle_sw_breakpoint(); 1624 } 1625 1626 /* 1627 * QEMU is not able to handle debug exception, so inject 1628 * program exception to guest; 1629 * Yes program exception NOT debug exception !! 1630 * When QEMU is using debug resources then debug exception must 1631 * be always set. To achieve this we set MSR_DE and also set 1632 * MSRP_DEP so guest cannot change MSR_DE. 1633 * When emulating debug resource for guest we want guest 1634 * to control MSR_DE (enable/disable debug interrupt on need). 1635 * Supporting both configurations are NOT possible. 1636 * So the result is that we cannot share debug resources 1637 * between QEMU and Guest on BOOKE architecture. 1638 * In the current design QEMU gets the priority over guest, 1639 * this means that if QEMU is using debug resources then guest 1640 * cannot use them; 1641 * For software breakpoint QEMU uses a privileged instruction; 1642 * So there cannot be any reason that we are here for guest 1643 * set debug exception, only possibility is guest executed a 1644 * privileged / illegal instruction and that's why we are 1645 * injecting a program interrupt. 1646 */ 1647 cpu_synchronize_state(cs); 1648 /* 1649 * env->nip is PC, so increment this by 4 to use 1650 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4. 1651 */ 1652 env->nip += 4; 1653 cs->exception_index = POWERPC_EXCP_PROGRAM; 1654 env->error_code = POWERPC_EXCP_INVAL; 1655 ppc_cpu_do_interrupt(cs); 1656 1657 return DEBUG_RETURN_GUEST; 1658 } 1659 1660 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1661 { 1662 PowerPCCPU *cpu = POWERPC_CPU(cs); 1663 CPUPPCState *env = &cpu->env; 1664 int ret; 1665 1666 qemu_mutex_lock_iothread(); 1667 1668 switch (run->exit_reason) { 1669 case KVM_EXIT_DCR: 1670 if (run->dcr.is_write) { 1671 trace_kvm_handle_dcr_write(); 1672 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); 1673 } else { 1674 trace_kvm_handle_dcr_read(); 1675 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); 1676 } 1677 break; 1678 case KVM_EXIT_HLT: 1679 trace_kvm_handle_halt(); 1680 ret = kvmppc_handle_halt(cpu); 1681 break; 1682 #if defined(TARGET_PPC64) 1683 case KVM_EXIT_PAPR_HCALL: 1684 trace_kvm_handle_papr_hcall(run->papr_hcall.nr); 1685 run->papr_hcall.ret = spapr_hypercall(cpu, 1686 run->papr_hcall.nr, 1687 run->papr_hcall.args); 1688 ret = 0; 1689 break; 1690 #endif 1691 case KVM_EXIT_EPR: 1692 trace_kvm_handle_epr(); 1693 run->epr.epr = ldl_phys(cs->as, env->mpic_iack); 1694 ret = 0; 1695 break; 1696 case KVM_EXIT_WATCHDOG: 1697 trace_kvm_handle_watchdog_expiry(); 1698 watchdog_perform_action(); 1699 ret = 0; 1700 break; 1701 1702 case KVM_EXIT_DEBUG: 1703 trace_kvm_handle_debug_exception(); 1704 if (kvm_handle_debug(cpu, run)) { 1705 ret = EXCP_DEBUG; 1706 break; 1707 } 1708 /* re-enter, this exception was guest-internal */ 1709 ret = 0; 1710 break; 1711 1712 #if defined(TARGET_PPC64) 1713 case KVM_EXIT_NMI: 1714 trace_kvm_handle_nmi_exception(); 1715 ret = kvm_handle_nmi(cpu, run); 1716 break; 1717 #endif 1718 1719 default: 1720 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); 1721 ret = -1; 1722 break; 1723 } 1724 1725 qemu_mutex_unlock_iothread(); 1726 return ret; 1727 } 1728 1729 int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1730 { 1731 CPUState *cs = CPU(cpu); 1732 uint32_t bits = tsr_bits; 1733 struct kvm_one_reg reg = { 1734 .id = KVM_REG_PPC_OR_TSR, 1735 .addr = (uintptr_t) &bits, 1736 }; 1737 1738 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1739 } 1740 1741 int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) 1742 { 1743 1744 CPUState *cs = CPU(cpu); 1745 uint32_t bits = tsr_bits; 1746 struct kvm_one_reg reg = { 1747 .id = KVM_REG_PPC_CLEAR_TSR, 1748 .addr = (uintptr_t) &bits, 1749 }; 1750 1751 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1752 } 1753 1754 int kvmppc_set_tcr(PowerPCCPU *cpu) 1755 { 1756 CPUState *cs = CPU(cpu); 1757 CPUPPCState *env = &cpu->env; 1758 uint32_t tcr = env->spr[SPR_BOOKE_TCR]; 1759 1760 struct kvm_one_reg reg = { 1761 .id = KVM_REG_PPC_TCR, 1762 .addr = (uintptr_t) &tcr, 1763 }; 1764 1765 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); 1766 } 1767 1768 int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu) 1769 { 1770 CPUState *cs = CPU(cpu); 1771 int ret; 1772 1773 if (!kvm_enabled()) { 1774 return -1; 1775 } 1776 1777 if (!cap_ppc_watchdog) { 1778 printf("warning: KVM does not support watchdog"); 1779 return -1; 1780 } 1781 1782 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0); 1783 if (ret < 0) { 1784 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n", 1785 __func__, strerror(-ret)); 1786 return ret; 1787 } 1788 1789 return ret; 1790 } 1791 1792 static int read_cpuinfo(const char *field, char *value, int len) 1793 { 1794 FILE *f; 1795 int ret = -1; 1796 int field_len = strlen(field); 1797 char line[512]; 1798 1799 f = fopen("/proc/cpuinfo", "r"); 1800 if (!f) { 1801 return -1; 1802 } 1803 1804 do { 1805 if (!fgets(line, sizeof(line), f)) { 1806 break; 1807 } 1808 if (!strncmp(line, field, field_len)) { 1809 pstrcpy(value, len, line); 1810 ret = 0; 1811 break; 1812 } 1813 } while (*line); 1814 1815 fclose(f); 1816 1817 return ret; 1818 } 1819 1820 static uint32_t kvmppc_get_tbfreq_procfs(void) 1821 { 1822 char line[512]; 1823 char *ns; 1824 uint32_t tbfreq_fallback = NANOSECONDS_PER_SECOND; 1825 uint32_t tbfreq_procfs; 1826 1827 if (read_cpuinfo("timebase", line, sizeof(line))) { 1828 return tbfreq_fallback; 1829 } 1830 1831 ns = strchr(line, ':'); 1832 if (!ns) { 1833 return tbfreq_fallback; 1834 } 1835 1836 tbfreq_procfs = atoi(++ns); 1837 1838 /* 0 is certainly not acceptable by the guest, return fallback value */ 1839 return tbfreq_procfs ? tbfreq_procfs : tbfreq_fallback; 1840 } 1841 1842 uint32_t kvmppc_get_tbfreq(void) 1843 { 1844 static uint32_t cached_tbfreq; 1845 1846 if (!cached_tbfreq) { 1847 cached_tbfreq = kvmppc_get_tbfreq_procfs(); 1848 } 1849 1850 return cached_tbfreq; 1851 } 1852 1853 bool kvmppc_get_host_serial(char **value) 1854 { 1855 return g_file_get_contents("/proc/device-tree/system-id", value, NULL, 1856 NULL); 1857 } 1858 1859 bool kvmppc_get_host_model(char **value) 1860 { 1861 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL); 1862 } 1863 1864 /* Try to find a device tree node for a CPU with clock-frequency property */ 1865 static int kvmppc_find_cpu_dt(char *buf, int buf_len) 1866 { 1867 struct dirent *dirp; 1868 DIR *dp; 1869 1870 dp = opendir(PROC_DEVTREE_CPU); 1871 if (!dp) { 1872 printf("Can't open directory " PROC_DEVTREE_CPU "\n"); 1873 return -1; 1874 } 1875 1876 buf[0] = '\0'; 1877 while ((dirp = readdir(dp)) != NULL) { 1878 FILE *f; 1879 1880 /* Don't accidentally read from the current and parent directories */ 1881 if (strcmp(dirp->d_name, ".") == 0 || strcmp(dirp->d_name, "..") == 0) { 1882 continue; 1883 } 1884 1885 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU, 1886 dirp->d_name); 1887 f = fopen(buf, "r"); 1888 if (f) { 1889 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name); 1890 fclose(f); 1891 break; 1892 } 1893 buf[0] = '\0'; 1894 } 1895 closedir(dp); 1896 if (buf[0] == '\0') { 1897 printf("Unknown host!\n"); 1898 return -1; 1899 } 1900 1901 return 0; 1902 } 1903 1904 static uint64_t kvmppc_read_int_dt(const char *filename) 1905 { 1906 union { 1907 uint32_t v32; 1908 uint64_t v64; 1909 } u; 1910 FILE *f; 1911 int len; 1912 1913 f = fopen(filename, "rb"); 1914 if (!f) { 1915 return -1; 1916 } 1917 1918 len = fread(&u, 1, sizeof(u), f); 1919 fclose(f); 1920 switch (len) { 1921 case 4: 1922 /* property is a 32-bit quantity */ 1923 return be32_to_cpu(u.v32); 1924 case 8: 1925 return be64_to_cpu(u.v64); 1926 } 1927 1928 return 0; 1929 } 1930 1931 /* 1932 * Read a CPU node property from the host device tree that's a single 1933 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong 1934 * (can't find or open the property, or doesn't understand the format) 1935 */ 1936 static uint64_t kvmppc_read_int_cpu_dt(const char *propname) 1937 { 1938 char buf[PATH_MAX], *tmp; 1939 uint64_t val; 1940 1941 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) { 1942 return -1; 1943 } 1944 1945 tmp = g_strdup_printf("%s/%s", buf, propname); 1946 val = kvmppc_read_int_dt(tmp); 1947 g_free(tmp); 1948 1949 return val; 1950 } 1951 1952 uint64_t kvmppc_get_clockfreq(void) 1953 { 1954 return kvmppc_read_int_cpu_dt("clock-frequency"); 1955 } 1956 1957 static int kvmppc_get_dec_bits(void) 1958 { 1959 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits"); 1960 1961 if (nr_bits > 0) { 1962 return nr_bits; 1963 } 1964 return 0; 1965 } 1966 1967 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo) 1968 { 1969 CPUState *cs = env_cpu(env); 1970 1971 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) && 1972 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { 1973 return 0; 1974 } 1975 1976 return 1; 1977 } 1978 1979 int kvmppc_get_hasidle(CPUPPCState *env) 1980 { 1981 struct kvm_ppc_pvinfo pvinfo; 1982 1983 if (!kvmppc_get_pvinfo(env, &pvinfo) && 1984 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) { 1985 return 1; 1986 } 1987 1988 return 0; 1989 } 1990 1991 int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) 1992 { 1993 uint32_t *hc = (uint32_t *)buf; 1994 struct kvm_ppc_pvinfo pvinfo; 1995 1996 if (!kvmppc_get_pvinfo(env, &pvinfo)) { 1997 memcpy(buf, pvinfo.hcall, buf_len); 1998 return 0; 1999 } 2000 2001 /* 2002 * Fallback to always fail hypercalls regardless of endianness: 2003 * 2004 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian) 2005 * li r3, -1 2006 * b .+8 (becomes nop in wrong endian) 2007 * bswap32(li r3, -1) 2008 */ 2009 2010 hc[0] = cpu_to_be32(0x08000048); 2011 hc[1] = cpu_to_be32(0x3860ffff); 2012 hc[2] = cpu_to_be32(0x48000008); 2013 hc[3] = cpu_to_be32(bswap32(0x3860ffff)); 2014 2015 return 1; 2016 } 2017 2018 static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall) 2019 { 2020 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1); 2021 } 2022 2023 void kvmppc_enable_logical_ci_hcalls(void) 2024 { 2025 /* 2026 * FIXME: it would be nice if we could detect the cases where 2027 * we're using a device which requires the in kernel 2028 * implementation of these hcalls, but the kernel lacks them and 2029 * produce a warning. 2030 */ 2031 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD); 2032 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE); 2033 } 2034 2035 void kvmppc_enable_set_mode_hcall(void) 2036 { 2037 kvmppc_enable_hcall(kvm_state, H_SET_MODE); 2038 } 2039 2040 void kvmppc_enable_clear_ref_mod_hcalls(void) 2041 { 2042 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF); 2043 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD); 2044 } 2045 2046 void kvmppc_enable_h_page_init(void) 2047 { 2048 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT); 2049 } 2050 2051 void kvmppc_enable_h_rpt_invalidate(void) 2052 { 2053 kvmppc_enable_hcall(kvm_state, H_RPT_INVALIDATE); 2054 } 2055 2056 void kvmppc_set_papr(PowerPCCPU *cpu) 2057 { 2058 CPUState *cs = CPU(cpu); 2059 int ret; 2060 2061 if (!kvm_enabled()) { 2062 return; 2063 } 2064 2065 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0); 2066 if (ret) { 2067 error_report("This vCPU type or KVM version does not support PAPR"); 2068 exit(1); 2069 } 2070 2071 /* 2072 * Update the capability flag so we sync the right information 2073 * with kvm 2074 */ 2075 cap_papr = 1; 2076 } 2077 2078 int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr) 2079 { 2080 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr); 2081 } 2082 2083 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) 2084 { 2085 CPUState *cs = CPU(cpu); 2086 int ret; 2087 2088 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy); 2089 if (ret && mpic_proxy) { 2090 error_report("This KVM version does not support EPR"); 2091 exit(1); 2092 } 2093 } 2094 2095 bool kvmppc_get_fwnmi(void) 2096 { 2097 return cap_fwnmi; 2098 } 2099 2100 int kvmppc_set_fwnmi(PowerPCCPU *cpu) 2101 { 2102 CPUState *cs = CPU(cpu); 2103 2104 return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0); 2105 } 2106 2107 int kvmppc_smt_threads(void) 2108 { 2109 return cap_ppc_smt ? cap_ppc_smt : 1; 2110 } 2111 2112 int kvmppc_set_smt_threads(int smt) 2113 { 2114 int ret; 2115 2116 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0); 2117 if (!ret) { 2118 cap_ppc_smt = smt; 2119 } 2120 return ret; 2121 } 2122 2123 void kvmppc_error_append_smt_possible_hint(Error *const *errp) 2124 { 2125 int i; 2126 GString *g; 2127 char *s; 2128 2129 assert(kvm_enabled()); 2130 if (cap_ppc_smt_possible) { 2131 g = g_string_new("Available VSMT modes:"); 2132 for (i = 63; i >= 0; i--) { 2133 if ((1UL << i) & cap_ppc_smt_possible) { 2134 g_string_append_printf(g, " %lu", (1UL << i)); 2135 } 2136 } 2137 s = g_string_free(g, false); 2138 error_append_hint(errp, "%s.\n", s); 2139 g_free(s); 2140 } else { 2141 error_append_hint(errp, 2142 "This KVM seems to be too old to support VSMT.\n"); 2143 } 2144 } 2145 2146 2147 #ifdef TARGET_PPC64 2148 uint64_t kvmppc_vrma_limit(unsigned int hash_shift) 2149 { 2150 struct kvm_ppc_smmu_info info; 2151 long rampagesize, best_page_shift; 2152 int i; 2153 2154 /* 2155 * Find the largest hardware supported page size that's less than 2156 * or equal to the (logical) backing page size of guest RAM 2157 */ 2158 kvm_get_smmu_info(&info, &error_fatal); 2159 rampagesize = qemu_minrampagesize(); 2160 best_page_shift = 0; 2161 2162 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) { 2163 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i]; 2164 2165 if (!sps->page_shift) { 2166 continue; 2167 } 2168 2169 if ((sps->page_shift > best_page_shift) 2170 && ((1UL << sps->page_shift) <= rampagesize)) { 2171 best_page_shift = sps->page_shift; 2172 } 2173 } 2174 2175 return 1ULL << (best_page_shift + hash_shift - 7); 2176 } 2177 #endif 2178 2179 bool kvmppc_spapr_use_multitce(void) 2180 { 2181 return cap_spapr_multitce; 2182 } 2183 2184 int kvmppc_spapr_enable_inkernel_multitce(void) 2185 { 2186 int ret; 2187 2188 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2189 H_PUT_TCE_INDIRECT, 1); 2190 if (!ret) { 2191 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0, 2192 H_STUFF_TCE, 1); 2193 } 2194 2195 return ret; 2196 } 2197 2198 void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift, 2199 uint64_t bus_offset, uint32_t nb_table, 2200 int *pfd, bool need_vfio) 2201 { 2202 long len; 2203 int fd; 2204 void *table; 2205 2206 /* 2207 * Must set fd to -1 so we don't try to munmap when called for 2208 * destroying the table, which the upper layers -will- do 2209 */ 2210 *pfd = -1; 2211 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) { 2212 return NULL; 2213 } 2214 2215 if (cap_spapr_tce_64) { 2216 struct kvm_create_spapr_tce_64 args = { 2217 .liobn = liobn, 2218 .page_shift = page_shift, 2219 .offset = bus_offset >> page_shift, 2220 .size = nb_table, 2221 .flags = 0 2222 }; 2223 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args); 2224 if (fd < 0) { 2225 fprintf(stderr, 2226 "KVM: Failed to create TCE64 table for liobn 0x%x\n", 2227 liobn); 2228 return NULL; 2229 } 2230 } else if (cap_spapr_tce) { 2231 uint64_t window_size = (uint64_t) nb_table << page_shift; 2232 struct kvm_create_spapr_tce args = { 2233 .liobn = liobn, 2234 .window_size = window_size, 2235 }; 2236 if ((window_size != args.window_size) || bus_offset) { 2237 return NULL; 2238 } 2239 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args); 2240 if (fd < 0) { 2241 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n", 2242 liobn); 2243 return NULL; 2244 } 2245 } else { 2246 return NULL; 2247 } 2248 2249 len = nb_table * sizeof(uint64_t); 2250 /* FIXME: round this up to page size */ 2251 2252 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); 2253 if (table == MAP_FAILED) { 2254 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n", 2255 liobn); 2256 close(fd); 2257 return NULL; 2258 } 2259 2260 *pfd = fd; 2261 return table; 2262 } 2263 2264 int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table) 2265 { 2266 long len; 2267 2268 if (fd < 0) { 2269 return -1; 2270 } 2271 2272 len = nb_table * sizeof(uint64_t); 2273 if ((munmap(table, len) < 0) || 2274 (close(fd) < 0)) { 2275 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s", 2276 strerror(errno)); 2277 /* Leak the table */ 2278 } 2279 2280 return 0; 2281 } 2282 2283 int kvmppc_reset_htab(int shift_hint) 2284 { 2285 uint32_t shift = shift_hint; 2286 2287 if (!kvm_enabled()) { 2288 /* Full emulation, tell caller to allocate htab itself */ 2289 return 0; 2290 } 2291 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) { 2292 int ret; 2293 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift); 2294 if (ret == -ENOTTY) { 2295 /* 2296 * At least some versions of PR KVM advertise the 2297 * capability, but don't implement the ioctl(). Oops. 2298 * Return 0 so that we allocate the htab in qemu, as is 2299 * correct for PR. 2300 */ 2301 return 0; 2302 } else if (ret < 0) { 2303 return ret; 2304 } 2305 return shift; 2306 } 2307 2308 /* 2309 * We have a kernel that predates the htab reset calls. For PR 2310 * KVM, we need to allocate the htab ourselves, for an HV KVM of 2311 * this era, it has allocated a 16MB fixed size hash table 2312 * already. 2313 */ 2314 if (kvmppc_is_pr(kvm_state)) { 2315 /* PR - tell caller to allocate htab */ 2316 return 0; 2317 } else { 2318 /* HV - assume 16MB kernel allocated htab */ 2319 return 24; 2320 } 2321 } 2322 2323 static inline uint32_t mfpvr(void) 2324 { 2325 uint32_t pvr; 2326 2327 asm ("mfpvr %0" 2328 : "=r"(pvr)); 2329 return pvr; 2330 } 2331 2332 static void alter_insns(uint64_t *word, uint64_t flags, bool on) 2333 { 2334 if (on) { 2335 *word |= flags; 2336 } else { 2337 *word &= ~flags; 2338 } 2339 } 2340 2341 static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) 2342 { 2343 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2344 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size"); 2345 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size"); 2346 2347 /* Now fix up the class with information we can query from the host */ 2348 pcc->pvr = mfpvr(); 2349 2350 alter_insns(&pcc->insns_flags, PPC_ALTIVEC, 2351 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC); 2352 alter_insns(&pcc->insns_flags2, PPC2_VSX, 2353 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX); 2354 alter_insns(&pcc->insns_flags2, PPC2_DFP, 2355 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP); 2356 2357 if (dcache_size != -1) { 2358 pcc->l1_dcache_size = dcache_size; 2359 } 2360 2361 if (icache_size != -1) { 2362 pcc->l1_icache_size = icache_size; 2363 } 2364 2365 #if defined(TARGET_PPC64) 2366 pcc->radix_page_info = kvm_get_radix_page_info(); 2367 2368 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) { 2369 /* 2370 * POWER9 DD1 has some bugs which make it not really ISA 3.00 2371 * compliant. More importantly, advertising ISA 3.00 2372 * architected mode may prevent guests from activating 2373 * necessary DD1 workarounds. 2374 */ 2375 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07 2376 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05); 2377 } 2378 #endif /* defined(TARGET_PPC64) */ 2379 } 2380 2381 bool kvmppc_has_cap_epr(void) 2382 { 2383 return cap_epr; 2384 } 2385 2386 bool kvmppc_has_cap_fixup_hcalls(void) 2387 { 2388 return cap_fixup_hcalls; 2389 } 2390 2391 bool kvmppc_has_cap_htm(void) 2392 { 2393 return cap_htm; 2394 } 2395 2396 bool kvmppc_has_cap_mmu_radix(void) 2397 { 2398 return cap_mmu_radix; 2399 } 2400 2401 bool kvmppc_has_cap_mmu_hash_v3(void) 2402 { 2403 return cap_mmu_hash_v3; 2404 } 2405 2406 static bool kvmppc_power8_host(void) 2407 { 2408 bool ret = false; 2409 #ifdef TARGET_PPC64 2410 { 2411 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr(); 2412 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) || 2413 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) || 2414 (base_pvr == CPU_POWERPC_POWER8_BASE); 2415 } 2416 #endif /* TARGET_PPC64 */ 2417 return ret; 2418 } 2419 2420 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c) 2421 { 2422 bool l1d_thread_priv_req = !kvmppc_power8_host(); 2423 2424 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) { 2425 return 2; 2426 } else if ((!l1d_thread_priv_req || 2427 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && 2428 (c.character & c.character_mask 2429 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) { 2430 return 1; 2431 } 2432 2433 return 0; 2434 } 2435 2436 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c) 2437 { 2438 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) { 2439 return 2; 2440 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) { 2441 return 1; 2442 } 2443 2444 return 0; 2445 } 2446 2447 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c) 2448 { 2449 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) && 2450 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) && 2451 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) { 2452 return SPAPR_CAP_FIXED_NA; 2453 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) { 2454 return SPAPR_CAP_WORKAROUND; 2455 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) { 2456 return SPAPR_CAP_FIXED_CCD; 2457 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) { 2458 return SPAPR_CAP_FIXED_IBS; 2459 } 2460 2461 return 0; 2462 } 2463 2464 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c) 2465 { 2466 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) { 2467 return 1; 2468 } 2469 return 0; 2470 } 2471 2472 bool kvmppc_has_cap_xive(void) 2473 { 2474 return cap_xive; 2475 } 2476 2477 static void kvmppc_get_cpu_characteristics(KVMState *s) 2478 { 2479 struct kvm_ppc_cpu_char c; 2480 int ret; 2481 2482 /* Assume broken */ 2483 cap_ppc_safe_cache = 0; 2484 cap_ppc_safe_bounds_check = 0; 2485 cap_ppc_safe_indirect_branch = 0; 2486 2487 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR); 2488 if (!ret) { 2489 return; 2490 } 2491 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c); 2492 if (ret < 0) { 2493 return; 2494 } 2495 2496 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c); 2497 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c); 2498 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c); 2499 cap_ppc_count_cache_flush_assist = 2500 parse_cap_ppc_count_cache_flush_assist(c); 2501 } 2502 2503 int kvmppc_get_cap_safe_cache(void) 2504 { 2505 return cap_ppc_safe_cache; 2506 } 2507 2508 int kvmppc_get_cap_safe_bounds_check(void) 2509 { 2510 return cap_ppc_safe_bounds_check; 2511 } 2512 2513 int kvmppc_get_cap_safe_indirect_branch(void) 2514 { 2515 return cap_ppc_safe_indirect_branch; 2516 } 2517 2518 int kvmppc_get_cap_count_cache_flush_assist(void) 2519 { 2520 return cap_ppc_count_cache_flush_assist; 2521 } 2522 2523 bool kvmppc_has_cap_nested_kvm_hv(void) 2524 { 2525 return !!cap_ppc_nested_kvm_hv; 2526 } 2527 2528 int kvmppc_set_cap_nested_kvm_hv(int enable) 2529 { 2530 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable); 2531 } 2532 2533 bool kvmppc_has_cap_spapr_vfio(void) 2534 { 2535 return cap_spapr_vfio; 2536 } 2537 2538 int kvmppc_get_cap_large_decr(void) 2539 { 2540 return cap_large_decr; 2541 } 2542 2543 int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable) 2544 { 2545 CPUState *cs = CPU(cpu); 2546 uint64_t lpcr = 0; 2547 2548 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2549 /* Do we need to modify the LPCR? */ 2550 if (!!(lpcr & LPCR_LD) != !!enable) { 2551 if (enable) { 2552 lpcr |= LPCR_LD; 2553 } else { 2554 lpcr &= ~LPCR_LD; 2555 } 2556 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2557 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr); 2558 2559 if (!!(lpcr & LPCR_LD) != !!enable) { 2560 return -1; 2561 } 2562 } 2563 2564 return 0; 2565 } 2566 2567 int kvmppc_has_cap_rpt_invalidate(void) 2568 { 2569 return cap_rpt_invalidate; 2570 } 2571 2572 PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void) 2573 { 2574 uint32_t host_pvr = mfpvr(); 2575 PowerPCCPUClass *pvr_pcc; 2576 2577 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr); 2578 if (pvr_pcc == NULL) { 2579 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr); 2580 } 2581 2582 return pvr_pcc; 2583 } 2584 2585 static void pseries_machine_class_fixup(ObjectClass *oc, void *opaque) 2586 { 2587 MachineClass *mc = MACHINE_CLASS(oc); 2588 2589 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU; 2590 } 2591 2592 static int kvm_ppc_register_host_cpu_type(void) 2593 { 2594 TypeInfo type_info = { 2595 .name = TYPE_HOST_POWERPC_CPU, 2596 .class_init = kvmppc_host_cpu_class_init, 2597 }; 2598 PowerPCCPUClass *pvr_pcc; 2599 ObjectClass *oc; 2600 DeviceClass *dc; 2601 int i; 2602 2603 pvr_pcc = kvm_ppc_get_host_cpu_class(); 2604 if (pvr_pcc == NULL) { 2605 return -1; 2606 } 2607 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc)); 2608 type_register(&type_info); 2609 /* override TCG default cpu type with 'host' cpu model */ 2610 object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE, 2611 false, NULL); 2612 2613 oc = object_class_by_name(type_info.name); 2614 g_assert(oc); 2615 2616 /* 2617 * Update generic CPU family class alias (e.g. on a POWER8NVL host, 2618 * we want "POWER8" to be a "family" alias that points to the current 2619 * host CPU type, too) 2620 */ 2621 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc)); 2622 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 2623 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) { 2624 char *suffix; 2625 2626 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc)); 2627 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX); 2628 if (suffix) { 2629 *suffix = 0; 2630 } 2631 break; 2632 } 2633 } 2634 2635 return 0; 2636 } 2637 2638 int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function) 2639 { 2640 struct kvm_rtas_token_args args = { 2641 .token = token, 2642 }; 2643 2644 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) { 2645 return -ENOENT; 2646 } 2647 2648 strncpy(args.name, function, sizeof(args.name) - 1); 2649 2650 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args); 2651 } 2652 2653 int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp) 2654 { 2655 struct kvm_get_htab_fd s = { 2656 .flags = write ? KVM_GET_HTAB_WRITE : 0, 2657 .start_index = index, 2658 }; 2659 int ret; 2660 2661 if (!cap_htab_fd) { 2662 error_setg(errp, "KVM version doesn't support %s the HPT", 2663 write ? "writing" : "reading"); 2664 return -ENOTSUP; 2665 } 2666 2667 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s); 2668 if (ret < 0) { 2669 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s", 2670 write ? "writing" : "reading", write ? "to" : "from", 2671 strerror(errno)); 2672 return -errno; 2673 } 2674 2675 return ret; 2676 } 2677 2678 int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns) 2679 { 2680 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2681 uint8_t buf[bufsize]; 2682 ssize_t rc; 2683 2684 do { 2685 rc = read(fd, buf, bufsize); 2686 if (rc < 0) { 2687 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n", 2688 strerror(errno)); 2689 return rc; 2690 } else if (rc) { 2691 uint8_t *buffer = buf; 2692 ssize_t n = rc; 2693 while (n) { 2694 struct kvm_get_htab_header *head = 2695 (struct kvm_get_htab_header *) buffer; 2696 size_t chunksize = sizeof(*head) + 2697 HASH_PTE_SIZE_64 * head->n_valid; 2698 2699 qemu_put_be32(f, head->index); 2700 qemu_put_be16(f, head->n_valid); 2701 qemu_put_be16(f, head->n_invalid); 2702 qemu_put_buffer(f, (void *)(head + 1), 2703 HASH_PTE_SIZE_64 * head->n_valid); 2704 2705 buffer += chunksize; 2706 n -= chunksize; 2707 } 2708 } 2709 } while ((rc != 0) 2710 && ((max_ns < 0) || 2711 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns))); 2712 2713 return (rc == 0) ? 1 : 0; 2714 } 2715 2716 int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, 2717 uint16_t n_valid, uint16_t n_invalid, Error **errp) 2718 { 2719 struct kvm_get_htab_header *buf; 2720 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64; 2721 ssize_t rc; 2722 2723 buf = alloca(chunksize); 2724 buf->index = index; 2725 buf->n_valid = n_valid; 2726 buf->n_invalid = n_invalid; 2727 2728 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid); 2729 2730 rc = write(fd, buf, chunksize); 2731 if (rc < 0) { 2732 error_setg_errno(errp, errno, "Error writing the KVM hash table"); 2733 return -errno; 2734 } 2735 if (rc != chunksize) { 2736 /* We should never get a short write on a single chunk */ 2737 error_setg(errp, "Short write while restoring the KVM hash table"); 2738 return -ENOSPC; 2739 } 2740 return 0; 2741 } 2742 2743 bool kvm_arch_stop_on_emulation_error(CPUState *cpu) 2744 { 2745 return true; 2746 } 2747 2748 void kvm_arch_init_irq_routing(KVMState *s) 2749 { 2750 } 2751 2752 void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n) 2753 { 2754 int fd, rc; 2755 int i; 2756 2757 fd = kvmppc_get_htab_fd(false, ptex, &error_abort); 2758 2759 i = 0; 2760 while (i < n) { 2761 struct kvm_get_htab_header *hdr; 2762 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP; 2763 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64]; 2764 2765 rc = read(fd, buf, sizeof(buf)); 2766 if (rc < 0) { 2767 hw_error("kvmppc_read_hptes: Unable to read HPTEs"); 2768 } 2769 2770 hdr = (struct kvm_get_htab_header *)buf; 2771 while ((i < n) && ((char *)hdr < (buf + rc))) { 2772 int invalid = hdr->n_invalid, valid = hdr->n_valid; 2773 2774 if (hdr->index != (ptex + i)) { 2775 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32 2776 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i); 2777 } 2778 2779 if (n - i < valid) { 2780 valid = n - i; 2781 } 2782 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid); 2783 i += valid; 2784 2785 if ((n - i) < invalid) { 2786 invalid = n - i; 2787 } 2788 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64); 2789 i += invalid; 2790 2791 hdr = (struct kvm_get_htab_header *) 2792 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid); 2793 } 2794 } 2795 2796 close(fd); 2797 } 2798 2799 void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1) 2800 { 2801 int fd, rc; 2802 struct { 2803 struct kvm_get_htab_header hdr; 2804 uint64_t pte0; 2805 uint64_t pte1; 2806 } buf; 2807 2808 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort); 2809 2810 buf.hdr.n_valid = 1; 2811 buf.hdr.n_invalid = 0; 2812 buf.hdr.index = ptex; 2813 buf.pte0 = cpu_to_be64(pte0); 2814 buf.pte1 = cpu_to_be64(pte1); 2815 2816 rc = write(fd, &buf, sizeof(buf)); 2817 if (rc != sizeof(buf)) { 2818 hw_error("kvmppc_write_hpte: Unable to update KVM HPT"); 2819 } 2820 close(fd); 2821 } 2822 2823 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 2824 uint64_t address, uint32_t data, PCIDevice *dev) 2825 { 2826 return 0; 2827 } 2828 2829 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 2830 int vector, PCIDevice *dev) 2831 { 2832 return 0; 2833 } 2834 2835 int kvm_arch_release_virq_post(int virq) 2836 { 2837 return 0; 2838 } 2839 2840 int kvm_arch_msi_data_to_gsi(uint32_t data) 2841 { 2842 return data & 0xffff; 2843 } 2844 2845 #if defined(TARGET_PPC64) 2846 int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run) 2847 { 2848 uint16_t flags = run->flags & KVM_RUN_PPC_NMI_DISP_MASK; 2849 2850 cpu_synchronize_state(CPU(cpu)); 2851 2852 spapr_mce_req_event(cpu, flags == KVM_RUN_PPC_NMI_DISP_FULLY_RECOV); 2853 2854 return 0; 2855 } 2856 #endif 2857 2858 int kvmppc_enable_hwrng(void) 2859 { 2860 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) { 2861 return -1; 2862 } 2863 2864 return kvmppc_enable_hcall(kvm_state, H_RANDOM); 2865 } 2866 2867 void kvmppc_check_papr_resize_hpt(Error **errp) 2868 { 2869 if (!kvm_enabled()) { 2870 return; /* No KVM, we're good */ 2871 } 2872 2873 if (cap_resize_hpt) { 2874 return; /* Kernel has explicit support, we're good */ 2875 } 2876 2877 /* Otherwise fallback on looking for PR KVM */ 2878 if (kvmppc_is_pr(kvm_state)) { 2879 return; 2880 } 2881 2882 error_setg(errp, 2883 "Hash page table resizing not available with this KVM version"); 2884 } 2885 2886 int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift) 2887 { 2888 CPUState *cs = CPU(cpu); 2889 struct kvm_ppc_resize_hpt rhpt = { 2890 .flags = flags, 2891 .shift = shift, 2892 }; 2893 2894 if (!cap_resize_hpt) { 2895 return -ENOSYS; 2896 } 2897 2898 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt); 2899 } 2900 2901 int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift) 2902 { 2903 CPUState *cs = CPU(cpu); 2904 struct kvm_ppc_resize_hpt rhpt = { 2905 .flags = flags, 2906 .shift = shift, 2907 }; 2908 2909 if (!cap_resize_hpt) { 2910 return -ENOSYS; 2911 } 2912 2913 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt); 2914 } 2915 2916 /* 2917 * This is a helper function to detect a post migration scenario 2918 * in which a guest, running as KVM-HV, freezes in cpu_post_load because 2919 * the guest kernel can't handle a PVR value other than the actual host 2920 * PVR in KVM_SET_SREGS, even if pvr_match() returns true. 2921 * 2922 * If we don't have cap_ppc_pvr_compat and we're not running in PR 2923 * (so, we're HV), return true. The workaround itself is done in 2924 * cpu_post_load. 2925 * 2926 * The order here is important: we'll only check for KVM PR as a 2927 * fallback if the guest kernel can't handle the situation itself. 2928 * We need to avoid as much as possible querying the running KVM type 2929 * in QEMU level. 2930 */ 2931 bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu) 2932 { 2933 CPUState *cs = CPU(cpu); 2934 2935 if (!kvm_enabled()) { 2936 return false; 2937 } 2938 2939 if (cap_ppc_pvr_compat) { 2940 return false; 2941 } 2942 2943 return !kvmppc_is_pr(cs->kvm_state); 2944 } 2945 2946 void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online) 2947 { 2948 CPUState *cs = CPU(cpu); 2949 2950 if (kvm_enabled()) { 2951 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online); 2952 } 2953 } 2954 2955 void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset) 2956 { 2957 CPUState *cs = CPU(cpu); 2958 2959 if (kvm_enabled()) { 2960 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset); 2961 } 2962 } 2963 2964 bool kvm_arch_cpu_check_are_resettable(void) 2965 { 2966 return true; 2967 } 2968 2969 void kvm_arch_accel_class_init(ObjectClass *oc) 2970 { 2971 } 2972