1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "exec/exec-all.h" 5 #include "hw/hw.h" 6 #include "hw/boards.h" 7 #include "sysemu/kvm.h" 8 #include "helper_regs.h" 9 #include "mmu-hash64.h" 10 #include "migration/cpu.h" 11 12 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) 13 { 14 PowerPCCPU *cpu = opaque; 15 CPUPPCState *env = &cpu->env; 16 unsigned int i, j; 17 target_ulong sdr1; 18 uint32_t fpscr; 19 target_ulong xer; 20 21 for (i = 0; i < 32; i++) 22 qemu_get_betls(f, &env->gpr[i]); 23 #if !defined(TARGET_PPC64) 24 for (i = 0; i < 32; i++) 25 qemu_get_betls(f, &env->gprh[i]); 26 #endif 27 qemu_get_betls(f, &env->lr); 28 qemu_get_betls(f, &env->ctr); 29 for (i = 0; i < 8; i++) 30 qemu_get_be32s(f, &env->crf[i]); 31 qemu_get_betls(f, &xer); 32 cpu_write_xer(env, xer); 33 qemu_get_betls(f, &env->reserve_addr); 34 qemu_get_betls(f, &env->msr); 35 for (i = 0; i < 4; i++) 36 qemu_get_betls(f, &env->tgpr[i]); 37 for (i = 0; i < 32; i++) { 38 union { 39 float64 d; 40 uint64_t l; 41 } u; 42 u.l = qemu_get_be64(f); 43 env->fpr[i] = u.d; 44 } 45 qemu_get_be32s(f, &fpscr); 46 env->fpscr = fpscr; 47 qemu_get_sbe32s(f, &env->access_type); 48 #if defined(TARGET_PPC64) 49 qemu_get_betls(f, &env->spr[SPR_ASR]); 50 qemu_get_sbe32s(f, &env->slb_nr); 51 #endif 52 qemu_get_betls(f, &sdr1); 53 for (i = 0; i < 32; i++) 54 qemu_get_betls(f, &env->sr[i]); 55 for (i = 0; i < 2; i++) 56 for (j = 0; j < 8; j++) 57 qemu_get_betls(f, &env->DBAT[i][j]); 58 for (i = 0; i < 2; i++) 59 for (j = 0; j < 8; j++) 60 qemu_get_betls(f, &env->IBAT[i][j]); 61 qemu_get_sbe32s(f, &env->nb_tlb); 62 qemu_get_sbe32s(f, &env->tlb_per_way); 63 qemu_get_sbe32s(f, &env->nb_ways); 64 qemu_get_sbe32s(f, &env->last_way); 65 qemu_get_sbe32s(f, &env->id_tlbs); 66 qemu_get_sbe32s(f, &env->nb_pids); 67 if (env->tlb.tlb6) { 68 // XXX assumes 6xx 69 for (i = 0; i < env->nb_tlb; i++) { 70 qemu_get_betls(f, &env->tlb.tlb6[i].pte0); 71 qemu_get_betls(f, &env->tlb.tlb6[i].pte1); 72 qemu_get_betls(f, &env->tlb.tlb6[i].EPN); 73 } 74 } 75 for (i = 0; i < 4; i++) 76 qemu_get_betls(f, &env->pb[i]); 77 for (i = 0; i < 1024; i++) 78 qemu_get_betls(f, &env->spr[i]); 79 if (!env->external_htab) { 80 ppc_store_sdr1(env, sdr1); 81 } 82 qemu_get_be32s(f, &env->vscr); 83 qemu_get_be64s(f, &env->spe_acc); 84 qemu_get_be32s(f, &env->spe_fscr); 85 qemu_get_betls(f, &env->msr_mask); 86 qemu_get_be32s(f, &env->flags); 87 qemu_get_sbe32s(f, &env->error_code); 88 qemu_get_be32s(f, &env->pending_interrupts); 89 qemu_get_be32s(f, &env->irq_input_state); 90 for (i = 0; i < POWERPC_EXCP_NB; i++) 91 qemu_get_betls(f, &env->excp_vectors[i]); 92 qemu_get_betls(f, &env->excp_prefix); 93 qemu_get_betls(f, &env->ivor_mask); 94 qemu_get_betls(f, &env->ivpr_mask); 95 qemu_get_betls(f, &env->hreset_vector); 96 qemu_get_betls(f, &env->nip); 97 qemu_get_betls(f, &env->hflags); 98 qemu_get_betls(f, &env->hflags_nmsr); 99 qemu_get_sbe32(f); /* Discard unused mmu_idx */ 100 qemu_get_sbe32(f); /* Discard unused power_mode */ 101 102 /* Recompute mmu indices */ 103 hreg_compute_mem_idx(env); 104 105 return 0; 106 } 107 108 static int get_avr(QEMUFile *f, void *pv, size_t size) 109 { 110 ppc_avr_t *v = pv; 111 112 v->u64[0] = qemu_get_be64(f); 113 v->u64[1] = qemu_get_be64(f); 114 115 return 0; 116 } 117 118 static void put_avr(QEMUFile *f, void *pv, size_t size) 119 { 120 ppc_avr_t *v = pv; 121 122 qemu_put_be64(f, v->u64[0]); 123 qemu_put_be64(f, v->u64[1]); 124 } 125 126 static const VMStateInfo vmstate_info_avr = { 127 .name = "avr", 128 .get = get_avr, 129 .put = put_avr, 130 }; 131 132 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ 133 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t) 134 135 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ 136 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) 137 138 static bool cpu_pre_2_8_migration(void *opaque, int version_id) 139 { 140 PowerPCCPU *cpu = opaque; 141 142 return cpu->pre_2_8_migration; 143 } 144 145 static void cpu_pre_save(void *opaque) 146 { 147 PowerPCCPU *cpu = opaque; 148 CPUPPCState *env = &cpu->env; 149 int i; 150 uint64_t insns_compat_mask = 151 PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB 152 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES 153 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES 154 | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT 155 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ 156 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC 157 | PPC_64B | PPC_64BX | PPC_ALTIVEC 158 | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; 159 uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX 160 | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 161 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 162 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 163 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 164 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; 165 166 env->spr[SPR_LR] = env->lr; 167 env->spr[SPR_CTR] = env->ctr; 168 env->spr[SPR_XER] = cpu_read_xer(env); 169 #if defined(TARGET_PPC64) 170 env->spr[SPR_CFAR] = env->cfar; 171 #endif 172 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; 173 174 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 175 env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i]; 176 env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i]; 177 env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i]; 178 env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i]; 179 } 180 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 181 env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4]; 182 env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4]; 183 env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4]; 184 env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4]; 185 } 186 187 /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ 188 if (cpu->pre_2_8_migration) { 189 cpu->mig_msr_mask = env->msr_mask; 190 cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; 191 cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; 192 cpu->mig_nb_BATs = env->nb_BATs; 193 } 194 } 195 196 static int cpu_post_load(void *opaque, int version_id) 197 { 198 PowerPCCPU *cpu = opaque; 199 CPUPPCState *env = &cpu->env; 200 int i; 201 target_ulong msr; 202 203 /* 204 * We always ignore the source PVR. The user or management 205 * software has to take care of running QEMU in a compatible mode. 206 */ 207 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; 208 env->lr = env->spr[SPR_LR]; 209 env->ctr = env->spr[SPR_CTR]; 210 cpu_write_xer(env, env->spr[SPR_XER]); 211 #if defined(TARGET_PPC64) 212 env->cfar = env->spr[SPR_CFAR]; 213 #endif 214 env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; 215 216 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 217 env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i]; 218 env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1]; 219 env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i]; 220 env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1]; 221 } 222 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 223 env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i]; 224 env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1]; 225 env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i]; 226 env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1]; 227 } 228 229 if (!env->external_htab) { 230 /* Restore htab_base and htab_mask variables */ 231 ppc_store_sdr1(env, env->spr[SPR_SDR1]); 232 } 233 234 /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */ 235 msr = env->msr; 236 env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB); 237 ppc_store_msr(env, msr); 238 239 hreg_compute_mem_idx(env); 240 241 return 0; 242 } 243 244 static bool fpu_needed(void *opaque) 245 { 246 PowerPCCPU *cpu = opaque; 247 248 return (cpu->env.insns_flags & PPC_FLOAT); 249 } 250 251 static const VMStateDescription vmstate_fpu = { 252 .name = "cpu/fpu", 253 .version_id = 1, 254 .minimum_version_id = 1, 255 .needed = fpu_needed, 256 .fields = (VMStateField[]) { 257 VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32), 258 VMSTATE_UINTTL(env.fpscr, PowerPCCPU), 259 VMSTATE_END_OF_LIST() 260 }, 261 }; 262 263 static bool altivec_needed(void *opaque) 264 { 265 PowerPCCPU *cpu = opaque; 266 267 return (cpu->env.insns_flags & PPC_ALTIVEC); 268 } 269 270 static const VMStateDescription vmstate_altivec = { 271 .name = "cpu/altivec", 272 .version_id = 1, 273 .minimum_version_id = 1, 274 .needed = altivec_needed, 275 .fields = (VMStateField[]) { 276 VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32), 277 VMSTATE_UINT32(env.vscr, PowerPCCPU), 278 VMSTATE_END_OF_LIST() 279 }, 280 }; 281 282 static bool vsx_needed(void *opaque) 283 { 284 PowerPCCPU *cpu = opaque; 285 286 return (cpu->env.insns_flags2 & PPC2_VSX); 287 } 288 289 static const VMStateDescription vmstate_vsx = { 290 .name = "cpu/vsx", 291 .version_id = 1, 292 .minimum_version_id = 1, 293 .needed = vsx_needed, 294 .fields = (VMStateField[]) { 295 VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32), 296 VMSTATE_END_OF_LIST() 297 }, 298 }; 299 300 #ifdef TARGET_PPC64 301 /* Transactional memory state */ 302 static bool tm_needed(void *opaque) 303 { 304 PowerPCCPU *cpu = opaque; 305 CPUPPCState *env = &cpu->env; 306 return msr_ts; 307 } 308 309 static const VMStateDescription vmstate_tm = { 310 .name = "cpu/tm", 311 .version_id = 1, 312 .minimum_version_id = 1, 313 .minimum_version_id_old = 1, 314 .needed = tm_needed, 315 .fields = (VMStateField []) { 316 VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32), 317 VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64), 318 VMSTATE_UINT64(env.tm_cr, PowerPCCPU), 319 VMSTATE_UINT64(env.tm_lr, PowerPCCPU), 320 VMSTATE_UINT64(env.tm_ctr, PowerPCCPU), 321 VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU), 322 VMSTATE_UINT64(env.tm_amr, PowerPCCPU), 323 VMSTATE_UINT64(env.tm_ppr, PowerPCCPU), 324 VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU), 325 VMSTATE_UINT32(env.tm_vscr, PowerPCCPU), 326 VMSTATE_UINT64(env.tm_dscr, PowerPCCPU), 327 VMSTATE_UINT64(env.tm_tar, PowerPCCPU), 328 VMSTATE_END_OF_LIST() 329 }, 330 }; 331 #endif 332 333 static bool sr_needed(void *opaque) 334 { 335 #ifdef TARGET_PPC64 336 PowerPCCPU *cpu = opaque; 337 338 return !(cpu->env.mmu_model & POWERPC_MMU_64); 339 #else 340 return true; 341 #endif 342 } 343 344 static const VMStateDescription vmstate_sr = { 345 .name = "cpu/sr", 346 .version_id = 1, 347 .minimum_version_id = 1, 348 .needed = sr_needed, 349 .fields = (VMStateField[]) { 350 VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), 351 VMSTATE_END_OF_LIST() 352 }, 353 }; 354 355 #ifdef TARGET_PPC64 356 static int get_slbe(QEMUFile *f, void *pv, size_t size) 357 { 358 ppc_slb_t *v = pv; 359 360 v->esid = qemu_get_be64(f); 361 v->vsid = qemu_get_be64(f); 362 363 return 0; 364 } 365 366 static void put_slbe(QEMUFile *f, void *pv, size_t size) 367 { 368 ppc_slb_t *v = pv; 369 370 qemu_put_be64(f, v->esid); 371 qemu_put_be64(f, v->vsid); 372 } 373 374 static const VMStateInfo vmstate_info_slbe = { 375 .name = "slbe", 376 .get = get_slbe, 377 .put = put_slbe, 378 }; 379 380 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ 381 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) 382 383 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \ 384 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) 385 386 static bool slb_needed(void *opaque) 387 { 388 PowerPCCPU *cpu = opaque; 389 390 /* We don't support any of the old segment table based 64-bit CPUs */ 391 return (cpu->env.mmu_model & POWERPC_MMU_64); 392 } 393 394 static int slb_post_load(void *opaque, int version_id) 395 { 396 PowerPCCPU *cpu = opaque; 397 CPUPPCState *env = &cpu->env; 398 int i; 399 400 /* We've pulled in the raw esid and vsid values from the migration 401 * stream, but we need to recompute the page size pointers */ 402 for (i = 0; i < env->slb_nr; i++) { 403 if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) { 404 /* Migration source had bad values in its SLB */ 405 return -1; 406 } 407 } 408 409 return 0; 410 } 411 412 static const VMStateDescription vmstate_slb = { 413 .name = "cpu/slb", 414 .version_id = 1, 415 .minimum_version_id = 1, 416 .needed = slb_needed, 417 .post_load = slb_post_load, 418 .fields = (VMStateField[]) { 419 VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU), 420 VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), 421 VMSTATE_END_OF_LIST() 422 } 423 }; 424 #endif /* TARGET_PPC64 */ 425 426 static const VMStateDescription vmstate_tlb6xx_entry = { 427 .name = "cpu/tlb6xx_entry", 428 .version_id = 1, 429 .minimum_version_id = 1, 430 .fields = (VMStateField[]) { 431 VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), 432 VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), 433 VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), 434 VMSTATE_END_OF_LIST() 435 }, 436 }; 437 438 static bool tlb6xx_needed(void *opaque) 439 { 440 PowerPCCPU *cpu = opaque; 441 CPUPPCState *env = &cpu->env; 442 443 return env->nb_tlb && (env->tlb_type == TLB_6XX); 444 } 445 446 static const VMStateDescription vmstate_tlb6xx = { 447 .name = "cpu/tlb6xx", 448 .version_id = 1, 449 .minimum_version_id = 1, 450 .needed = tlb6xx_needed, 451 .fields = (VMStateField[]) { 452 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), 453 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, 454 env.nb_tlb, 455 vmstate_tlb6xx_entry, 456 ppc6xx_tlb_t), 457 VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), 458 VMSTATE_END_OF_LIST() 459 } 460 }; 461 462 static const VMStateDescription vmstate_tlbemb_entry = { 463 .name = "cpu/tlbemb_entry", 464 .version_id = 1, 465 .minimum_version_id = 1, 466 .fields = (VMStateField[]) { 467 VMSTATE_UINT64(RPN, ppcemb_tlb_t), 468 VMSTATE_UINTTL(EPN, ppcemb_tlb_t), 469 VMSTATE_UINTTL(PID, ppcemb_tlb_t), 470 VMSTATE_UINTTL(size, ppcemb_tlb_t), 471 VMSTATE_UINT32(prot, ppcemb_tlb_t), 472 VMSTATE_UINT32(attr, ppcemb_tlb_t), 473 VMSTATE_END_OF_LIST() 474 }, 475 }; 476 477 static bool tlbemb_needed(void *opaque) 478 { 479 PowerPCCPU *cpu = opaque; 480 CPUPPCState *env = &cpu->env; 481 482 return env->nb_tlb && (env->tlb_type == TLB_EMB); 483 } 484 485 static bool pbr403_needed(void *opaque) 486 { 487 PowerPCCPU *cpu = opaque; 488 uint32_t pvr = cpu->env.spr[SPR_PVR]; 489 490 return (pvr & 0xffff0000) == 0x00200000; 491 } 492 493 static const VMStateDescription vmstate_pbr403 = { 494 .name = "cpu/pbr403", 495 .version_id = 1, 496 .minimum_version_id = 1, 497 .needed = pbr403_needed, 498 .fields = (VMStateField[]) { 499 VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4), 500 VMSTATE_END_OF_LIST() 501 }, 502 }; 503 504 static const VMStateDescription vmstate_tlbemb = { 505 .name = "cpu/tlb6xx", 506 .version_id = 1, 507 .minimum_version_id = 1, 508 .needed = tlbemb_needed, 509 .fields = (VMStateField[]) { 510 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), 511 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, 512 env.nb_tlb, 513 vmstate_tlbemb_entry, 514 ppcemb_tlb_t), 515 /* 403 protection registers */ 516 VMSTATE_END_OF_LIST() 517 }, 518 .subsections = (const VMStateDescription*[]) { 519 &vmstate_pbr403, 520 NULL 521 } 522 }; 523 524 static const VMStateDescription vmstate_tlbmas_entry = { 525 .name = "cpu/tlbmas_entry", 526 .version_id = 1, 527 .minimum_version_id = 1, 528 .fields = (VMStateField[]) { 529 VMSTATE_UINT32(mas8, ppcmas_tlb_t), 530 VMSTATE_UINT32(mas1, ppcmas_tlb_t), 531 VMSTATE_UINT64(mas2, ppcmas_tlb_t), 532 VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), 533 VMSTATE_END_OF_LIST() 534 }, 535 }; 536 537 static bool tlbmas_needed(void *opaque) 538 { 539 PowerPCCPU *cpu = opaque; 540 CPUPPCState *env = &cpu->env; 541 542 return env->nb_tlb && (env->tlb_type == TLB_MAS); 543 } 544 545 static const VMStateDescription vmstate_tlbmas = { 546 .name = "cpu/tlbmas", 547 .version_id = 1, 548 .minimum_version_id = 1, 549 .needed = tlbmas_needed, 550 .fields = (VMStateField[]) { 551 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), 552 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, 553 env.nb_tlb, 554 vmstate_tlbmas_entry, 555 ppcmas_tlb_t), 556 VMSTATE_END_OF_LIST() 557 } 558 }; 559 560 const VMStateDescription vmstate_ppc_cpu = { 561 .name = "cpu", 562 .version_id = 5, 563 .minimum_version_id = 5, 564 .minimum_version_id_old = 4, 565 .load_state_old = cpu_load_old, 566 .pre_save = cpu_pre_save, 567 .post_load = cpu_post_load, 568 .fields = (VMStateField[]) { 569 VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */ 570 571 /* User mode architected state */ 572 VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), 573 #if !defined(TARGET_PPC64) 574 VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), 575 #endif 576 VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), 577 VMSTATE_UINTTL(env.nip, PowerPCCPU), 578 579 /* SPRs */ 580 VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), 581 VMSTATE_UINT64(env.spe_acc, PowerPCCPU), 582 583 /* Reservation */ 584 VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), 585 586 /* Supervisor mode architected state */ 587 VMSTATE_UINTTL(env.msr, PowerPCCPU), 588 589 /* Internal state */ 590 VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), 591 /* FIXME: access_type? */ 592 593 /* Sanity checking */ 594 VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), 595 VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration), 596 VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU, 597 cpu_pre_2_8_migration), 598 VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration), 599 VMSTATE_END_OF_LIST() 600 }, 601 .subsections = (const VMStateDescription*[]) { 602 &vmstate_fpu, 603 &vmstate_altivec, 604 &vmstate_vsx, 605 &vmstate_sr, 606 #ifdef TARGET_PPC64 607 &vmstate_tm, 608 &vmstate_slb, 609 #endif /* TARGET_PPC64 */ 610 &vmstate_tlb6xx, 611 &vmstate_tlbemb, 612 &vmstate_tlbmas, 613 NULL 614 } 615 }; 616