1 #include "qemu/osdep.h" 2 #include "qemu-common.h" 3 #include "cpu.h" 4 #include "exec/exec-all.h" 5 #include "hw/hw.h" 6 #include "hw/boards.h" 7 #include "sysemu/kvm.h" 8 #include "helper_regs.h" 9 #include "mmu-hash64.h" 10 #include "migration/cpu.h" 11 #include "qapi/error.h" 12 #include "kvm_ppc.h" 13 14 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) 15 { 16 PowerPCCPU *cpu = opaque; 17 CPUPPCState *env = &cpu->env; 18 unsigned int i, j; 19 target_ulong sdr1; 20 uint32_t fpscr; 21 #if defined(TARGET_PPC64) 22 int32_t slb_nr; 23 #endif 24 target_ulong xer; 25 26 for (i = 0; i < 32; i++) 27 qemu_get_betls(f, &env->gpr[i]); 28 #if !defined(TARGET_PPC64) 29 for (i = 0; i < 32; i++) 30 qemu_get_betls(f, &env->gprh[i]); 31 #endif 32 qemu_get_betls(f, &env->lr); 33 qemu_get_betls(f, &env->ctr); 34 for (i = 0; i < 8; i++) 35 qemu_get_be32s(f, &env->crf[i]); 36 qemu_get_betls(f, &xer); 37 cpu_write_xer(env, xer); 38 qemu_get_betls(f, &env->reserve_addr); 39 qemu_get_betls(f, &env->msr); 40 for (i = 0; i < 4; i++) 41 qemu_get_betls(f, &env->tgpr[i]); 42 for (i = 0; i < 32; i++) { 43 union { 44 float64 d; 45 uint64_t l; 46 } u; 47 u.l = qemu_get_be64(f); 48 env->fpr[i] = u.d; 49 } 50 qemu_get_be32s(f, &fpscr); 51 env->fpscr = fpscr; 52 qemu_get_sbe32s(f, &env->access_type); 53 #if defined(TARGET_PPC64) 54 qemu_get_betls(f, &env->spr[SPR_ASR]); 55 qemu_get_sbe32s(f, &slb_nr); 56 #endif 57 qemu_get_betls(f, &sdr1); 58 for (i = 0; i < 32; i++) 59 qemu_get_betls(f, &env->sr[i]); 60 for (i = 0; i < 2; i++) 61 for (j = 0; j < 8; j++) 62 qemu_get_betls(f, &env->DBAT[i][j]); 63 for (i = 0; i < 2; i++) 64 for (j = 0; j < 8; j++) 65 qemu_get_betls(f, &env->IBAT[i][j]); 66 qemu_get_sbe32s(f, &env->nb_tlb); 67 qemu_get_sbe32s(f, &env->tlb_per_way); 68 qemu_get_sbe32s(f, &env->nb_ways); 69 qemu_get_sbe32s(f, &env->last_way); 70 qemu_get_sbe32s(f, &env->id_tlbs); 71 qemu_get_sbe32s(f, &env->nb_pids); 72 if (env->tlb.tlb6) { 73 // XXX assumes 6xx 74 for (i = 0; i < env->nb_tlb; i++) { 75 qemu_get_betls(f, &env->tlb.tlb6[i].pte0); 76 qemu_get_betls(f, &env->tlb.tlb6[i].pte1); 77 qemu_get_betls(f, &env->tlb.tlb6[i].EPN); 78 } 79 } 80 for (i = 0; i < 4; i++) 81 qemu_get_betls(f, &env->pb[i]); 82 for (i = 0; i < 1024; i++) 83 qemu_get_betls(f, &env->spr[i]); 84 if (!cpu->vhyp) { 85 ppc_store_sdr1(env, sdr1); 86 } 87 qemu_get_be32s(f, &env->vscr); 88 qemu_get_be64s(f, &env->spe_acc); 89 qemu_get_be32s(f, &env->spe_fscr); 90 qemu_get_betls(f, &env->msr_mask); 91 qemu_get_be32s(f, &env->flags); 92 qemu_get_sbe32s(f, &env->error_code); 93 qemu_get_be32s(f, &env->pending_interrupts); 94 qemu_get_be32s(f, &env->irq_input_state); 95 for (i = 0; i < POWERPC_EXCP_NB; i++) 96 qemu_get_betls(f, &env->excp_vectors[i]); 97 qemu_get_betls(f, &env->excp_prefix); 98 qemu_get_betls(f, &env->ivor_mask); 99 qemu_get_betls(f, &env->ivpr_mask); 100 qemu_get_betls(f, &env->hreset_vector); 101 qemu_get_betls(f, &env->nip); 102 qemu_get_betls(f, &env->hflags); 103 qemu_get_betls(f, &env->hflags_nmsr); 104 qemu_get_sbe32(f); /* Discard unused mmu_idx */ 105 qemu_get_sbe32(f); /* Discard unused power_mode */ 106 107 /* Recompute mmu indices */ 108 hreg_compute_mem_idx(env); 109 110 return 0; 111 } 112 113 static int get_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field) 114 { 115 ppc_avr_t *v = pv; 116 117 v->u64[0] = qemu_get_be64(f); 118 v->u64[1] = qemu_get_be64(f); 119 120 return 0; 121 } 122 123 static int put_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field, 124 QJSON *vmdesc) 125 { 126 ppc_avr_t *v = pv; 127 128 qemu_put_be64(f, v->u64[0]); 129 qemu_put_be64(f, v->u64[1]); 130 return 0; 131 } 132 133 static const VMStateInfo vmstate_info_avr = { 134 .name = "avr", 135 .get = get_avr, 136 .put = put_avr, 137 }; 138 139 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ 140 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t) 141 142 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ 143 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) 144 145 static bool cpu_pre_2_8_migration(void *opaque, int version_id) 146 { 147 PowerPCCPU *cpu = opaque; 148 149 return cpu->pre_2_8_migration; 150 } 151 152 #if defined(TARGET_PPC64) 153 static bool cpu_pre_2_13_migration(void *opaque, int version_id) 154 { 155 PowerPCCPU *cpu = opaque; 156 157 return cpu->pre_2_13_migration; 158 } 159 #endif 160 161 static int cpu_pre_save(void *opaque) 162 { 163 PowerPCCPU *cpu = opaque; 164 CPUPPCState *env = &cpu->env; 165 int i; 166 uint64_t insns_compat_mask = 167 PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB 168 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES 169 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES 170 | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT 171 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ 172 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC 173 | PPC_64B | PPC_64BX | PPC_ALTIVEC 174 | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; 175 uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX 176 | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 177 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 178 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 179 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 180 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; 181 182 env->spr[SPR_LR] = env->lr; 183 env->spr[SPR_CTR] = env->ctr; 184 env->spr[SPR_XER] = cpu_read_xer(env); 185 #if defined(TARGET_PPC64) 186 env->spr[SPR_CFAR] = env->cfar; 187 #endif 188 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; 189 190 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 191 env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i]; 192 env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i]; 193 env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i]; 194 env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i]; 195 } 196 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 197 env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4]; 198 env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4]; 199 env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4]; 200 env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4]; 201 } 202 203 /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ 204 if (cpu->pre_2_8_migration) { 205 /* Mask out bits that got added to msr_mask since the versions 206 * which stupidly included it in the migration stream. */ 207 target_ulong metamask = 0 208 #if defined(TARGET_PPC64) 209 | (1ULL << MSR_TS0) 210 | (1ULL << MSR_TS1) 211 #endif 212 ; 213 cpu->mig_msr_mask = env->msr_mask & ~metamask; 214 cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; 215 cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; 216 cpu->mig_nb_BATs = env->nb_BATs; 217 } 218 if (cpu->pre_2_13_migration) { 219 if (cpu->hash64_opts) { 220 cpu->mig_slb_nr = cpu->hash64_opts->slb_size; 221 } 222 } 223 224 return 0; 225 } 226 227 /* 228 * Determine if a given PVR is a "close enough" match to the CPU 229 * object. For TCG and KVM PR it would probably be sufficient to 230 * require an exact PVR match. However for KVM HV the user is 231 * restricted to a PVR exactly matching the host CPU. The correct way 232 * to handle this is to put the guest into an architected 233 * compatibility mode. However, to allow a more forgiving transition 234 * and migration from before this was widely done, we allow migration 235 * between sufficiently similar PVRs, as determined by the CPU class's 236 * pvr_match() hook. 237 */ 238 static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr) 239 { 240 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 241 242 if (pvr == pcc->pvr) { 243 return true; 244 } 245 return pcc->pvr_match(pcc, pvr); 246 } 247 248 static int cpu_post_load(void *opaque, int version_id) 249 { 250 PowerPCCPU *cpu = opaque; 251 CPUPPCState *env = &cpu->env; 252 int i; 253 target_ulong msr; 254 255 /* 256 * If we're operating in compat mode, we should be ok as long as 257 * the destination supports the same compatiblity mode. 258 * 259 * Otherwise, however, we require that the destination has exactly 260 * the same CPU model as the source. 261 */ 262 263 #if defined(TARGET_PPC64) 264 if (cpu->compat_pvr) { 265 uint32_t compat_pvr = cpu->compat_pvr; 266 Error *local_err = NULL; 267 268 cpu->compat_pvr = 0; 269 ppc_set_compat(cpu, compat_pvr, &local_err); 270 if (local_err) { 271 error_report_err(local_err); 272 return -1; 273 } 274 } else 275 #endif 276 { 277 if (!pvr_match(cpu, env->spr[SPR_PVR])) { 278 return -1; 279 } 280 } 281 282 /* 283 * If we're running with KVM HV, there is a chance that the guest 284 * is running with KVM HV and its kernel does not have the 285 * capability of dealing with a different PVR other than this 286 * exact host PVR in KVM_SET_SREGS. If that happens, the 287 * guest freezes after migration. 288 * 289 * The function kvmppc_pvr_workaround_required does this verification 290 * by first checking if the kernel has the cap, returning true immediately 291 * if that is the case. Otherwise, it checks if we're running in KVM PR. 292 * If the guest kernel does not have the cap and we're not running KVM-PR 293 * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will 294 * receive the PVR it expects as a workaround. 295 * 296 */ 297 #if defined(CONFIG_KVM) 298 if (kvmppc_pvr_workaround_required(cpu)) { 299 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; 300 } 301 #endif 302 303 env->lr = env->spr[SPR_LR]; 304 env->ctr = env->spr[SPR_CTR]; 305 cpu_write_xer(env, env->spr[SPR_XER]); 306 #if defined(TARGET_PPC64) 307 env->cfar = env->spr[SPR_CFAR]; 308 #endif 309 env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; 310 311 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 312 env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i]; 313 env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1]; 314 env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i]; 315 env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1]; 316 } 317 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) { 318 env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i]; 319 env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1]; 320 env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i]; 321 env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1]; 322 } 323 324 if (!cpu->vhyp) { 325 ppc_store_sdr1(env, env->spr[SPR_SDR1]); 326 } 327 328 /* Invalidate all supported msr bits except MSR_TGPR/MSR_HVB before restoring */ 329 msr = env->msr; 330 env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); 331 ppc_store_msr(env, msr); 332 333 hreg_compute_mem_idx(env); 334 335 return 0; 336 } 337 338 static bool fpu_needed(void *opaque) 339 { 340 PowerPCCPU *cpu = opaque; 341 342 return (cpu->env.insns_flags & PPC_FLOAT); 343 } 344 345 static const VMStateDescription vmstate_fpu = { 346 .name = "cpu/fpu", 347 .version_id = 1, 348 .minimum_version_id = 1, 349 .needed = fpu_needed, 350 .fields = (VMStateField[]) { 351 VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32), 352 VMSTATE_UINTTL(env.fpscr, PowerPCCPU), 353 VMSTATE_END_OF_LIST() 354 }, 355 }; 356 357 static bool altivec_needed(void *opaque) 358 { 359 PowerPCCPU *cpu = opaque; 360 361 return (cpu->env.insns_flags & PPC_ALTIVEC); 362 } 363 364 static const VMStateDescription vmstate_altivec = { 365 .name = "cpu/altivec", 366 .version_id = 1, 367 .minimum_version_id = 1, 368 .needed = altivec_needed, 369 .fields = (VMStateField[]) { 370 VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32), 371 VMSTATE_UINT32(env.vscr, PowerPCCPU), 372 VMSTATE_END_OF_LIST() 373 }, 374 }; 375 376 static bool vsx_needed(void *opaque) 377 { 378 PowerPCCPU *cpu = opaque; 379 380 return (cpu->env.insns_flags2 & PPC2_VSX); 381 } 382 383 static const VMStateDescription vmstate_vsx = { 384 .name = "cpu/vsx", 385 .version_id = 1, 386 .minimum_version_id = 1, 387 .needed = vsx_needed, 388 .fields = (VMStateField[]) { 389 VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32), 390 VMSTATE_END_OF_LIST() 391 }, 392 }; 393 394 #ifdef TARGET_PPC64 395 /* Transactional memory state */ 396 static bool tm_needed(void *opaque) 397 { 398 PowerPCCPU *cpu = opaque; 399 CPUPPCState *env = &cpu->env; 400 return msr_ts; 401 } 402 403 static const VMStateDescription vmstate_tm = { 404 .name = "cpu/tm", 405 .version_id = 1, 406 .minimum_version_id = 1, 407 .minimum_version_id_old = 1, 408 .needed = tm_needed, 409 .fields = (VMStateField []) { 410 VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32), 411 VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64), 412 VMSTATE_UINT64(env.tm_cr, PowerPCCPU), 413 VMSTATE_UINT64(env.tm_lr, PowerPCCPU), 414 VMSTATE_UINT64(env.tm_ctr, PowerPCCPU), 415 VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU), 416 VMSTATE_UINT64(env.tm_amr, PowerPCCPU), 417 VMSTATE_UINT64(env.tm_ppr, PowerPCCPU), 418 VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU), 419 VMSTATE_UINT32(env.tm_vscr, PowerPCCPU), 420 VMSTATE_UINT64(env.tm_dscr, PowerPCCPU), 421 VMSTATE_UINT64(env.tm_tar, PowerPCCPU), 422 VMSTATE_END_OF_LIST() 423 }, 424 }; 425 #endif 426 427 static bool sr_needed(void *opaque) 428 { 429 #ifdef TARGET_PPC64 430 PowerPCCPU *cpu = opaque; 431 432 return !(cpu->env.mmu_model & POWERPC_MMU_64); 433 #else 434 return true; 435 #endif 436 } 437 438 static const VMStateDescription vmstate_sr = { 439 .name = "cpu/sr", 440 .version_id = 1, 441 .minimum_version_id = 1, 442 .needed = sr_needed, 443 .fields = (VMStateField[]) { 444 VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), 445 VMSTATE_END_OF_LIST() 446 }, 447 }; 448 449 #ifdef TARGET_PPC64 450 static int get_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field) 451 { 452 ppc_slb_t *v = pv; 453 454 v->esid = qemu_get_be64(f); 455 v->vsid = qemu_get_be64(f); 456 457 return 0; 458 } 459 460 static int put_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field, 461 QJSON *vmdesc) 462 { 463 ppc_slb_t *v = pv; 464 465 qemu_put_be64(f, v->esid); 466 qemu_put_be64(f, v->vsid); 467 return 0; 468 } 469 470 static const VMStateInfo vmstate_info_slbe = { 471 .name = "slbe", 472 .get = get_slbe, 473 .put = put_slbe, 474 }; 475 476 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ 477 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) 478 479 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \ 480 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) 481 482 static bool slb_needed(void *opaque) 483 { 484 PowerPCCPU *cpu = opaque; 485 486 /* We don't support any of the old segment table based 64-bit CPUs */ 487 return (cpu->env.mmu_model & POWERPC_MMU_64); 488 } 489 490 static int slb_post_load(void *opaque, int version_id) 491 { 492 PowerPCCPU *cpu = opaque; 493 CPUPPCState *env = &cpu->env; 494 int i; 495 496 /* We've pulled in the raw esid and vsid values from the migration 497 * stream, but we need to recompute the page size pointers */ 498 for (i = 0; i < cpu->hash64_opts->slb_size; i++) { 499 if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) { 500 /* Migration source had bad values in its SLB */ 501 return -1; 502 } 503 } 504 505 return 0; 506 } 507 508 static const VMStateDescription vmstate_slb = { 509 .name = "cpu/slb", 510 .version_id = 1, 511 .minimum_version_id = 1, 512 .needed = slb_needed, 513 .post_load = slb_post_load, 514 .fields = (VMStateField[]) { 515 VMSTATE_INT32_TEST(mig_slb_nr, PowerPCCPU, cpu_pre_2_13_migration), 516 VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), 517 VMSTATE_END_OF_LIST() 518 } 519 }; 520 #endif /* TARGET_PPC64 */ 521 522 static const VMStateDescription vmstate_tlb6xx_entry = { 523 .name = "cpu/tlb6xx_entry", 524 .version_id = 1, 525 .minimum_version_id = 1, 526 .fields = (VMStateField[]) { 527 VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), 528 VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), 529 VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), 530 VMSTATE_END_OF_LIST() 531 }, 532 }; 533 534 static bool tlb6xx_needed(void *opaque) 535 { 536 PowerPCCPU *cpu = opaque; 537 CPUPPCState *env = &cpu->env; 538 539 return env->nb_tlb && (env->tlb_type == TLB_6XX); 540 } 541 542 static const VMStateDescription vmstate_tlb6xx = { 543 .name = "cpu/tlb6xx", 544 .version_id = 1, 545 .minimum_version_id = 1, 546 .needed = tlb6xx_needed, 547 .fields = (VMStateField[]) { 548 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 549 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, 550 env.nb_tlb, 551 vmstate_tlb6xx_entry, 552 ppc6xx_tlb_t), 553 VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), 554 VMSTATE_END_OF_LIST() 555 } 556 }; 557 558 static const VMStateDescription vmstate_tlbemb_entry = { 559 .name = "cpu/tlbemb_entry", 560 .version_id = 1, 561 .minimum_version_id = 1, 562 .fields = (VMStateField[]) { 563 VMSTATE_UINT64(RPN, ppcemb_tlb_t), 564 VMSTATE_UINTTL(EPN, ppcemb_tlb_t), 565 VMSTATE_UINTTL(PID, ppcemb_tlb_t), 566 VMSTATE_UINTTL(size, ppcemb_tlb_t), 567 VMSTATE_UINT32(prot, ppcemb_tlb_t), 568 VMSTATE_UINT32(attr, ppcemb_tlb_t), 569 VMSTATE_END_OF_LIST() 570 }, 571 }; 572 573 static bool tlbemb_needed(void *opaque) 574 { 575 PowerPCCPU *cpu = opaque; 576 CPUPPCState *env = &cpu->env; 577 578 return env->nb_tlb && (env->tlb_type == TLB_EMB); 579 } 580 581 static bool pbr403_needed(void *opaque) 582 { 583 PowerPCCPU *cpu = opaque; 584 uint32_t pvr = cpu->env.spr[SPR_PVR]; 585 586 return (pvr & 0xffff0000) == 0x00200000; 587 } 588 589 static const VMStateDescription vmstate_pbr403 = { 590 .name = "cpu/pbr403", 591 .version_id = 1, 592 .minimum_version_id = 1, 593 .needed = pbr403_needed, 594 .fields = (VMStateField[]) { 595 VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4), 596 VMSTATE_END_OF_LIST() 597 }, 598 }; 599 600 static const VMStateDescription vmstate_tlbemb = { 601 .name = "cpu/tlb6xx", 602 .version_id = 1, 603 .minimum_version_id = 1, 604 .needed = tlbemb_needed, 605 .fields = (VMStateField[]) { 606 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 607 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, 608 env.nb_tlb, 609 vmstate_tlbemb_entry, 610 ppcemb_tlb_t), 611 /* 403 protection registers */ 612 VMSTATE_END_OF_LIST() 613 }, 614 .subsections = (const VMStateDescription*[]) { 615 &vmstate_pbr403, 616 NULL 617 } 618 }; 619 620 static const VMStateDescription vmstate_tlbmas_entry = { 621 .name = "cpu/tlbmas_entry", 622 .version_id = 1, 623 .minimum_version_id = 1, 624 .fields = (VMStateField[]) { 625 VMSTATE_UINT32(mas8, ppcmas_tlb_t), 626 VMSTATE_UINT32(mas1, ppcmas_tlb_t), 627 VMSTATE_UINT64(mas2, ppcmas_tlb_t), 628 VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), 629 VMSTATE_END_OF_LIST() 630 }, 631 }; 632 633 static bool tlbmas_needed(void *opaque) 634 { 635 PowerPCCPU *cpu = opaque; 636 CPUPPCState *env = &cpu->env; 637 638 return env->nb_tlb && (env->tlb_type == TLB_MAS); 639 } 640 641 static const VMStateDescription vmstate_tlbmas = { 642 .name = "cpu/tlbmas", 643 .version_id = 1, 644 .minimum_version_id = 1, 645 .needed = tlbmas_needed, 646 .fields = (VMStateField[]) { 647 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 648 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, 649 env.nb_tlb, 650 vmstate_tlbmas_entry, 651 ppcmas_tlb_t), 652 VMSTATE_END_OF_LIST() 653 } 654 }; 655 656 static bool compat_needed(void *opaque) 657 { 658 PowerPCCPU *cpu = opaque; 659 660 assert(!(cpu->compat_pvr && !cpu->vhyp)); 661 return !cpu->pre_2_10_migration && cpu->compat_pvr != 0; 662 } 663 664 static const VMStateDescription vmstate_compat = { 665 .name = "cpu/compat", 666 .version_id = 1, 667 .minimum_version_id = 1, 668 .needed = compat_needed, 669 .fields = (VMStateField[]) { 670 VMSTATE_UINT32(compat_pvr, PowerPCCPU), 671 VMSTATE_END_OF_LIST() 672 } 673 }; 674 675 const VMStateDescription vmstate_ppc_cpu = { 676 .name = "cpu", 677 .version_id = 5, 678 .minimum_version_id = 5, 679 .minimum_version_id_old = 4, 680 .load_state_old = cpu_load_old, 681 .pre_save = cpu_pre_save, 682 .post_load = cpu_post_load, 683 .fields = (VMStateField[]) { 684 VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */ 685 686 /* User mode architected state */ 687 VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), 688 #if !defined(TARGET_PPC64) 689 VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), 690 #endif 691 VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), 692 VMSTATE_UINTTL(env.nip, PowerPCCPU), 693 694 /* SPRs */ 695 VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), 696 VMSTATE_UINT64(env.spe_acc, PowerPCCPU), 697 698 /* Reservation */ 699 VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), 700 701 /* Supervisor mode architected state */ 702 VMSTATE_UINTTL(env.msr, PowerPCCPU), 703 704 /* Internal state */ 705 VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), 706 /* FIXME: access_type? */ 707 708 /* Sanity checking */ 709 VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), 710 VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration), 711 VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU, 712 cpu_pre_2_8_migration), 713 VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration), 714 VMSTATE_END_OF_LIST() 715 }, 716 .subsections = (const VMStateDescription*[]) { 717 &vmstate_fpu, 718 &vmstate_altivec, 719 &vmstate_vsx, 720 &vmstate_sr, 721 #ifdef TARGET_PPC64 722 &vmstate_tm, 723 &vmstate_slb, 724 #endif /* TARGET_PPC64 */ 725 &vmstate_tlb6xx, 726 &vmstate_tlbemb, 727 &vmstate_tlbmas, 728 &vmstate_compat, 729 NULL 730 } 731 }; 732