1 #include "qemu/osdep.h" 2 #include "cpu.h" 3 #include "exec/exec-all.h" 4 #include "sysemu/kvm.h" 5 #include "helper_regs.h" 6 #include "mmu-hash64.h" 7 #include "migration/cpu.h" 8 #include "qapi/error.h" 9 #include "qemu/main-loop.h" 10 #include "kvm_ppc.h" 11 #include "power8-pmu.h" 12 13 static void post_load_update_msr(CPUPPCState *env) 14 { 15 target_ulong msr = env->msr; 16 17 /* 18 * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB 19 * before restoring. Note that this recomputes hflags. 20 */ 21 env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); 22 ppc_store_msr(env, msr); 23 pmu_update_summaries(env); 24 } 25 26 static int get_avr(QEMUFile *f, void *pv, size_t size, 27 const VMStateField *field) 28 { 29 ppc_avr_t *v = pv; 30 31 v->u64[0] = qemu_get_be64(f); 32 v->u64[1] = qemu_get_be64(f); 33 34 return 0; 35 } 36 37 static int put_avr(QEMUFile *f, void *pv, size_t size, 38 const VMStateField *field, JSONWriter *vmdesc) 39 { 40 ppc_avr_t *v = pv; 41 42 qemu_put_be64(f, v->u64[0]); 43 qemu_put_be64(f, v->u64[1]); 44 return 0; 45 } 46 47 static const VMStateInfo vmstate_info_avr = { 48 .name = "avr", 49 .get = get_avr, 50 .put = put_avr, 51 }; 52 53 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ 54 VMSTATE_SUB_ARRAY(_f, _s, 32, _n, _v, vmstate_info_avr, ppc_avr_t) 55 56 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ 57 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) 58 59 static int get_fpr(QEMUFile *f, void *pv, size_t size, 60 const VMStateField *field) 61 { 62 ppc_vsr_t *v = pv; 63 64 v->VsrD(0) = qemu_get_be64(f); 65 66 return 0; 67 } 68 69 static int put_fpr(QEMUFile *f, void *pv, size_t size, 70 const VMStateField *field, JSONWriter *vmdesc) 71 { 72 ppc_vsr_t *v = pv; 73 74 qemu_put_be64(f, v->VsrD(0)); 75 return 0; 76 } 77 78 static const VMStateInfo vmstate_info_fpr = { 79 .name = "fpr", 80 .get = get_fpr, 81 .put = put_fpr, 82 }; 83 84 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \ 85 VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_fpr, ppc_vsr_t) 86 87 #define VMSTATE_FPR_ARRAY(_f, _s, _n) \ 88 VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0) 89 90 static int get_vsr(QEMUFile *f, void *pv, size_t size, 91 const VMStateField *field) 92 { 93 ppc_vsr_t *v = pv; 94 95 v->VsrD(1) = qemu_get_be64(f); 96 97 return 0; 98 } 99 100 static int put_vsr(QEMUFile *f, void *pv, size_t size, 101 const VMStateField *field, JSONWriter *vmdesc) 102 { 103 ppc_vsr_t *v = pv; 104 105 qemu_put_be64(f, v->VsrD(1)); 106 return 0; 107 } 108 109 static const VMStateInfo vmstate_info_vsr = { 110 .name = "vsr", 111 .get = get_vsr, 112 .put = put_vsr, 113 }; 114 115 #define VMSTATE_VSR_ARRAY_V(_f, _s, _n, _v) \ 116 VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_vsr, ppc_vsr_t) 117 118 #define VMSTATE_VSR_ARRAY(_f, _s, _n) \ 119 VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0) 120 121 static bool cpu_pre_2_8_migration(void *opaque, int version_id) 122 { 123 PowerPCCPU *cpu = opaque; 124 125 return cpu->pre_2_8_migration; 126 } 127 128 #if defined(TARGET_PPC64) 129 static bool cpu_pre_3_0_migration(void *opaque, int version_id) 130 { 131 PowerPCCPU *cpu = opaque; 132 133 return cpu->pre_3_0_migration; 134 } 135 #endif 136 137 static int cpu_pre_save(void *opaque) 138 { 139 PowerPCCPU *cpu = opaque; 140 CPUPPCState *env = &cpu->env; 141 int i; 142 uint64_t insns_compat_mask = 143 PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB 144 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES 145 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES 146 | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT 147 | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ 148 | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC 149 | PPC_64B | PPC_64BX | PPC_ALTIVEC 150 | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; 151 uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX 152 | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 153 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 154 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 155 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 156 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; 157 158 env->spr[SPR_LR] = env->lr; 159 env->spr[SPR_CTR] = env->ctr; 160 env->spr[SPR_XER] = cpu_read_xer(env); 161 #if defined(TARGET_PPC64) 162 env->spr[SPR_CFAR] = env->cfar; 163 #endif 164 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; 165 166 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 167 env->spr[SPR_DBAT0U + 2 * i] = env->DBAT[0][i]; 168 env->spr[SPR_DBAT0U + 2 * i + 1] = env->DBAT[1][i]; 169 env->spr[SPR_IBAT0U + 2 * i] = env->IBAT[0][i]; 170 env->spr[SPR_IBAT0U + 2 * i + 1] = env->IBAT[1][i]; 171 } 172 for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) { 173 env->spr[SPR_DBAT4U + 2 * i] = env->DBAT[0][i + 4]; 174 env->spr[SPR_DBAT4U + 2 * i + 1] = env->DBAT[1][i + 4]; 175 env->spr[SPR_IBAT4U + 2 * i] = env->IBAT[0][i + 4]; 176 env->spr[SPR_IBAT4U + 2 * i + 1] = env->IBAT[1][i + 4]; 177 } 178 179 /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ 180 if (cpu->pre_2_8_migration) { 181 /* 182 * Mask out bits that got added to msr_mask since the versions 183 * which stupidly included it in the migration stream. 184 */ 185 target_ulong metamask = 0 186 #if defined(TARGET_PPC64) 187 | (1ULL << MSR_TS0) 188 | (1ULL << MSR_TS1) 189 #endif 190 ; 191 cpu->mig_msr_mask = env->msr_mask & ~metamask; 192 cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; 193 /* 194 * CPU models supported by old machines all have 195 * PPC_MEM_TLBIE, so we set it unconditionally to allow 196 * backward migration from a POWER9 host to a POWER8 host. 197 */ 198 cpu->mig_insns_flags |= PPC_MEM_TLBIE; 199 cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; 200 cpu->mig_nb_BATs = env->nb_BATs; 201 } 202 if (cpu->pre_3_0_migration) { 203 if (cpu->hash64_opts) { 204 cpu->mig_slb_nr = cpu->hash64_opts->slb_size; 205 } 206 } 207 208 /* Used to retain migration compatibility for pre 6.0 for 601 machines. */ 209 env->hflags_compat_nmsr = 0; 210 211 return 0; 212 } 213 214 /* 215 * Determine if a given PVR is a "close enough" match to the CPU 216 * object. For TCG and KVM PR it would probably be sufficient to 217 * require an exact PVR match. However for KVM HV the user is 218 * restricted to a PVR exactly matching the host CPU. The correct way 219 * to handle this is to put the guest into an architected 220 * compatibility mode. However, to allow a more forgiving transition 221 * and migration from before this was widely done, we allow migration 222 * between sufficiently similar PVRs, as determined by the CPU class's 223 * pvr_match() hook. 224 */ 225 static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr) 226 { 227 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 228 229 if (pvr == pcc->pvr) { 230 return true; 231 } 232 return pcc->pvr_match(pcc, pvr); 233 } 234 235 static int cpu_post_load(void *opaque, int version_id) 236 { 237 PowerPCCPU *cpu = opaque; 238 CPUPPCState *env = &cpu->env; 239 int i; 240 241 /* 242 * If we're operating in compat mode, we should be ok as long as 243 * the destination supports the same compatibility mode. 244 * 245 * Otherwise, however, we require that the destination has exactly 246 * the same CPU model as the source. 247 */ 248 249 #if defined(TARGET_PPC64) 250 if (cpu->compat_pvr) { 251 uint32_t compat_pvr = cpu->compat_pvr; 252 Error *local_err = NULL; 253 int ret; 254 255 cpu->compat_pvr = 0; 256 ret = ppc_set_compat(cpu, compat_pvr, &local_err); 257 if (ret < 0) { 258 error_report_err(local_err); 259 return ret; 260 } 261 } else 262 #endif 263 { 264 if (!pvr_match(cpu, env->spr[SPR_PVR])) { 265 return -EINVAL; 266 } 267 } 268 269 /* 270 * If we're running with KVM HV, there is a chance that the guest 271 * is running with KVM HV and its kernel does not have the 272 * capability of dealing with a different PVR other than this 273 * exact host PVR in KVM_SET_SREGS. If that happens, the 274 * guest freezes after migration. 275 * 276 * The function kvmppc_pvr_workaround_required does this verification 277 * by first checking if the kernel has the cap, returning true immediately 278 * if that is the case. Otherwise, it checks if we're running in KVM PR. 279 * If the guest kernel does not have the cap and we're not running KVM-PR 280 * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will 281 * receive the PVR it expects as a workaround. 282 * 283 */ 284 if (kvmppc_pvr_workaround_required(cpu)) { 285 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; 286 } 287 288 env->lr = env->spr[SPR_LR]; 289 env->ctr = env->spr[SPR_CTR]; 290 cpu_write_xer(env, env->spr[SPR_XER]); 291 #if defined(TARGET_PPC64) 292 env->cfar = env->spr[SPR_CFAR]; 293 #endif 294 env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; 295 296 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { 297 env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2 * i]; 298 env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2 * i + 1]; 299 env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2 * i]; 300 env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2 * i + 1]; 301 } 302 for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) { 303 env->DBAT[0][i + 4] = env->spr[SPR_DBAT4U + 2 * i]; 304 env->DBAT[1][i + 4] = env->spr[SPR_DBAT4U + 2 * i + 1]; 305 env->IBAT[0][i + 4] = env->spr[SPR_IBAT4U + 2 * i]; 306 env->IBAT[1][i + 4] = env->spr[SPR_IBAT4U + 2 * i + 1]; 307 } 308 309 if (!cpu->vhyp) { 310 ppc_store_sdr1(env, env->spr[SPR_SDR1]); 311 } 312 313 post_load_update_msr(env); 314 315 return 0; 316 } 317 318 static bool fpu_needed(void *opaque) 319 { 320 PowerPCCPU *cpu = opaque; 321 322 return cpu->env.insns_flags & PPC_FLOAT; 323 } 324 325 static const VMStateDescription vmstate_fpu = { 326 .name = "cpu/fpu", 327 .version_id = 1, 328 .minimum_version_id = 1, 329 .needed = fpu_needed, 330 .fields = (VMStateField[]) { 331 VMSTATE_FPR_ARRAY(env.vsr, PowerPCCPU, 32), 332 VMSTATE_UINTTL(env.fpscr, PowerPCCPU), 333 VMSTATE_END_OF_LIST() 334 }, 335 }; 336 337 static bool altivec_needed(void *opaque) 338 { 339 PowerPCCPU *cpu = opaque; 340 341 return cpu->env.insns_flags & PPC_ALTIVEC; 342 } 343 344 static int get_vscr(QEMUFile *f, void *opaque, size_t size, 345 const VMStateField *field) 346 { 347 PowerPCCPU *cpu = opaque; 348 ppc_store_vscr(&cpu->env, qemu_get_be32(f)); 349 return 0; 350 } 351 352 static int put_vscr(QEMUFile *f, void *opaque, size_t size, 353 const VMStateField *field, JSONWriter *vmdesc) 354 { 355 PowerPCCPU *cpu = opaque; 356 qemu_put_be32(f, ppc_get_vscr(&cpu->env)); 357 return 0; 358 } 359 360 static const VMStateInfo vmstate_vscr = { 361 .name = "cpu/altivec/vscr", 362 .get = get_vscr, 363 .put = put_vscr, 364 }; 365 366 static const VMStateDescription vmstate_altivec = { 367 .name = "cpu/altivec", 368 .version_id = 1, 369 .minimum_version_id = 1, 370 .needed = altivec_needed, 371 .fields = (VMStateField[]) { 372 VMSTATE_AVR_ARRAY(env.vsr, PowerPCCPU, 32), 373 /* 374 * Save the architecture value of the vscr, not the internally 375 * expanded version. Since this architecture value does not 376 * exist in memory to be stored, this requires a but of hoop 377 * jumping. We want OFFSET=0 so that we effectively pass CPU 378 * to the helper functions. 379 */ 380 { 381 .name = "vscr", 382 .version_id = 0, 383 .size = sizeof(uint32_t), 384 .info = &vmstate_vscr, 385 .flags = VMS_SINGLE, 386 .offset = 0 387 }, 388 VMSTATE_END_OF_LIST() 389 }, 390 }; 391 392 static bool vsx_needed(void *opaque) 393 { 394 PowerPCCPU *cpu = opaque; 395 396 return cpu->env.insns_flags2 & PPC2_VSX; 397 } 398 399 static const VMStateDescription vmstate_vsx = { 400 .name = "cpu/vsx", 401 .version_id = 1, 402 .minimum_version_id = 1, 403 .needed = vsx_needed, 404 .fields = (VMStateField[]) { 405 VMSTATE_VSR_ARRAY(env.vsr, PowerPCCPU, 32), 406 VMSTATE_END_OF_LIST() 407 }, 408 }; 409 410 #ifdef TARGET_PPC64 411 /* Transactional memory state */ 412 static bool tm_needed(void *opaque) 413 { 414 PowerPCCPU *cpu = opaque; 415 CPUPPCState *env = &cpu->env; 416 return msr_ts; 417 } 418 419 static const VMStateDescription vmstate_tm = { 420 .name = "cpu/tm", 421 .version_id = 1, 422 .minimum_version_id = 1, 423 .needed = tm_needed, 424 .fields = (VMStateField []) { 425 VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32), 426 VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64), 427 VMSTATE_UINT64(env.tm_cr, PowerPCCPU), 428 VMSTATE_UINT64(env.tm_lr, PowerPCCPU), 429 VMSTATE_UINT64(env.tm_ctr, PowerPCCPU), 430 VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU), 431 VMSTATE_UINT64(env.tm_amr, PowerPCCPU), 432 VMSTATE_UINT64(env.tm_ppr, PowerPCCPU), 433 VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU), 434 VMSTATE_UINT32(env.tm_vscr, PowerPCCPU), 435 VMSTATE_UINT64(env.tm_dscr, PowerPCCPU), 436 VMSTATE_UINT64(env.tm_tar, PowerPCCPU), 437 VMSTATE_END_OF_LIST() 438 }, 439 }; 440 #endif 441 442 static bool sr_needed(void *opaque) 443 { 444 #ifdef TARGET_PPC64 445 PowerPCCPU *cpu = opaque; 446 447 return !mmu_is_64bit(cpu->env.mmu_model); 448 #else 449 return true; 450 #endif 451 } 452 453 static const VMStateDescription vmstate_sr = { 454 .name = "cpu/sr", 455 .version_id = 1, 456 .minimum_version_id = 1, 457 .needed = sr_needed, 458 .fields = (VMStateField[]) { 459 VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), 460 VMSTATE_END_OF_LIST() 461 }, 462 }; 463 464 #ifdef TARGET_PPC64 465 static int get_slbe(QEMUFile *f, void *pv, size_t size, 466 const VMStateField *field) 467 { 468 ppc_slb_t *v = pv; 469 470 v->esid = qemu_get_be64(f); 471 v->vsid = qemu_get_be64(f); 472 473 return 0; 474 } 475 476 static int put_slbe(QEMUFile *f, void *pv, size_t size, 477 const VMStateField *field, JSONWriter *vmdesc) 478 { 479 ppc_slb_t *v = pv; 480 481 qemu_put_be64(f, v->esid); 482 qemu_put_be64(f, v->vsid); 483 return 0; 484 } 485 486 static const VMStateInfo vmstate_info_slbe = { 487 .name = "slbe", 488 .get = get_slbe, 489 .put = put_slbe, 490 }; 491 492 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ 493 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) 494 495 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \ 496 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) 497 498 static bool slb_needed(void *opaque) 499 { 500 PowerPCCPU *cpu = opaque; 501 502 /* We don't support any of the old segment table based 64-bit CPUs */ 503 return mmu_is_64bit(cpu->env.mmu_model); 504 } 505 506 static int slb_post_load(void *opaque, int version_id) 507 { 508 PowerPCCPU *cpu = opaque; 509 CPUPPCState *env = &cpu->env; 510 int i; 511 512 /* 513 * We've pulled in the raw esid and vsid values from the migration 514 * stream, but we need to recompute the page size pointers 515 */ 516 for (i = 0; i < cpu->hash64_opts->slb_size; i++) { 517 if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) { 518 /* Migration source had bad values in its SLB */ 519 return -1; 520 } 521 } 522 523 return 0; 524 } 525 526 static const VMStateDescription vmstate_slb = { 527 .name = "cpu/slb", 528 .version_id = 1, 529 .minimum_version_id = 1, 530 .needed = slb_needed, 531 .post_load = slb_post_load, 532 .fields = (VMStateField[]) { 533 VMSTATE_INT32_TEST(mig_slb_nr, PowerPCCPU, cpu_pre_3_0_migration), 534 VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), 535 VMSTATE_END_OF_LIST() 536 } 537 }; 538 #endif /* TARGET_PPC64 */ 539 540 static const VMStateDescription vmstate_tlb6xx_entry = { 541 .name = "cpu/tlb6xx_entry", 542 .version_id = 1, 543 .minimum_version_id = 1, 544 .fields = (VMStateField[]) { 545 VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), 546 VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), 547 VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), 548 VMSTATE_END_OF_LIST() 549 }, 550 }; 551 552 static bool tlb6xx_needed(void *opaque) 553 { 554 PowerPCCPU *cpu = opaque; 555 CPUPPCState *env = &cpu->env; 556 557 return env->nb_tlb && (env->tlb_type == TLB_6XX); 558 } 559 560 static const VMStateDescription vmstate_tlb6xx = { 561 .name = "cpu/tlb6xx", 562 .version_id = 1, 563 .minimum_version_id = 1, 564 .needed = tlb6xx_needed, 565 .fields = (VMStateField[]) { 566 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 567 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, 568 env.nb_tlb, 569 vmstate_tlb6xx_entry, 570 ppc6xx_tlb_t), 571 VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), 572 VMSTATE_END_OF_LIST() 573 } 574 }; 575 576 static const VMStateDescription vmstate_tlbemb_entry = { 577 .name = "cpu/tlbemb_entry", 578 .version_id = 1, 579 .minimum_version_id = 1, 580 .fields = (VMStateField[]) { 581 VMSTATE_UINT64(RPN, ppcemb_tlb_t), 582 VMSTATE_UINTTL(EPN, ppcemb_tlb_t), 583 VMSTATE_UINTTL(PID, ppcemb_tlb_t), 584 VMSTATE_UINTTL(size, ppcemb_tlb_t), 585 VMSTATE_UINT32(prot, ppcemb_tlb_t), 586 VMSTATE_UINT32(attr, ppcemb_tlb_t), 587 VMSTATE_END_OF_LIST() 588 }, 589 }; 590 591 static bool tlbemb_needed(void *opaque) 592 { 593 PowerPCCPU *cpu = opaque; 594 CPUPPCState *env = &cpu->env; 595 596 return env->nb_tlb && (env->tlb_type == TLB_EMB); 597 } 598 599 static const VMStateDescription vmstate_tlbemb = { 600 .name = "cpu/tlb6xx", 601 .version_id = 1, 602 .minimum_version_id = 1, 603 .needed = tlbemb_needed, 604 .fields = (VMStateField[]) { 605 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 606 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, 607 env.nb_tlb, 608 vmstate_tlbemb_entry, 609 ppcemb_tlb_t), 610 VMSTATE_END_OF_LIST() 611 }, 612 }; 613 614 static const VMStateDescription vmstate_tlbmas_entry = { 615 .name = "cpu/tlbmas_entry", 616 .version_id = 1, 617 .minimum_version_id = 1, 618 .fields = (VMStateField[]) { 619 VMSTATE_UINT32(mas8, ppcmas_tlb_t), 620 VMSTATE_UINT32(mas1, ppcmas_tlb_t), 621 VMSTATE_UINT64(mas2, ppcmas_tlb_t), 622 VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), 623 VMSTATE_END_OF_LIST() 624 }, 625 }; 626 627 static bool tlbmas_needed(void *opaque) 628 { 629 PowerPCCPU *cpu = opaque; 630 CPUPPCState *env = &cpu->env; 631 632 return env->nb_tlb && (env->tlb_type == TLB_MAS); 633 } 634 635 static const VMStateDescription vmstate_tlbmas = { 636 .name = "cpu/tlbmas", 637 .version_id = 1, 638 .minimum_version_id = 1, 639 .needed = tlbmas_needed, 640 .fields = (VMStateField[]) { 641 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL), 642 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, 643 env.nb_tlb, 644 vmstate_tlbmas_entry, 645 ppcmas_tlb_t), 646 VMSTATE_END_OF_LIST() 647 } 648 }; 649 650 static bool compat_needed(void *opaque) 651 { 652 PowerPCCPU *cpu = opaque; 653 654 assert(!(cpu->compat_pvr && !cpu->vhyp)); 655 return !cpu->pre_2_10_migration && cpu->compat_pvr != 0; 656 } 657 658 static const VMStateDescription vmstate_compat = { 659 .name = "cpu/compat", 660 .version_id = 1, 661 .minimum_version_id = 1, 662 .needed = compat_needed, 663 .fields = (VMStateField[]) { 664 VMSTATE_UINT32(compat_pvr, PowerPCCPU), 665 VMSTATE_END_OF_LIST() 666 } 667 }; 668 669 const VMStateDescription vmstate_ppc_cpu = { 670 .name = "cpu", 671 .version_id = 5, 672 .minimum_version_id = 5, 673 .pre_save = cpu_pre_save, 674 .post_load = cpu_post_load, 675 .fields = (VMStateField[]) { 676 VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */ 677 678 /* User mode architected state */ 679 VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), 680 #if !defined(TARGET_PPC64) 681 VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), 682 #endif 683 VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), 684 VMSTATE_UINTTL(env.nip, PowerPCCPU), 685 686 /* SPRs */ 687 VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), 688 VMSTATE_UINT64(env.spe_acc, PowerPCCPU), 689 690 /* Reservation */ 691 VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), 692 693 /* Supervisor mode architected state */ 694 VMSTATE_UINTTL(env.msr, PowerPCCPU), 695 696 /* Backward compatible internal state */ 697 VMSTATE_UINTTL(env.hflags_compat_nmsr, PowerPCCPU), 698 699 /* Sanity checking */ 700 VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), 701 VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration), 702 VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU, 703 cpu_pre_2_8_migration), 704 VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration), 705 VMSTATE_END_OF_LIST() 706 }, 707 .subsections = (const VMStateDescription*[]) { 708 &vmstate_fpu, 709 &vmstate_altivec, 710 &vmstate_vsx, 711 &vmstate_sr, 712 #ifdef TARGET_PPC64 713 &vmstate_tm, 714 &vmstate_slb, 715 #endif /* TARGET_PPC64 */ 716 &vmstate_tlb6xx, 717 &vmstate_tlbemb, 718 &vmstate_tlbmas, 719 &vmstate_compat, 720 NULL 721 } 722 }; 723