1 /* 2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (c) 2013 David Gibson, IBM Corporation 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/exec-all.h" 23 #include "exec/helper-proto.h" 24 #include "qemu/error-report.h" 25 #include "sysemu/hw_accel.h" 26 #include "kvm_ppc.h" 27 #include "mmu-hash64.h" 28 #include "exec/log.h" 29 #include "hw/hw.h" 30 #include "mmu-book3s-v3.h" 31 32 //#define DEBUG_SLB 33 34 #ifdef DEBUG_SLB 35 # define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__) 36 #else 37 # define LOG_SLB(...) do { } while (0) 38 #endif 39 40 /* 41 * SLB handling 42 */ 43 44 static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr) 45 { 46 CPUPPCState *env = &cpu->env; 47 uint64_t esid_256M, esid_1T; 48 int n; 49 50 LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr); 51 52 esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V; 53 esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V; 54 55 for (n = 0; n < cpu->hash64_opts->slb_size; n++) { 56 ppc_slb_t *slb = &env->slb[n]; 57 58 LOG_SLB("%s: slot %d %016" PRIx64 " %016" 59 PRIx64 "\n", __func__, n, slb->esid, slb->vsid); 60 /* We check for 1T matches on all MMUs here - if the MMU 61 * doesn't have 1T segment support, we will have prevented 1T 62 * entries from being inserted in the slbmte code. */ 63 if (((slb->esid == esid_256M) && 64 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M)) 65 || ((slb->esid == esid_1T) && 66 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) { 67 return slb; 68 } 69 } 70 71 return NULL; 72 } 73 74 void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu) 75 { 76 CPUPPCState *env = &cpu->env; 77 int i; 78 uint64_t slbe, slbv; 79 80 cpu_synchronize_state(CPU(cpu)); 81 82 cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n"); 83 for (i = 0; i < cpu->hash64_opts->slb_size; i++) { 84 slbe = env->slb[i].esid; 85 slbv = env->slb[i].vsid; 86 if (slbe == 0 && slbv == 0) { 87 continue; 88 } 89 cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n", 90 i, slbe, slbv); 91 } 92 } 93 94 void helper_slbia(CPUPPCState *env) 95 { 96 PowerPCCPU *cpu = ppc_env_get_cpu(env); 97 int n; 98 99 /* XXX: Warning: slbia never invalidates the first segment */ 100 for (n = 1; n < cpu->hash64_opts->slb_size; n++) { 101 ppc_slb_t *slb = &env->slb[n]; 102 103 if (slb->esid & SLB_ESID_V) { 104 slb->esid &= ~SLB_ESID_V; 105 /* XXX: given the fact that segment size is 256 MB or 1TB, 106 * and we still don't have a tlb_flush_mask(env, n, mask) 107 * in QEMU, we just invalidate all TLBs 108 */ 109 env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; 110 } 111 } 112 } 113 114 static void __helper_slbie(CPUPPCState *env, target_ulong addr, 115 target_ulong global) 116 { 117 PowerPCCPU *cpu = ppc_env_get_cpu(env); 118 ppc_slb_t *slb; 119 120 slb = slb_lookup(cpu, addr); 121 if (!slb) { 122 return; 123 } 124 125 if (slb->esid & SLB_ESID_V) { 126 slb->esid &= ~SLB_ESID_V; 127 128 /* XXX: given the fact that segment size is 256 MB or 1TB, 129 * and we still don't have a tlb_flush_mask(env, n, mask) 130 * in QEMU, we just invalidate all TLBs 131 */ 132 env->tlb_need_flush |= 133 (global == false ? TLB_NEED_LOCAL_FLUSH : TLB_NEED_GLOBAL_FLUSH); 134 } 135 } 136 137 void helper_slbie(CPUPPCState *env, target_ulong addr) 138 { 139 __helper_slbie(env, addr, false); 140 } 141 142 void helper_slbieg(CPUPPCState *env, target_ulong addr) 143 { 144 __helper_slbie(env, addr, true); 145 } 146 147 int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, 148 target_ulong esid, target_ulong vsid) 149 { 150 CPUPPCState *env = &cpu->env; 151 ppc_slb_t *slb = &env->slb[slot]; 152 const PPCHash64SegmentPageSizes *sps = NULL; 153 int i; 154 155 if (slot >= cpu->hash64_opts->slb_size) { 156 return -1; /* Bad slot number */ 157 } 158 if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) { 159 return -1; /* Reserved bits set */ 160 } 161 if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) { 162 return -1; /* Bad segment size */ 163 } 164 if ((vsid & SLB_VSID_B) && !(ppc_hash64_has(cpu, PPC_HASH64_1TSEG))) { 165 return -1; /* 1T segment on MMU that doesn't support it */ 166 } 167 168 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 169 const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i]; 170 171 if (!sps1->page_shift) { 172 break; 173 } 174 175 if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) { 176 sps = sps1; 177 break; 178 } 179 } 180 181 if (!sps) { 182 error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu 183 " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx, 184 slot, esid, vsid); 185 return -1; 186 } 187 188 slb->esid = esid; 189 slb->vsid = vsid; 190 slb->sps = sps; 191 192 LOG_SLB("%s: " TARGET_FMT_lu " " TARGET_FMT_lx " - " TARGET_FMT_lx 193 " => %016" PRIx64 " %016" PRIx64 "\n", __func__, slot, esid, vsid, 194 slb->esid, slb->vsid); 195 196 return 0; 197 } 198 199 static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb, 200 target_ulong *rt) 201 { 202 CPUPPCState *env = &cpu->env; 203 int slot = rb & 0xfff; 204 ppc_slb_t *slb = &env->slb[slot]; 205 206 if (slot >= cpu->hash64_opts->slb_size) { 207 return -1; 208 } 209 210 *rt = slb->esid; 211 return 0; 212 } 213 214 static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb, 215 target_ulong *rt) 216 { 217 CPUPPCState *env = &cpu->env; 218 int slot = rb & 0xfff; 219 ppc_slb_t *slb = &env->slb[slot]; 220 221 if (slot >= cpu->hash64_opts->slb_size) { 222 return -1; 223 } 224 225 *rt = slb->vsid; 226 return 0; 227 } 228 229 static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb, 230 target_ulong *rt) 231 { 232 CPUPPCState *env = &cpu->env; 233 ppc_slb_t *slb; 234 235 if (!msr_is_64bit(env, env->msr)) { 236 rb &= 0xffffffff; 237 } 238 slb = slb_lookup(cpu, rb); 239 if (slb == NULL) { 240 *rt = (target_ulong)-1ul; 241 } else { 242 *rt = slb->vsid; 243 } 244 return 0; 245 } 246 247 void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) 248 { 249 PowerPCCPU *cpu = ppc_env_get_cpu(env); 250 251 if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) { 252 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 253 POWERPC_EXCP_INVAL, GETPC()); 254 } 255 } 256 257 target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb) 258 { 259 PowerPCCPU *cpu = ppc_env_get_cpu(env); 260 target_ulong rt = 0; 261 262 if (ppc_load_slb_esid(cpu, rb, &rt) < 0) { 263 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 264 POWERPC_EXCP_INVAL, GETPC()); 265 } 266 return rt; 267 } 268 269 target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb) 270 { 271 PowerPCCPU *cpu = ppc_env_get_cpu(env); 272 target_ulong rt = 0; 273 274 if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) { 275 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 276 POWERPC_EXCP_INVAL, GETPC()); 277 } 278 return rt; 279 } 280 281 target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb) 282 { 283 PowerPCCPU *cpu = ppc_env_get_cpu(env); 284 target_ulong rt = 0; 285 286 if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) { 287 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, 288 POWERPC_EXCP_INVAL, GETPC()); 289 } 290 return rt; 291 } 292 293 /* Check No-Execute or Guarded Storage */ 294 static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu, 295 ppc_hash_pte64_t pte) 296 { 297 /* Exec permissions CANNOT take away read or write permissions */ 298 return (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) ? 299 PAGE_READ | PAGE_WRITE : PAGE_READ | PAGE_WRITE | PAGE_EXEC; 300 } 301 302 /* Check Basic Storage Protection */ 303 static int ppc_hash64_pte_prot(PowerPCCPU *cpu, 304 ppc_slb_t *slb, ppc_hash_pte64_t pte) 305 { 306 CPUPPCState *env = &cpu->env; 307 unsigned pp, key; 308 /* Some pp bit combinations have undefined behaviour, so default 309 * to no access in those cases */ 310 int prot = 0; 311 312 key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP) 313 : (slb->vsid & SLB_VSID_KS)); 314 pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61); 315 316 if (key == 0) { 317 switch (pp) { 318 case 0x0: 319 case 0x1: 320 case 0x2: 321 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 322 break; 323 324 case 0x3: 325 case 0x6: 326 prot = PAGE_READ | PAGE_EXEC; 327 break; 328 } 329 } else { 330 switch (pp) { 331 case 0x0: 332 case 0x6: 333 break; 334 335 case 0x1: 336 case 0x3: 337 prot = PAGE_READ | PAGE_EXEC; 338 break; 339 340 case 0x2: 341 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 342 break; 343 } 344 } 345 346 return prot; 347 } 348 349 /* Check the instruction access permissions specified in the IAMR */ 350 static int ppc_hash64_iamr_prot(PowerPCCPU *cpu, int key) 351 { 352 CPUPPCState *env = &cpu->env; 353 int iamr_bits = (env->spr[SPR_IAMR] >> 2 * (31 - key)) & 0x3; 354 355 /* 356 * An instruction fetch is permitted if the IAMR bit is 0. 357 * If the bit is set, return PAGE_READ | PAGE_WRITE because this bit 358 * can only take away EXEC permissions not READ or WRITE permissions. 359 * If bit is cleared return PAGE_READ | PAGE_WRITE | PAGE_EXEC since 360 * EXEC permissions are allowed. 361 */ 362 return (iamr_bits & 0x1) ? PAGE_READ | PAGE_WRITE : 363 PAGE_READ | PAGE_WRITE | PAGE_EXEC; 364 } 365 366 static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte) 367 { 368 CPUPPCState *env = &cpu->env; 369 int key, amrbits; 370 int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 371 372 /* Only recent MMUs implement Virtual Page Class Key Protection */ 373 if (!ppc_hash64_has(cpu, PPC_HASH64_AMR)) { 374 return prot; 375 } 376 377 key = HPTE64_R_KEY(pte.pte1); 378 amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3; 379 380 /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */ 381 /* env->spr[SPR_AMR]); */ 382 383 /* 384 * A store is permitted if the AMR bit is 0. Remove write 385 * protection if it is set. 386 */ 387 if (amrbits & 0x2) { 388 prot &= ~PAGE_WRITE; 389 } 390 /* 391 * A load is permitted if the AMR bit is 0. Remove read 392 * protection if it is set. 393 */ 394 if (amrbits & 0x1) { 395 prot &= ~PAGE_READ; 396 } 397 398 switch (env->mmu_model) { 399 /* 400 * MMU version 2.07 and later support IAMR 401 * Check if the IAMR allows the instruction access - it will return 402 * PAGE_EXEC if it doesn't (and thus that bit will be cleared) or 0 403 * if it does (and prot will be unchanged indicating execution support). 404 */ 405 case POWERPC_MMU_2_07: 406 case POWERPC_MMU_3_00: 407 prot &= ppc_hash64_iamr_prot(cpu, key); 408 break; 409 default: 410 break; 411 } 412 413 return prot; 414 } 415 416 const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu, 417 hwaddr ptex, int n) 418 { 419 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 420 hwaddr base; 421 hwaddr plen = n * HASH_PTE_SIZE_64; 422 const ppc_hash_pte64_t *hptes; 423 424 if (cpu->vhyp) { 425 PPCVirtualHypervisorClass *vhc = 426 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 427 return vhc->map_hptes(cpu->vhyp, ptex, n); 428 } 429 base = ppc_hash64_hpt_base(cpu); 430 431 if (!base) { 432 return NULL; 433 } 434 435 hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false, 436 MEMTXATTRS_UNSPECIFIED); 437 if (plen < (n * HASH_PTE_SIZE_64)) { 438 hw_error("%s: Unable to map all requested HPTEs\n", __func__); 439 } 440 return hptes; 441 } 442 443 void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes, 444 hwaddr ptex, int n) 445 { 446 if (cpu->vhyp) { 447 PPCVirtualHypervisorClass *vhc = 448 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 449 vhc->unmap_hptes(cpu->vhyp, hptes, ptex, n); 450 return; 451 } 452 453 address_space_unmap(CPU(cpu)->as, (void *)hptes, n * HASH_PTE_SIZE_64, 454 false, n * HASH_PTE_SIZE_64); 455 } 456 457 static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps, 458 uint64_t pte0, uint64_t pte1) 459 { 460 int i; 461 462 if (!(pte0 & HPTE64_V_LARGE)) { 463 if (sps->page_shift != 12) { 464 /* 4kiB page in a non 4kiB segment */ 465 return 0; 466 } 467 /* Normal 4kiB page */ 468 return 12; 469 } 470 471 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 472 const PPCHash64PageSize *ps = &sps->enc[i]; 473 uint64_t mask; 474 475 if (!ps->page_shift) { 476 break; 477 } 478 479 if (ps->page_shift == 12) { 480 /* L bit is set so this can't be a 4kiB page */ 481 continue; 482 } 483 484 mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN; 485 486 if ((pte1 & mask) == ((uint64_t)ps->pte_enc << HPTE64_R_RPN_SHIFT)) { 487 return ps->page_shift; 488 } 489 } 490 491 return 0; /* Bad page size encoding */ 492 } 493 494 static void ppc64_v3_new_to_old_hpte(target_ulong *pte0, target_ulong *pte1) 495 { 496 /* Insert B into pte0 */ 497 *pte0 = (*pte0 & HPTE64_V_COMMON_BITS) | 498 ((*pte1 & HPTE64_R_3_0_SSIZE_MASK) << 499 (HPTE64_V_SSIZE_SHIFT - HPTE64_R_3_0_SSIZE_SHIFT)); 500 501 /* Remove B from pte1 */ 502 *pte1 = *pte1 & ~HPTE64_R_3_0_SSIZE_MASK; 503 } 504 505 506 static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash, 507 const PPCHash64SegmentPageSizes *sps, 508 target_ulong ptem, 509 ppc_hash_pte64_t *pte, unsigned *pshift) 510 { 511 int i; 512 const ppc_hash_pte64_t *pteg; 513 target_ulong pte0, pte1; 514 target_ulong ptex; 515 516 ptex = (hash & ppc_hash64_hpt_mask(cpu)) * HPTES_PER_GROUP; 517 pteg = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 518 if (!pteg) { 519 return -1; 520 } 521 for (i = 0; i < HPTES_PER_GROUP; i++) { 522 pte0 = ppc_hash64_hpte0(cpu, pteg, i); 523 /* 524 * pte0 contains the valid bit and must be read before pte1, 525 * otherwise we might see an old pte1 with a new valid bit and 526 * thus an inconsistent hpte value 527 */ 528 smp_rmb(); 529 pte1 = ppc_hash64_hpte1(cpu, pteg, i); 530 531 /* Convert format if necessary */ 532 if (cpu->env.mmu_model == POWERPC_MMU_3_00 && !cpu->vhyp) { 533 ppc64_v3_new_to_old_hpte(&pte0, &pte1); 534 } 535 536 /* This compares V, B, H (secondary) and the AVPN */ 537 if (HPTE64_V_COMPARE(pte0, ptem)) { 538 *pshift = hpte_page_shift(sps, pte0, pte1); 539 /* 540 * If there is no match, ignore the PTE, it could simply 541 * be for a different segment size encoding and the 542 * architecture specifies we should not match. Linux will 543 * potentially leave behind PTEs for the wrong base page 544 * size when demoting segments. 545 */ 546 if (*pshift == 0) { 547 continue; 548 } 549 /* We don't do anything with pshift yet as qemu TLB only deals 550 * with 4K pages anyway 551 */ 552 pte->pte0 = pte0; 553 pte->pte1 = pte1; 554 ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP); 555 return ptex + i; 556 } 557 } 558 ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP); 559 /* 560 * We didn't find a valid entry. 561 */ 562 return -1; 563 } 564 565 static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, 566 ppc_slb_t *slb, target_ulong eaddr, 567 ppc_hash_pte64_t *pte, unsigned *pshift) 568 { 569 CPUPPCState *env = &cpu->env; 570 hwaddr hash, ptex; 571 uint64_t vsid, epnmask, epn, ptem; 572 const PPCHash64SegmentPageSizes *sps = slb->sps; 573 574 /* The SLB store path should prevent any bad page size encodings 575 * getting in there, so: */ 576 assert(sps); 577 578 /* If ISL is set in LPCR we need to clamp the page size to 4K */ 579 if (env->spr[SPR_LPCR] & LPCR_ISL) { 580 /* We assume that when using TCG, 4k is first entry of SPS */ 581 sps = &cpu->hash64_opts->sps[0]; 582 assert(sps->page_shift == 12); 583 } 584 585 epnmask = ~((1ULL << sps->page_shift) - 1); 586 587 if (slb->vsid & SLB_VSID_B) { 588 /* 1TB segment */ 589 vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T; 590 epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask; 591 hash = vsid ^ (vsid << 25) ^ (epn >> sps->page_shift); 592 } else { 593 /* 256M segment */ 594 vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT; 595 epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask; 596 hash = vsid ^ (epn >> sps->page_shift); 597 } 598 ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN); 599 ptem |= HPTE64_V_VALID; 600 601 /* Page address translation */ 602 qemu_log_mask(CPU_LOG_MMU, 603 "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx 604 " hash " TARGET_FMT_plx "\n", 605 ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash); 606 607 /* Primary PTEG lookup */ 608 qemu_log_mask(CPU_LOG_MMU, 609 "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx 610 " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx 611 " hash=" TARGET_FMT_plx "\n", 612 ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), 613 vsid, ptem, hash); 614 ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift); 615 616 if (ptex == -1) { 617 /* Secondary PTEG lookup */ 618 ptem |= HPTE64_V_SECONDARY; 619 qemu_log_mask(CPU_LOG_MMU, 620 "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx 621 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx 622 " hash=" TARGET_FMT_plx "\n", ppc_hash64_hpt_base(cpu), 623 ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash); 624 625 ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift); 626 } 627 628 return ptex; 629 } 630 631 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, 632 uint64_t pte0, uint64_t pte1) 633 { 634 int i; 635 636 if (!(pte0 & HPTE64_V_LARGE)) { 637 return 12; 638 } 639 640 /* 641 * The encodings in env->sps need to be carefully chosen so that 642 * this gives an unambiguous result. 643 */ 644 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 645 const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i]; 646 unsigned shift; 647 648 if (!sps->page_shift) { 649 break; 650 } 651 652 shift = hpte_page_shift(sps, pte0, pte1); 653 if (shift) { 654 return shift; 655 } 656 } 657 658 return 0; 659 } 660 661 static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code) 662 { 663 CPUPPCState *env = &POWERPC_CPU(cs)->env; 664 bool vpm; 665 666 if (msr_ir) { 667 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); 668 } else { 669 switch (env->mmu_model) { 670 case POWERPC_MMU_3_00: 671 /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */ 672 vpm = true; 673 break; 674 default: 675 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); 676 break; 677 } 678 } 679 if (vpm && !msr_hv) { 680 cs->exception_index = POWERPC_EXCP_HISI; 681 } else { 682 cs->exception_index = POWERPC_EXCP_ISI; 683 } 684 env->error_code = error_code; 685 } 686 687 static void ppc_hash64_set_dsi(CPUState *cs, uint64_t dar, uint64_t dsisr) 688 { 689 CPUPPCState *env = &POWERPC_CPU(cs)->env; 690 bool vpm; 691 692 if (msr_dr) { 693 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); 694 } else { 695 switch (env->mmu_model) { 696 case POWERPC_MMU_3_00: 697 /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */ 698 vpm = true; 699 break; 700 default: 701 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); 702 break; 703 } 704 } 705 if (vpm && !msr_hv) { 706 cs->exception_index = POWERPC_EXCP_HDSI; 707 env->spr[SPR_HDAR] = dar; 708 env->spr[SPR_HDSISR] = dsisr; 709 } else { 710 cs->exception_index = POWERPC_EXCP_DSI; 711 env->spr[SPR_DAR] = dar; 712 env->spr[SPR_DSISR] = dsisr; 713 } 714 env->error_code = 0; 715 } 716 717 718 int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, 719 int rwx, int mmu_idx) 720 { 721 CPUState *cs = CPU(cpu); 722 CPUPPCState *env = &cpu->env; 723 ppc_slb_t *slb; 724 unsigned apshift; 725 hwaddr ptex; 726 ppc_hash_pte64_t pte; 727 int exec_prot, pp_prot, amr_prot, prot; 728 uint64_t new_pte1; 729 const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC}; 730 hwaddr raddr; 731 732 assert((rwx == 0) || (rwx == 1) || (rwx == 2)); 733 734 /* Note on LPCR usage: 970 uses HID4, but our special variant 735 * of store_spr copies relevant fields into env->spr[SPR_LPCR]. 736 * Similarily we filter unimplemented bits when storing into 737 * LPCR depending on the MMU version. This code can thus just 738 * use the LPCR "as-is". 739 */ 740 741 /* 1. Handle real mode accesses */ 742 if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { 743 /* Translation is supposedly "off" */ 744 /* In real mode the top 4 effective address bits are (mostly) ignored */ 745 raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; 746 747 /* In HV mode, add HRMOR if top EA bit is clear */ 748 if (msr_hv || !env->has_hv_mode) { 749 if (!(eaddr >> 63)) { 750 raddr |= env->spr[SPR_HRMOR]; 751 } 752 } else { 753 /* Otherwise, check VPM for RMA vs VRMA */ 754 if (env->spr[SPR_LPCR] & LPCR_VPM0) { 755 slb = &env->vrma_slb; 756 if (slb->sps) { 757 goto skip_slb_search; 758 } 759 /* Not much else to do here */ 760 cs->exception_index = POWERPC_EXCP_MCHECK; 761 env->error_code = 0; 762 return 1; 763 } else if (raddr < env->rmls) { 764 /* RMA. Check bounds in RMLS */ 765 raddr |= env->spr[SPR_RMOR]; 766 } else { 767 /* The access failed, generate the approriate interrupt */ 768 if (rwx == 2) { 769 ppc_hash64_set_isi(cs, SRR1_PROTFAULT); 770 } else { 771 int dsisr = DSISR_PROTFAULT; 772 if (rwx == 1) { 773 dsisr |= DSISR_ISSTORE; 774 } 775 ppc_hash64_set_dsi(cs, eaddr, dsisr); 776 } 777 return 1; 778 } 779 } 780 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, 781 PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, 782 TARGET_PAGE_SIZE); 783 return 0; 784 } 785 786 /* 2. Translation is on, so look up the SLB */ 787 slb = slb_lookup(cpu, eaddr); 788 if (!slb) { 789 /* No entry found, check if in-memory segment tables are in use */ 790 if (ppc64_use_proc_tbl(cpu)) { 791 /* TODO - Unsupported */ 792 error_report("Segment Table Support Unimplemented"); 793 exit(1); 794 } 795 /* Segment still not found, generate the appropriate interrupt */ 796 if (rwx == 2) { 797 cs->exception_index = POWERPC_EXCP_ISEG; 798 env->error_code = 0; 799 } else { 800 cs->exception_index = POWERPC_EXCP_DSEG; 801 env->error_code = 0; 802 env->spr[SPR_DAR] = eaddr; 803 } 804 return 1; 805 } 806 807 skip_slb_search: 808 809 /* 3. Check for segment level no-execute violation */ 810 if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) { 811 ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD); 812 return 1; 813 } 814 815 /* 4. Locate the PTE in the hash table */ 816 ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift); 817 if (ptex == -1) { 818 if (rwx == 2) { 819 ppc_hash64_set_isi(cs, SRR1_NOPTE); 820 } else { 821 int dsisr = DSISR_NOPTE; 822 if (rwx == 1) { 823 dsisr |= DSISR_ISSTORE; 824 } 825 ppc_hash64_set_dsi(cs, eaddr, dsisr); 826 } 827 return 1; 828 } 829 qemu_log_mask(CPU_LOG_MMU, 830 "found PTE at index %08" HWADDR_PRIx "\n", ptex); 831 832 /* 5. Check access permissions */ 833 834 exec_prot = ppc_hash64_pte_noexec_guard(cpu, pte); 835 pp_prot = ppc_hash64_pte_prot(cpu, slb, pte); 836 amr_prot = ppc_hash64_amr_prot(cpu, pte); 837 prot = exec_prot & pp_prot & amr_prot; 838 839 if ((need_prot[rwx] & ~prot) != 0) { 840 /* Access right violation */ 841 qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); 842 if (rwx == 2) { 843 int srr1 = 0; 844 if (PAGE_EXEC & ~exec_prot) { 845 srr1 |= SRR1_NOEXEC_GUARD; /* Access violates noexec or guard */ 846 } else if (PAGE_EXEC & ~pp_prot) { 847 srr1 |= SRR1_PROTFAULT; /* Access violates access authority */ 848 } 849 if (PAGE_EXEC & ~amr_prot) { 850 srr1 |= SRR1_IAMR; /* Access violates virt pg class key prot */ 851 } 852 ppc_hash64_set_isi(cs, srr1); 853 } else { 854 int dsisr = 0; 855 if (need_prot[rwx] & ~pp_prot) { 856 dsisr |= DSISR_PROTFAULT; 857 } 858 if (rwx == 1) { 859 dsisr |= DSISR_ISSTORE; 860 } 861 if (need_prot[rwx] & ~amr_prot) { 862 dsisr |= DSISR_AMR; 863 } 864 ppc_hash64_set_dsi(cs, eaddr, dsisr); 865 } 866 return 1; 867 } 868 869 qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); 870 871 /* 6. Update PTE referenced and changed bits if necessary */ 872 873 new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */ 874 if (rwx == 1) { 875 new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */ 876 } else { 877 /* Treat the page as read-only for now, so that a later write 878 * will pass through this function again to set the C bit */ 879 prot &= ~PAGE_WRITE; 880 } 881 882 if (new_pte1 != pte.pte1) { 883 ppc_hash64_store_hpte(cpu, ptex, pte.pte0, new_pte1); 884 } 885 886 /* 7. Determine the real address from the PTE */ 887 888 raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr); 889 890 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, 891 prot, mmu_idx, 1ULL << apshift); 892 893 return 0; 894 } 895 896 hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) 897 { 898 CPUPPCState *env = &cpu->env; 899 ppc_slb_t *slb; 900 hwaddr ptex, raddr; 901 ppc_hash_pte64_t pte; 902 unsigned apshift; 903 904 /* Handle real mode */ 905 if (msr_dr == 0) { 906 /* In real mode the top 4 effective address bits are ignored */ 907 raddr = addr & 0x0FFFFFFFFFFFFFFFULL; 908 909 /* In HV mode, add HRMOR if top EA bit is clear */ 910 if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { 911 return raddr | env->spr[SPR_HRMOR]; 912 } 913 914 /* Otherwise, check VPM for RMA vs VRMA */ 915 if (env->spr[SPR_LPCR] & LPCR_VPM0) { 916 slb = &env->vrma_slb; 917 if (!slb->sps) { 918 return -1; 919 } 920 } else if (raddr < env->rmls) { 921 /* RMA. Check bounds in RMLS */ 922 return raddr | env->spr[SPR_RMOR]; 923 } else { 924 return -1; 925 } 926 } else { 927 slb = slb_lookup(cpu, addr); 928 if (!slb) { 929 return -1; 930 } 931 } 932 933 ptex = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift); 934 if (ptex == -1) { 935 return -1; 936 } 937 938 return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr) 939 & TARGET_PAGE_MASK; 940 } 941 942 void ppc_hash64_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 943 uint64_t pte0, uint64_t pte1) 944 { 945 hwaddr base; 946 hwaddr offset = ptex * HASH_PTE_SIZE_64; 947 948 if (cpu->vhyp) { 949 PPCVirtualHypervisorClass *vhc = 950 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 951 vhc->store_hpte(cpu->vhyp, ptex, pte0, pte1); 952 return; 953 } 954 base = ppc_hash64_hpt_base(cpu); 955 956 stq_phys(CPU(cpu)->as, base + offset, pte0); 957 stq_phys(CPU(cpu)->as, base + offset + HASH_PTE_SIZE_64 / 2, pte1); 958 } 959 960 void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex, 961 target_ulong pte0, target_ulong pte1) 962 { 963 /* 964 * XXX: given the fact that there are too many segments to 965 * invalidate, and we still don't have a tlb_flush_mask(env, n, 966 * mask) in QEMU, we just invalidate all TLBs 967 */ 968 cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH; 969 } 970 971 static void ppc_hash64_update_rmls(PowerPCCPU *cpu) 972 { 973 CPUPPCState *env = &cpu->env; 974 uint64_t lpcr = env->spr[SPR_LPCR]; 975 976 /* 977 * This is the full 4 bits encoding of POWER8. Previous 978 * CPUs only support a subset of these but the filtering 979 * is done when writing LPCR 980 */ 981 switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) { 982 case 0x8: /* 32MB */ 983 env->rmls = 0x2000000ull; 984 break; 985 case 0x3: /* 64MB */ 986 env->rmls = 0x4000000ull; 987 break; 988 case 0x7: /* 128MB */ 989 env->rmls = 0x8000000ull; 990 break; 991 case 0x4: /* 256MB */ 992 env->rmls = 0x10000000ull; 993 break; 994 case 0x2: /* 1GB */ 995 env->rmls = 0x40000000ull; 996 break; 997 case 0x1: /* 16GB */ 998 env->rmls = 0x400000000ull; 999 break; 1000 default: 1001 /* What to do here ??? */ 1002 env->rmls = 0; 1003 } 1004 } 1005 1006 static void ppc_hash64_update_vrma(PowerPCCPU *cpu) 1007 { 1008 CPUPPCState *env = &cpu->env; 1009 const PPCHash64SegmentPageSizes *sps = NULL; 1010 target_ulong esid, vsid, lpcr; 1011 ppc_slb_t *slb = &env->vrma_slb; 1012 uint32_t vrmasd; 1013 int i; 1014 1015 /* First clear it */ 1016 slb->esid = slb->vsid = 0; 1017 slb->sps = NULL; 1018 1019 /* Is VRMA enabled ? */ 1020 lpcr = env->spr[SPR_LPCR]; 1021 if (!(lpcr & LPCR_VPM0)) { 1022 return; 1023 } 1024 1025 /* Make one up. Mostly ignore the ESID which will not be 1026 * needed for translation 1027 */ 1028 vsid = SLB_VSID_VRMA; 1029 vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; 1030 vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP); 1031 esid = SLB_ESID_V; 1032 1033 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 1034 const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i]; 1035 1036 if (!sps1->page_shift) { 1037 break; 1038 } 1039 1040 if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) { 1041 sps = sps1; 1042 break; 1043 } 1044 } 1045 1046 if (!sps) { 1047 error_report("Bad page size encoding esid 0x"TARGET_FMT_lx 1048 " vsid 0x"TARGET_FMT_lx, esid, vsid); 1049 return; 1050 } 1051 1052 slb->vsid = vsid; 1053 slb->esid = esid; 1054 slb->sps = sps; 1055 } 1056 1057 void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) 1058 { 1059 CPUPPCState *env = &cpu->env; 1060 uint64_t lpcr = 0; 1061 1062 /* Filter out bits */ 1063 switch (env->mmu_model) { 1064 case POWERPC_MMU_64B: /* 970 */ 1065 if (val & 0x40) { 1066 lpcr |= LPCR_LPES0; 1067 } 1068 if (val & 0x8000000000000000ull) { 1069 lpcr |= LPCR_LPES1; 1070 } 1071 if (val & 0x20) { 1072 lpcr |= (0x4ull << LPCR_RMLS_SHIFT); 1073 } 1074 if (val & 0x4000000000000000ull) { 1075 lpcr |= (0x2ull << LPCR_RMLS_SHIFT); 1076 } 1077 if (val & 0x2000000000000000ull) { 1078 lpcr |= (0x1ull << LPCR_RMLS_SHIFT); 1079 } 1080 env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26; 1081 1082 /* XXX We could also write LPID from HID4 here 1083 * but since we don't tag any translation on it 1084 * it doesn't actually matter 1085 */ 1086 /* XXX For proper emulation of 970 we also need 1087 * to dig HRMOR out of HID5 1088 */ 1089 break; 1090 case POWERPC_MMU_2_03: /* P5p */ 1091 lpcr = val & (LPCR_RMLS | LPCR_ILE | 1092 LPCR_LPES0 | LPCR_LPES1 | 1093 LPCR_RMI | LPCR_HDICE); 1094 break; 1095 case POWERPC_MMU_2_06: /* P7 */ 1096 lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 1097 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 1098 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 1099 LPCR_MER | LPCR_TC | 1100 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE); 1101 break; 1102 case POWERPC_MMU_2_07: /* P8 */ 1103 lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 1104 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 1105 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 1106 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 1107 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE); 1108 break; 1109 case POWERPC_MMU_3_00: /* P9 */ 1110 lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 1111 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 1112 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 1113 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 1114 LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | 1115 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); 1116 /* 1117 * If we have a virtual hypervisor, we need to bring back RMLS. It 1118 * doesn't exist on an actual P9 but that's all we know how to 1119 * configure with softmmu at the moment 1120 */ 1121 if (cpu->vhyp) { 1122 lpcr |= (val & LPCR_RMLS); 1123 } 1124 break; 1125 default: 1126 ; 1127 } 1128 env->spr[SPR_LPCR] = lpcr; 1129 ppc_hash64_update_rmls(cpu); 1130 ppc_hash64_update_vrma(cpu); 1131 } 1132 1133 void helper_store_lpcr(CPUPPCState *env, target_ulong val) 1134 { 1135 PowerPCCPU *cpu = ppc_env_get_cpu(env); 1136 1137 ppc_store_lpcr(cpu, val); 1138 } 1139 1140 void ppc_hash64_init(PowerPCCPU *cpu) 1141 { 1142 CPUPPCState *env = &cpu->env; 1143 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1144 1145 if (!pcc->hash64_opts) { 1146 assert(!(env->mmu_model & POWERPC_MMU_64)); 1147 return; 1148 } 1149 1150 cpu->hash64_opts = g_memdup(pcc->hash64_opts, sizeof(*cpu->hash64_opts)); 1151 } 1152 1153 void ppc_hash64_finalize(PowerPCCPU *cpu) 1154 { 1155 g_free(cpu->hash64_opts); 1156 } 1157 1158 const PPCHash64Options ppc_hash64_opts_basic = { 1159 .flags = 0, 1160 .slb_size = 64, 1161 .sps = { 1162 { .page_shift = 12, /* 4K */ 1163 .slb_enc = 0, 1164 .enc = { { .page_shift = 12, .pte_enc = 0 } } 1165 }, 1166 { .page_shift = 24, /* 16M */ 1167 .slb_enc = 0x100, 1168 .enc = { { .page_shift = 24, .pte_enc = 0 } } 1169 }, 1170 }, 1171 }; 1172 1173 const PPCHash64Options ppc_hash64_opts_POWER7 = { 1174 .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE, 1175 .slb_size = 32, 1176 .sps = { 1177 { 1178 .page_shift = 12, /* 4K */ 1179 .slb_enc = 0, 1180 .enc = { { .page_shift = 12, .pte_enc = 0 }, 1181 { .page_shift = 16, .pte_enc = 0x7 }, 1182 { .page_shift = 24, .pte_enc = 0x38 }, }, 1183 }, 1184 { 1185 .page_shift = 16, /* 64K */ 1186 .slb_enc = SLB_VSID_64K, 1187 .enc = { { .page_shift = 16, .pte_enc = 0x1 }, 1188 { .page_shift = 24, .pte_enc = 0x8 }, }, 1189 }, 1190 { 1191 .page_shift = 24, /* 16M */ 1192 .slb_enc = SLB_VSID_16M, 1193 .enc = { { .page_shift = 24, .pte_enc = 0 }, }, 1194 }, 1195 { 1196 .page_shift = 34, /* 16G */ 1197 .slb_enc = SLB_VSID_16G, 1198 .enc = { { .page_shift = 34, .pte_enc = 0x3 }, }, 1199 }, 1200 } 1201 }; 1202 1203 void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu, 1204 bool (*cb)(void *, uint32_t, uint32_t), 1205 void *opaque) 1206 { 1207 PPCHash64Options *opts = cpu->hash64_opts; 1208 int i; 1209 int n = 0; 1210 bool ci_largepage = false; 1211 1212 assert(opts); 1213 1214 n = 0; 1215 for (i = 0; i < ARRAY_SIZE(opts->sps); i++) { 1216 PPCHash64SegmentPageSizes *sps = &opts->sps[i]; 1217 int j; 1218 int m = 0; 1219 1220 assert(n <= i); 1221 1222 if (!sps->page_shift) { 1223 break; 1224 } 1225 1226 for (j = 0; j < ARRAY_SIZE(sps->enc); j++) { 1227 PPCHash64PageSize *ps = &sps->enc[j]; 1228 1229 assert(m <= j); 1230 if (!ps->page_shift) { 1231 break; 1232 } 1233 1234 if (cb(opaque, sps->page_shift, ps->page_shift)) { 1235 if (ps->page_shift >= 16) { 1236 ci_largepage = true; 1237 } 1238 sps->enc[m++] = *ps; 1239 } 1240 } 1241 1242 /* Clear rest of the row */ 1243 for (j = m; j < ARRAY_SIZE(sps->enc); j++) { 1244 memset(&sps->enc[j], 0, sizeof(sps->enc[j])); 1245 } 1246 1247 if (m) { 1248 n++; 1249 } 1250 } 1251 1252 /* Clear the rest of the table */ 1253 for (i = n; i < ARRAY_SIZE(opts->sps); i++) { 1254 memset(&opts->sps[i], 0, sizeof(opts->sps[i])); 1255 } 1256 1257 if (!ci_largepage) { 1258 opts->flags &= ~PPC_HASH64_CI_LARGEPAGE; 1259 } 1260 } 1261