1 /* 2 * PowerPC Radix MMU mulation helpers for QEMU. 3 * 4 * Copyright (c) 2016 Suraj Jitindar Singh, IBM Corporation 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/exec-all.h" 23 #include "qemu/error-report.h" 24 #include "sysemu/kvm.h" 25 #include "kvm_ppc.h" 26 #include "exec/log.h" 27 #include "internal.h" 28 #include "mmu-radix64.h" 29 #include "mmu-book3s-v3.h" 30 31 static bool ppc_radix64_get_fully_qualified_addr(const CPUPPCState *env, 32 vaddr eaddr, 33 uint64_t *lpid, uint64_t *pid) 34 { 35 /* When EA(2:11) are nonzero, raise a segment interrupt */ 36 if (eaddr & ~R_EADDR_VALID_MASK) { 37 return false; 38 } 39 40 if (FIELD_EX64(env->msr, MSR, HV)) { /* MSR[HV] -> Hypervisor/bare metal */ 41 switch (eaddr & R_EADDR_QUADRANT) { 42 case R_EADDR_QUADRANT0: 43 *lpid = 0; 44 *pid = env->spr[SPR_BOOKS_PID]; 45 break; 46 case R_EADDR_QUADRANT1: 47 *lpid = env->spr[SPR_LPIDR]; 48 *pid = env->spr[SPR_BOOKS_PID]; 49 break; 50 case R_EADDR_QUADRANT2: 51 *lpid = env->spr[SPR_LPIDR]; 52 *pid = 0; 53 break; 54 case R_EADDR_QUADRANT3: 55 *lpid = 0; 56 *pid = 0; 57 break; 58 default: 59 g_assert_not_reached(); 60 } 61 } else { /* !MSR[HV] -> Guest */ 62 switch (eaddr & R_EADDR_QUADRANT) { 63 case R_EADDR_QUADRANT0: /* Guest application */ 64 *lpid = env->spr[SPR_LPIDR]; 65 *pid = env->spr[SPR_BOOKS_PID]; 66 break; 67 case R_EADDR_QUADRANT1: /* Illegal */ 68 case R_EADDR_QUADRANT2: 69 return false; 70 case R_EADDR_QUADRANT3: /* Guest OS */ 71 *lpid = env->spr[SPR_LPIDR]; 72 *pid = 0; /* pid set to 0 -> addresses guest operating system */ 73 break; 74 default: 75 g_assert_not_reached(); 76 } 77 } 78 79 return true; 80 } 81 82 static void ppc_radix64_raise_segi(PowerPCCPU *cpu, MMUAccessType access_type, 83 vaddr eaddr) 84 { 85 CPUState *cs = CPU(cpu); 86 CPUPPCState *env = &cpu->env; 87 88 switch (access_type) { 89 case MMU_INST_FETCH: 90 /* Instruction Segment Interrupt */ 91 cs->exception_index = POWERPC_EXCP_ISEG; 92 break; 93 case MMU_DATA_STORE: 94 case MMU_DATA_LOAD: 95 /* Data Segment Interrupt */ 96 cs->exception_index = POWERPC_EXCP_DSEG; 97 env->spr[SPR_DAR] = eaddr; 98 break; 99 default: 100 g_assert_not_reached(); 101 } 102 env->error_code = 0; 103 } 104 105 static inline const char *access_str(MMUAccessType access_type) 106 { 107 return access_type == MMU_DATA_LOAD ? "reading" : 108 (access_type == MMU_DATA_STORE ? "writing" : "execute"); 109 } 110 111 static void ppc_radix64_raise_si(PowerPCCPU *cpu, MMUAccessType access_type, 112 vaddr eaddr, uint32_t cause) 113 { 114 CPUState *cs = CPU(cpu); 115 CPUPPCState *env = &cpu->env; 116 117 qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx" cause %08x\n", 118 __func__, access_str(access_type), 119 eaddr, cause); 120 121 switch (access_type) { 122 case MMU_INST_FETCH: 123 /* Instruction Storage Interrupt */ 124 cs->exception_index = POWERPC_EXCP_ISI; 125 env->error_code = cause; 126 break; 127 case MMU_DATA_STORE: 128 cause |= DSISR_ISSTORE; 129 /* fall through */ 130 case MMU_DATA_LOAD: 131 /* Data Storage Interrupt */ 132 cs->exception_index = POWERPC_EXCP_DSI; 133 env->spr[SPR_DSISR] = cause; 134 env->spr[SPR_DAR] = eaddr; 135 env->error_code = 0; 136 break; 137 default: 138 g_assert_not_reached(); 139 } 140 } 141 142 static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, MMUAccessType access_type, 143 vaddr eaddr, hwaddr g_raddr, uint32_t cause) 144 { 145 CPUState *cs = CPU(cpu); 146 CPUPPCState *env = &cpu->env; 147 148 qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx" 0x%" 149 HWADDR_PRIx" cause %08x\n", 150 __func__, access_str(access_type), 151 eaddr, g_raddr, cause); 152 153 switch (access_type) { 154 case MMU_INST_FETCH: 155 /* H Instruction Storage Interrupt */ 156 cs->exception_index = POWERPC_EXCP_HISI; 157 env->spr[SPR_ASDR] = g_raddr; 158 env->error_code = cause; 159 break; 160 case MMU_DATA_STORE: 161 cause |= DSISR_ISSTORE; 162 /* fall through */ 163 case MMU_DATA_LOAD: 164 /* H Data Storage Interrupt */ 165 cs->exception_index = POWERPC_EXCP_HDSI; 166 env->spr[SPR_HDSISR] = cause; 167 env->spr[SPR_HDAR] = eaddr; 168 env->spr[SPR_ASDR] = g_raddr; 169 env->error_code = 0; 170 break; 171 default: 172 g_assert_not_reached(); 173 } 174 } 175 176 static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMUAccessType access_type, 177 uint64_t pte, int *fault_cause, int *prot, 178 int mmu_idx, bool partition_scoped) 179 { 180 CPUPPCState *env = &cpu->env; 181 int need_prot; 182 183 /* Check Page Attributes (pte58:59) */ 184 if ((pte & R_PTE_ATT) == R_PTE_ATT_NI_IO && access_type == MMU_INST_FETCH) { 185 /* 186 * Radix PTE entries with the non-idempotent I/O attribute are treated 187 * as guarded storage 188 */ 189 *fault_cause |= SRR1_NOEXEC_GUARD; 190 return true; 191 } 192 193 /* Determine permissions allowed by Encoded Access Authority */ 194 if (!partition_scoped && (pte & R_PTE_EAA_PRIV) && 195 FIELD_EX64(env->msr, MSR, PR)) { 196 *prot = 0; 197 } else if (mmuidx_pr(mmu_idx) || (pte & R_PTE_EAA_PRIV) || 198 partition_scoped) { 199 *prot = ppc_radix64_get_prot_eaa(pte); 200 } else { /* !MSR_PR && !(pte & R_PTE_EAA_PRIV) && !partition_scoped */ 201 *prot = ppc_radix64_get_prot_eaa(pte); 202 *prot &= ppc_radix64_get_prot_amr(cpu); /* Least combined permissions */ 203 } 204 205 /* Check if requested access type is allowed */ 206 need_prot = prot_for_access_type(access_type); 207 if (need_prot & ~*prot) { /* Page Protected for that Access */ 208 *fault_cause |= access_type == MMU_INST_FETCH ? SRR1_NOEXEC_GUARD : 209 DSISR_PROTFAULT; 210 return true; 211 } 212 213 return false; 214 } 215 216 static void ppc_radix64_set_rc(PowerPCCPU *cpu, MMUAccessType access_type, 217 uint64_t pte, hwaddr pte_addr, int *prot) 218 { 219 CPUState *cs = CPU(cpu); 220 uint64_t npte; 221 222 npte = pte | R_PTE_R; /* Always set reference bit */ 223 224 if (access_type == MMU_DATA_STORE) { /* Store/Write */ 225 npte |= R_PTE_C; /* Set change bit */ 226 } else { 227 /* 228 * Treat the page as read-only for now, so that a later write 229 * will pass through this function again to set the C bit. 230 */ 231 *prot &= ~PAGE_WRITE; 232 } 233 234 if (pte ^ npte) { /* If pte has changed then write it back */ 235 stq_phys(cs->as, pte_addr, npte); 236 } 237 } 238 239 static int ppc_radix64_next_level(AddressSpace *as, vaddr eaddr, 240 uint64_t *pte_addr, uint64_t *nls, 241 int *psize, uint64_t *pte, int *fault_cause) 242 { 243 uint64_t index, pde; 244 245 if (*nls < 5) { /* Directory maps less than 2**5 entries */ 246 *fault_cause |= DSISR_R_BADCONFIG; 247 return 1; 248 } 249 250 /* Read page <directory/table> entry from guest address space */ 251 pde = ldq_phys(as, *pte_addr); 252 if (!(pde & R_PTE_VALID)) { /* Invalid Entry */ 253 *fault_cause |= DSISR_NOPTE; 254 return 1; 255 } 256 257 *pte = pde; 258 *psize -= *nls; 259 if (!(pde & R_PTE_LEAF)) { /* Prepare for next iteration */ 260 *nls = pde & R_PDE_NLS; 261 index = eaddr >> (*psize - *nls); /* Shift */ 262 index &= ((1UL << *nls) - 1); /* Mask */ 263 *pte_addr = (pde & R_PDE_NLB) + (index * sizeof(pde)); 264 } 265 return 0; 266 } 267 268 static int ppc_radix64_walk_tree(AddressSpace *as, vaddr eaddr, 269 uint64_t base_addr, uint64_t nls, 270 hwaddr *raddr, int *psize, uint64_t *pte, 271 int *fault_cause, hwaddr *pte_addr) 272 { 273 uint64_t index, pde, rpn , mask; 274 275 if (nls < 5) { /* Directory maps less than 2**5 entries */ 276 *fault_cause |= DSISR_R_BADCONFIG; 277 return 1; 278 } 279 280 index = eaddr >> (*psize - nls); /* Shift */ 281 index &= ((1UL << nls) - 1); /* Mask */ 282 *pte_addr = base_addr + (index * sizeof(pde)); 283 do { 284 int ret; 285 286 ret = ppc_radix64_next_level(as, eaddr, pte_addr, &nls, psize, &pde, 287 fault_cause); 288 if (ret) { 289 return ret; 290 } 291 } while (!(pde & R_PTE_LEAF)); 292 293 *pte = pde; 294 rpn = pde & R_PTE_RPN; 295 mask = (1UL << *psize) - 1; 296 297 /* Or high bits of rpn and low bits to ea to form whole real addr */ 298 *raddr = (rpn & ~mask) | (eaddr & mask); 299 return 0; 300 } 301 302 static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate) 303 { 304 CPUPPCState *env = &cpu->env; 305 306 if (!(pate->dw0 & PATE0_HR)) { 307 return false; 308 } 309 if (lpid == 0 && !FIELD_EX64(env->msr, MSR, HV)) { 310 return false; 311 } 312 if ((pate->dw0 & PATE1_R_PRTS) < 5) { 313 return false; 314 } 315 /* More checks ... */ 316 return true; 317 } 318 319 static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, 320 MMUAccessType access_type, 321 vaddr eaddr, hwaddr g_raddr, 322 ppc_v3_pate_t pate, 323 hwaddr *h_raddr, int *h_prot, 324 int *h_page_size, bool pde_addr, 325 int mmu_idx, bool guest_visible) 326 { 327 int fault_cause = 0; 328 hwaddr pte_addr; 329 uint64_t pte; 330 331 qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx 332 " mmu_idx %u 0x%"HWADDR_PRIx"\n", 333 __func__, access_str(access_type), 334 eaddr, mmu_idx, g_raddr); 335 336 *h_page_size = PRTBE_R_GET_RTS(pate.dw0); 337 /* No valid pte or access denied due to protection */ 338 if (ppc_radix64_walk_tree(CPU(cpu)->as, g_raddr, pate.dw0 & PRTBE_R_RPDB, 339 pate.dw0 & PRTBE_R_RPDS, h_raddr, h_page_size, 340 &pte, &fault_cause, &pte_addr) || 341 ppc_radix64_check_prot(cpu, access_type, pte, 342 &fault_cause, h_prot, mmu_idx, true)) { 343 if (pde_addr) { /* address being translated was that of a guest pde */ 344 fault_cause |= DSISR_PRTABLE_FAULT; 345 } 346 if (guest_visible) { 347 ppc_radix64_raise_hsi(cpu, access_type, eaddr, g_raddr, fault_cause); 348 } 349 return 1; 350 } 351 352 if (guest_visible) { 353 ppc_radix64_set_rc(cpu, access_type, pte, pte_addr, h_prot); 354 } 355 356 return 0; 357 } 358 359 /* 360 * The spapr vhc has a flat partition scope provided by qemu memory when 361 * not nested. 362 * 363 * When running a nested guest, the addressing is 2-level radix on top of the 364 * vhc memory, so it works practically identically to the bare metal 2-level 365 * radix. So that code is selected directly. A cleaner and more flexible nested 366 * hypervisor implementation would allow the vhc to provide a ->nested_xlate() 367 * function but that is not required for the moment. 368 */ 369 static bool vhyp_flat_addressing(PowerPCCPU *cpu) 370 { 371 if (cpu->vhyp) { 372 return !vhyp_cpu_in_nested(cpu); 373 } 374 return false; 375 } 376 377 static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, 378 MMUAccessType access_type, 379 vaddr eaddr, uint64_t pid, 380 ppc_v3_pate_t pate, hwaddr *g_raddr, 381 int *g_prot, int *g_page_size, 382 int mmu_idx, bool guest_visible) 383 { 384 CPUState *cs = CPU(cpu); 385 CPUPPCState *env = &cpu->env; 386 uint64_t offset, size, prtbe_addr, prtbe0, base_addr, nls, index, pte; 387 int fault_cause = 0, h_page_size, h_prot; 388 hwaddr h_raddr, pte_addr; 389 int ret; 390 391 qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx 392 " mmu_idx %u pid %"PRIu64"\n", 393 __func__, access_str(access_type), 394 eaddr, mmu_idx, pid); 395 396 /* Index Process Table by PID to Find Corresponding Process Table Entry */ 397 offset = pid * sizeof(struct prtb_entry); 398 size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12); 399 if (offset >= size) { 400 /* offset exceeds size of the process table */ 401 if (guest_visible) { 402 ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE); 403 } 404 return 1; 405 } 406 prtbe_addr = (pate.dw1 & PATE1_R_PRTB) + offset; 407 408 if (vhyp_flat_addressing(cpu)) { 409 prtbe0 = ldq_phys(cs->as, prtbe_addr); 410 } else { 411 /* 412 * Process table addresses are subject to partition-scoped 413 * translation 414 * 415 * On a Radix host, the partition-scoped page table for LPID=0 416 * is only used to translate the effective addresses of the 417 * process table entries. 418 */ 419 ret = ppc_radix64_partition_scoped_xlate(cpu, 0, eaddr, prtbe_addr, 420 pate, &h_raddr, &h_prot, 421 &h_page_size, true, 422 /* mmu_idx is 5 because we're translating from hypervisor scope */ 423 5, guest_visible); 424 if (ret) { 425 return ret; 426 } 427 prtbe0 = ldq_phys(cs->as, h_raddr); 428 } 429 430 /* Walk Radix Tree from Process Table Entry to Convert EA to RA */ 431 *g_page_size = PRTBE_R_GET_RTS(prtbe0); 432 base_addr = prtbe0 & PRTBE_R_RPDB; 433 nls = prtbe0 & PRTBE_R_RPDS; 434 if (FIELD_EX64(env->msr, MSR, HV) || vhyp_flat_addressing(cpu)) { 435 /* 436 * Can treat process table addresses as real addresses 437 */ 438 ret = ppc_radix64_walk_tree(cs->as, eaddr & R_EADDR_MASK, base_addr, 439 nls, g_raddr, g_page_size, &pte, 440 &fault_cause, &pte_addr); 441 if (ret) { 442 /* No valid PTE */ 443 if (guest_visible) { 444 ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause); 445 } 446 return ret; 447 } 448 } else { 449 uint64_t rpn, mask; 450 451 index = (eaddr & R_EADDR_MASK) >> (*g_page_size - nls); /* Shift */ 452 index &= ((1UL << nls) - 1); /* Mask */ 453 pte_addr = base_addr + (index * sizeof(pte)); 454 455 /* 456 * Each process table address is subject to a partition-scoped 457 * translation 458 */ 459 do { 460 ret = ppc_radix64_partition_scoped_xlate(cpu, 0, eaddr, pte_addr, 461 pate, &h_raddr, &h_prot, 462 &h_page_size, true, 463 /* mmu_idx is 5 because we're translating from hypervisor scope */ 464 5, guest_visible); 465 if (ret) { 466 return ret; 467 } 468 469 ret = ppc_radix64_next_level(cs->as, eaddr & R_EADDR_MASK, &h_raddr, 470 &nls, g_page_size, &pte, &fault_cause); 471 if (ret) { 472 /* No valid pte */ 473 if (guest_visible) { 474 ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause); 475 } 476 return ret; 477 } 478 pte_addr = h_raddr; 479 } while (!(pte & R_PTE_LEAF)); 480 481 rpn = pte & R_PTE_RPN; 482 mask = (1UL << *g_page_size) - 1; 483 484 /* Or high bits of rpn and low bits to ea to form whole real addr */ 485 *g_raddr = (rpn & ~mask) | (eaddr & mask); 486 } 487 488 if (ppc_radix64_check_prot(cpu, access_type, pte, &fault_cause, 489 g_prot, mmu_idx, false)) { 490 /* Access denied due to protection */ 491 if (guest_visible) { 492 ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause); 493 } 494 return 1; 495 } 496 497 if (guest_visible) { 498 ppc_radix64_set_rc(cpu, access_type, pte, pte_addr, g_prot); 499 } 500 501 return 0; 502 } 503 504 /* 505 * Radix tree translation is a 2 steps translation process: 506 * 507 * 1. Process-scoped translation: Guest Eff Addr -> Guest Real Addr 508 * 2. Partition-scoped translation: Guest Real Addr -> Host Real Addr 509 * 510 * MSR[HV] 511 * +-------------+----------------+---------------+ 512 * | | HV = 0 | HV = 1 | 513 * +-------------+----------------+---------------+ 514 * | Relocation | Partition | No | 515 * | = Off | Scoped | Translation | 516 * Relocation +-------------+----------------+---------------+ 517 * | Relocation | Partition & | Process | 518 * | = On | Process Scoped | Scoped | 519 * +-------------+----------------+---------------+ 520 */ 521 static bool ppc_radix64_xlate_impl(PowerPCCPU *cpu, vaddr eaddr, 522 MMUAccessType access_type, hwaddr *raddr, 523 int *psizep, int *protp, int mmu_idx, 524 bool guest_visible) 525 { 526 CPUPPCState *env = &cpu->env; 527 uint64_t lpid, pid; 528 ppc_v3_pate_t pate; 529 int psize, prot; 530 hwaddr g_raddr; 531 bool relocation; 532 533 assert(!(mmuidx_hv(mmu_idx) && cpu->vhyp)); 534 535 relocation = !mmuidx_real(mmu_idx); 536 537 /* HV or virtual hypervisor Real Mode Access */ 538 if (!relocation && (mmuidx_hv(mmu_idx) || vhyp_flat_addressing(cpu))) { 539 /* In real mode top 4 effective addr bits (mostly) ignored */ 540 *raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; 541 542 /* In HV mode, add HRMOR if top EA bit is clear */ 543 if (mmuidx_hv(mmu_idx) || !env->has_hv_mode) { 544 if (!(eaddr >> 63)) { 545 *raddr |= env->spr[SPR_HRMOR]; 546 } 547 } 548 *protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 549 *psizep = TARGET_PAGE_BITS; 550 return true; 551 } 552 553 /* 554 * Check UPRT (we avoid the check in real mode to deal with 555 * transitional states during kexec. 556 */ 557 if (guest_visible && !ppc64_use_proc_tbl(cpu)) { 558 qemu_log_mask(LOG_GUEST_ERROR, 559 "LPCR:UPRT not set in radix mode ! LPCR=" 560 TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 561 } 562 563 /* Virtual Mode Access - get the fully qualified address */ 564 if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pid)) { 565 if (guest_visible) { 566 ppc_radix64_raise_segi(cpu, access_type, eaddr); 567 } 568 return false; 569 } 570 571 /* Get Process Table */ 572 if (cpu->vhyp) { 573 PPCVirtualHypervisorClass *vhc; 574 vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 575 if (!vhc->get_pate(cpu->vhyp, cpu, lpid, &pate)) { 576 if (guest_visible) { 577 ppc_radix64_raise_hsi(cpu, access_type, eaddr, eaddr, 578 DSISR_R_BADCONFIG); 579 } 580 return false; 581 } 582 } else { 583 if (!ppc64_v3_get_pate(cpu, lpid, &pate)) { 584 if (guest_visible) { 585 ppc_radix64_raise_hsi(cpu, access_type, eaddr, eaddr, 586 DSISR_R_BADCONFIG); 587 } 588 return false; 589 } 590 if (!validate_pate(cpu, lpid, &pate)) { 591 if (guest_visible) { 592 ppc_radix64_raise_hsi(cpu, access_type, eaddr, eaddr, 593 DSISR_R_BADCONFIG); 594 } 595 return false; 596 } 597 } 598 599 *psizep = INT_MAX; 600 *protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 601 602 /* 603 * Perform process-scoped translation if relocation enabled. 604 * 605 * - Translates an effective address to a host real address in 606 * quadrants 0 and 3 when HV=1. 607 * 608 * - Translates an effective address to a guest real address. 609 */ 610 if (relocation) { 611 int ret = ppc_radix64_process_scoped_xlate(cpu, access_type, eaddr, pid, 612 pate, &g_raddr, &prot, 613 &psize, mmu_idx, guest_visible); 614 if (ret) { 615 return false; 616 } 617 *psizep = MIN(*psizep, psize); 618 *protp &= prot; 619 } else { 620 g_raddr = eaddr & R_EADDR_MASK; 621 } 622 623 if (vhyp_flat_addressing(cpu)) { 624 *raddr = g_raddr; 625 } else { 626 /* 627 * Perform partition-scoped translation if !HV or HV access to 628 * quadrants 1 or 2. Translates a guest real address to a host 629 * real address. 630 */ 631 if (lpid || !mmuidx_hv(mmu_idx)) { 632 int ret; 633 634 ret = ppc_radix64_partition_scoped_xlate(cpu, access_type, eaddr, 635 g_raddr, pate, raddr, 636 &prot, &psize, false, 637 mmu_idx, guest_visible); 638 if (ret) { 639 return false; 640 } 641 *psizep = MIN(*psizep, psize); 642 *protp &= prot; 643 } else { 644 *raddr = g_raddr; 645 } 646 } 647 648 return true; 649 } 650 651 bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, 652 hwaddr *raddrp, int *psizep, int *protp, int mmu_idx, 653 bool guest_visible) 654 { 655 bool ret = ppc_radix64_xlate_impl(cpu, eaddr, access_type, raddrp, 656 psizep, protp, mmu_idx, guest_visible); 657 658 qemu_log_mask(CPU_LOG_MMU, "%s for %s @0x%"VADDR_PRIx 659 " mmu_idx %u (prot %c%c%c) -> 0x%"HWADDR_PRIx"\n", 660 __func__, access_str(access_type), 661 eaddr, mmu_idx, 662 *protp & PAGE_READ ? 'r' : '-', 663 *protp & PAGE_WRITE ? 'w' : '-', 664 *protp & PAGE_EXEC ? 'x' : '-', 665 *raddrp); 666 667 return ret; 668 } 669