1 /* 2 * PowerPC emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "disas/disas.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "tcg/tcg-op-gvec.h" 28 #include "qemu/host-utils.h" 29 #include "qemu/main-loop.h" 30 #include "exec/cpu_ldst.h" 31 32 #include "exec/helper-proto.h" 33 #include "exec/helper-gen.h" 34 35 #include "trace-tcg.h" 36 #include "exec/translator.h" 37 #include "exec/log.h" 38 #include "qemu/atomic128.h" 39 40 41 #define CPU_SINGLE_STEP 0x1 42 #define CPU_BRANCH_STEP 0x2 43 #define GDBSTUB_SINGLE_STEP 0x4 44 45 /* Include definitions for instructions classes and implementations flags */ 46 /* #define PPC_DEBUG_DISAS */ 47 /* #define DO_PPC_STATISTICS */ 48 49 #ifdef PPC_DEBUG_DISAS 50 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 51 #else 52 # define LOG_DISAS(...) do { } while (0) 53 #endif 54 /*****************************************************************************/ 55 /* Code translation helpers */ 56 57 /* global register indexes */ 58 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 59 + 10 * 4 + 22 * 5 /* SPE GPRh */ 60 + 8 * 5 /* CRF */]; 61 static TCGv cpu_gpr[32]; 62 static TCGv cpu_gprh[32]; 63 static TCGv_i32 cpu_crf[8]; 64 static TCGv cpu_nip; 65 static TCGv cpu_msr; 66 static TCGv cpu_ctr; 67 static TCGv cpu_lr; 68 #if defined(TARGET_PPC64) 69 static TCGv cpu_cfar; 70 #endif 71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 72 static TCGv cpu_reserve; 73 static TCGv cpu_reserve_val; 74 static TCGv cpu_fpscr; 75 static TCGv_i32 cpu_access_type; 76 77 #include "exec/gen-icount.h" 78 79 void ppc_translate_init(void) 80 { 81 int i; 82 char *p; 83 size_t cpu_reg_names_size; 84 85 p = cpu_reg_names; 86 cpu_reg_names_size = sizeof(cpu_reg_names); 87 88 for (i = 0; i < 8; i++) { 89 snprintf(p, cpu_reg_names_size, "crf%d", i); 90 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 91 offsetof(CPUPPCState, crf[i]), p); 92 p += 5; 93 cpu_reg_names_size -= 5; 94 } 95 96 for (i = 0; i < 32; i++) { 97 snprintf(p, cpu_reg_names_size, "r%d", i); 98 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 99 offsetof(CPUPPCState, gpr[i]), p); 100 p += (i < 10) ? 3 : 4; 101 cpu_reg_names_size -= (i < 10) ? 3 : 4; 102 snprintf(p, cpu_reg_names_size, "r%dH", i); 103 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 104 offsetof(CPUPPCState, gprh[i]), p); 105 p += (i < 10) ? 4 : 5; 106 cpu_reg_names_size -= (i < 10) ? 4 : 5; 107 } 108 109 cpu_nip = tcg_global_mem_new(cpu_env, 110 offsetof(CPUPPCState, nip), "nip"); 111 112 cpu_msr = tcg_global_mem_new(cpu_env, 113 offsetof(CPUPPCState, msr), "msr"); 114 115 cpu_ctr = tcg_global_mem_new(cpu_env, 116 offsetof(CPUPPCState, ctr), "ctr"); 117 118 cpu_lr = tcg_global_mem_new(cpu_env, 119 offsetof(CPUPPCState, lr), "lr"); 120 121 #if defined(TARGET_PPC64) 122 cpu_cfar = tcg_global_mem_new(cpu_env, 123 offsetof(CPUPPCState, cfar), "cfar"); 124 #endif 125 126 cpu_xer = tcg_global_mem_new(cpu_env, 127 offsetof(CPUPPCState, xer), "xer"); 128 cpu_so = tcg_global_mem_new(cpu_env, 129 offsetof(CPUPPCState, so), "SO"); 130 cpu_ov = tcg_global_mem_new(cpu_env, 131 offsetof(CPUPPCState, ov), "OV"); 132 cpu_ca = tcg_global_mem_new(cpu_env, 133 offsetof(CPUPPCState, ca), "CA"); 134 cpu_ov32 = tcg_global_mem_new(cpu_env, 135 offsetof(CPUPPCState, ov32), "OV32"); 136 cpu_ca32 = tcg_global_mem_new(cpu_env, 137 offsetof(CPUPPCState, ca32), "CA32"); 138 139 cpu_reserve = tcg_global_mem_new(cpu_env, 140 offsetof(CPUPPCState, reserve_addr), 141 "reserve_addr"); 142 cpu_reserve_val = tcg_global_mem_new(cpu_env, 143 offsetof(CPUPPCState, reserve_val), 144 "reserve_val"); 145 146 cpu_fpscr = tcg_global_mem_new(cpu_env, 147 offsetof(CPUPPCState, fpscr), "fpscr"); 148 149 cpu_access_type = tcg_global_mem_new_i32(cpu_env, 150 offsetof(CPUPPCState, access_type), 151 "access_type"); 152 } 153 154 /* internal defines */ 155 struct DisasContext { 156 DisasContextBase base; 157 uint32_t opcode; 158 uint32_t exception; 159 /* Routine used to access memory */ 160 bool pr, hv, dr, le_mode; 161 bool lazy_tlb_flush; 162 bool need_access_type; 163 int mem_idx; 164 int access_type; 165 /* Translation flags */ 166 MemOp default_tcg_memop_mask; 167 #if defined(TARGET_PPC64) 168 bool sf_mode; 169 bool has_cfar; 170 #endif 171 bool fpu_enabled; 172 bool altivec_enabled; 173 bool vsx_enabled; 174 bool spe_enabled; 175 bool tm_enabled; 176 bool gtse; 177 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 178 int singlestep_enabled; 179 uint32_t flags; 180 uint64_t insns_flags; 181 uint64_t insns_flags2; 182 }; 183 184 /* Return true iff byteswap is needed in a scalar memop */ 185 static inline bool need_byteswap(const DisasContext *ctx) 186 { 187 #if defined(TARGET_WORDS_BIGENDIAN) 188 return ctx->le_mode; 189 #else 190 return !ctx->le_mode; 191 #endif 192 } 193 194 /* True when active word size < size of target_long. */ 195 #ifdef TARGET_PPC64 196 # define NARROW_MODE(C) (!(C)->sf_mode) 197 #else 198 # define NARROW_MODE(C) 0 199 #endif 200 201 struct opc_handler_t { 202 /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 203 uint32_t inval1; 204 /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 205 uint32_t inval2; 206 /* instruction type */ 207 uint64_t type; 208 /* extended instruction type */ 209 uint64_t type2; 210 /* handler */ 211 void (*handler)(DisasContext *ctx); 212 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 213 const char *oname; 214 #endif 215 #if defined(DO_PPC_STATISTICS) 216 uint64_t count; 217 #endif 218 }; 219 220 /* SPR load/store helpers */ 221 static inline void gen_load_spr(TCGv t, int reg) 222 { 223 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 224 } 225 226 static inline void gen_store_spr(int reg, TCGv t) 227 { 228 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 229 } 230 231 static inline void gen_set_access_type(DisasContext *ctx, int access_type) 232 { 233 if (ctx->need_access_type && ctx->access_type != access_type) { 234 tcg_gen_movi_i32(cpu_access_type, access_type); 235 ctx->access_type = access_type; 236 } 237 } 238 239 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 240 { 241 if (NARROW_MODE(ctx)) { 242 nip = (uint32_t)nip; 243 } 244 tcg_gen_movi_tl(cpu_nip, nip); 245 } 246 247 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 248 { 249 TCGv_i32 t0, t1; 250 251 /* 252 * These are all synchronous exceptions, we set the PC back to the 253 * faulting instruction 254 */ 255 if (ctx->exception == POWERPC_EXCP_NONE) { 256 gen_update_nip(ctx, ctx->base.pc_next - 4); 257 } 258 t0 = tcg_const_i32(excp); 259 t1 = tcg_const_i32(error); 260 gen_helper_raise_exception_err(cpu_env, t0, t1); 261 tcg_temp_free_i32(t0); 262 tcg_temp_free_i32(t1); 263 ctx->exception = (excp); 264 } 265 266 static void gen_exception(DisasContext *ctx, uint32_t excp) 267 { 268 TCGv_i32 t0; 269 270 /* 271 * These are all synchronous exceptions, we set the PC back to the 272 * faulting instruction 273 */ 274 if (ctx->exception == POWERPC_EXCP_NONE) { 275 gen_update_nip(ctx, ctx->base.pc_next - 4); 276 } 277 t0 = tcg_const_i32(excp); 278 gen_helper_raise_exception(cpu_env, t0); 279 tcg_temp_free_i32(t0); 280 ctx->exception = (excp); 281 } 282 283 static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 284 target_ulong nip) 285 { 286 TCGv_i32 t0; 287 288 gen_update_nip(ctx, nip); 289 t0 = tcg_const_i32(excp); 290 gen_helper_raise_exception(cpu_env, t0); 291 tcg_temp_free_i32(t0); 292 ctx->exception = (excp); 293 } 294 295 /* 296 * Tells the caller what is the appropriate exception to generate and prepares 297 * SPR registers for this exception. 298 * 299 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 300 * POWERPC_EXCP_DEBUG (on BookE). 301 */ 302 static uint32_t gen_prep_dbgex(DisasContext *ctx) 303 { 304 if (ctx->flags & POWERPC_FLAG_DE) { 305 target_ulong dbsr = 0; 306 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 307 dbsr = DBCR0_ICMP; 308 } else { 309 /* Must have been branch */ 310 dbsr = DBCR0_BRT; 311 } 312 TCGv t0 = tcg_temp_new(); 313 gen_load_spr(t0, SPR_BOOKE_DBSR); 314 tcg_gen_ori_tl(t0, t0, dbsr); 315 gen_store_spr(SPR_BOOKE_DBSR, t0); 316 tcg_temp_free(t0); 317 return POWERPC_EXCP_DEBUG; 318 } else { 319 return POWERPC_EXCP_TRACE; 320 } 321 } 322 323 static void gen_debug_exception(DisasContext *ctx) 324 { 325 TCGv_i32 t0; 326 327 /* 328 * These are all synchronous exceptions, we set the PC back to the 329 * faulting instruction 330 */ 331 if ((ctx->exception != POWERPC_EXCP_BRANCH) && 332 (ctx->exception != POWERPC_EXCP_SYNC)) { 333 gen_update_nip(ctx, ctx->base.pc_next); 334 } 335 t0 = tcg_const_i32(EXCP_DEBUG); 336 gen_helper_raise_exception(cpu_env, t0); 337 tcg_temp_free_i32(t0); 338 } 339 340 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 341 { 342 /* Will be converted to program check if needed */ 343 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 344 } 345 346 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 347 { 348 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 349 } 350 351 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 352 { 353 /* Will be converted to program check if needed */ 354 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 355 } 356 357 /* Stop translation */ 358 static inline void gen_stop_exception(DisasContext *ctx) 359 { 360 gen_update_nip(ctx, ctx->base.pc_next); 361 ctx->exception = POWERPC_EXCP_STOP; 362 } 363 364 #ifndef CONFIG_USER_ONLY 365 /* No need to update nip here, as execution flow will change */ 366 static inline void gen_sync_exception(DisasContext *ctx) 367 { 368 ctx->exception = POWERPC_EXCP_SYNC; 369 } 370 #endif 371 372 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 373 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 374 375 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 376 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 377 378 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 379 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 380 381 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 382 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 383 384 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 385 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 386 387 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 388 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 389 390 typedef struct opcode_t { 391 unsigned char opc1, opc2, opc3, opc4; 392 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 393 unsigned char pad[4]; 394 #endif 395 opc_handler_t handler; 396 const char *oname; 397 } opcode_t; 398 399 /* Helpers for priv. check */ 400 #define GEN_PRIV \ 401 do { \ 402 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 403 } while (0) 404 405 #if defined(CONFIG_USER_ONLY) 406 #define CHK_HV GEN_PRIV 407 #define CHK_SV GEN_PRIV 408 #define CHK_HVRM GEN_PRIV 409 #else 410 #define CHK_HV \ 411 do { \ 412 if (unlikely(ctx->pr || !ctx->hv)) { \ 413 GEN_PRIV; \ 414 } \ 415 } while (0) 416 #define CHK_SV \ 417 do { \ 418 if (unlikely(ctx->pr)) { \ 419 GEN_PRIV; \ 420 } \ 421 } while (0) 422 #define CHK_HVRM \ 423 do { \ 424 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 425 GEN_PRIV; \ 426 } \ 427 } while (0) 428 #endif 429 430 #define CHK_NONE 431 432 /*****************************************************************************/ 433 /* PowerPC instructions table */ 434 435 #if defined(DO_PPC_STATISTICS) 436 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 437 { \ 438 .opc1 = op1, \ 439 .opc2 = op2, \ 440 .opc3 = op3, \ 441 .opc4 = 0xff, \ 442 .handler = { \ 443 .inval1 = invl, \ 444 .type = _typ, \ 445 .type2 = _typ2, \ 446 .handler = &gen_##name, \ 447 .oname = stringify(name), \ 448 }, \ 449 .oname = stringify(name), \ 450 } 451 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 452 { \ 453 .opc1 = op1, \ 454 .opc2 = op2, \ 455 .opc3 = op3, \ 456 .opc4 = 0xff, \ 457 .handler = { \ 458 .inval1 = invl1, \ 459 .inval2 = invl2, \ 460 .type = _typ, \ 461 .type2 = _typ2, \ 462 .handler = &gen_##name, \ 463 .oname = stringify(name), \ 464 }, \ 465 .oname = stringify(name), \ 466 } 467 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 468 { \ 469 .opc1 = op1, \ 470 .opc2 = op2, \ 471 .opc3 = op3, \ 472 .opc4 = 0xff, \ 473 .handler = { \ 474 .inval1 = invl, \ 475 .type = _typ, \ 476 .type2 = _typ2, \ 477 .handler = &gen_##name, \ 478 .oname = onam, \ 479 }, \ 480 .oname = onam, \ 481 } 482 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 483 { \ 484 .opc1 = op1, \ 485 .opc2 = op2, \ 486 .opc3 = op3, \ 487 .opc4 = op4, \ 488 .handler = { \ 489 .inval1 = invl, \ 490 .type = _typ, \ 491 .type2 = _typ2, \ 492 .handler = &gen_##name, \ 493 .oname = stringify(name), \ 494 }, \ 495 .oname = stringify(name), \ 496 } 497 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 498 { \ 499 .opc1 = op1, \ 500 .opc2 = op2, \ 501 .opc3 = op3, \ 502 .opc4 = op4, \ 503 .handler = { \ 504 .inval1 = invl, \ 505 .type = _typ, \ 506 .type2 = _typ2, \ 507 .handler = &gen_##name, \ 508 .oname = onam, \ 509 }, \ 510 .oname = onam, \ 511 } 512 #else 513 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 514 { \ 515 .opc1 = op1, \ 516 .opc2 = op2, \ 517 .opc3 = op3, \ 518 .opc4 = 0xff, \ 519 .handler = { \ 520 .inval1 = invl, \ 521 .type = _typ, \ 522 .type2 = _typ2, \ 523 .handler = &gen_##name, \ 524 }, \ 525 .oname = stringify(name), \ 526 } 527 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 528 { \ 529 .opc1 = op1, \ 530 .opc2 = op2, \ 531 .opc3 = op3, \ 532 .opc4 = 0xff, \ 533 .handler = { \ 534 .inval1 = invl1, \ 535 .inval2 = invl2, \ 536 .type = _typ, \ 537 .type2 = _typ2, \ 538 .handler = &gen_##name, \ 539 }, \ 540 .oname = stringify(name), \ 541 } 542 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 543 { \ 544 .opc1 = op1, \ 545 .opc2 = op2, \ 546 .opc3 = op3, \ 547 .opc4 = 0xff, \ 548 .handler = { \ 549 .inval1 = invl, \ 550 .type = _typ, \ 551 .type2 = _typ2, \ 552 .handler = &gen_##name, \ 553 }, \ 554 .oname = onam, \ 555 } 556 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 557 { \ 558 .opc1 = op1, \ 559 .opc2 = op2, \ 560 .opc3 = op3, \ 561 .opc4 = op4, \ 562 .handler = { \ 563 .inval1 = invl, \ 564 .type = _typ, \ 565 .type2 = _typ2, \ 566 .handler = &gen_##name, \ 567 }, \ 568 .oname = stringify(name), \ 569 } 570 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 571 { \ 572 .opc1 = op1, \ 573 .opc2 = op2, \ 574 .opc3 = op3, \ 575 .opc4 = op4, \ 576 .handler = { \ 577 .inval1 = invl, \ 578 .type = _typ, \ 579 .type2 = _typ2, \ 580 .handler = &gen_##name, \ 581 }, \ 582 .oname = onam, \ 583 } 584 #endif 585 586 /* Invalid instruction */ 587 static void gen_invalid(DisasContext *ctx) 588 { 589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 590 } 591 592 static opc_handler_t invalid_handler = { 593 .inval1 = 0xFFFFFFFF, 594 .inval2 = 0xFFFFFFFF, 595 .type = PPC_NONE, 596 .type2 = PPC_NONE, 597 .handler = gen_invalid, 598 }; 599 600 /*** Integer comparison ***/ 601 602 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 603 { 604 TCGv t0 = tcg_temp_new(); 605 TCGv t1 = tcg_temp_new(); 606 TCGv_i32 t = tcg_temp_new_i32(); 607 608 tcg_gen_movi_tl(t0, CRF_EQ); 609 tcg_gen_movi_tl(t1, CRF_LT); 610 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 611 t0, arg0, arg1, t1, t0); 612 tcg_gen_movi_tl(t1, CRF_GT); 613 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 614 t0, arg0, arg1, t1, t0); 615 616 tcg_gen_trunc_tl_i32(t, t0); 617 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 618 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 619 620 tcg_temp_free(t0); 621 tcg_temp_free(t1); 622 tcg_temp_free_i32(t); 623 } 624 625 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 626 { 627 TCGv t0 = tcg_const_tl(arg1); 628 gen_op_cmp(arg0, t0, s, crf); 629 tcg_temp_free(t0); 630 } 631 632 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 633 { 634 TCGv t0, t1; 635 t0 = tcg_temp_new(); 636 t1 = tcg_temp_new(); 637 if (s) { 638 tcg_gen_ext32s_tl(t0, arg0); 639 tcg_gen_ext32s_tl(t1, arg1); 640 } else { 641 tcg_gen_ext32u_tl(t0, arg0); 642 tcg_gen_ext32u_tl(t1, arg1); 643 } 644 gen_op_cmp(t0, t1, s, crf); 645 tcg_temp_free(t1); 646 tcg_temp_free(t0); 647 } 648 649 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 650 { 651 TCGv t0 = tcg_const_tl(arg1); 652 gen_op_cmp32(arg0, t0, s, crf); 653 tcg_temp_free(t0); 654 } 655 656 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 657 { 658 if (NARROW_MODE(ctx)) { 659 gen_op_cmpi32(reg, 0, 1, 0); 660 } else { 661 gen_op_cmpi(reg, 0, 1, 0); 662 } 663 } 664 665 /* cmp */ 666 static void gen_cmp(DisasContext *ctx) 667 { 668 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 669 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 670 1, crfD(ctx->opcode)); 671 } else { 672 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 673 1, crfD(ctx->opcode)); 674 } 675 } 676 677 /* cmpi */ 678 static void gen_cmpi(DisasContext *ctx) 679 { 680 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 681 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 682 1, crfD(ctx->opcode)); 683 } else { 684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 685 1, crfD(ctx->opcode)); 686 } 687 } 688 689 /* cmpl */ 690 static void gen_cmpl(DisasContext *ctx) 691 { 692 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 693 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 694 0, crfD(ctx->opcode)); 695 } else { 696 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 697 0, crfD(ctx->opcode)); 698 } 699 } 700 701 /* cmpli */ 702 static void gen_cmpli(DisasContext *ctx) 703 { 704 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 705 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 706 0, crfD(ctx->opcode)); 707 } else { 708 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 709 0, crfD(ctx->opcode)); 710 } 711 } 712 713 /* cmprb - range comparison: isupper, isaplha, islower*/ 714 static void gen_cmprb(DisasContext *ctx) 715 { 716 TCGv_i32 src1 = tcg_temp_new_i32(); 717 TCGv_i32 src2 = tcg_temp_new_i32(); 718 TCGv_i32 src2lo = tcg_temp_new_i32(); 719 TCGv_i32 src2hi = tcg_temp_new_i32(); 720 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 721 722 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 723 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 724 725 tcg_gen_andi_i32(src1, src1, 0xFF); 726 tcg_gen_ext8u_i32(src2lo, src2); 727 tcg_gen_shri_i32(src2, src2, 8); 728 tcg_gen_ext8u_i32(src2hi, src2); 729 730 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 731 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 732 tcg_gen_and_i32(crf, src2lo, src2hi); 733 734 if (ctx->opcode & 0x00200000) { 735 tcg_gen_shri_i32(src2, src2, 8); 736 tcg_gen_ext8u_i32(src2lo, src2); 737 tcg_gen_shri_i32(src2, src2, 8); 738 tcg_gen_ext8u_i32(src2hi, src2); 739 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 740 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 741 tcg_gen_and_i32(src2lo, src2lo, src2hi); 742 tcg_gen_or_i32(crf, crf, src2lo); 743 } 744 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 745 tcg_temp_free_i32(src1); 746 tcg_temp_free_i32(src2); 747 tcg_temp_free_i32(src2lo); 748 tcg_temp_free_i32(src2hi); 749 } 750 751 #if defined(TARGET_PPC64) 752 /* cmpeqb */ 753 static void gen_cmpeqb(DisasContext *ctx) 754 { 755 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 756 cpu_gpr[rB(ctx->opcode)]); 757 } 758 #endif 759 760 /* isel (PowerPC 2.03 specification) */ 761 static void gen_isel(DisasContext *ctx) 762 { 763 uint32_t bi = rC(ctx->opcode); 764 uint32_t mask = 0x08 >> (bi & 0x03); 765 TCGv t0 = tcg_temp_new(); 766 TCGv zr; 767 768 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 769 tcg_gen_andi_tl(t0, t0, mask); 770 771 zr = tcg_const_tl(0); 772 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 773 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 774 cpu_gpr[rB(ctx->opcode)]); 775 tcg_temp_free(zr); 776 tcg_temp_free(t0); 777 } 778 779 /* cmpb: PowerPC 2.05 specification */ 780 static void gen_cmpb(DisasContext *ctx) 781 { 782 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 783 cpu_gpr[rB(ctx->opcode)]); 784 } 785 786 /*** Integer arithmetic ***/ 787 788 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 789 TCGv arg1, TCGv arg2, int sub) 790 { 791 TCGv t0 = tcg_temp_new(); 792 793 tcg_gen_xor_tl(cpu_ov, arg0, arg2); 794 tcg_gen_xor_tl(t0, arg1, arg2); 795 if (sub) { 796 tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 797 } else { 798 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 799 } 800 tcg_temp_free(t0); 801 if (NARROW_MODE(ctx)) { 802 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 803 if (is_isa300(ctx)) { 804 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 805 } 806 } else { 807 if (is_isa300(ctx)) { 808 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 809 } 810 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 811 } 812 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 813 } 814 815 static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 816 TCGv res, TCGv arg0, TCGv arg1, 817 TCGv ca32, int sub) 818 { 819 TCGv t0; 820 821 if (!is_isa300(ctx)) { 822 return; 823 } 824 825 t0 = tcg_temp_new(); 826 if (sub) { 827 tcg_gen_eqv_tl(t0, arg0, arg1); 828 } else { 829 tcg_gen_xor_tl(t0, arg0, arg1); 830 } 831 tcg_gen_xor_tl(t0, t0, res); 832 tcg_gen_extract_tl(ca32, t0, 32, 1); 833 tcg_temp_free(t0); 834 } 835 836 /* Common add function */ 837 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 838 TCGv arg2, TCGv ca, TCGv ca32, 839 bool add_ca, bool compute_ca, 840 bool compute_ov, bool compute_rc0) 841 { 842 TCGv t0 = ret; 843 844 if (compute_ca || compute_ov) { 845 t0 = tcg_temp_new(); 846 } 847 848 if (compute_ca) { 849 if (NARROW_MODE(ctx)) { 850 /* 851 * Caution: a non-obvious corner case of the spec is that 852 * we must produce the *entire* 64-bit addition, but 853 * produce the carry into bit 32. 854 */ 855 TCGv t1 = tcg_temp_new(); 856 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 857 tcg_gen_add_tl(t0, arg1, arg2); 858 if (add_ca) { 859 tcg_gen_add_tl(t0, t0, ca); 860 } 861 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 862 tcg_temp_free(t1); 863 tcg_gen_extract_tl(ca, ca, 32, 1); 864 if (is_isa300(ctx)) { 865 tcg_gen_mov_tl(ca32, ca); 866 } 867 } else { 868 TCGv zero = tcg_const_tl(0); 869 if (add_ca) { 870 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 871 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 872 } else { 873 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 874 } 875 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 876 tcg_temp_free(zero); 877 } 878 } else { 879 tcg_gen_add_tl(t0, arg1, arg2); 880 if (add_ca) { 881 tcg_gen_add_tl(t0, t0, ca); 882 } 883 } 884 885 if (compute_ov) { 886 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 887 } 888 if (unlikely(compute_rc0)) { 889 gen_set_Rc0(ctx, t0); 890 } 891 892 if (t0 != ret) { 893 tcg_gen_mov_tl(ret, t0); 894 tcg_temp_free(t0); 895 } 896 } 897 /* Add functions with two operands */ 898 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 899 static void glue(gen_, name)(DisasContext *ctx) \ 900 { \ 901 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 902 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 903 ca, glue(ca, 32), \ 904 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 905 } 906 /* Add functions with one operand and one immediate */ 907 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 908 add_ca, compute_ca, compute_ov) \ 909 static void glue(gen_, name)(DisasContext *ctx) \ 910 { \ 911 TCGv t0 = tcg_const_tl(const_val); \ 912 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 913 cpu_gpr[rA(ctx->opcode)], t0, \ 914 ca, glue(ca, 32), \ 915 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 916 tcg_temp_free(t0); \ 917 } 918 919 /* add add. addo addo. */ 920 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 921 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 922 /* addc addc. addco addco. */ 923 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 924 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 925 /* adde adde. addeo addeo. */ 926 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 927 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 928 /* addme addme. addmeo addmeo. */ 929 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 930 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 931 /* addex */ 932 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 933 /* addze addze. addzeo addzeo.*/ 934 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 935 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 936 /* addi */ 937 static void gen_addi(DisasContext *ctx) 938 { 939 target_long simm = SIMM(ctx->opcode); 940 941 if (rA(ctx->opcode) == 0) { 942 /* li case */ 943 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 944 } else { 945 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 946 cpu_gpr[rA(ctx->opcode)], simm); 947 } 948 } 949 /* addic addic.*/ 950 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 951 { 952 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 953 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 954 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 955 tcg_temp_free(c); 956 } 957 958 static void gen_addic(DisasContext *ctx) 959 { 960 gen_op_addic(ctx, 0); 961 } 962 963 static void gen_addic_(DisasContext *ctx) 964 { 965 gen_op_addic(ctx, 1); 966 } 967 968 /* addis */ 969 static void gen_addis(DisasContext *ctx) 970 { 971 target_long simm = SIMM(ctx->opcode); 972 973 if (rA(ctx->opcode) == 0) { 974 /* lis case */ 975 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 976 } else { 977 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 978 cpu_gpr[rA(ctx->opcode)], simm << 16); 979 } 980 } 981 982 /* addpcis */ 983 static void gen_addpcis(DisasContext *ctx) 984 { 985 target_long d = DX(ctx->opcode); 986 987 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 988 } 989 990 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 991 TCGv arg2, int sign, int compute_ov) 992 { 993 TCGv_i32 t0 = tcg_temp_new_i32(); 994 TCGv_i32 t1 = tcg_temp_new_i32(); 995 TCGv_i32 t2 = tcg_temp_new_i32(); 996 TCGv_i32 t3 = tcg_temp_new_i32(); 997 998 tcg_gen_trunc_tl_i32(t0, arg1); 999 tcg_gen_trunc_tl_i32(t1, arg2); 1000 if (sign) { 1001 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1002 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1003 tcg_gen_and_i32(t2, t2, t3); 1004 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1005 tcg_gen_or_i32(t2, t2, t3); 1006 tcg_gen_movi_i32(t3, 0); 1007 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1008 tcg_gen_div_i32(t3, t0, t1); 1009 tcg_gen_extu_i32_tl(ret, t3); 1010 } else { 1011 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1012 tcg_gen_movi_i32(t3, 0); 1013 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1014 tcg_gen_divu_i32(t3, t0, t1); 1015 tcg_gen_extu_i32_tl(ret, t3); 1016 } 1017 if (compute_ov) { 1018 tcg_gen_extu_i32_tl(cpu_ov, t2); 1019 if (is_isa300(ctx)) { 1020 tcg_gen_extu_i32_tl(cpu_ov32, t2); 1021 } 1022 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1023 } 1024 tcg_temp_free_i32(t0); 1025 tcg_temp_free_i32(t1); 1026 tcg_temp_free_i32(t2); 1027 tcg_temp_free_i32(t3); 1028 1029 if (unlikely(Rc(ctx->opcode) != 0)) { 1030 gen_set_Rc0(ctx, ret); 1031 } 1032 } 1033 /* Div functions */ 1034 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1035 static void glue(gen_, name)(DisasContext *ctx) \ 1036 { \ 1037 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1038 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1039 sign, compute_ov); \ 1040 } 1041 /* divwu divwu. divwuo divwuo. */ 1042 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1043 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1044 /* divw divw. divwo divwo. */ 1045 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1046 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1047 1048 /* div[wd]eu[o][.] */ 1049 #define GEN_DIVE(name, hlpr, compute_ov) \ 1050 static void gen_##name(DisasContext *ctx) \ 1051 { \ 1052 TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1053 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1054 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1055 tcg_temp_free_i32(t0); \ 1056 if (unlikely(Rc(ctx->opcode) != 0)) { \ 1057 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1058 } \ 1059 } 1060 1061 GEN_DIVE(divweu, divweu, 0); 1062 GEN_DIVE(divweuo, divweu, 1); 1063 GEN_DIVE(divwe, divwe, 0); 1064 GEN_DIVE(divweo, divwe, 1); 1065 1066 #if defined(TARGET_PPC64) 1067 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1068 TCGv arg2, int sign, int compute_ov) 1069 { 1070 TCGv_i64 t0 = tcg_temp_new_i64(); 1071 TCGv_i64 t1 = tcg_temp_new_i64(); 1072 TCGv_i64 t2 = tcg_temp_new_i64(); 1073 TCGv_i64 t3 = tcg_temp_new_i64(); 1074 1075 tcg_gen_mov_i64(t0, arg1); 1076 tcg_gen_mov_i64(t1, arg2); 1077 if (sign) { 1078 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1079 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1080 tcg_gen_and_i64(t2, t2, t3); 1081 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1082 tcg_gen_or_i64(t2, t2, t3); 1083 tcg_gen_movi_i64(t3, 0); 1084 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1085 tcg_gen_div_i64(ret, t0, t1); 1086 } else { 1087 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1088 tcg_gen_movi_i64(t3, 0); 1089 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1090 tcg_gen_divu_i64(ret, t0, t1); 1091 } 1092 if (compute_ov) { 1093 tcg_gen_mov_tl(cpu_ov, t2); 1094 if (is_isa300(ctx)) { 1095 tcg_gen_mov_tl(cpu_ov32, t2); 1096 } 1097 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1098 } 1099 tcg_temp_free_i64(t0); 1100 tcg_temp_free_i64(t1); 1101 tcg_temp_free_i64(t2); 1102 tcg_temp_free_i64(t3); 1103 1104 if (unlikely(Rc(ctx->opcode) != 0)) { 1105 gen_set_Rc0(ctx, ret); 1106 } 1107 } 1108 1109 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1110 static void glue(gen_, name)(DisasContext *ctx) \ 1111 { \ 1112 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1113 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1114 sign, compute_ov); \ 1115 } 1116 /* divdu divdu. divduo divduo. */ 1117 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1118 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1119 /* divd divd. divdo divdo. */ 1120 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1121 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1122 1123 GEN_DIVE(divdeu, divdeu, 0); 1124 GEN_DIVE(divdeuo, divdeu, 1); 1125 GEN_DIVE(divde, divde, 0); 1126 GEN_DIVE(divdeo, divde, 1); 1127 #endif 1128 1129 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1130 TCGv arg2, int sign) 1131 { 1132 TCGv_i32 t0 = tcg_temp_new_i32(); 1133 TCGv_i32 t1 = tcg_temp_new_i32(); 1134 1135 tcg_gen_trunc_tl_i32(t0, arg1); 1136 tcg_gen_trunc_tl_i32(t1, arg2); 1137 if (sign) { 1138 TCGv_i32 t2 = tcg_temp_new_i32(); 1139 TCGv_i32 t3 = tcg_temp_new_i32(); 1140 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1141 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1142 tcg_gen_and_i32(t2, t2, t3); 1143 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1144 tcg_gen_or_i32(t2, t2, t3); 1145 tcg_gen_movi_i32(t3, 0); 1146 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1147 tcg_gen_rem_i32(t3, t0, t1); 1148 tcg_gen_ext_i32_tl(ret, t3); 1149 tcg_temp_free_i32(t2); 1150 tcg_temp_free_i32(t3); 1151 } else { 1152 TCGv_i32 t2 = tcg_const_i32(1); 1153 TCGv_i32 t3 = tcg_const_i32(0); 1154 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1155 tcg_gen_remu_i32(t3, t0, t1); 1156 tcg_gen_extu_i32_tl(ret, t3); 1157 tcg_temp_free_i32(t2); 1158 tcg_temp_free_i32(t3); 1159 } 1160 tcg_temp_free_i32(t0); 1161 tcg_temp_free_i32(t1); 1162 } 1163 1164 #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1165 static void glue(gen_, name)(DisasContext *ctx) \ 1166 { \ 1167 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1168 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1169 sign); \ 1170 } 1171 1172 GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1173 GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1174 1175 #if defined(TARGET_PPC64) 1176 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1177 TCGv arg2, int sign) 1178 { 1179 TCGv_i64 t0 = tcg_temp_new_i64(); 1180 TCGv_i64 t1 = tcg_temp_new_i64(); 1181 1182 tcg_gen_mov_i64(t0, arg1); 1183 tcg_gen_mov_i64(t1, arg2); 1184 if (sign) { 1185 TCGv_i64 t2 = tcg_temp_new_i64(); 1186 TCGv_i64 t3 = tcg_temp_new_i64(); 1187 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1188 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1189 tcg_gen_and_i64(t2, t2, t3); 1190 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1191 tcg_gen_or_i64(t2, t2, t3); 1192 tcg_gen_movi_i64(t3, 0); 1193 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1194 tcg_gen_rem_i64(ret, t0, t1); 1195 tcg_temp_free_i64(t2); 1196 tcg_temp_free_i64(t3); 1197 } else { 1198 TCGv_i64 t2 = tcg_const_i64(1); 1199 TCGv_i64 t3 = tcg_const_i64(0); 1200 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1201 tcg_gen_remu_i64(ret, t0, t1); 1202 tcg_temp_free_i64(t2); 1203 tcg_temp_free_i64(t3); 1204 } 1205 tcg_temp_free_i64(t0); 1206 tcg_temp_free_i64(t1); 1207 } 1208 1209 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1210 static void glue(gen_, name)(DisasContext *ctx) \ 1211 { \ 1212 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1213 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1214 sign); \ 1215 } 1216 1217 GEN_INT_ARITH_MODD(modud, 0x08, 0); 1218 GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1219 #endif 1220 1221 /* mulhw mulhw. */ 1222 static void gen_mulhw(DisasContext *ctx) 1223 { 1224 TCGv_i32 t0 = tcg_temp_new_i32(); 1225 TCGv_i32 t1 = tcg_temp_new_i32(); 1226 1227 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1228 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1229 tcg_gen_muls2_i32(t0, t1, t0, t1); 1230 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1231 tcg_temp_free_i32(t0); 1232 tcg_temp_free_i32(t1); 1233 if (unlikely(Rc(ctx->opcode) != 0)) { 1234 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1235 } 1236 } 1237 1238 /* mulhwu mulhwu. */ 1239 static void gen_mulhwu(DisasContext *ctx) 1240 { 1241 TCGv_i32 t0 = tcg_temp_new_i32(); 1242 TCGv_i32 t1 = tcg_temp_new_i32(); 1243 1244 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1245 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1246 tcg_gen_mulu2_i32(t0, t1, t0, t1); 1247 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1248 tcg_temp_free_i32(t0); 1249 tcg_temp_free_i32(t1); 1250 if (unlikely(Rc(ctx->opcode) != 0)) { 1251 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1252 } 1253 } 1254 1255 /* mullw mullw. */ 1256 static void gen_mullw(DisasContext *ctx) 1257 { 1258 #if defined(TARGET_PPC64) 1259 TCGv_i64 t0, t1; 1260 t0 = tcg_temp_new_i64(); 1261 t1 = tcg_temp_new_i64(); 1262 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1263 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1264 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1265 tcg_temp_free(t0); 1266 tcg_temp_free(t1); 1267 #else 1268 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1269 cpu_gpr[rB(ctx->opcode)]); 1270 #endif 1271 if (unlikely(Rc(ctx->opcode) != 0)) { 1272 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1273 } 1274 } 1275 1276 /* mullwo mullwo. */ 1277 static void gen_mullwo(DisasContext *ctx) 1278 { 1279 TCGv_i32 t0 = tcg_temp_new_i32(); 1280 TCGv_i32 t1 = tcg_temp_new_i32(); 1281 1282 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1283 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1284 tcg_gen_muls2_i32(t0, t1, t0, t1); 1285 #if defined(TARGET_PPC64) 1286 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1287 #else 1288 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1289 #endif 1290 1291 tcg_gen_sari_i32(t0, t0, 31); 1292 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1293 tcg_gen_extu_i32_tl(cpu_ov, t0); 1294 if (is_isa300(ctx)) { 1295 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1296 } 1297 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1298 1299 tcg_temp_free_i32(t0); 1300 tcg_temp_free_i32(t1); 1301 if (unlikely(Rc(ctx->opcode) != 0)) { 1302 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1303 } 1304 } 1305 1306 /* mulli */ 1307 static void gen_mulli(DisasContext *ctx) 1308 { 1309 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1310 SIMM(ctx->opcode)); 1311 } 1312 1313 #if defined(TARGET_PPC64) 1314 /* mulhd mulhd. */ 1315 static void gen_mulhd(DisasContext *ctx) 1316 { 1317 TCGv lo = tcg_temp_new(); 1318 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1319 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1320 tcg_temp_free(lo); 1321 if (unlikely(Rc(ctx->opcode) != 0)) { 1322 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1323 } 1324 } 1325 1326 /* mulhdu mulhdu. */ 1327 static void gen_mulhdu(DisasContext *ctx) 1328 { 1329 TCGv lo = tcg_temp_new(); 1330 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1331 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1332 tcg_temp_free(lo); 1333 if (unlikely(Rc(ctx->opcode) != 0)) { 1334 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1335 } 1336 } 1337 1338 /* mulld mulld. */ 1339 static void gen_mulld(DisasContext *ctx) 1340 { 1341 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1342 cpu_gpr[rB(ctx->opcode)]); 1343 if (unlikely(Rc(ctx->opcode) != 0)) { 1344 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1345 } 1346 } 1347 1348 /* mulldo mulldo. */ 1349 static void gen_mulldo(DisasContext *ctx) 1350 { 1351 TCGv_i64 t0 = tcg_temp_new_i64(); 1352 TCGv_i64 t1 = tcg_temp_new_i64(); 1353 1354 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1355 cpu_gpr[rB(ctx->opcode)]); 1356 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1357 1358 tcg_gen_sari_i64(t0, t0, 63); 1359 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 1360 if (is_isa300(ctx)) { 1361 tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1362 } 1363 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1364 1365 tcg_temp_free_i64(t0); 1366 tcg_temp_free_i64(t1); 1367 1368 if (unlikely(Rc(ctx->opcode) != 0)) { 1369 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1370 } 1371 } 1372 #endif 1373 1374 /* Common subf function */ 1375 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1376 TCGv arg2, bool add_ca, bool compute_ca, 1377 bool compute_ov, bool compute_rc0) 1378 { 1379 TCGv t0 = ret; 1380 1381 if (compute_ca || compute_ov) { 1382 t0 = tcg_temp_new(); 1383 } 1384 1385 if (compute_ca) { 1386 /* dest = ~arg1 + arg2 [+ ca]. */ 1387 if (NARROW_MODE(ctx)) { 1388 /* 1389 * Caution: a non-obvious corner case of the spec is that 1390 * we must produce the *entire* 64-bit addition, but 1391 * produce the carry into bit 32. 1392 */ 1393 TCGv inv1 = tcg_temp_new(); 1394 TCGv t1 = tcg_temp_new(); 1395 tcg_gen_not_tl(inv1, arg1); 1396 if (add_ca) { 1397 tcg_gen_add_tl(t0, arg2, cpu_ca); 1398 } else { 1399 tcg_gen_addi_tl(t0, arg2, 1); 1400 } 1401 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1402 tcg_gen_add_tl(t0, t0, inv1); 1403 tcg_temp_free(inv1); 1404 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1405 tcg_temp_free(t1); 1406 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 1407 if (is_isa300(ctx)) { 1408 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 1409 } 1410 } else if (add_ca) { 1411 TCGv zero, inv1 = tcg_temp_new(); 1412 tcg_gen_not_tl(inv1, arg1); 1413 zero = tcg_const_tl(0); 1414 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1415 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 1416 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 1417 tcg_temp_free(zero); 1418 tcg_temp_free(inv1); 1419 } else { 1420 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1421 tcg_gen_sub_tl(t0, arg2, arg1); 1422 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 1423 } 1424 } else if (add_ca) { 1425 /* 1426 * Since we're ignoring carry-out, we can simplify the 1427 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 1428 */ 1429 tcg_gen_sub_tl(t0, arg2, arg1); 1430 tcg_gen_add_tl(t0, t0, cpu_ca); 1431 tcg_gen_subi_tl(t0, t0, 1); 1432 } else { 1433 tcg_gen_sub_tl(t0, arg2, arg1); 1434 } 1435 1436 if (compute_ov) { 1437 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1438 } 1439 if (unlikely(compute_rc0)) { 1440 gen_set_Rc0(ctx, t0); 1441 } 1442 1443 if (t0 != ret) { 1444 tcg_gen_mov_tl(ret, t0); 1445 tcg_temp_free(t0); 1446 } 1447 } 1448 /* Sub functions with Two operands functions */ 1449 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1450 static void glue(gen_, name)(DisasContext *ctx) \ 1451 { \ 1452 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1453 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1454 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1455 } 1456 /* Sub functions with one operand and one immediate */ 1457 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1458 add_ca, compute_ca, compute_ov) \ 1459 static void glue(gen_, name)(DisasContext *ctx) \ 1460 { \ 1461 TCGv t0 = tcg_const_tl(const_val); \ 1462 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1463 cpu_gpr[rA(ctx->opcode)], t0, \ 1464 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1465 tcg_temp_free(t0); \ 1466 } 1467 /* subf subf. subfo subfo. */ 1468 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1469 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1470 /* subfc subfc. subfco subfco. */ 1471 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1472 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1473 /* subfe subfe. subfeo subfo. */ 1474 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1475 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1476 /* subfme subfme. subfmeo subfmeo. */ 1477 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1478 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1479 /* subfze subfze. subfzeo subfzeo.*/ 1480 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1481 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1482 1483 /* subfic */ 1484 static void gen_subfic(DisasContext *ctx) 1485 { 1486 TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1487 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1488 c, 0, 1, 0, 0); 1489 tcg_temp_free(c); 1490 } 1491 1492 /* neg neg. nego nego. */ 1493 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1494 { 1495 TCGv zero = tcg_const_tl(0); 1496 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1497 zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1498 tcg_temp_free(zero); 1499 } 1500 1501 static void gen_neg(DisasContext *ctx) 1502 { 1503 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 1504 if (unlikely(Rc(ctx->opcode))) { 1505 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1506 } 1507 } 1508 1509 static void gen_nego(DisasContext *ctx) 1510 { 1511 gen_op_arith_neg(ctx, 1); 1512 } 1513 1514 /*** Integer logical ***/ 1515 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1516 static void glue(gen_, name)(DisasContext *ctx) \ 1517 { \ 1518 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1519 cpu_gpr[rB(ctx->opcode)]); \ 1520 if (unlikely(Rc(ctx->opcode) != 0)) \ 1521 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1522 } 1523 1524 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1525 static void glue(gen_, name)(DisasContext *ctx) \ 1526 { \ 1527 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1528 if (unlikely(Rc(ctx->opcode) != 0)) \ 1529 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1530 } 1531 1532 /* and & and. */ 1533 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1534 /* andc & andc. */ 1535 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1536 1537 /* andi. */ 1538 static void gen_andi_(DisasContext *ctx) 1539 { 1540 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1541 UIMM(ctx->opcode)); 1542 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1543 } 1544 1545 /* andis. */ 1546 static void gen_andis_(DisasContext *ctx) 1547 { 1548 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1549 UIMM(ctx->opcode) << 16); 1550 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1551 } 1552 1553 /* cntlzw */ 1554 static void gen_cntlzw(DisasContext *ctx) 1555 { 1556 TCGv_i32 t = tcg_temp_new_i32(); 1557 1558 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 1559 tcg_gen_clzi_i32(t, t, 32); 1560 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 1561 tcg_temp_free_i32(t); 1562 1563 if (unlikely(Rc(ctx->opcode) != 0)) { 1564 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1565 } 1566 } 1567 1568 /* cnttzw */ 1569 static void gen_cnttzw(DisasContext *ctx) 1570 { 1571 TCGv_i32 t = tcg_temp_new_i32(); 1572 1573 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 1574 tcg_gen_ctzi_i32(t, t, 32); 1575 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 1576 tcg_temp_free_i32(t); 1577 1578 if (unlikely(Rc(ctx->opcode) != 0)) { 1579 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1580 } 1581 } 1582 1583 /* eqv & eqv. */ 1584 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1585 /* extsb & extsb. */ 1586 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1587 /* extsh & extsh. */ 1588 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1589 /* nand & nand. */ 1590 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1591 /* nor & nor. */ 1592 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1593 1594 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1595 static void gen_pause(DisasContext *ctx) 1596 { 1597 TCGv_i32 t0 = tcg_const_i32(0); 1598 tcg_gen_st_i32(t0, cpu_env, 1599 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1600 tcg_temp_free_i32(t0); 1601 1602 /* Stop translation, this gives other CPUs a chance to run */ 1603 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1604 } 1605 #endif /* defined(TARGET_PPC64) */ 1606 1607 /* or & or. */ 1608 static void gen_or(DisasContext *ctx) 1609 { 1610 int rs, ra, rb; 1611 1612 rs = rS(ctx->opcode); 1613 ra = rA(ctx->opcode); 1614 rb = rB(ctx->opcode); 1615 /* Optimisation for mr. ri case */ 1616 if (rs != ra || rs != rb) { 1617 if (rs != rb) { 1618 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1619 } else { 1620 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1621 } 1622 if (unlikely(Rc(ctx->opcode) != 0)) { 1623 gen_set_Rc0(ctx, cpu_gpr[ra]); 1624 } 1625 } else if (unlikely(Rc(ctx->opcode) != 0)) { 1626 gen_set_Rc0(ctx, cpu_gpr[rs]); 1627 #if defined(TARGET_PPC64) 1628 } else if (rs != 0) { /* 0 is nop */ 1629 int prio = 0; 1630 1631 switch (rs) { 1632 case 1: 1633 /* Set process priority to low */ 1634 prio = 2; 1635 break; 1636 case 6: 1637 /* Set process priority to medium-low */ 1638 prio = 3; 1639 break; 1640 case 2: 1641 /* Set process priority to normal */ 1642 prio = 4; 1643 break; 1644 #if !defined(CONFIG_USER_ONLY) 1645 case 31: 1646 if (!ctx->pr) { 1647 /* Set process priority to very low */ 1648 prio = 1; 1649 } 1650 break; 1651 case 5: 1652 if (!ctx->pr) { 1653 /* Set process priority to medium-hight */ 1654 prio = 5; 1655 } 1656 break; 1657 case 3: 1658 if (!ctx->pr) { 1659 /* Set process priority to high */ 1660 prio = 6; 1661 } 1662 break; 1663 case 7: 1664 if (ctx->hv && !ctx->pr) { 1665 /* Set process priority to very high */ 1666 prio = 7; 1667 } 1668 break; 1669 #endif 1670 default: 1671 break; 1672 } 1673 if (prio) { 1674 TCGv t0 = tcg_temp_new(); 1675 gen_load_spr(t0, SPR_PPR); 1676 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1677 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1678 gen_store_spr(SPR_PPR, t0); 1679 tcg_temp_free(t0); 1680 } 1681 #if !defined(CONFIG_USER_ONLY) 1682 /* 1683 * Pause out of TCG otherwise spin loops with smt_low eat too 1684 * much CPU and the kernel hangs. This applies to all 1685 * encodings other than no-op, e.g., miso(rs=26), yield(27), 1686 * mdoio(29), mdoom(30), and all currently undefined. 1687 */ 1688 gen_pause(ctx); 1689 #endif 1690 #endif 1691 } 1692 } 1693 /* orc & orc. */ 1694 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1695 1696 /* xor & xor. */ 1697 static void gen_xor(DisasContext *ctx) 1698 { 1699 /* Optimisation for "set to zero" case */ 1700 if (rS(ctx->opcode) != rB(ctx->opcode)) { 1701 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1702 cpu_gpr[rB(ctx->opcode)]); 1703 } else { 1704 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1705 } 1706 if (unlikely(Rc(ctx->opcode) != 0)) { 1707 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1708 } 1709 } 1710 1711 /* ori */ 1712 static void gen_ori(DisasContext *ctx) 1713 { 1714 target_ulong uimm = UIMM(ctx->opcode); 1715 1716 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1717 return; 1718 } 1719 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1720 } 1721 1722 /* oris */ 1723 static void gen_oris(DisasContext *ctx) 1724 { 1725 target_ulong uimm = UIMM(ctx->opcode); 1726 1727 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1728 /* NOP */ 1729 return; 1730 } 1731 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1732 uimm << 16); 1733 } 1734 1735 /* xori */ 1736 static void gen_xori(DisasContext *ctx) 1737 { 1738 target_ulong uimm = UIMM(ctx->opcode); 1739 1740 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1741 /* NOP */ 1742 return; 1743 } 1744 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1745 } 1746 1747 /* xoris */ 1748 static void gen_xoris(DisasContext *ctx) 1749 { 1750 target_ulong uimm = UIMM(ctx->opcode); 1751 1752 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1753 /* NOP */ 1754 return; 1755 } 1756 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1757 uimm << 16); 1758 } 1759 1760 /* popcntb : PowerPC 2.03 specification */ 1761 static void gen_popcntb(DisasContext *ctx) 1762 { 1763 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1764 } 1765 1766 static void gen_popcntw(DisasContext *ctx) 1767 { 1768 #if defined(TARGET_PPC64) 1769 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1770 #else 1771 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1772 #endif 1773 } 1774 1775 #if defined(TARGET_PPC64) 1776 /* popcntd: PowerPC 2.06 specification */ 1777 static void gen_popcntd(DisasContext *ctx) 1778 { 1779 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1780 } 1781 #endif 1782 1783 /* prtyw: PowerPC 2.05 specification */ 1784 static void gen_prtyw(DisasContext *ctx) 1785 { 1786 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1787 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1788 TCGv t0 = tcg_temp_new(); 1789 tcg_gen_shri_tl(t0, rs, 16); 1790 tcg_gen_xor_tl(ra, rs, t0); 1791 tcg_gen_shri_tl(t0, ra, 8); 1792 tcg_gen_xor_tl(ra, ra, t0); 1793 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1794 tcg_temp_free(t0); 1795 } 1796 1797 #if defined(TARGET_PPC64) 1798 /* prtyd: PowerPC 2.05 specification */ 1799 static void gen_prtyd(DisasContext *ctx) 1800 { 1801 TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1802 TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1803 TCGv t0 = tcg_temp_new(); 1804 tcg_gen_shri_tl(t0, rs, 32); 1805 tcg_gen_xor_tl(ra, rs, t0); 1806 tcg_gen_shri_tl(t0, ra, 16); 1807 tcg_gen_xor_tl(ra, ra, t0); 1808 tcg_gen_shri_tl(t0, ra, 8); 1809 tcg_gen_xor_tl(ra, ra, t0); 1810 tcg_gen_andi_tl(ra, ra, 1); 1811 tcg_temp_free(t0); 1812 } 1813 #endif 1814 1815 #if defined(TARGET_PPC64) 1816 /* bpermd */ 1817 static void gen_bpermd(DisasContext *ctx) 1818 { 1819 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1820 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1821 } 1822 #endif 1823 1824 #if defined(TARGET_PPC64) 1825 /* extsw & extsw. */ 1826 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1827 1828 /* cntlzd */ 1829 static void gen_cntlzd(DisasContext *ctx) 1830 { 1831 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1832 if (unlikely(Rc(ctx->opcode) != 0)) { 1833 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1834 } 1835 } 1836 1837 /* cnttzd */ 1838 static void gen_cnttzd(DisasContext *ctx) 1839 { 1840 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1841 if (unlikely(Rc(ctx->opcode) != 0)) { 1842 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1843 } 1844 } 1845 1846 /* darn */ 1847 static void gen_darn(DisasContext *ctx) 1848 { 1849 int l = L(ctx->opcode); 1850 1851 if (l > 2) { 1852 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1853 } else { 1854 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 1855 gen_io_start(); 1856 } 1857 if (l == 0) { 1858 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1859 } else { 1860 /* Return 64-bit random for both CRN and RRN */ 1861 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1862 } 1863 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 1864 gen_stop_exception(ctx); 1865 } 1866 } 1867 } 1868 #endif 1869 1870 /*** Integer rotate ***/ 1871 1872 /* rlwimi & rlwimi. */ 1873 static void gen_rlwimi(DisasContext *ctx) 1874 { 1875 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1876 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1877 uint32_t sh = SH(ctx->opcode); 1878 uint32_t mb = MB(ctx->opcode); 1879 uint32_t me = ME(ctx->opcode); 1880 1881 if (sh == (31 - me) && mb <= me) { 1882 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1883 } else { 1884 target_ulong mask; 1885 bool mask_in_32b = true; 1886 TCGv t1; 1887 1888 #if defined(TARGET_PPC64) 1889 mb += 32; 1890 me += 32; 1891 #endif 1892 mask = MASK(mb, me); 1893 1894 #if defined(TARGET_PPC64) 1895 if (mask > 0xffffffffu) { 1896 mask_in_32b = false; 1897 } 1898 #endif 1899 t1 = tcg_temp_new(); 1900 if (mask_in_32b) { 1901 TCGv_i32 t0 = tcg_temp_new_i32(); 1902 tcg_gen_trunc_tl_i32(t0, t_rs); 1903 tcg_gen_rotli_i32(t0, t0, sh); 1904 tcg_gen_extu_i32_tl(t1, t0); 1905 tcg_temp_free_i32(t0); 1906 } else { 1907 #if defined(TARGET_PPC64) 1908 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1909 tcg_gen_rotli_i64(t1, t1, sh); 1910 #else 1911 g_assert_not_reached(); 1912 #endif 1913 } 1914 1915 tcg_gen_andi_tl(t1, t1, mask); 1916 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1917 tcg_gen_or_tl(t_ra, t_ra, t1); 1918 tcg_temp_free(t1); 1919 } 1920 if (unlikely(Rc(ctx->opcode) != 0)) { 1921 gen_set_Rc0(ctx, t_ra); 1922 } 1923 } 1924 1925 /* rlwinm & rlwinm. */ 1926 static void gen_rlwinm(DisasContext *ctx) 1927 { 1928 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1929 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1930 int sh = SH(ctx->opcode); 1931 int mb = MB(ctx->opcode); 1932 int me = ME(ctx->opcode); 1933 int len = me - mb + 1; 1934 int rsh = (32 - sh) & 31; 1935 1936 if (sh != 0 && len > 0 && me == (31 - sh)) { 1937 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 1938 } else if (me == 31 && rsh + len <= 32) { 1939 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1940 } else { 1941 target_ulong mask; 1942 bool mask_in_32b = true; 1943 #if defined(TARGET_PPC64) 1944 mb += 32; 1945 me += 32; 1946 #endif 1947 mask = MASK(mb, me); 1948 #if defined(TARGET_PPC64) 1949 if (mask > 0xffffffffu) { 1950 mask_in_32b = false; 1951 } 1952 #endif 1953 if (mask_in_32b) { 1954 if (sh == 0) { 1955 tcg_gen_andi_tl(t_ra, t_rs, mask); 1956 } else { 1957 TCGv_i32 t0 = tcg_temp_new_i32(); 1958 tcg_gen_trunc_tl_i32(t0, t_rs); 1959 tcg_gen_rotli_i32(t0, t0, sh); 1960 tcg_gen_andi_i32(t0, t0, mask); 1961 tcg_gen_extu_i32_tl(t_ra, t0); 1962 tcg_temp_free_i32(t0); 1963 } 1964 } else { 1965 #if defined(TARGET_PPC64) 1966 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1967 tcg_gen_rotli_i64(t_ra, t_ra, sh); 1968 tcg_gen_andi_i64(t_ra, t_ra, mask); 1969 #else 1970 g_assert_not_reached(); 1971 #endif 1972 } 1973 } 1974 if (unlikely(Rc(ctx->opcode) != 0)) { 1975 gen_set_Rc0(ctx, t_ra); 1976 } 1977 } 1978 1979 /* rlwnm & rlwnm. */ 1980 static void gen_rlwnm(DisasContext *ctx) 1981 { 1982 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1983 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1984 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1985 uint32_t mb = MB(ctx->opcode); 1986 uint32_t me = ME(ctx->opcode); 1987 target_ulong mask; 1988 bool mask_in_32b = true; 1989 1990 #if defined(TARGET_PPC64) 1991 mb += 32; 1992 me += 32; 1993 #endif 1994 mask = MASK(mb, me); 1995 1996 #if defined(TARGET_PPC64) 1997 if (mask > 0xffffffffu) { 1998 mask_in_32b = false; 1999 } 2000 #endif 2001 if (mask_in_32b) { 2002 TCGv_i32 t0 = tcg_temp_new_i32(); 2003 TCGv_i32 t1 = tcg_temp_new_i32(); 2004 tcg_gen_trunc_tl_i32(t0, t_rb); 2005 tcg_gen_trunc_tl_i32(t1, t_rs); 2006 tcg_gen_andi_i32(t0, t0, 0x1f); 2007 tcg_gen_rotl_i32(t1, t1, t0); 2008 tcg_gen_extu_i32_tl(t_ra, t1); 2009 tcg_temp_free_i32(t0); 2010 tcg_temp_free_i32(t1); 2011 } else { 2012 #if defined(TARGET_PPC64) 2013 TCGv_i64 t0 = tcg_temp_new_i64(); 2014 tcg_gen_andi_i64(t0, t_rb, 0x1f); 2015 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2016 tcg_gen_rotl_i64(t_ra, t_ra, t0); 2017 tcg_temp_free_i64(t0); 2018 #else 2019 g_assert_not_reached(); 2020 #endif 2021 } 2022 2023 tcg_gen_andi_tl(t_ra, t_ra, mask); 2024 2025 if (unlikely(Rc(ctx->opcode) != 0)) { 2026 gen_set_Rc0(ctx, t_ra); 2027 } 2028 } 2029 2030 #if defined(TARGET_PPC64) 2031 #define GEN_PPC64_R2(name, opc1, opc2) \ 2032 static void glue(gen_, name##0)(DisasContext *ctx) \ 2033 { \ 2034 gen_##name(ctx, 0); \ 2035 } \ 2036 \ 2037 static void glue(gen_, name##1)(DisasContext *ctx) \ 2038 { \ 2039 gen_##name(ctx, 1); \ 2040 } 2041 #define GEN_PPC64_R4(name, opc1, opc2) \ 2042 static void glue(gen_, name##0)(DisasContext *ctx) \ 2043 { \ 2044 gen_##name(ctx, 0, 0); \ 2045 } \ 2046 \ 2047 static void glue(gen_, name##1)(DisasContext *ctx) \ 2048 { \ 2049 gen_##name(ctx, 0, 1); \ 2050 } \ 2051 \ 2052 static void glue(gen_, name##2)(DisasContext *ctx) \ 2053 { \ 2054 gen_##name(ctx, 1, 0); \ 2055 } \ 2056 \ 2057 static void glue(gen_, name##3)(DisasContext *ctx) \ 2058 { \ 2059 gen_##name(ctx, 1, 1); \ 2060 } 2061 2062 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2063 { 2064 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2065 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2066 int len = me - mb + 1; 2067 int rsh = (64 - sh) & 63; 2068 2069 if (sh != 0 && len > 0 && me == (63 - sh)) { 2070 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 2071 } else if (me == 63 && rsh + len <= 64) { 2072 tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2073 } else { 2074 tcg_gen_rotli_tl(t_ra, t_rs, sh); 2075 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2076 } 2077 if (unlikely(Rc(ctx->opcode) != 0)) { 2078 gen_set_Rc0(ctx, t_ra); 2079 } 2080 } 2081 2082 /* rldicl - rldicl. */ 2083 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2084 { 2085 uint32_t sh, mb; 2086 2087 sh = SH(ctx->opcode) | (shn << 5); 2088 mb = MB(ctx->opcode) | (mbn << 5); 2089 gen_rldinm(ctx, mb, 63, sh); 2090 } 2091 GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2092 2093 /* rldicr - rldicr. */ 2094 static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2095 { 2096 uint32_t sh, me; 2097 2098 sh = SH(ctx->opcode) | (shn << 5); 2099 me = MB(ctx->opcode) | (men << 5); 2100 gen_rldinm(ctx, 0, me, sh); 2101 } 2102 GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2103 2104 /* rldic - rldic. */ 2105 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2106 { 2107 uint32_t sh, mb; 2108 2109 sh = SH(ctx->opcode) | (shn << 5); 2110 mb = MB(ctx->opcode) | (mbn << 5); 2111 gen_rldinm(ctx, mb, 63 - sh, sh); 2112 } 2113 GEN_PPC64_R4(rldic, 0x1E, 0x04); 2114 2115 static void gen_rldnm(DisasContext *ctx, int mb, int me) 2116 { 2117 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2118 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2119 TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2120 TCGv t0; 2121 2122 t0 = tcg_temp_new(); 2123 tcg_gen_andi_tl(t0, t_rb, 0x3f); 2124 tcg_gen_rotl_tl(t_ra, t_rs, t0); 2125 tcg_temp_free(t0); 2126 2127 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2128 if (unlikely(Rc(ctx->opcode) != 0)) { 2129 gen_set_Rc0(ctx, t_ra); 2130 } 2131 } 2132 2133 /* rldcl - rldcl. */ 2134 static inline void gen_rldcl(DisasContext *ctx, int mbn) 2135 { 2136 uint32_t mb; 2137 2138 mb = MB(ctx->opcode) | (mbn << 5); 2139 gen_rldnm(ctx, mb, 63); 2140 } 2141 GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2142 2143 /* rldcr - rldcr. */ 2144 static inline void gen_rldcr(DisasContext *ctx, int men) 2145 { 2146 uint32_t me; 2147 2148 me = MB(ctx->opcode) | (men << 5); 2149 gen_rldnm(ctx, 0, me); 2150 } 2151 GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2152 2153 /* rldimi - rldimi. */ 2154 static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2155 { 2156 TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2157 TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2158 uint32_t sh = SH(ctx->opcode) | (shn << 5); 2159 uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2160 uint32_t me = 63 - sh; 2161 2162 if (mb <= me) { 2163 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2164 } else { 2165 target_ulong mask = MASK(mb, me); 2166 TCGv t1 = tcg_temp_new(); 2167 2168 tcg_gen_rotli_tl(t1, t_rs, sh); 2169 tcg_gen_andi_tl(t1, t1, mask); 2170 tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2171 tcg_gen_or_tl(t_ra, t_ra, t1); 2172 tcg_temp_free(t1); 2173 } 2174 if (unlikely(Rc(ctx->opcode) != 0)) { 2175 gen_set_Rc0(ctx, t_ra); 2176 } 2177 } 2178 GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2179 #endif 2180 2181 /*** Integer shift ***/ 2182 2183 /* slw & slw. */ 2184 static void gen_slw(DisasContext *ctx) 2185 { 2186 TCGv t0, t1; 2187 2188 t0 = tcg_temp_new(); 2189 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2190 #if defined(TARGET_PPC64) 2191 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2192 tcg_gen_sari_tl(t0, t0, 0x3f); 2193 #else 2194 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2195 tcg_gen_sari_tl(t0, t0, 0x1f); 2196 #endif 2197 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2198 t1 = tcg_temp_new(); 2199 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2200 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2201 tcg_temp_free(t1); 2202 tcg_temp_free(t0); 2203 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2204 if (unlikely(Rc(ctx->opcode) != 0)) { 2205 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2206 } 2207 } 2208 2209 /* sraw & sraw. */ 2210 static void gen_sraw(DisasContext *ctx) 2211 { 2212 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2213 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2214 if (unlikely(Rc(ctx->opcode) != 0)) { 2215 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2216 } 2217 } 2218 2219 /* srawi & srawi. */ 2220 static void gen_srawi(DisasContext *ctx) 2221 { 2222 int sh = SH(ctx->opcode); 2223 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2224 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2225 if (sh == 0) { 2226 tcg_gen_ext32s_tl(dst, src); 2227 tcg_gen_movi_tl(cpu_ca, 0); 2228 if (is_isa300(ctx)) { 2229 tcg_gen_movi_tl(cpu_ca32, 0); 2230 } 2231 } else { 2232 TCGv t0; 2233 tcg_gen_ext32s_tl(dst, src); 2234 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2235 t0 = tcg_temp_new(); 2236 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2237 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2238 tcg_temp_free(t0); 2239 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2240 if (is_isa300(ctx)) { 2241 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2242 } 2243 tcg_gen_sari_tl(dst, dst, sh); 2244 } 2245 if (unlikely(Rc(ctx->opcode) != 0)) { 2246 gen_set_Rc0(ctx, dst); 2247 } 2248 } 2249 2250 /* srw & srw. */ 2251 static void gen_srw(DisasContext *ctx) 2252 { 2253 TCGv t0, t1; 2254 2255 t0 = tcg_temp_new(); 2256 /* AND rS with a mask that is 0 when rB >= 0x20 */ 2257 #if defined(TARGET_PPC64) 2258 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2259 tcg_gen_sari_tl(t0, t0, 0x3f); 2260 #else 2261 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2262 tcg_gen_sari_tl(t0, t0, 0x1f); 2263 #endif 2264 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2265 tcg_gen_ext32u_tl(t0, t0); 2266 t1 = tcg_temp_new(); 2267 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2268 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2269 tcg_temp_free(t1); 2270 tcg_temp_free(t0); 2271 if (unlikely(Rc(ctx->opcode) != 0)) { 2272 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2273 } 2274 } 2275 2276 #if defined(TARGET_PPC64) 2277 /* sld & sld. */ 2278 static void gen_sld(DisasContext *ctx) 2279 { 2280 TCGv t0, t1; 2281 2282 t0 = tcg_temp_new(); 2283 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2284 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2285 tcg_gen_sari_tl(t0, t0, 0x3f); 2286 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2287 t1 = tcg_temp_new(); 2288 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2289 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2290 tcg_temp_free(t1); 2291 tcg_temp_free(t0); 2292 if (unlikely(Rc(ctx->opcode) != 0)) { 2293 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2294 } 2295 } 2296 2297 /* srad & srad. */ 2298 static void gen_srad(DisasContext *ctx) 2299 { 2300 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2301 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2302 if (unlikely(Rc(ctx->opcode) != 0)) { 2303 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2304 } 2305 } 2306 /* sradi & sradi. */ 2307 static inline void gen_sradi(DisasContext *ctx, int n) 2308 { 2309 int sh = SH(ctx->opcode) + (n << 5); 2310 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2311 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2312 if (sh == 0) { 2313 tcg_gen_mov_tl(dst, src); 2314 tcg_gen_movi_tl(cpu_ca, 0); 2315 if (is_isa300(ctx)) { 2316 tcg_gen_movi_tl(cpu_ca32, 0); 2317 } 2318 } else { 2319 TCGv t0; 2320 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2321 t0 = tcg_temp_new(); 2322 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2323 tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2324 tcg_temp_free(t0); 2325 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2326 if (is_isa300(ctx)) { 2327 tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2328 } 2329 tcg_gen_sari_tl(dst, src, sh); 2330 } 2331 if (unlikely(Rc(ctx->opcode) != 0)) { 2332 gen_set_Rc0(ctx, dst); 2333 } 2334 } 2335 2336 static void gen_sradi0(DisasContext *ctx) 2337 { 2338 gen_sradi(ctx, 0); 2339 } 2340 2341 static void gen_sradi1(DisasContext *ctx) 2342 { 2343 gen_sradi(ctx, 1); 2344 } 2345 2346 /* extswsli & extswsli. */ 2347 static inline void gen_extswsli(DisasContext *ctx, int n) 2348 { 2349 int sh = SH(ctx->opcode) + (n << 5); 2350 TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2351 TCGv src = cpu_gpr[rS(ctx->opcode)]; 2352 2353 tcg_gen_ext32s_tl(dst, src); 2354 tcg_gen_shli_tl(dst, dst, sh); 2355 if (unlikely(Rc(ctx->opcode) != 0)) { 2356 gen_set_Rc0(ctx, dst); 2357 } 2358 } 2359 2360 static void gen_extswsli0(DisasContext *ctx) 2361 { 2362 gen_extswsli(ctx, 0); 2363 } 2364 2365 static void gen_extswsli1(DisasContext *ctx) 2366 { 2367 gen_extswsli(ctx, 1); 2368 } 2369 2370 /* srd & srd. */ 2371 static void gen_srd(DisasContext *ctx) 2372 { 2373 TCGv t0, t1; 2374 2375 t0 = tcg_temp_new(); 2376 /* AND rS with a mask that is 0 when rB >= 0x40 */ 2377 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2378 tcg_gen_sari_tl(t0, t0, 0x3f); 2379 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2380 t1 = tcg_temp_new(); 2381 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2382 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2383 tcg_temp_free(t1); 2384 tcg_temp_free(t0); 2385 if (unlikely(Rc(ctx->opcode) != 0)) { 2386 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2387 } 2388 } 2389 #endif 2390 2391 /*** Addressing modes ***/ 2392 /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2393 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2394 target_long maskl) 2395 { 2396 target_long simm = SIMM(ctx->opcode); 2397 2398 simm &= ~maskl; 2399 if (rA(ctx->opcode) == 0) { 2400 if (NARROW_MODE(ctx)) { 2401 simm = (uint32_t)simm; 2402 } 2403 tcg_gen_movi_tl(EA, simm); 2404 } else if (likely(simm != 0)) { 2405 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2406 if (NARROW_MODE(ctx)) { 2407 tcg_gen_ext32u_tl(EA, EA); 2408 } 2409 } else { 2410 if (NARROW_MODE(ctx)) { 2411 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2412 } else { 2413 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2414 } 2415 } 2416 } 2417 2418 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2419 { 2420 if (rA(ctx->opcode) == 0) { 2421 if (NARROW_MODE(ctx)) { 2422 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2423 } else { 2424 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2425 } 2426 } else { 2427 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2428 if (NARROW_MODE(ctx)) { 2429 tcg_gen_ext32u_tl(EA, EA); 2430 } 2431 } 2432 } 2433 2434 static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2435 { 2436 if (rA(ctx->opcode) == 0) { 2437 tcg_gen_movi_tl(EA, 0); 2438 } else if (NARROW_MODE(ctx)) { 2439 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2440 } else { 2441 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2442 } 2443 } 2444 2445 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2446 target_long val) 2447 { 2448 tcg_gen_addi_tl(ret, arg1, val); 2449 if (NARROW_MODE(ctx)) { 2450 tcg_gen_ext32u_tl(ret, ret); 2451 } 2452 } 2453 2454 static inline void gen_align_no_le(DisasContext *ctx) 2455 { 2456 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2457 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2458 } 2459 2460 /*** Integer load ***/ 2461 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2462 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2463 2464 #define GEN_QEMU_LOAD_TL(ldop, op) \ 2465 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2466 TCGv val, \ 2467 TCGv addr) \ 2468 { \ 2469 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2470 } 2471 2472 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2473 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2474 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2475 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2476 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2477 2478 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2479 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2480 2481 #define GEN_QEMU_LOAD_64(ldop, op) \ 2482 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2483 TCGv_i64 val, \ 2484 TCGv addr) \ 2485 { \ 2486 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2487 } 2488 2489 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2490 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2491 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2492 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2493 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2494 2495 #if defined(TARGET_PPC64) 2496 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2497 #endif 2498 2499 #define GEN_QEMU_STORE_TL(stop, op) \ 2500 static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2501 TCGv val, \ 2502 TCGv addr) \ 2503 { \ 2504 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2505 } 2506 2507 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2508 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2509 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2510 2511 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2512 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2513 2514 #define GEN_QEMU_STORE_64(stop, op) \ 2515 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2516 TCGv_i64 val, \ 2517 TCGv addr) \ 2518 { \ 2519 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2520 } 2521 2522 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2523 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2524 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2525 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2526 2527 #if defined(TARGET_PPC64) 2528 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2529 #endif 2530 2531 #define GEN_LD(name, ldop, opc, type) \ 2532 static void glue(gen_, name)(DisasContext *ctx) \ 2533 { \ 2534 TCGv EA; \ 2535 gen_set_access_type(ctx, ACCESS_INT); \ 2536 EA = tcg_temp_new(); \ 2537 gen_addr_imm_index(ctx, EA, 0); \ 2538 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2539 tcg_temp_free(EA); \ 2540 } 2541 2542 #define GEN_LDU(name, ldop, opc, type) \ 2543 static void glue(gen_, name##u)(DisasContext *ctx) \ 2544 { \ 2545 TCGv EA; \ 2546 if (unlikely(rA(ctx->opcode) == 0 || \ 2547 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2548 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2549 return; \ 2550 } \ 2551 gen_set_access_type(ctx, ACCESS_INT); \ 2552 EA = tcg_temp_new(); \ 2553 if (type == PPC_64B) \ 2554 gen_addr_imm_index(ctx, EA, 0x03); \ 2555 else \ 2556 gen_addr_imm_index(ctx, EA, 0); \ 2557 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2558 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2559 tcg_temp_free(EA); \ 2560 } 2561 2562 #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2563 static void glue(gen_, name##ux)(DisasContext *ctx) \ 2564 { \ 2565 TCGv EA; \ 2566 if (unlikely(rA(ctx->opcode) == 0 || \ 2567 rA(ctx->opcode) == rD(ctx->opcode))) { \ 2568 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2569 return; \ 2570 } \ 2571 gen_set_access_type(ctx, ACCESS_INT); \ 2572 EA = tcg_temp_new(); \ 2573 gen_addr_reg_index(ctx, EA); \ 2574 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2575 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2576 tcg_temp_free(EA); \ 2577 } 2578 2579 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2580 static void glue(gen_, name##x)(DisasContext *ctx) \ 2581 { \ 2582 TCGv EA; \ 2583 chk; \ 2584 gen_set_access_type(ctx, ACCESS_INT); \ 2585 EA = tcg_temp_new(); \ 2586 gen_addr_reg_index(ctx, EA); \ 2587 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2588 tcg_temp_free(EA); \ 2589 } 2590 2591 #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2592 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2593 2594 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2595 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2596 2597 #define GEN_LDS(name, ldop, op, type) \ 2598 GEN_LD(name, ldop, op | 0x20, type); \ 2599 GEN_LDU(name, ldop, op | 0x21, type); \ 2600 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2601 GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2602 2603 /* lbz lbzu lbzux lbzx */ 2604 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2605 /* lha lhau lhaux lhax */ 2606 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2607 /* lhz lhzu lhzux lhzx */ 2608 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2609 /* lwz lwzu lwzux lwzx */ 2610 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 2611 2612 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 2613 static void glue(gen_, name##epx)(DisasContext *ctx) \ 2614 { \ 2615 TCGv EA; \ 2616 CHK_SV; \ 2617 gen_set_access_type(ctx, ACCESS_INT); \ 2618 EA = tcg_temp_new(); \ 2619 gen_addr_reg_index(ctx, EA); \ 2620 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 2621 tcg_temp_free(EA); \ 2622 } 2623 2624 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 2625 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 2626 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 2627 #if defined(TARGET_PPC64) 2628 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 2629 #endif 2630 2631 #if defined(TARGET_PPC64) 2632 /* lwaux */ 2633 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2634 /* lwax */ 2635 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2636 /* ldux */ 2637 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2638 /* ldx */ 2639 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2640 2641 /* CI load/store variants */ 2642 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2643 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2644 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2645 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2646 2647 static void gen_ld(DisasContext *ctx) 2648 { 2649 TCGv EA; 2650 if (Rc(ctx->opcode)) { 2651 if (unlikely(rA(ctx->opcode) == 0 || 2652 rA(ctx->opcode) == rD(ctx->opcode))) { 2653 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2654 return; 2655 } 2656 } 2657 gen_set_access_type(ctx, ACCESS_INT); 2658 EA = tcg_temp_new(); 2659 gen_addr_imm_index(ctx, EA, 0x03); 2660 if (ctx->opcode & 0x02) { 2661 /* lwa (lwau is undefined) */ 2662 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2663 } else { 2664 /* ld - ldu */ 2665 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2666 } 2667 if (Rc(ctx->opcode)) { 2668 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2669 } 2670 tcg_temp_free(EA); 2671 } 2672 2673 /* lq */ 2674 static void gen_lq(DisasContext *ctx) 2675 { 2676 int ra, rd; 2677 TCGv EA, hi, lo; 2678 2679 /* lq is a legal user mode instruction starting in ISA 2.07 */ 2680 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2681 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2682 2683 if (!legal_in_user_mode && ctx->pr) { 2684 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2685 return; 2686 } 2687 2688 if (!le_is_supported && ctx->le_mode) { 2689 gen_align_no_le(ctx); 2690 return; 2691 } 2692 ra = rA(ctx->opcode); 2693 rd = rD(ctx->opcode); 2694 if (unlikely((rd & 1) || rd == ra)) { 2695 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2696 return; 2697 } 2698 2699 gen_set_access_type(ctx, ACCESS_INT); 2700 EA = tcg_temp_new(); 2701 gen_addr_imm_index(ctx, EA, 0x0F); 2702 2703 /* Note that the low part is always in RD+1, even in LE mode. */ 2704 lo = cpu_gpr[rd + 1]; 2705 hi = cpu_gpr[rd]; 2706 2707 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2708 if (HAVE_ATOMIC128) { 2709 TCGv_i32 oi = tcg_temp_new_i32(); 2710 if (ctx->le_mode) { 2711 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 2712 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 2713 } else { 2714 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 2715 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 2716 } 2717 tcg_temp_free_i32(oi); 2718 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 2719 } else { 2720 /* Restart with exclusive lock. */ 2721 gen_helper_exit_atomic(cpu_env); 2722 ctx->base.is_jmp = DISAS_NORETURN; 2723 } 2724 } else if (ctx->le_mode) { 2725 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2726 gen_addr_add(ctx, EA, EA, 8); 2727 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 2728 } else { 2729 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 2730 gen_addr_add(ctx, EA, EA, 8); 2731 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2732 } 2733 tcg_temp_free(EA); 2734 } 2735 #endif 2736 2737 /*** Integer store ***/ 2738 #define GEN_ST(name, stop, opc, type) \ 2739 static void glue(gen_, name)(DisasContext *ctx) \ 2740 { \ 2741 TCGv EA; \ 2742 gen_set_access_type(ctx, ACCESS_INT); \ 2743 EA = tcg_temp_new(); \ 2744 gen_addr_imm_index(ctx, EA, 0); \ 2745 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2746 tcg_temp_free(EA); \ 2747 } 2748 2749 #define GEN_STU(name, stop, opc, type) \ 2750 static void glue(gen_, stop##u)(DisasContext *ctx) \ 2751 { \ 2752 TCGv EA; \ 2753 if (unlikely(rA(ctx->opcode) == 0)) { \ 2754 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2755 return; \ 2756 } \ 2757 gen_set_access_type(ctx, ACCESS_INT); \ 2758 EA = tcg_temp_new(); \ 2759 if (type == PPC_64B) \ 2760 gen_addr_imm_index(ctx, EA, 0x03); \ 2761 else \ 2762 gen_addr_imm_index(ctx, EA, 0); \ 2763 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2764 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2765 tcg_temp_free(EA); \ 2766 } 2767 2768 #define GEN_STUX(name, stop, opc2, opc3, type) \ 2769 static void glue(gen_, name##ux)(DisasContext *ctx) \ 2770 { \ 2771 TCGv EA; \ 2772 if (unlikely(rA(ctx->opcode) == 0)) { \ 2773 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2774 return; \ 2775 } \ 2776 gen_set_access_type(ctx, ACCESS_INT); \ 2777 EA = tcg_temp_new(); \ 2778 gen_addr_reg_index(ctx, EA); \ 2779 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2780 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2781 tcg_temp_free(EA); \ 2782 } 2783 2784 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2785 static void glue(gen_, name##x)(DisasContext *ctx) \ 2786 { \ 2787 TCGv EA; \ 2788 chk; \ 2789 gen_set_access_type(ctx, ACCESS_INT); \ 2790 EA = tcg_temp_new(); \ 2791 gen_addr_reg_index(ctx, EA); \ 2792 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2793 tcg_temp_free(EA); \ 2794 } 2795 #define GEN_STX(name, stop, opc2, opc3, type) \ 2796 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2797 2798 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2799 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2800 2801 #define GEN_STS(name, stop, op, type) \ 2802 GEN_ST(name, stop, op | 0x20, type); \ 2803 GEN_STU(name, stop, op | 0x21, type); \ 2804 GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2805 GEN_STX(name, stop, 0x17, op | 0x00, type) 2806 2807 /* stb stbu stbux stbx */ 2808 GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2809 /* sth sthu sthux sthx */ 2810 GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2811 /* stw stwu stwux stwx */ 2812 GEN_STS(stw, st32, 0x04, PPC_INTEGER); 2813 2814 #define GEN_STEPX(name, stop, opc2, opc3) \ 2815 static void glue(gen_, name##epx)(DisasContext *ctx) \ 2816 { \ 2817 TCGv EA; \ 2818 CHK_SV; \ 2819 gen_set_access_type(ctx, ACCESS_INT); \ 2820 EA = tcg_temp_new(); \ 2821 gen_addr_reg_index(ctx, EA); \ 2822 tcg_gen_qemu_st_tl( \ 2823 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 2824 tcg_temp_free(EA); \ 2825 } 2826 2827 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 2828 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 2829 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 2830 #if defined(TARGET_PPC64) 2831 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 2832 #endif 2833 2834 #if defined(TARGET_PPC64) 2835 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2836 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2837 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2838 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2839 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2840 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2841 2842 static void gen_std(DisasContext *ctx) 2843 { 2844 int rs; 2845 TCGv EA; 2846 2847 rs = rS(ctx->opcode); 2848 if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2849 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2850 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2851 TCGv hi, lo; 2852 2853 if (!(ctx->insns_flags & PPC_64BX)) { 2854 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2855 } 2856 2857 if (!legal_in_user_mode && ctx->pr) { 2858 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2859 return; 2860 } 2861 2862 if (!le_is_supported && ctx->le_mode) { 2863 gen_align_no_le(ctx); 2864 return; 2865 } 2866 2867 if (unlikely(rs & 1)) { 2868 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2869 return; 2870 } 2871 gen_set_access_type(ctx, ACCESS_INT); 2872 EA = tcg_temp_new(); 2873 gen_addr_imm_index(ctx, EA, 0x03); 2874 2875 /* Note that the low part is always in RS+1, even in LE mode. */ 2876 lo = cpu_gpr[rs + 1]; 2877 hi = cpu_gpr[rs]; 2878 2879 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2880 if (HAVE_ATOMIC128) { 2881 TCGv_i32 oi = tcg_temp_new_i32(); 2882 if (ctx->le_mode) { 2883 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 2884 gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 2885 } else { 2886 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 2887 gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 2888 } 2889 tcg_temp_free_i32(oi); 2890 } else { 2891 /* Restart with exclusive lock. */ 2892 gen_helper_exit_atomic(cpu_env); 2893 ctx->base.is_jmp = DISAS_NORETURN; 2894 } 2895 } else if (ctx->le_mode) { 2896 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2897 gen_addr_add(ctx, EA, EA, 8); 2898 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 2899 } else { 2900 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 2901 gen_addr_add(ctx, EA, EA, 8); 2902 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2903 } 2904 tcg_temp_free(EA); 2905 } else { 2906 /* std / stdu */ 2907 if (Rc(ctx->opcode)) { 2908 if (unlikely(rA(ctx->opcode) == 0)) { 2909 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2910 return; 2911 } 2912 } 2913 gen_set_access_type(ctx, ACCESS_INT); 2914 EA = tcg_temp_new(); 2915 gen_addr_imm_index(ctx, EA, 0x03); 2916 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2917 if (Rc(ctx->opcode)) { 2918 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2919 } 2920 tcg_temp_free(EA); 2921 } 2922 } 2923 #endif 2924 /*** Integer load and store with byte reverse ***/ 2925 2926 /* lhbrx */ 2927 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2928 2929 /* lwbrx */ 2930 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2931 2932 #if defined(TARGET_PPC64) 2933 /* ldbrx */ 2934 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2935 /* stdbrx */ 2936 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2937 #endif /* TARGET_PPC64 */ 2938 2939 /* sthbrx */ 2940 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2941 /* stwbrx */ 2942 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2943 2944 /*** Integer load and store multiple ***/ 2945 2946 /* lmw */ 2947 static void gen_lmw(DisasContext *ctx) 2948 { 2949 TCGv t0; 2950 TCGv_i32 t1; 2951 2952 if (ctx->le_mode) { 2953 gen_align_no_le(ctx); 2954 return; 2955 } 2956 gen_set_access_type(ctx, ACCESS_INT); 2957 t0 = tcg_temp_new(); 2958 t1 = tcg_const_i32(rD(ctx->opcode)); 2959 gen_addr_imm_index(ctx, t0, 0); 2960 gen_helper_lmw(cpu_env, t0, t1); 2961 tcg_temp_free(t0); 2962 tcg_temp_free_i32(t1); 2963 } 2964 2965 /* stmw */ 2966 static void gen_stmw(DisasContext *ctx) 2967 { 2968 TCGv t0; 2969 TCGv_i32 t1; 2970 2971 if (ctx->le_mode) { 2972 gen_align_no_le(ctx); 2973 return; 2974 } 2975 gen_set_access_type(ctx, ACCESS_INT); 2976 t0 = tcg_temp_new(); 2977 t1 = tcg_const_i32(rS(ctx->opcode)); 2978 gen_addr_imm_index(ctx, t0, 0); 2979 gen_helper_stmw(cpu_env, t0, t1); 2980 tcg_temp_free(t0); 2981 tcg_temp_free_i32(t1); 2982 } 2983 2984 /*** Integer load and store strings ***/ 2985 2986 /* lswi */ 2987 /* 2988 * PowerPC32 specification says we must generate an exception if rA is 2989 * in the range of registers to be loaded. In an other hand, IBM says 2990 * this is valid, but rA won't be loaded. For now, I'll follow the 2991 * spec... 2992 */ 2993 static void gen_lswi(DisasContext *ctx) 2994 { 2995 TCGv t0; 2996 TCGv_i32 t1, t2; 2997 int nb = NB(ctx->opcode); 2998 int start = rD(ctx->opcode); 2999 int ra = rA(ctx->opcode); 3000 int nr; 3001 3002 if (ctx->le_mode) { 3003 gen_align_no_le(ctx); 3004 return; 3005 } 3006 if (nb == 0) { 3007 nb = 32; 3008 } 3009 nr = DIV_ROUND_UP(nb, 4); 3010 if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3011 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3012 return; 3013 } 3014 gen_set_access_type(ctx, ACCESS_INT); 3015 t0 = tcg_temp_new(); 3016 gen_addr_register(ctx, t0); 3017 t1 = tcg_const_i32(nb); 3018 t2 = tcg_const_i32(start); 3019 gen_helper_lsw(cpu_env, t0, t1, t2); 3020 tcg_temp_free(t0); 3021 tcg_temp_free_i32(t1); 3022 tcg_temp_free_i32(t2); 3023 } 3024 3025 /* lswx */ 3026 static void gen_lswx(DisasContext *ctx) 3027 { 3028 TCGv t0; 3029 TCGv_i32 t1, t2, t3; 3030 3031 if (ctx->le_mode) { 3032 gen_align_no_le(ctx); 3033 return; 3034 } 3035 gen_set_access_type(ctx, ACCESS_INT); 3036 t0 = tcg_temp_new(); 3037 gen_addr_reg_index(ctx, t0); 3038 t1 = tcg_const_i32(rD(ctx->opcode)); 3039 t2 = tcg_const_i32(rA(ctx->opcode)); 3040 t3 = tcg_const_i32(rB(ctx->opcode)); 3041 gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3042 tcg_temp_free(t0); 3043 tcg_temp_free_i32(t1); 3044 tcg_temp_free_i32(t2); 3045 tcg_temp_free_i32(t3); 3046 } 3047 3048 /* stswi */ 3049 static void gen_stswi(DisasContext *ctx) 3050 { 3051 TCGv t0; 3052 TCGv_i32 t1, t2; 3053 int nb = NB(ctx->opcode); 3054 3055 if (ctx->le_mode) { 3056 gen_align_no_le(ctx); 3057 return; 3058 } 3059 gen_set_access_type(ctx, ACCESS_INT); 3060 t0 = tcg_temp_new(); 3061 gen_addr_register(ctx, t0); 3062 if (nb == 0) { 3063 nb = 32; 3064 } 3065 t1 = tcg_const_i32(nb); 3066 t2 = tcg_const_i32(rS(ctx->opcode)); 3067 gen_helper_stsw(cpu_env, t0, t1, t2); 3068 tcg_temp_free(t0); 3069 tcg_temp_free_i32(t1); 3070 tcg_temp_free_i32(t2); 3071 } 3072 3073 /* stswx */ 3074 static void gen_stswx(DisasContext *ctx) 3075 { 3076 TCGv t0; 3077 TCGv_i32 t1, t2; 3078 3079 if (ctx->le_mode) { 3080 gen_align_no_le(ctx); 3081 return; 3082 } 3083 gen_set_access_type(ctx, ACCESS_INT); 3084 t0 = tcg_temp_new(); 3085 gen_addr_reg_index(ctx, t0); 3086 t1 = tcg_temp_new_i32(); 3087 tcg_gen_trunc_tl_i32(t1, cpu_xer); 3088 tcg_gen_andi_i32(t1, t1, 0x7F); 3089 t2 = tcg_const_i32(rS(ctx->opcode)); 3090 gen_helper_stsw(cpu_env, t0, t1, t2); 3091 tcg_temp_free(t0); 3092 tcg_temp_free_i32(t1); 3093 tcg_temp_free_i32(t2); 3094 } 3095 3096 /*** Memory synchronisation ***/ 3097 /* eieio */ 3098 static void gen_eieio(DisasContext *ctx) 3099 { 3100 TCGBar bar = TCG_MO_LD_ST; 3101 3102 /* 3103 * POWER9 has a eieio instruction variant using bit 6 as a hint to 3104 * tell the CPU it is a store-forwarding barrier. 3105 */ 3106 if (ctx->opcode & 0x2000000) { 3107 /* 3108 * ISA says that "Reserved fields in instructions are ignored 3109 * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3110 * as this is not an instruction software should be using, 3111 * complain to the user. 3112 */ 3113 if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3114 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3115 TARGET_FMT_lx "\n", ctx->base.pc_next - 4); 3116 } else { 3117 bar = TCG_MO_ST_LD; 3118 } 3119 } 3120 3121 tcg_gen_mb(bar | TCG_BAR_SC); 3122 } 3123 3124 #if !defined(CONFIG_USER_ONLY) 3125 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3126 { 3127 TCGv_i32 t; 3128 TCGLabel *l; 3129 3130 if (!ctx->lazy_tlb_flush) { 3131 return; 3132 } 3133 l = gen_new_label(); 3134 t = tcg_temp_new_i32(); 3135 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3136 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3137 if (global) { 3138 gen_helper_check_tlb_flush_global(cpu_env); 3139 } else { 3140 gen_helper_check_tlb_flush_local(cpu_env); 3141 } 3142 gen_set_label(l); 3143 tcg_temp_free_i32(t); 3144 } 3145 #else 3146 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3147 #endif 3148 3149 /* isync */ 3150 static void gen_isync(DisasContext *ctx) 3151 { 3152 /* 3153 * We need to check for a pending TLB flush. This can only happen in 3154 * kernel mode however so check MSR_PR 3155 */ 3156 if (!ctx->pr) { 3157 gen_check_tlb_flush(ctx, false); 3158 } 3159 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3160 gen_stop_exception(ctx); 3161 } 3162 3163 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3164 3165 static void gen_load_locked(DisasContext *ctx, MemOp memop) 3166 { 3167 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 3168 TCGv t0 = tcg_temp_new(); 3169 3170 gen_set_access_type(ctx, ACCESS_RES); 3171 gen_addr_reg_index(ctx, t0); 3172 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 3173 tcg_gen_mov_tl(cpu_reserve, t0); 3174 tcg_gen_mov_tl(cpu_reserve_val, gpr); 3175 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 3176 tcg_temp_free(t0); 3177 } 3178 3179 #define LARX(name, memop) \ 3180 static void gen_##name(DisasContext *ctx) \ 3181 { \ 3182 gen_load_locked(ctx, memop); \ 3183 } 3184 3185 /* lwarx */ 3186 LARX(lbarx, DEF_MEMOP(MO_UB)) 3187 LARX(lharx, DEF_MEMOP(MO_UW)) 3188 LARX(lwarx, DEF_MEMOP(MO_UL)) 3189 3190 static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 3191 TCGv EA, TCGCond cond, int addend) 3192 { 3193 TCGv t = tcg_temp_new(); 3194 TCGv t2 = tcg_temp_new(); 3195 TCGv u = tcg_temp_new(); 3196 3197 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3198 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 3199 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 3200 tcg_gen_addi_tl(u, t, addend); 3201 3202 /* E.g. for fetch and increment bounded... */ 3203 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 3204 tcg_gen_movcond_tl(cond, u, t, t2, u, t); 3205 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 3206 3207 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 3208 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 3209 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 3210 3211 tcg_temp_free(t); 3212 tcg_temp_free(t2); 3213 tcg_temp_free(u); 3214 } 3215 3216 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 3217 { 3218 uint32_t gpr_FC = FC(ctx->opcode); 3219 TCGv EA = tcg_temp_new(); 3220 int rt = rD(ctx->opcode); 3221 bool need_serial; 3222 TCGv src, dst; 3223 3224 gen_addr_register(ctx, EA); 3225 dst = cpu_gpr[rt]; 3226 src = cpu_gpr[(rt + 1) & 31]; 3227 3228 need_serial = false; 3229 memop |= MO_ALIGN; 3230 switch (gpr_FC) { 3231 case 0: /* Fetch and add */ 3232 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 3233 break; 3234 case 1: /* Fetch and xor */ 3235 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 3236 break; 3237 case 2: /* Fetch and or */ 3238 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 3239 break; 3240 case 3: /* Fetch and 'and' */ 3241 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 3242 break; 3243 case 4: /* Fetch and max unsigned */ 3244 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3245 break; 3246 case 5: /* Fetch and max signed */ 3247 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3248 break; 3249 case 6: /* Fetch and min unsigned */ 3250 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3251 break; 3252 case 7: /* Fetch and min signed */ 3253 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3254 break; 3255 case 8: /* Swap */ 3256 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 3257 break; 3258 3259 case 16: /* Compare and swap not equal */ 3260 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3261 need_serial = true; 3262 } else { 3263 TCGv t0 = tcg_temp_new(); 3264 TCGv t1 = tcg_temp_new(); 3265 3266 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 3267 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 3268 tcg_gen_mov_tl(t1, src); 3269 } else { 3270 tcg_gen_ext32u_tl(t1, src); 3271 } 3272 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 3273 cpu_gpr[(rt + 2) & 31], t0); 3274 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 3275 tcg_gen_mov_tl(dst, t0); 3276 3277 tcg_temp_free(t0); 3278 tcg_temp_free(t1); 3279 } 3280 break; 3281 3282 case 24: /* Fetch and increment bounded */ 3283 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3284 need_serial = true; 3285 } else { 3286 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 3287 } 3288 break; 3289 case 25: /* Fetch and increment equal */ 3290 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3291 need_serial = true; 3292 } else { 3293 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 3294 } 3295 break; 3296 case 28: /* Fetch and decrement bounded */ 3297 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3298 need_serial = true; 3299 } else { 3300 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 3301 } 3302 break; 3303 3304 default: 3305 /* invoke data storage error handler */ 3306 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3307 } 3308 tcg_temp_free(EA); 3309 3310 if (need_serial) { 3311 /* Restart with exclusive lock. */ 3312 gen_helper_exit_atomic(cpu_env); 3313 ctx->base.is_jmp = DISAS_NORETURN; 3314 } 3315 } 3316 3317 static void gen_lwat(DisasContext *ctx) 3318 { 3319 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 3320 } 3321 3322 #ifdef TARGET_PPC64 3323 static void gen_ldat(DisasContext *ctx) 3324 { 3325 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 3326 } 3327 #endif 3328 3329 static void gen_st_atomic(DisasContext *ctx, MemOp memop) 3330 { 3331 uint32_t gpr_FC = FC(ctx->opcode); 3332 TCGv EA = tcg_temp_new(); 3333 TCGv src, discard; 3334 3335 gen_addr_register(ctx, EA); 3336 src = cpu_gpr[rD(ctx->opcode)]; 3337 discard = tcg_temp_new(); 3338 3339 memop |= MO_ALIGN; 3340 switch (gpr_FC) { 3341 case 0: /* add and Store */ 3342 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3343 break; 3344 case 1: /* xor and Store */ 3345 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3346 break; 3347 case 2: /* Or and Store */ 3348 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3349 break; 3350 case 3: /* 'and' and Store */ 3351 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3352 break; 3353 case 4: /* Store max unsigned */ 3354 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3355 break; 3356 case 5: /* Store max signed */ 3357 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3358 break; 3359 case 6: /* Store min unsigned */ 3360 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3361 break; 3362 case 7: /* Store min signed */ 3363 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3364 break; 3365 case 24: /* Store twin */ 3366 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3367 /* Restart with exclusive lock. */ 3368 gen_helper_exit_atomic(cpu_env); 3369 ctx->base.is_jmp = DISAS_NORETURN; 3370 } else { 3371 TCGv t = tcg_temp_new(); 3372 TCGv t2 = tcg_temp_new(); 3373 TCGv s = tcg_temp_new(); 3374 TCGv s2 = tcg_temp_new(); 3375 TCGv ea_plus_s = tcg_temp_new(); 3376 3377 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 3378 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 3379 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 3380 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 3381 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 3382 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 3383 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 3384 3385 tcg_temp_free(ea_plus_s); 3386 tcg_temp_free(s2); 3387 tcg_temp_free(s); 3388 tcg_temp_free(t2); 3389 tcg_temp_free(t); 3390 } 3391 break; 3392 default: 3393 /* invoke data storage error handler */ 3394 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 3395 } 3396 tcg_temp_free(discard); 3397 tcg_temp_free(EA); 3398 } 3399 3400 static void gen_stwat(DisasContext *ctx) 3401 { 3402 gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 3403 } 3404 3405 #ifdef TARGET_PPC64 3406 static void gen_stdat(DisasContext *ctx) 3407 { 3408 gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 3409 } 3410 #endif 3411 3412 static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3413 { 3414 TCGLabel *l1 = gen_new_label(); 3415 TCGLabel *l2 = gen_new_label(); 3416 TCGv t0 = tcg_temp_new(); 3417 int reg = rS(ctx->opcode); 3418 3419 gen_set_access_type(ctx, ACCESS_RES); 3420 gen_addr_reg_index(ctx, t0); 3421 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3422 tcg_temp_free(t0); 3423 3424 t0 = tcg_temp_new(); 3425 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3426 cpu_gpr[reg], ctx->mem_idx, 3427 DEF_MEMOP(memop) | MO_ALIGN); 3428 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3429 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3430 tcg_gen_or_tl(t0, t0, cpu_so); 3431 tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3432 tcg_temp_free(t0); 3433 tcg_gen_br(l2); 3434 3435 gen_set_label(l1); 3436 3437 /* 3438 * Address mismatch implies failure. But we still need to provide 3439 * the memory barrier semantics of the instruction. 3440 */ 3441 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3442 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3443 3444 gen_set_label(l2); 3445 tcg_gen_movi_tl(cpu_reserve, -1); 3446 } 3447 3448 #define STCX(name, memop) \ 3449 static void gen_##name(DisasContext *ctx) \ 3450 { \ 3451 gen_conditional_store(ctx, memop); \ 3452 } 3453 3454 STCX(stbcx_, DEF_MEMOP(MO_UB)) 3455 STCX(sthcx_, DEF_MEMOP(MO_UW)) 3456 STCX(stwcx_, DEF_MEMOP(MO_UL)) 3457 3458 #if defined(TARGET_PPC64) 3459 /* ldarx */ 3460 LARX(ldarx, DEF_MEMOP(MO_Q)) 3461 /* stdcx. */ 3462 STCX(stdcx_, DEF_MEMOP(MO_Q)) 3463 3464 /* lqarx */ 3465 static void gen_lqarx(DisasContext *ctx) 3466 { 3467 int rd = rD(ctx->opcode); 3468 TCGv EA, hi, lo; 3469 3470 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3471 (rd == rB(ctx->opcode)))) { 3472 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3473 return; 3474 } 3475 3476 gen_set_access_type(ctx, ACCESS_RES); 3477 EA = tcg_temp_new(); 3478 gen_addr_reg_index(ctx, EA); 3479 3480 /* Note that the low part is always in RD+1, even in LE mode. */ 3481 lo = cpu_gpr[rd + 1]; 3482 hi = cpu_gpr[rd]; 3483 3484 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3485 if (HAVE_ATOMIC128) { 3486 TCGv_i32 oi = tcg_temp_new_i32(); 3487 if (ctx->le_mode) { 3488 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 3489 ctx->mem_idx)); 3490 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3491 } else { 3492 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 3493 ctx->mem_idx)); 3494 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3495 } 3496 tcg_temp_free_i32(oi); 3497 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3498 } else { 3499 /* Restart with exclusive lock. */ 3500 gen_helper_exit_atomic(cpu_env); 3501 ctx->base.is_jmp = DISAS_NORETURN; 3502 tcg_temp_free(EA); 3503 return; 3504 } 3505 } else if (ctx->le_mode) { 3506 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 3507 tcg_gen_mov_tl(cpu_reserve, EA); 3508 gen_addr_add(ctx, EA, EA, 8); 3509 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3510 } else { 3511 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 3512 tcg_gen_mov_tl(cpu_reserve, EA); 3513 gen_addr_add(ctx, EA, EA, 8); 3514 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3515 } 3516 tcg_temp_free(EA); 3517 3518 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 3519 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3520 } 3521 3522 /* stqcx. */ 3523 static void gen_stqcx_(DisasContext *ctx) 3524 { 3525 int rs = rS(ctx->opcode); 3526 TCGv EA, hi, lo; 3527 3528 if (unlikely(rs & 1)) { 3529 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3530 return; 3531 } 3532 3533 gen_set_access_type(ctx, ACCESS_RES); 3534 EA = tcg_temp_new(); 3535 gen_addr_reg_index(ctx, EA); 3536 3537 /* Note that the low part is always in RS+1, even in LE mode. */ 3538 lo = cpu_gpr[rs + 1]; 3539 hi = cpu_gpr[rs]; 3540 3541 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3542 if (HAVE_CMPXCHG128) { 3543 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 3544 if (ctx->le_mode) { 3545 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 3546 EA, lo, hi, oi); 3547 } else { 3548 gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 3549 EA, lo, hi, oi); 3550 } 3551 tcg_temp_free_i32(oi); 3552 } else { 3553 /* Restart with exclusive lock. */ 3554 gen_helper_exit_atomic(cpu_env); 3555 ctx->base.is_jmp = DISAS_NORETURN; 3556 } 3557 tcg_temp_free(EA); 3558 } else { 3559 TCGLabel *lab_fail = gen_new_label(); 3560 TCGLabel *lab_over = gen_new_label(); 3561 TCGv_i64 t0 = tcg_temp_new_i64(); 3562 TCGv_i64 t1 = tcg_temp_new_i64(); 3563 3564 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 3565 tcg_temp_free(EA); 3566 3567 gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 3568 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 3569 ? offsetof(CPUPPCState, reserve_val2) 3570 : offsetof(CPUPPCState, reserve_val))); 3571 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 3572 3573 tcg_gen_addi_i64(t0, cpu_reserve, 8); 3574 gen_qemu_ld64_i64(ctx, t0, t0); 3575 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 3576 ? offsetof(CPUPPCState, reserve_val) 3577 : offsetof(CPUPPCState, reserve_val2))); 3578 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 3579 3580 /* Success */ 3581 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 3582 tcg_gen_addi_i64(t0, cpu_reserve, 8); 3583 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 3584 3585 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3586 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 3587 tcg_gen_br(lab_over); 3588 3589 gen_set_label(lab_fail); 3590 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3591 3592 gen_set_label(lab_over); 3593 tcg_gen_movi_tl(cpu_reserve, -1); 3594 tcg_temp_free_i64(t0); 3595 tcg_temp_free_i64(t1); 3596 } 3597 } 3598 #endif /* defined(TARGET_PPC64) */ 3599 3600 /* sync */ 3601 static void gen_sync(DisasContext *ctx) 3602 { 3603 uint32_t l = (ctx->opcode >> 21) & 3; 3604 3605 /* 3606 * We may need to check for a pending TLB flush. 3607 * 3608 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3609 * 3610 * Additionally, this can only happen in kernel mode however so 3611 * check MSR_PR as well. 3612 */ 3613 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3614 gen_check_tlb_flush(ctx, true); 3615 } 3616 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3617 } 3618 3619 /* wait */ 3620 static void gen_wait(DisasContext *ctx) 3621 { 3622 TCGv_i32 t0 = tcg_const_i32(1); 3623 tcg_gen_st_i32(t0, cpu_env, 3624 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3625 tcg_temp_free_i32(t0); 3626 /* Stop translation, as the CPU is supposed to sleep from now */ 3627 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3628 } 3629 3630 #if defined(TARGET_PPC64) 3631 static void gen_doze(DisasContext *ctx) 3632 { 3633 #if defined(CONFIG_USER_ONLY) 3634 GEN_PRIV; 3635 #else 3636 TCGv_i32 t; 3637 3638 CHK_HV; 3639 t = tcg_const_i32(PPC_PM_DOZE); 3640 gen_helper_pminsn(cpu_env, t); 3641 tcg_temp_free_i32(t); 3642 /* Stop translation, as the CPU is supposed to sleep from now */ 3643 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3644 #endif /* defined(CONFIG_USER_ONLY) */ 3645 } 3646 3647 static void gen_nap(DisasContext *ctx) 3648 { 3649 #if defined(CONFIG_USER_ONLY) 3650 GEN_PRIV; 3651 #else 3652 TCGv_i32 t; 3653 3654 CHK_HV; 3655 t = tcg_const_i32(PPC_PM_NAP); 3656 gen_helper_pminsn(cpu_env, t); 3657 tcg_temp_free_i32(t); 3658 /* Stop translation, as the CPU is supposed to sleep from now */ 3659 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3660 #endif /* defined(CONFIG_USER_ONLY) */ 3661 } 3662 3663 static void gen_stop(DisasContext *ctx) 3664 { 3665 #if defined(CONFIG_USER_ONLY) 3666 GEN_PRIV; 3667 #else 3668 TCGv_i32 t; 3669 3670 CHK_HV; 3671 t = tcg_const_i32(PPC_PM_STOP); 3672 gen_helper_pminsn(cpu_env, t); 3673 tcg_temp_free_i32(t); 3674 /* Stop translation, as the CPU is supposed to sleep from now */ 3675 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3676 #endif /* defined(CONFIG_USER_ONLY) */ 3677 } 3678 3679 static void gen_sleep(DisasContext *ctx) 3680 { 3681 #if defined(CONFIG_USER_ONLY) 3682 GEN_PRIV; 3683 #else 3684 TCGv_i32 t; 3685 3686 CHK_HV; 3687 t = tcg_const_i32(PPC_PM_SLEEP); 3688 gen_helper_pminsn(cpu_env, t); 3689 tcg_temp_free_i32(t); 3690 /* Stop translation, as the CPU is supposed to sleep from now */ 3691 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3692 #endif /* defined(CONFIG_USER_ONLY) */ 3693 } 3694 3695 static void gen_rvwinkle(DisasContext *ctx) 3696 { 3697 #if defined(CONFIG_USER_ONLY) 3698 GEN_PRIV; 3699 #else 3700 TCGv_i32 t; 3701 3702 CHK_HV; 3703 t = tcg_const_i32(PPC_PM_RVWINKLE); 3704 gen_helper_pminsn(cpu_env, t); 3705 tcg_temp_free_i32(t); 3706 /* Stop translation, as the CPU is supposed to sleep from now */ 3707 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3708 #endif /* defined(CONFIG_USER_ONLY) */ 3709 } 3710 #endif /* #if defined(TARGET_PPC64) */ 3711 3712 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3713 { 3714 #if defined(TARGET_PPC64) 3715 if (ctx->has_cfar) { 3716 tcg_gen_movi_tl(cpu_cfar, nip); 3717 } 3718 #endif 3719 } 3720 3721 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3722 { 3723 if (unlikely(ctx->singlestep_enabled)) { 3724 return false; 3725 } 3726 3727 #ifndef CONFIG_USER_ONLY 3728 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3729 #else 3730 return true; 3731 #endif 3732 } 3733 3734 static void gen_lookup_and_goto_ptr(DisasContext *ctx) 3735 { 3736 int sse = ctx->singlestep_enabled; 3737 if (unlikely(sse)) { 3738 if (sse & GDBSTUB_SINGLE_STEP) { 3739 gen_debug_exception(ctx); 3740 } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 3741 uint32_t excp = gen_prep_dbgex(ctx); 3742 gen_exception(ctx, excp); 3743 } 3744 tcg_gen_exit_tb(NULL, 0); 3745 } else { 3746 tcg_gen_lookup_and_goto_ptr(); 3747 } 3748 } 3749 3750 /*** Branch ***/ 3751 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3752 { 3753 if (NARROW_MODE(ctx)) { 3754 dest = (uint32_t) dest; 3755 } 3756 if (use_goto_tb(ctx, dest)) { 3757 tcg_gen_goto_tb(n); 3758 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3759 tcg_gen_exit_tb(ctx->base.tb, n); 3760 } else { 3761 tcg_gen_movi_tl(cpu_nip, dest & ~3); 3762 gen_lookup_and_goto_ptr(ctx); 3763 } 3764 } 3765 3766 static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3767 { 3768 if (NARROW_MODE(ctx)) { 3769 nip = (uint32_t)nip; 3770 } 3771 tcg_gen_movi_tl(cpu_lr, nip); 3772 } 3773 3774 /* b ba bl bla */ 3775 static void gen_b(DisasContext *ctx) 3776 { 3777 target_ulong li, target; 3778 3779 ctx->exception = POWERPC_EXCP_BRANCH; 3780 /* sign extend LI */ 3781 li = LI(ctx->opcode); 3782 li = (li ^ 0x02000000) - 0x02000000; 3783 if (likely(AA(ctx->opcode) == 0)) { 3784 target = ctx->base.pc_next + li - 4; 3785 } else { 3786 target = li; 3787 } 3788 if (LK(ctx->opcode)) { 3789 gen_setlr(ctx, ctx->base.pc_next); 3790 } 3791 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3792 gen_goto_tb(ctx, 0, target); 3793 } 3794 3795 #define BCOND_IM 0 3796 #define BCOND_LR 1 3797 #define BCOND_CTR 2 3798 #define BCOND_TAR 3 3799 3800 static void gen_bcond(DisasContext *ctx, int type) 3801 { 3802 uint32_t bo = BO(ctx->opcode); 3803 TCGLabel *l1; 3804 TCGv target; 3805 ctx->exception = POWERPC_EXCP_BRANCH; 3806 3807 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3808 target = tcg_temp_local_new(); 3809 if (type == BCOND_CTR) { 3810 tcg_gen_mov_tl(target, cpu_ctr); 3811 } else if (type == BCOND_TAR) { 3812 gen_load_spr(target, SPR_TAR); 3813 } else { 3814 tcg_gen_mov_tl(target, cpu_lr); 3815 } 3816 } else { 3817 target = NULL; 3818 } 3819 if (LK(ctx->opcode)) { 3820 gen_setlr(ctx, ctx->base.pc_next); 3821 } 3822 l1 = gen_new_label(); 3823 if ((bo & 0x4) == 0) { 3824 /* Decrement and test CTR */ 3825 TCGv temp = tcg_temp_new(); 3826 3827 if (type == BCOND_CTR) { 3828 /* 3829 * All ISAs up to v3 describe this form of bcctr as invalid but 3830 * some processors, ie. 64-bit server processors compliant with 3831 * arch 2.x, do implement a "test and decrement" logic instead, 3832 * as described in their respective UMs. This logic involves CTR 3833 * to act as both the branch target and a counter, which makes 3834 * it basically useless and thus never used in real code. 3835 * 3836 * This form was hence chosen to trigger extra micro-architectural 3837 * side-effect on real HW needed for the Spectre v2 workaround. 3838 * It is up to guests that implement such workaround, ie. linux, to 3839 * use this form in a way it just triggers the side-effect without 3840 * doing anything else harmful. 3841 */ 3842 if (unlikely(!is_book3s_arch2x(ctx))) { 3843 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3844 tcg_temp_free(temp); 3845 tcg_temp_free(target); 3846 return; 3847 } 3848 3849 if (NARROW_MODE(ctx)) { 3850 tcg_gen_ext32u_tl(temp, cpu_ctr); 3851 } else { 3852 tcg_gen_mov_tl(temp, cpu_ctr); 3853 } 3854 if (bo & 0x2) { 3855 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3856 } else { 3857 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3858 } 3859 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3860 } else { 3861 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3862 if (NARROW_MODE(ctx)) { 3863 tcg_gen_ext32u_tl(temp, cpu_ctr); 3864 } else { 3865 tcg_gen_mov_tl(temp, cpu_ctr); 3866 } 3867 if (bo & 0x2) { 3868 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3869 } else { 3870 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3871 } 3872 } 3873 tcg_temp_free(temp); 3874 } 3875 if ((bo & 0x10) == 0) { 3876 /* Test CR */ 3877 uint32_t bi = BI(ctx->opcode); 3878 uint32_t mask = 0x08 >> (bi & 0x03); 3879 TCGv_i32 temp = tcg_temp_new_i32(); 3880 3881 if (bo & 0x8) { 3882 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3883 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3884 } else { 3885 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3886 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3887 } 3888 tcg_temp_free_i32(temp); 3889 } 3890 gen_update_cfar(ctx, ctx->base.pc_next - 4); 3891 if (type == BCOND_IM) { 3892 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3893 if (likely(AA(ctx->opcode) == 0)) { 3894 gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); 3895 } else { 3896 gen_goto_tb(ctx, 0, li); 3897 } 3898 } else { 3899 if (NARROW_MODE(ctx)) { 3900 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3901 } else { 3902 tcg_gen_andi_tl(cpu_nip, target, ~3); 3903 } 3904 gen_lookup_and_goto_ptr(ctx); 3905 tcg_temp_free(target); 3906 } 3907 if ((bo & 0x14) != 0x14) { 3908 /* fallthrough case */ 3909 gen_set_label(l1); 3910 gen_goto_tb(ctx, 1, ctx->base.pc_next); 3911 } 3912 } 3913 3914 static void gen_bc(DisasContext *ctx) 3915 { 3916 gen_bcond(ctx, BCOND_IM); 3917 } 3918 3919 static void gen_bcctr(DisasContext *ctx) 3920 { 3921 gen_bcond(ctx, BCOND_CTR); 3922 } 3923 3924 static void gen_bclr(DisasContext *ctx) 3925 { 3926 gen_bcond(ctx, BCOND_LR); 3927 } 3928 3929 static void gen_bctar(DisasContext *ctx) 3930 { 3931 gen_bcond(ctx, BCOND_TAR); 3932 } 3933 3934 /*** Condition register logical ***/ 3935 #define GEN_CRLOGIC(name, tcg_op, opc) \ 3936 static void glue(gen_, name)(DisasContext *ctx) \ 3937 { \ 3938 uint8_t bitmask; \ 3939 int sh; \ 3940 TCGv_i32 t0, t1; \ 3941 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3942 t0 = tcg_temp_new_i32(); \ 3943 if (sh > 0) \ 3944 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3945 else if (sh < 0) \ 3946 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3947 else \ 3948 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3949 t1 = tcg_temp_new_i32(); \ 3950 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3951 if (sh > 0) \ 3952 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3953 else if (sh < 0) \ 3954 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3955 else \ 3956 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3957 tcg_op(t0, t0, t1); \ 3958 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3959 tcg_gen_andi_i32(t0, t0, bitmask); \ 3960 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3961 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3962 tcg_temp_free_i32(t0); \ 3963 tcg_temp_free_i32(t1); \ 3964 } 3965 3966 /* crand */ 3967 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3968 /* crandc */ 3969 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3970 /* creqv */ 3971 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3972 /* crnand */ 3973 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3974 /* crnor */ 3975 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3976 /* cror */ 3977 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3978 /* crorc */ 3979 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3980 /* crxor */ 3981 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3982 3983 /* mcrf */ 3984 static void gen_mcrf(DisasContext *ctx) 3985 { 3986 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3987 } 3988 3989 /*** System linkage ***/ 3990 3991 /* rfi (supervisor only) */ 3992 static void gen_rfi(DisasContext *ctx) 3993 { 3994 #if defined(CONFIG_USER_ONLY) 3995 GEN_PRIV; 3996 #else 3997 /* 3998 * This instruction doesn't exist anymore on 64-bit server 3999 * processors compliant with arch 2.x 4000 */ 4001 if (is_book3s_arch2x(ctx)) { 4002 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4003 return; 4004 } 4005 /* Restore CPU state */ 4006 CHK_SV; 4007 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4008 gen_io_start(); 4009 } 4010 gen_update_cfar(ctx, ctx->base.pc_next - 4); 4011 gen_helper_rfi(cpu_env); 4012 gen_sync_exception(ctx); 4013 #endif 4014 } 4015 4016 #if defined(TARGET_PPC64) 4017 static void gen_rfid(DisasContext *ctx) 4018 { 4019 #if defined(CONFIG_USER_ONLY) 4020 GEN_PRIV; 4021 #else 4022 /* Restore CPU state */ 4023 CHK_SV; 4024 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4025 gen_io_start(); 4026 } 4027 gen_update_cfar(ctx, ctx->base.pc_next - 4); 4028 gen_helper_rfid(cpu_env); 4029 gen_sync_exception(ctx); 4030 #endif 4031 } 4032 4033 #if !defined(CONFIG_USER_ONLY) 4034 static void gen_rfscv(DisasContext *ctx) 4035 { 4036 #if defined(CONFIG_USER_ONLY) 4037 GEN_PRIV; 4038 #else 4039 /* Restore CPU state */ 4040 CHK_SV; 4041 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4042 gen_io_start(); 4043 } 4044 gen_update_cfar(ctx, ctx->base.pc_next - 4); 4045 gen_helper_rfscv(cpu_env); 4046 gen_sync_exception(ctx); 4047 #endif 4048 } 4049 #endif 4050 4051 static void gen_hrfid(DisasContext *ctx) 4052 { 4053 #if defined(CONFIG_USER_ONLY) 4054 GEN_PRIV; 4055 #else 4056 /* Restore CPU state */ 4057 CHK_HV; 4058 gen_helper_hrfid(cpu_env); 4059 gen_sync_exception(ctx); 4060 #endif 4061 } 4062 #endif 4063 4064 /* sc */ 4065 #if defined(CONFIG_USER_ONLY) 4066 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4067 #else 4068 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4069 #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4070 #endif 4071 static void gen_sc(DisasContext *ctx) 4072 { 4073 uint32_t lev; 4074 4075 lev = (ctx->opcode >> 5) & 0x7F; 4076 gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4077 } 4078 4079 #if defined(TARGET_PPC64) 4080 #if !defined(CONFIG_USER_ONLY) 4081 static void gen_scv(DisasContext *ctx) 4082 { 4083 uint32_t lev = (ctx->opcode >> 5) & 0x7F; 4084 4085 /* Set the PC back to the faulting instruction. */ 4086 if (ctx->exception == POWERPC_EXCP_NONE) { 4087 gen_update_nip(ctx, ctx->base.pc_next - 4); 4088 } 4089 gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 4090 4091 /* This need not be exact, just not POWERPC_EXCP_NONE */ 4092 ctx->exception = POWERPC_SYSCALL_VECTORED; 4093 } 4094 #endif 4095 #endif 4096 4097 /*** Trap ***/ 4098 4099 /* Check for unconditional traps (always or never) */ 4100 static bool check_unconditional_trap(DisasContext *ctx) 4101 { 4102 /* Trap never */ 4103 if (TO(ctx->opcode) == 0) { 4104 return true; 4105 } 4106 /* Trap always */ 4107 if (TO(ctx->opcode) == 31) { 4108 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4109 return true; 4110 } 4111 return false; 4112 } 4113 4114 /* tw */ 4115 static void gen_tw(DisasContext *ctx) 4116 { 4117 TCGv_i32 t0; 4118 4119 if (check_unconditional_trap(ctx)) { 4120 return; 4121 } 4122 t0 = tcg_const_i32(TO(ctx->opcode)); 4123 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4124 t0); 4125 tcg_temp_free_i32(t0); 4126 } 4127 4128 /* twi */ 4129 static void gen_twi(DisasContext *ctx) 4130 { 4131 TCGv t0; 4132 TCGv_i32 t1; 4133 4134 if (check_unconditional_trap(ctx)) { 4135 return; 4136 } 4137 t0 = tcg_const_tl(SIMM(ctx->opcode)); 4138 t1 = tcg_const_i32(TO(ctx->opcode)); 4139 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4140 tcg_temp_free(t0); 4141 tcg_temp_free_i32(t1); 4142 } 4143 4144 #if defined(TARGET_PPC64) 4145 /* td */ 4146 static void gen_td(DisasContext *ctx) 4147 { 4148 TCGv_i32 t0; 4149 4150 if (check_unconditional_trap(ctx)) { 4151 return; 4152 } 4153 t0 = tcg_const_i32(TO(ctx->opcode)); 4154 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4155 t0); 4156 tcg_temp_free_i32(t0); 4157 } 4158 4159 /* tdi */ 4160 static void gen_tdi(DisasContext *ctx) 4161 { 4162 TCGv t0; 4163 TCGv_i32 t1; 4164 4165 if (check_unconditional_trap(ctx)) { 4166 return; 4167 } 4168 t0 = tcg_const_tl(SIMM(ctx->opcode)); 4169 t1 = tcg_const_i32(TO(ctx->opcode)); 4170 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4171 tcg_temp_free(t0); 4172 tcg_temp_free_i32(t1); 4173 } 4174 #endif 4175 4176 /*** Processor control ***/ 4177 4178 static void gen_read_xer(DisasContext *ctx, TCGv dst) 4179 { 4180 TCGv t0 = tcg_temp_new(); 4181 TCGv t1 = tcg_temp_new(); 4182 TCGv t2 = tcg_temp_new(); 4183 tcg_gen_mov_tl(dst, cpu_xer); 4184 tcg_gen_shli_tl(t0, cpu_so, XER_SO); 4185 tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 4186 tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 4187 tcg_gen_or_tl(t0, t0, t1); 4188 tcg_gen_or_tl(dst, dst, t2); 4189 tcg_gen_or_tl(dst, dst, t0); 4190 if (is_isa300(ctx)) { 4191 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 4192 tcg_gen_or_tl(dst, dst, t0); 4193 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 4194 tcg_gen_or_tl(dst, dst, t0); 4195 } 4196 tcg_temp_free(t0); 4197 tcg_temp_free(t1); 4198 tcg_temp_free(t2); 4199 } 4200 4201 static void gen_write_xer(TCGv src) 4202 { 4203 /* Write all flags, while reading back check for isa300 */ 4204 tcg_gen_andi_tl(cpu_xer, src, 4205 ~((1u << XER_SO) | 4206 (1u << XER_OV) | (1u << XER_OV32) | 4207 (1u << XER_CA) | (1u << XER_CA32))); 4208 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 4209 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 4210 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 4211 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 4212 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 4213 } 4214 4215 /* mcrxr */ 4216 static void gen_mcrxr(DisasContext *ctx) 4217 { 4218 TCGv_i32 t0 = tcg_temp_new_i32(); 4219 TCGv_i32 t1 = tcg_temp_new_i32(); 4220 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4221 4222 tcg_gen_trunc_tl_i32(t0, cpu_so); 4223 tcg_gen_trunc_tl_i32(t1, cpu_ov); 4224 tcg_gen_trunc_tl_i32(dst, cpu_ca); 4225 tcg_gen_shli_i32(t0, t0, 3); 4226 tcg_gen_shli_i32(t1, t1, 2); 4227 tcg_gen_shli_i32(dst, dst, 1); 4228 tcg_gen_or_i32(dst, dst, t0); 4229 tcg_gen_or_i32(dst, dst, t1); 4230 tcg_temp_free_i32(t0); 4231 tcg_temp_free_i32(t1); 4232 4233 tcg_gen_movi_tl(cpu_so, 0); 4234 tcg_gen_movi_tl(cpu_ov, 0); 4235 tcg_gen_movi_tl(cpu_ca, 0); 4236 } 4237 4238 #ifdef TARGET_PPC64 4239 /* mcrxrx */ 4240 static void gen_mcrxrx(DisasContext *ctx) 4241 { 4242 TCGv t0 = tcg_temp_new(); 4243 TCGv t1 = tcg_temp_new(); 4244 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4245 4246 /* copy OV and OV32 */ 4247 tcg_gen_shli_tl(t0, cpu_ov, 1); 4248 tcg_gen_or_tl(t0, t0, cpu_ov32); 4249 tcg_gen_shli_tl(t0, t0, 2); 4250 /* copy CA and CA32 */ 4251 tcg_gen_shli_tl(t1, cpu_ca, 1); 4252 tcg_gen_or_tl(t1, t1, cpu_ca32); 4253 tcg_gen_or_tl(t0, t0, t1); 4254 tcg_gen_trunc_tl_i32(dst, t0); 4255 tcg_temp_free(t0); 4256 tcg_temp_free(t1); 4257 } 4258 #endif 4259 4260 /* mfcr mfocrf */ 4261 static void gen_mfcr(DisasContext *ctx) 4262 { 4263 uint32_t crm, crn; 4264 4265 if (likely(ctx->opcode & 0x00100000)) { 4266 crm = CRM(ctx->opcode); 4267 if (likely(crm && ((crm & (crm - 1)) == 0))) { 4268 crn = ctz32(crm); 4269 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4270 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4271 cpu_gpr[rD(ctx->opcode)], crn * 4); 4272 } 4273 } else { 4274 TCGv_i32 t0 = tcg_temp_new_i32(); 4275 tcg_gen_mov_i32(t0, cpu_crf[0]); 4276 tcg_gen_shli_i32(t0, t0, 4); 4277 tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4278 tcg_gen_shli_i32(t0, t0, 4); 4279 tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4280 tcg_gen_shli_i32(t0, t0, 4); 4281 tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4282 tcg_gen_shli_i32(t0, t0, 4); 4283 tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4284 tcg_gen_shli_i32(t0, t0, 4); 4285 tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4286 tcg_gen_shli_i32(t0, t0, 4); 4287 tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4288 tcg_gen_shli_i32(t0, t0, 4); 4289 tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4290 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4291 tcg_temp_free_i32(t0); 4292 } 4293 } 4294 4295 /* mfmsr */ 4296 static void gen_mfmsr(DisasContext *ctx) 4297 { 4298 CHK_SV; 4299 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4300 } 4301 4302 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 4303 { 4304 #if 0 4305 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 4306 printf("ERROR: try to access SPR %d !\n", sprn); 4307 #endif 4308 } 4309 #define SPR_NOACCESS (&spr_noaccess) 4310 4311 /* mfspr */ 4312 static inline void gen_op_mfspr(DisasContext *ctx) 4313 { 4314 void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4315 uint32_t sprn = SPR(ctx->opcode); 4316 4317 #if defined(CONFIG_USER_ONLY) 4318 read_cb = ctx->spr_cb[sprn].uea_read; 4319 #else 4320 if (ctx->pr) { 4321 read_cb = ctx->spr_cb[sprn].uea_read; 4322 } else if (ctx->hv) { 4323 read_cb = ctx->spr_cb[sprn].hea_read; 4324 } else { 4325 read_cb = ctx->spr_cb[sprn].oea_read; 4326 } 4327 #endif 4328 if (likely(read_cb != NULL)) { 4329 if (likely(read_cb != SPR_NOACCESS)) { 4330 (*read_cb)(ctx, rD(ctx->opcode), sprn); 4331 } else { 4332 /* Privilege exception */ 4333 /* 4334 * This is a hack to avoid warnings when running Linux: 4335 * this OS breaks the PowerPC virtualisation model, 4336 * allowing userland application to read the PVR 4337 */ 4338 if (sprn != SPR_PVR) { 4339 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 4340 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4341 ctx->base.pc_next - 4); 4342 } 4343 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4344 } 4345 } else { 4346 /* ISA 2.07 defines these as no-ops */ 4347 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4348 (sprn >= 808 && sprn <= 811)) { 4349 /* This is a nop */ 4350 return; 4351 } 4352 /* Not defined */ 4353 qemu_log_mask(LOG_GUEST_ERROR, 4354 "Trying to read invalid spr %d (0x%03x) at " 4355 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4356 4357 /* 4358 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4359 * generate a priv, a hv emu or a no-op 4360 */ 4361 if (sprn & 0x10) { 4362 if (ctx->pr) { 4363 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4364 } 4365 } else { 4366 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4367 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4368 } 4369 } 4370 } 4371 } 4372 4373 static void gen_mfspr(DisasContext *ctx) 4374 { 4375 gen_op_mfspr(ctx); 4376 } 4377 4378 /* mftb */ 4379 static void gen_mftb(DisasContext *ctx) 4380 { 4381 gen_op_mfspr(ctx); 4382 } 4383 4384 /* mtcrf mtocrf*/ 4385 static void gen_mtcrf(DisasContext *ctx) 4386 { 4387 uint32_t crm, crn; 4388 4389 crm = CRM(ctx->opcode); 4390 if (likely((ctx->opcode & 0x00100000))) { 4391 if (crm && ((crm & (crm - 1)) == 0)) { 4392 TCGv_i32 temp = tcg_temp_new_i32(); 4393 crn = ctz32(crm); 4394 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4395 tcg_gen_shri_i32(temp, temp, crn * 4); 4396 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4397 tcg_temp_free_i32(temp); 4398 } 4399 } else { 4400 TCGv_i32 temp = tcg_temp_new_i32(); 4401 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4402 for (crn = 0 ; crn < 8 ; crn++) { 4403 if (crm & (1 << crn)) { 4404 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4405 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4406 } 4407 } 4408 tcg_temp_free_i32(temp); 4409 } 4410 } 4411 4412 /* mtmsr */ 4413 #if defined(TARGET_PPC64) 4414 static void gen_mtmsrd(DisasContext *ctx) 4415 { 4416 CHK_SV; 4417 4418 #if !defined(CONFIG_USER_ONLY) 4419 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4420 gen_io_start(); 4421 } 4422 if (ctx->opcode & 0x00010000) { 4423 /* L=1 form only updates EE and RI */ 4424 TCGv t0 = tcg_temp_new(); 4425 TCGv t1 = tcg_temp_new(); 4426 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4427 (1 << MSR_RI) | (1 << MSR_EE)); 4428 tcg_gen_andi_tl(t1, cpu_msr, 4429 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4430 tcg_gen_or_tl(t1, t1, t0); 4431 4432 gen_helper_store_msr(cpu_env, t1); 4433 tcg_temp_free(t0); 4434 tcg_temp_free(t1); 4435 4436 } else { 4437 /* 4438 * XXX: we need to update nip before the store if we enter 4439 * power saving mode, we will exit the loop directly from 4440 * ppc_store_msr 4441 */ 4442 gen_update_nip(ctx, ctx->base.pc_next); 4443 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4444 } 4445 /* Must stop the translation as machine state (may have) changed */ 4446 gen_stop_exception(ctx); 4447 #endif /* !defined(CONFIG_USER_ONLY) */ 4448 } 4449 #endif /* defined(TARGET_PPC64) */ 4450 4451 static void gen_mtmsr(DisasContext *ctx) 4452 { 4453 CHK_SV; 4454 4455 #if !defined(CONFIG_USER_ONLY) 4456 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4457 gen_io_start(); 4458 } 4459 if (ctx->opcode & 0x00010000) { 4460 /* L=1 form only updates EE and RI */ 4461 TCGv t0 = tcg_temp_new(); 4462 TCGv t1 = tcg_temp_new(); 4463 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4464 (1 << MSR_RI) | (1 << MSR_EE)); 4465 tcg_gen_andi_tl(t1, cpu_msr, 4466 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4467 tcg_gen_or_tl(t1, t1, t0); 4468 4469 gen_helper_store_msr(cpu_env, t1); 4470 tcg_temp_free(t0); 4471 tcg_temp_free(t1); 4472 4473 } else { 4474 TCGv msr = tcg_temp_new(); 4475 4476 /* 4477 * XXX: we need to update nip before the store if we enter 4478 * power saving mode, we will exit the loop directly from 4479 * ppc_store_msr 4480 */ 4481 gen_update_nip(ctx, ctx->base.pc_next); 4482 #if defined(TARGET_PPC64) 4483 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4484 #else 4485 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4486 #endif 4487 gen_helper_store_msr(cpu_env, msr); 4488 tcg_temp_free(msr); 4489 } 4490 /* Must stop the translation as machine state (may have) changed */ 4491 gen_stop_exception(ctx); 4492 #endif 4493 } 4494 4495 /* mtspr */ 4496 static void gen_mtspr(DisasContext *ctx) 4497 { 4498 void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4499 uint32_t sprn = SPR(ctx->opcode); 4500 4501 #if defined(CONFIG_USER_ONLY) 4502 write_cb = ctx->spr_cb[sprn].uea_write; 4503 #else 4504 if (ctx->pr) { 4505 write_cb = ctx->spr_cb[sprn].uea_write; 4506 } else if (ctx->hv) { 4507 write_cb = ctx->spr_cb[sprn].hea_write; 4508 } else { 4509 write_cb = ctx->spr_cb[sprn].oea_write; 4510 } 4511 #endif 4512 if (likely(write_cb != NULL)) { 4513 if (likely(write_cb != SPR_NOACCESS)) { 4514 (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4515 } else { 4516 /* Privilege exception */ 4517 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 4518 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4519 ctx->base.pc_next - 4); 4520 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4521 } 4522 } else { 4523 /* ISA 2.07 defines these as no-ops */ 4524 if ((ctx->insns_flags2 & PPC2_ISA207S) && 4525 (sprn >= 808 && sprn <= 811)) { 4526 /* This is a nop */ 4527 return; 4528 } 4529 4530 /* Not defined */ 4531 qemu_log_mask(LOG_GUEST_ERROR, 4532 "Trying to write invalid spr %d (0x%03x) at " 4533 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4534 4535 4536 /* 4537 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4538 * generate a priv, a hv emu or a no-op 4539 */ 4540 if (sprn & 0x10) { 4541 if (ctx->pr) { 4542 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4543 } 4544 } else { 4545 if (ctx->pr || sprn == 0) { 4546 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4547 } 4548 } 4549 } 4550 } 4551 4552 #if defined(TARGET_PPC64) 4553 /* setb */ 4554 static void gen_setb(DisasContext *ctx) 4555 { 4556 TCGv_i32 t0 = tcg_temp_new_i32(); 4557 TCGv_i32 t8 = tcg_temp_new_i32(); 4558 TCGv_i32 tm1 = tcg_temp_new_i32(); 4559 int crf = crfS(ctx->opcode); 4560 4561 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4562 tcg_gen_movi_i32(t8, 8); 4563 tcg_gen_movi_i32(tm1, -1); 4564 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4565 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4566 4567 tcg_temp_free_i32(t0); 4568 tcg_temp_free_i32(t8); 4569 tcg_temp_free_i32(tm1); 4570 } 4571 #endif 4572 4573 /*** Cache management ***/ 4574 4575 /* dcbf */ 4576 static void gen_dcbf(DisasContext *ctx) 4577 { 4578 /* XXX: specification says this is treated as a load by the MMU */ 4579 TCGv t0; 4580 gen_set_access_type(ctx, ACCESS_CACHE); 4581 t0 = tcg_temp_new(); 4582 gen_addr_reg_index(ctx, t0); 4583 gen_qemu_ld8u(ctx, t0, t0); 4584 tcg_temp_free(t0); 4585 } 4586 4587 /* dcbfep (external PID dcbf) */ 4588 static void gen_dcbfep(DisasContext *ctx) 4589 { 4590 /* XXX: specification says this is treated as a load by the MMU */ 4591 TCGv t0; 4592 CHK_SV; 4593 gen_set_access_type(ctx, ACCESS_CACHE); 4594 t0 = tcg_temp_new(); 4595 gen_addr_reg_index(ctx, t0); 4596 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4597 tcg_temp_free(t0); 4598 } 4599 4600 /* dcbi (Supervisor only) */ 4601 static void gen_dcbi(DisasContext *ctx) 4602 { 4603 #if defined(CONFIG_USER_ONLY) 4604 GEN_PRIV; 4605 #else 4606 TCGv EA, val; 4607 4608 CHK_SV; 4609 EA = tcg_temp_new(); 4610 gen_set_access_type(ctx, ACCESS_CACHE); 4611 gen_addr_reg_index(ctx, EA); 4612 val = tcg_temp_new(); 4613 /* XXX: specification says this should be treated as a store by the MMU */ 4614 gen_qemu_ld8u(ctx, val, EA); 4615 gen_qemu_st8(ctx, val, EA); 4616 tcg_temp_free(val); 4617 tcg_temp_free(EA); 4618 #endif /* defined(CONFIG_USER_ONLY) */ 4619 } 4620 4621 /* dcdst */ 4622 static void gen_dcbst(DisasContext *ctx) 4623 { 4624 /* XXX: specification say this is treated as a load by the MMU */ 4625 TCGv t0; 4626 gen_set_access_type(ctx, ACCESS_CACHE); 4627 t0 = tcg_temp_new(); 4628 gen_addr_reg_index(ctx, t0); 4629 gen_qemu_ld8u(ctx, t0, t0); 4630 tcg_temp_free(t0); 4631 } 4632 4633 /* dcbstep (dcbstep External PID version) */ 4634 static void gen_dcbstep(DisasContext *ctx) 4635 { 4636 /* XXX: specification say this is treated as a load by the MMU */ 4637 TCGv t0; 4638 gen_set_access_type(ctx, ACCESS_CACHE); 4639 t0 = tcg_temp_new(); 4640 gen_addr_reg_index(ctx, t0); 4641 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 4642 tcg_temp_free(t0); 4643 } 4644 4645 /* dcbt */ 4646 static void gen_dcbt(DisasContext *ctx) 4647 { 4648 /* 4649 * interpreted as no-op 4650 * XXX: specification say this is treated as a load by the MMU but 4651 * does not generate any exception 4652 */ 4653 } 4654 4655 /* dcbtep */ 4656 static void gen_dcbtep(DisasContext *ctx) 4657 { 4658 /* 4659 * interpreted as no-op 4660 * XXX: specification say this is treated as a load by the MMU but 4661 * does not generate any exception 4662 */ 4663 } 4664 4665 /* dcbtst */ 4666 static void gen_dcbtst(DisasContext *ctx) 4667 { 4668 /* 4669 * interpreted as no-op 4670 * XXX: specification say this is treated as a load by the MMU but 4671 * does not generate any exception 4672 */ 4673 } 4674 4675 /* dcbtstep */ 4676 static void gen_dcbtstep(DisasContext *ctx) 4677 { 4678 /* 4679 * interpreted as no-op 4680 * XXX: specification say this is treated as a load by the MMU but 4681 * does not generate any exception 4682 */ 4683 } 4684 4685 /* dcbtls */ 4686 static void gen_dcbtls(DisasContext *ctx) 4687 { 4688 /* Always fails locking the cache */ 4689 TCGv t0 = tcg_temp_new(); 4690 gen_load_spr(t0, SPR_Exxx_L1CSR0); 4691 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4692 gen_store_spr(SPR_Exxx_L1CSR0, t0); 4693 tcg_temp_free(t0); 4694 } 4695 4696 /* dcbz */ 4697 static void gen_dcbz(DisasContext *ctx) 4698 { 4699 TCGv tcgv_addr; 4700 TCGv_i32 tcgv_op; 4701 4702 gen_set_access_type(ctx, ACCESS_CACHE); 4703 tcgv_addr = tcg_temp_new(); 4704 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4705 gen_addr_reg_index(ctx, tcgv_addr); 4706 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4707 tcg_temp_free(tcgv_addr); 4708 tcg_temp_free_i32(tcgv_op); 4709 } 4710 4711 /* dcbzep */ 4712 static void gen_dcbzep(DisasContext *ctx) 4713 { 4714 TCGv tcgv_addr; 4715 TCGv_i32 tcgv_op; 4716 4717 gen_set_access_type(ctx, ACCESS_CACHE); 4718 tcgv_addr = tcg_temp_new(); 4719 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4720 gen_addr_reg_index(ctx, tcgv_addr); 4721 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 4722 tcg_temp_free(tcgv_addr); 4723 tcg_temp_free_i32(tcgv_op); 4724 } 4725 4726 /* dst / dstt */ 4727 static void gen_dst(DisasContext *ctx) 4728 { 4729 if (rA(ctx->opcode) == 0) { 4730 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4731 } else { 4732 /* interpreted as no-op */ 4733 } 4734 } 4735 4736 /* dstst /dststt */ 4737 static void gen_dstst(DisasContext *ctx) 4738 { 4739 if (rA(ctx->opcode) == 0) { 4740 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4741 } else { 4742 /* interpreted as no-op */ 4743 } 4744 4745 } 4746 4747 /* dss / dssall */ 4748 static void gen_dss(DisasContext *ctx) 4749 { 4750 /* interpreted as no-op */ 4751 } 4752 4753 /* icbi */ 4754 static void gen_icbi(DisasContext *ctx) 4755 { 4756 TCGv t0; 4757 gen_set_access_type(ctx, ACCESS_CACHE); 4758 t0 = tcg_temp_new(); 4759 gen_addr_reg_index(ctx, t0); 4760 gen_helper_icbi(cpu_env, t0); 4761 tcg_temp_free(t0); 4762 } 4763 4764 /* icbiep */ 4765 static void gen_icbiep(DisasContext *ctx) 4766 { 4767 TCGv t0; 4768 gen_set_access_type(ctx, ACCESS_CACHE); 4769 t0 = tcg_temp_new(); 4770 gen_addr_reg_index(ctx, t0); 4771 gen_helper_icbiep(cpu_env, t0); 4772 tcg_temp_free(t0); 4773 } 4774 4775 /* Optional: */ 4776 /* dcba */ 4777 static void gen_dcba(DisasContext *ctx) 4778 { 4779 /* 4780 * interpreted as no-op 4781 * XXX: specification say this is treated as a store by the MMU 4782 * but does not generate any exception 4783 */ 4784 } 4785 4786 /*** Segment register manipulation ***/ 4787 /* Supervisor only: */ 4788 4789 /* mfsr */ 4790 static void gen_mfsr(DisasContext *ctx) 4791 { 4792 #if defined(CONFIG_USER_ONLY) 4793 GEN_PRIV; 4794 #else 4795 TCGv t0; 4796 4797 CHK_SV; 4798 t0 = tcg_const_tl(SR(ctx->opcode)); 4799 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4800 tcg_temp_free(t0); 4801 #endif /* defined(CONFIG_USER_ONLY) */ 4802 } 4803 4804 /* mfsrin */ 4805 static void gen_mfsrin(DisasContext *ctx) 4806 { 4807 #if defined(CONFIG_USER_ONLY) 4808 GEN_PRIV; 4809 #else 4810 TCGv t0; 4811 4812 CHK_SV; 4813 t0 = tcg_temp_new(); 4814 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4815 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4816 tcg_temp_free(t0); 4817 #endif /* defined(CONFIG_USER_ONLY) */ 4818 } 4819 4820 /* mtsr */ 4821 static void gen_mtsr(DisasContext *ctx) 4822 { 4823 #if defined(CONFIG_USER_ONLY) 4824 GEN_PRIV; 4825 #else 4826 TCGv t0; 4827 4828 CHK_SV; 4829 t0 = tcg_const_tl(SR(ctx->opcode)); 4830 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4831 tcg_temp_free(t0); 4832 #endif /* defined(CONFIG_USER_ONLY) */ 4833 } 4834 4835 /* mtsrin */ 4836 static void gen_mtsrin(DisasContext *ctx) 4837 { 4838 #if defined(CONFIG_USER_ONLY) 4839 GEN_PRIV; 4840 #else 4841 TCGv t0; 4842 CHK_SV; 4843 4844 t0 = tcg_temp_new(); 4845 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4846 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4847 tcg_temp_free(t0); 4848 #endif /* defined(CONFIG_USER_ONLY) */ 4849 } 4850 4851 #if defined(TARGET_PPC64) 4852 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4853 4854 /* mfsr */ 4855 static void gen_mfsr_64b(DisasContext *ctx) 4856 { 4857 #if defined(CONFIG_USER_ONLY) 4858 GEN_PRIV; 4859 #else 4860 TCGv t0; 4861 4862 CHK_SV; 4863 t0 = tcg_const_tl(SR(ctx->opcode)); 4864 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4865 tcg_temp_free(t0); 4866 #endif /* defined(CONFIG_USER_ONLY) */ 4867 } 4868 4869 /* mfsrin */ 4870 static void gen_mfsrin_64b(DisasContext *ctx) 4871 { 4872 #if defined(CONFIG_USER_ONLY) 4873 GEN_PRIV; 4874 #else 4875 TCGv t0; 4876 4877 CHK_SV; 4878 t0 = tcg_temp_new(); 4879 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4880 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4881 tcg_temp_free(t0); 4882 #endif /* defined(CONFIG_USER_ONLY) */ 4883 } 4884 4885 /* mtsr */ 4886 static void gen_mtsr_64b(DisasContext *ctx) 4887 { 4888 #if defined(CONFIG_USER_ONLY) 4889 GEN_PRIV; 4890 #else 4891 TCGv t0; 4892 4893 CHK_SV; 4894 t0 = tcg_const_tl(SR(ctx->opcode)); 4895 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4896 tcg_temp_free(t0); 4897 #endif /* defined(CONFIG_USER_ONLY) */ 4898 } 4899 4900 /* mtsrin */ 4901 static void gen_mtsrin_64b(DisasContext *ctx) 4902 { 4903 #if defined(CONFIG_USER_ONLY) 4904 GEN_PRIV; 4905 #else 4906 TCGv t0; 4907 4908 CHK_SV; 4909 t0 = tcg_temp_new(); 4910 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4911 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4912 tcg_temp_free(t0); 4913 #endif /* defined(CONFIG_USER_ONLY) */ 4914 } 4915 4916 /* slbmte */ 4917 static void gen_slbmte(DisasContext *ctx) 4918 { 4919 #if defined(CONFIG_USER_ONLY) 4920 GEN_PRIV; 4921 #else 4922 CHK_SV; 4923 4924 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4925 cpu_gpr[rS(ctx->opcode)]); 4926 #endif /* defined(CONFIG_USER_ONLY) */ 4927 } 4928 4929 static void gen_slbmfee(DisasContext *ctx) 4930 { 4931 #if defined(CONFIG_USER_ONLY) 4932 GEN_PRIV; 4933 #else 4934 CHK_SV; 4935 4936 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4937 cpu_gpr[rB(ctx->opcode)]); 4938 #endif /* defined(CONFIG_USER_ONLY) */ 4939 } 4940 4941 static void gen_slbmfev(DisasContext *ctx) 4942 { 4943 #if defined(CONFIG_USER_ONLY) 4944 GEN_PRIV; 4945 #else 4946 CHK_SV; 4947 4948 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4949 cpu_gpr[rB(ctx->opcode)]); 4950 #endif /* defined(CONFIG_USER_ONLY) */ 4951 } 4952 4953 static void gen_slbfee_(DisasContext *ctx) 4954 { 4955 #if defined(CONFIG_USER_ONLY) 4956 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4957 #else 4958 TCGLabel *l1, *l2; 4959 4960 if (unlikely(ctx->pr)) { 4961 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4962 return; 4963 } 4964 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4965 cpu_gpr[rB(ctx->opcode)]); 4966 l1 = gen_new_label(); 4967 l2 = gen_new_label(); 4968 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4969 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4970 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4971 tcg_gen_br(l2); 4972 gen_set_label(l1); 4973 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4974 gen_set_label(l2); 4975 #endif 4976 } 4977 #endif /* defined(TARGET_PPC64) */ 4978 4979 /*** Lookaside buffer management ***/ 4980 /* Optional & supervisor only: */ 4981 4982 /* tlbia */ 4983 static void gen_tlbia(DisasContext *ctx) 4984 { 4985 #if defined(CONFIG_USER_ONLY) 4986 GEN_PRIV; 4987 #else 4988 CHK_HV; 4989 4990 gen_helper_tlbia(cpu_env); 4991 #endif /* defined(CONFIG_USER_ONLY) */ 4992 } 4993 4994 /* tlbiel */ 4995 static void gen_tlbiel(DisasContext *ctx) 4996 { 4997 #if defined(CONFIG_USER_ONLY) 4998 GEN_PRIV; 4999 #else 5000 CHK_SV; 5001 5002 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5003 #endif /* defined(CONFIG_USER_ONLY) */ 5004 } 5005 5006 /* tlbie */ 5007 static void gen_tlbie(DisasContext *ctx) 5008 { 5009 #if defined(CONFIG_USER_ONLY) 5010 GEN_PRIV; 5011 #else 5012 TCGv_i32 t1; 5013 5014 if (ctx->gtse) { 5015 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 5016 } else { 5017 CHK_HV; /* Else hypervisor privileged */ 5018 } 5019 5020 if (NARROW_MODE(ctx)) { 5021 TCGv t0 = tcg_temp_new(); 5022 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 5023 gen_helper_tlbie(cpu_env, t0); 5024 tcg_temp_free(t0); 5025 } else { 5026 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5027 } 5028 t1 = tcg_temp_new_i32(); 5029 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5030 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 5031 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5032 tcg_temp_free_i32(t1); 5033 #endif /* defined(CONFIG_USER_ONLY) */ 5034 } 5035 5036 /* tlbsync */ 5037 static void gen_tlbsync(DisasContext *ctx) 5038 { 5039 #if defined(CONFIG_USER_ONLY) 5040 GEN_PRIV; 5041 #else 5042 5043 if (ctx->gtse) { 5044 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 5045 } else { 5046 CHK_HV; /* Else hypervisor privileged */ 5047 } 5048 5049 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5050 if (ctx->insns_flags & PPC_BOOKE) { 5051 gen_check_tlb_flush(ctx, true); 5052 } 5053 #endif /* defined(CONFIG_USER_ONLY) */ 5054 } 5055 5056 #if defined(TARGET_PPC64) 5057 /* slbia */ 5058 static void gen_slbia(DisasContext *ctx) 5059 { 5060 #if defined(CONFIG_USER_ONLY) 5061 GEN_PRIV; 5062 #else 5063 uint32_t ih = (ctx->opcode >> 21) & 0x7; 5064 TCGv_i32 t0 = tcg_const_i32(ih); 5065 5066 CHK_SV; 5067 5068 gen_helper_slbia(cpu_env, t0); 5069 tcg_temp_free_i32(t0); 5070 #endif /* defined(CONFIG_USER_ONLY) */ 5071 } 5072 5073 /* slbie */ 5074 static void gen_slbie(DisasContext *ctx) 5075 { 5076 #if defined(CONFIG_USER_ONLY) 5077 GEN_PRIV; 5078 #else 5079 CHK_SV; 5080 5081 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5082 #endif /* defined(CONFIG_USER_ONLY) */ 5083 } 5084 5085 /* slbieg */ 5086 static void gen_slbieg(DisasContext *ctx) 5087 { 5088 #if defined(CONFIG_USER_ONLY) 5089 GEN_PRIV; 5090 #else 5091 CHK_SV; 5092 5093 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5094 #endif /* defined(CONFIG_USER_ONLY) */ 5095 } 5096 5097 /* slbsync */ 5098 static void gen_slbsync(DisasContext *ctx) 5099 { 5100 #if defined(CONFIG_USER_ONLY) 5101 GEN_PRIV; 5102 #else 5103 CHK_SV; 5104 gen_check_tlb_flush(ctx, true); 5105 #endif /* defined(CONFIG_USER_ONLY) */ 5106 } 5107 5108 #endif /* defined(TARGET_PPC64) */ 5109 5110 /*** External control ***/ 5111 /* Optional: */ 5112 5113 /* eciwx */ 5114 static void gen_eciwx(DisasContext *ctx) 5115 { 5116 TCGv t0; 5117 /* Should check EAR[E] ! */ 5118 gen_set_access_type(ctx, ACCESS_EXT); 5119 t0 = tcg_temp_new(); 5120 gen_addr_reg_index(ctx, t0); 5121 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5122 DEF_MEMOP(MO_UL | MO_ALIGN)); 5123 tcg_temp_free(t0); 5124 } 5125 5126 /* ecowx */ 5127 static void gen_ecowx(DisasContext *ctx) 5128 { 5129 TCGv t0; 5130 /* Should check EAR[E] ! */ 5131 gen_set_access_type(ctx, ACCESS_EXT); 5132 t0 = tcg_temp_new(); 5133 gen_addr_reg_index(ctx, t0); 5134 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5135 DEF_MEMOP(MO_UL | MO_ALIGN)); 5136 tcg_temp_free(t0); 5137 } 5138 5139 /* PowerPC 601 specific instructions */ 5140 5141 /* abs - abs. */ 5142 static void gen_abs(DisasContext *ctx) 5143 { 5144 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5145 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5146 5147 tcg_gen_abs_tl(d, a); 5148 if (unlikely(Rc(ctx->opcode) != 0)) { 5149 gen_set_Rc0(ctx, d); 5150 } 5151 } 5152 5153 /* abso - abso. */ 5154 static void gen_abso(DisasContext *ctx) 5155 { 5156 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5157 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5158 5159 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5160 tcg_gen_abs_tl(d, a); 5161 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5162 if (unlikely(Rc(ctx->opcode) != 0)) { 5163 gen_set_Rc0(ctx, d); 5164 } 5165 } 5166 5167 /* clcs */ 5168 static void gen_clcs(DisasContext *ctx) 5169 { 5170 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5171 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5172 tcg_temp_free_i32(t0); 5173 /* Rc=1 sets CR0 to an undefined state */ 5174 } 5175 5176 /* div - div. */ 5177 static void gen_div(DisasContext *ctx) 5178 { 5179 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5180 cpu_gpr[rB(ctx->opcode)]); 5181 if (unlikely(Rc(ctx->opcode) != 0)) { 5182 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5183 } 5184 } 5185 5186 /* divo - divo. */ 5187 static void gen_divo(DisasContext *ctx) 5188 { 5189 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5190 cpu_gpr[rB(ctx->opcode)]); 5191 if (unlikely(Rc(ctx->opcode) != 0)) { 5192 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5193 } 5194 } 5195 5196 /* divs - divs. */ 5197 static void gen_divs(DisasContext *ctx) 5198 { 5199 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5200 cpu_gpr[rB(ctx->opcode)]); 5201 if (unlikely(Rc(ctx->opcode) != 0)) { 5202 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5203 } 5204 } 5205 5206 /* divso - divso. */ 5207 static void gen_divso(DisasContext *ctx) 5208 { 5209 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5210 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5211 if (unlikely(Rc(ctx->opcode) != 0)) { 5212 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5213 } 5214 } 5215 5216 /* doz - doz. */ 5217 static void gen_doz(DisasContext *ctx) 5218 { 5219 TCGLabel *l1 = gen_new_label(); 5220 TCGLabel *l2 = gen_new_label(); 5221 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5222 cpu_gpr[rA(ctx->opcode)], l1); 5223 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5224 cpu_gpr[rA(ctx->opcode)]); 5225 tcg_gen_br(l2); 5226 gen_set_label(l1); 5227 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5228 gen_set_label(l2); 5229 if (unlikely(Rc(ctx->opcode) != 0)) { 5230 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5231 } 5232 } 5233 5234 /* dozo - dozo. */ 5235 static void gen_dozo(DisasContext *ctx) 5236 { 5237 TCGLabel *l1 = gen_new_label(); 5238 TCGLabel *l2 = gen_new_label(); 5239 TCGv t0 = tcg_temp_new(); 5240 TCGv t1 = tcg_temp_new(); 5241 TCGv t2 = tcg_temp_new(); 5242 /* Start with XER OV disabled, the most likely case */ 5243 tcg_gen_movi_tl(cpu_ov, 0); 5244 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5245 cpu_gpr[rA(ctx->opcode)], l1); 5246 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5247 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5248 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5249 tcg_gen_andc_tl(t1, t1, t2); 5250 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5251 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5252 tcg_gen_movi_tl(cpu_ov, 1); 5253 tcg_gen_movi_tl(cpu_so, 1); 5254 tcg_gen_br(l2); 5255 gen_set_label(l1); 5256 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5257 gen_set_label(l2); 5258 tcg_temp_free(t0); 5259 tcg_temp_free(t1); 5260 tcg_temp_free(t2); 5261 if (unlikely(Rc(ctx->opcode) != 0)) { 5262 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5263 } 5264 } 5265 5266 /* dozi */ 5267 static void gen_dozi(DisasContext *ctx) 5268 { 5269 target_long simm = SIMM(ctx->opcode); 5270 TCGLabel *l1 = gen_new_label(); 5271 TCGLabel *l2 = gen_new_label(); 5272 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5273 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5274 tcg_gen_br(l2); 5275 gen_set_label(l1); 5276 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5277 gen_set_label(l2); 5278 if (unlikely(Rc(ctx->opcode) != 0)) { 5279 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5280 } 5281 } 5282 5283 /* lscbx - lscbx. */ 5284 static void gen_lscbx(DisasContext *ctx) 5285 { 5286 TCGv t0 = tcg_temp_new(); 5287 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5288 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5289 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5290 5291 gen_addr_reg_index(ctx, t0); 5292 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5293 tcg_temp_free_i32(t1); 5294 tcg_temp_free_i32(t2); 5295 tcg_temp_free_i32(t3); 5296 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5297 tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5298 if (unlikely(Rc(ctx->opcode) != 0)) { 5299 gen_set_Rc0(ctx, t0); 5300 } 5301 tcg_temp_free(t0); 5302 } 5303 5304 /* maskg - maskg. */ 5305 static void gen_maskg(DisasContext *ctx) 5306 { 5307 TCGLabel *l1 = gen_new_label(); 5308 TCGv t0 = tcg_temp_new(); 5309 TCGv t1 = tcg_temp_new(); 5310 TCGv t2 = tcg_temp_new(); 5311 TCGv t3 = tcg_temp_new(); 5312 tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5313 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5314 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5315 tcg_gen_addi_tl(t2, t0, 1); 5316 tcg_gen_shr_tl(t2, t3, t2); 5317 tcg_gen_shr_tl(t3, t3, t1); 5318 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5319 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5320 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5321 gen_set_label(l1); 5322 tcg_temp_free(t0); 5323 tcg_temp_free(t1); 5324 tcg_temp_free(t2); 5325 tcg_temp_free(t3); 5326 if (unlikely(Rc(ctx->opcode) != 0)) { 5327 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5328 } 5329 } 5330 5331 /* maskir - maskir. */ 5332 static void gen_maskir(DisasContext *ctx) 5333 { 5334 TCGv t0 = tcg_temp_new(); 5335 TCGv t1 = tcg_temp_new(); 5336 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5337 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5338 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5339 tcg_temp_free(t0); 5340 tcg_temp_free(t1); 5341 if (unlikely(Rc(ctx->opcode) != 0)) { 5342 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5343 } 5344 } 5345 5346 /* mul - mul. */ 5347 static void gen_mul(DisasContext *ctx) 5348 { 5349 TCGv_i64 t0 = tcg_temp_new_i64(); 5350 TCGv_i64 t1 = tcg_temp_new_i64(); 5351 TCGv t2 = tcg_temp_new(); 5352 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5353 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5354 tcg_gen_mul_i64(t0, t0, t1); 5355 tcg_gen_trunc_i64_tl(t2, t0); 5356 gen_store_spr(SPR_MQ, t2); 5357 tcg_gen_shri_i64(t1, t0, 32); 5358 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5359 tcg_temp_free_i64(t0); 5360 tcg_temp_free_i64(t1); 5361 tcg_temp_free(t2); 5362 if (unlikely(Rc(ctx->opcode) != 0)) { 5363 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5364 } 5365 } 5366 5367 /* mulo - mulo. */ 5368 static void gen_mulo(DisasContext *ctx) 5369 { 5370 TCGLabel *l1 = gen_new_label(); 5371 TCGv_i64 t0 = tcg_temp_new_i64(); 5372 TCGv_i64 t1 = tcg_temp_new_i64(); 5373 TCGv t2 = tcg_temp_new(); 5374 /* Start with XER OV disabled, the most likely case */ 5375 tcg_gen_movi_tl(cpu_ov, 0); 5376 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5377 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5378 tcg_gen_mul_i64(t0, t0, t1); 5379 tcg_gen_trunc_i64_tl(t2, t0); 5380 gen_store_spr(SPR_MQ, t2); 5381 tcg_gen_shri_i64(t1, t0, 32); 5382 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5383 tcg_gen_ext32s_i64(t1, t0); 5384 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5385 tcg_gen_movi_tl(cpu_ov, 1); 5386 tcg_gen_movi_tl(cpu_so, 1); 5387 gen_set_label(l1); 5388 tcg_temp_free_i64(t0); 5389 tcg_temp_free_i64(t1); 5390 tcg_temp_free(t2); 5391 if (unlikely(Rc(ctx->opcode) != 0)) { 5392 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5393 } 5394 } 5395 5396 /* nabs - nabs. */ 5397 static void gen_nabs(DisasContext *ctx) 5398 { 5399 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5400 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5401 5402 tcg_gen_abs_tl(d, a); 5403 tcg_gen_neg_tl(d, d); 5404 if (unlikely(Rc(ctx->opcode) != 0)) { 5405 gen_set_Rc0(ctx, d); 5406 } 5407 } 5408 5409 /* nabso - nabso. */ 5410 static void gen_nabso(DisasContext *ctx) 5411 { 5412 TCGv d = cpu_gpr[rD(ctx->opcode)]; 5413 TCGv a = cpu_gpr[rA(ctx->opcode)]; 5414 5415 tcg_gen_abs_tl(d, a); 5416 tcg_gen_neg_tl(d, d); 5417 /* nabs never overflows */ 5418 tcg_gen_movi_tl(cpu_ov, 0); 5419 if (unlikely(Rc(ctx->opcode) != 0)) { 5420 gen_set_Rc0(ctx, d); 5421 } 5422 } 5423 5424 /* rlmi - rlmi. */ 5425 static void gen_rlmi(DisasContext *ctx) 5426 { 5427 uint32_t mb = MB(ctx->opcode); 5428 uint32_t me = ME(ctx->opcode); 5429 TCGv t0 = tcg_temp_new(); 5430 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5431 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5432 tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5433 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 5434 ~MASK(mb, me)); 5435 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5436 tcg_temp_free(t0); 5437 if (unlikely(Rc(ctx->opcode) != 0)) { 5438 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5439 } 5440 } 5441 5442 /* rrib - rrib. */ 5443 static void gen_rrib(DisasContext *ctx) 5444 { 5445 TCGv t0 = tcg_temp_new(); 5446 TCGv t1 = tcg_temp_new(); 5447 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5448 tcg_gen_movi_tl(t1, 0x80000000); 5449 tcg_gen_shr_tl(t1, t1, t0); 5450 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5451 tcg_gen_and_tl(t0, t0, t1); 5452 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5453 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5454 tcg_temp_free(t0); 5455 tcg_temp_free(t1); 5456 if (unlikely(Rc(ctx->opcode) != 0)) { 5457 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5458 } 5459 } 5460 5461 /* sle - sle. */ 5462 static void gen_sle(DisasContext *ctx) 5463 { 5464 TCGv t0 = tcg_temp_new(); 5465 TCGv t1 = tcg_temp_new(); 5466 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5467 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5468 tcg_gen_subfi_tl(t1, 32, t1); 5469 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5470 tcg_gen_or_tl(t1, t0, t1); 5471 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5472 gen_store_spr(SPR_MQ, t1); 5473 tcg_temp_free(t0); 5474 tcg_temp_free(t1); 5475 if (unlikely(Rc(ctx->opcode) != 0)) { 5476 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5477 } 5478 } 5479 5480 /* sleq - sleq. */ 5481 static void gen_sleq(DisasContext *ctx) 5482 { 5483 TCGv t0 = tcg_temp_new(); 5484 TCGv t1 = tcg_temp_new(); 5485 TCGv t2 = tcg_temp_new(); 5486 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5487 tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5488 tcg_gen_shl_tl(t2, t2, t0); 5489 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5490 gen_load_spr(t1, SPR_MQ); 5491 gen_store_spr(SPR_MQ, t0); 5492 tcg_gen_and_tl(t0, t0, t2); 5493 tcg_gen_andc_tl(t1, t1, t2); 5494 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5495 tcg_temp_free(t0); 5496 tcg_temp_free(t1); 5497 tcg_temp_free(t2); 5498 if (unlikely(Rc(ctx->opcode) != 0)) { 5499 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5500 } 5501 } 5502 5503 /* sliq - sliq. */ 5504 static void gen_sliq(DisasContext *ctx) 5505 { 5506 int sh = SH(ctx->opcode); 5507 TCGv t0 = tcg_temp_new(); 5508 TCGv t1 = tcg_temp_new(); 5509 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5510 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5511 tcg_gen_or_tl(t1, t0, t1); 5512 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5513 gen_store_spr(SPR_MQ, t1); 5514 tcg_temp_free(t0); 5515 tcg_temp_free(t1); 5516 if (unlikely(Rc(ctx->opcode) != 0)) { 5517 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5518 } 5519 } 5520 5521 /* slliq - slliq. */ 5522 static void gen_slliq(DisasContext *ctx) 5523 { 5524 int sh = SH(ctx->opcode); 5525 TCGv t0 = tcg_temp_new(); 5526 TCGv t1 = tcg_temp_new(); 5527 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5528 gen_load_spr(t1, SPR_MQ); 5529 gen_store_spr(SPR_MQ, t0); 5530 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5531 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5532 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5533 tcg_temp_free(t0); 5534 tcg_temp_free(t1); 5535 if (unlikely(Rc(ctx->opcode) != 0)) { 5536 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5537 } 5538 } 5539 5540 /* sllq - sllq. */ 5541 static void gen_sllq(DisasContext *ctx) 5542 { 5543 TCGLabel *l1 = gen_new_label(); 5544 TCGLabel *l2 = gen_new_label(); 5545 TCGv t0 = tcg_temp_local_new(); 5546 TCGv t1 = tcg_temp_local_new(); 5547 TCGv t2 = tcg_temp_local_new(); 5548 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5549 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5550 tcg_gen_shl_tl(t1, t1, t2); 5551 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5552 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5553 gen_load_spr(t0, SPR_MQ); 5554 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5555 tcg_gen_br(l2); 5556 gen_set_label(l1); 5557 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5558 gen_load_spr(t2, SPR_MQ); 5559 tcg_gen_andc_tl(t1, t2, t1); 5560 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5561 gen_set_label(l2); 5562 tcg_temp_free(t0); 5563 tcg_temp_free(t1); 5564 tcg_temp_free(t2); 5565 if (unlikely(Rc(ctx->opcode) != 0)) { 5566 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5567 } 5568 } 5569 5570 /* slq - slq. */ 5571 static void gen_slq(DisasContext *ctx) 5572 { 5573 TCGLabel *l1 = gen_new_label(); 5574 TCGv t0 = tcg_temp_new(); 5575 TCGv t1 = tcg_temp_new(); 5576 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5577 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5578 tcg_gen_subfi_tl(t1, 32, t1); 5579 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5580 tcg_gen_or_tl(t1, t0, t1); 5581 gen_store_spr(SPR_MQ, t1); 5582 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5583 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5584 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5585 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5586 gen_set_label(l1); 5587 tcg_temp_free(t0); 5588 tcg_temp_free(t1); 5589 if (unlikely(Rc(ctx->opcode) != 0)) { 5590 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5591 } 5592 } 5593 5594 /* sraiq - sraiq. */ 5595 static void gen_sraiq(DisasContext *ctx) 5596 { 5597 int sh = SH(ctx->opcode); 5598 TCGLabel *l1 = gen_new_label(); 5599 TCGv t0 = tcg_temp_new(); 5600 TCGv t1 = tcg_temp_new(); 5601 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5602 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5603 tcg_gen_or_tl(t0, t0, t1); 5604 gen_store_spr(SPR_MQ, t0); 5605 tcg_gen_movi_tl(cpu_ca, 0); 5606 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5607 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5608 tcg_gen_movi_tl(cpu_ca, 1); 5609 gen_set_label(l1); 5610 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5611 tcg_temp_free(t0); 5612 tcg_temp_free(t1); 5613 if (unlikely(Rc(ctx->opcode) != 0)) { 5614 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5615 } 5616 } 5617 5618 /* sraq - sraq. */ 5619 static void gen_sraq(DisasContext *ctx) 5620 { 5621 TCGLabel *l1 = gen_new_label(); 5622 TCGLabel *l2 = gen_new_label(); 5623 TCGv t0 = tcg_temp_new(); 5624 TCGv t1 = tcg_temp_local_new(); 5625 TCGv t2 = tcg_temp_local_new(); 5626 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5627 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5628 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5629 tcg_gen_subfi_tl(t2, 32, t2); 5630 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5631 tcg_gen_or_tl(t0, t0, t2); 5632 gen_store_spr(SPR_MQ, t0); 5633 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5634 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5635 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5636 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5637 gen_set_label(l1); 5638 tcg_temp_free(t0); 5639 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5640 tcg_gen_movi_tl(cpu_ca, 0); 5641 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5642 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5643 tcg_gen_movi_tl(cpu_ca, 1); 5644 gen_set_label(l2); 5645 tcg_temp_free(t1); 5646 tcg_temp_free(t2); 5647 if (unlikely(Rc(ctx->opcode) != 0)) { 5648 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5649 } 5650 } 5651 5652 /* sre - sre. */ 5653 static void gen_sre(DisasContext *ctx) 5654 { 5655 TCGv t0 = tcg_temp_new(); 5656 TCGv t1 = tcg_temp_new(); 5657 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5658 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5659 tcg_gen_subfi_tl(t1, 32, t1); 5660 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5661 tcg_gen_or_tl(t1, t0, t1); 5662 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5663 gen_store_spr(SPR_MQ, t1); 5664 tcg_temp_free(t0); 5665 tcg_temp_free(t1); 5666 if (unlikely(Rc(ctx->opcode) != 0)) { 5667 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5668 } 5669 } 5670 5671 /* srea - srea. */ 5672 static void gen_srea(DisasContext *ctx) 5673 { 5674 TCGv t0 = tcg_temp_new(); 5675 TCGv t1 = tcg_temp_new(); 5676 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5677 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5678 gen_store_spr(SPR_MQ, t0); 5679 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5680 tcg_temp_free(t0); 5681 tcg_temp_free(t1); 5682 if (unlikely(Rc(ctx->opcode) != 0)) { 5683 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5684 } 5685 } 5686 5687 /* sreq */ 5688 static void gen_sreq(DisasContext *ctx) 5689 { 5690 TCGv t0 = tcg_temp_new(); 5691 TCGv t1 = tcg_temp_new(); 5692 TCGv t2 = tcg_temp_new(); 5693 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5694 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5695 tcg_gen_shr_tl(t1, t1, t0); 5696 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5697 gen_load_spr(t2, SPR_MQ); 5698 gen_store_spr(SPR_MQ, t0); 5699 tcg_gen_and_tl(t0, t0, t1); 5700 tcg_gen_andc_tl(t2, t2, t1); 5701 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5702 tcg_temp_free(t0); 5703 tcg_temp_free(t1); 5704 tcg_temp_free(t2); 5705 if (unlikely(Rc(ctx->opcode) != 0)) { 5706 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5707 } 5708 } 5709 5710 /* sriq */ 5711 static void gen_sriq(DisasContext *ctx) 5712 { 5713 int sh = SH(ctx->opcode); 5714 TCGv t0 = tcg_temp_new(); 5715 TCGv t1 = tcg_temp_new(); 5716 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5717 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5718 tcg_gen_or_tl(t1, t0, t1); 5719 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5720 gen_store_spr(SPR_MQ, t1); 5721 tcg_temp_free(t0); 5722 tcg_temp_free(t1); 5723 if (unlikely(Rc(ctx->opcode) != 0)) { 5724 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5725 } 5726 } 5727 5728 /* srliq */ 5729 static void gen_srliq(DisasContext *ctx) 5730 { 5731 int sh = SH(ctx->opcode); 5732 TCGv t0 = tcg_temp_new(); 5733 TCGv t1 = tcg_temp_new(); 5734 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5735 gen_load_spr(t1, SPR_MQ); 5736 gen_store_spr(SPR_MQ, t0); 5737 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5738 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5739 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5740 tcg_temp_free(t0); 5741 tcg_temp_free(t1); 5742 if (unlikely(Rc(ctx->opcode) != 0)) { 5743 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5744 } 5745 } 5746 5747 /* srlq */ 5748 static void gen_srlq(DisasContext *ctx) 5749 { 5750 TCGLabel *l1 = gen_new_label(); 5751 TCGLabel *l2 = gen_new_label(); 5752 TCGv t0 = tcg_temp_local_new(); 5753 TCGv t1 = tcg_temp_local_new(); 5754 TCGv t2 = tcg_temp_local_new(); 5755 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5756 tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5757 tcg_gen_shr_tl(t2, t1, t2); 5758 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5759 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5760 gen_load_spr(t0, SPR_MQ); 5761 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5762 tcg_gen_br(l2); 5763 gen_set_label(l1); 5764 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5765 tcg_gen_and_tl(t0, t0, t2); 5766 gen_load_spr(t1, SPR_MQ); 5767 tcg_gen_andc_tl(t1, t1, t2); 5768 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5769 gen_set_label(l2); 5770 tcg_temp_free(t0); 5771 tcg_temp_free(t1); 5772 tcg_temp_free(t2); 5773 if (unlikely(Rc(ctx->opcode) != 0)) { 5774 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5775 } 5776 } 5777 5778 /* srq */ 5779 static void gen_srq(DisasContext *ctx) 5780 { 5781 TCGLabel *l1 = gen_new_label(); 5782 TCGv t0 = tcg_temp_new(); 5783 TCGv t1 = tcg_temp_new(); 5784 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5785 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5786 tcg_gen_subfi_tl(t1, 32, t1); 5787 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5788 tcg_gen_or_tl(t1, t0, t1); 5789 gen_store_spr(SPR_MQ, t1); 5790 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5791 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5792 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5793 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5794 gen_set_label(l1); 5795 tcg_temp_free(t0); 5796 tcg_temp_free(t1); 5797 if (unlikely(Rc(ctx->opcode) != 0)) { 5798 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5799 } 5800 } 5801 5802 /* PowerPC 602 specific instructions */ 5803 5804 /* dsa */ 5805 static void gen_dsa(DisasContext *ctx) 5806 { 5807 /* XXX: TODO */ 5808 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5809 } 5810 5811 /* esa */ 5812 static void gen_esa(DisasContext *ctx) 5813 { 5814 /* XXX: TODO */ 5815 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5816 } 5817 5818 /* mfrom */ 5819 static void gen_mfrom(DisasContext *ctx) 5820 { 5821 #if defined(CONFIG_USER_ONLY) 5822 GEN_PRIV; 5823 #else 5824 CHK_SV; 5825 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5826 #endif /* defined(CONFIG_USER_ONLY) */ 5827 } 5828 5829 /* 602 - 603 - G2 TLB management */ 5830 5831 /* tlbld */ 5832 static void gen_tlbld_6xx(DisasContext *ctx) 5833 { 5834 #if defined(CONFIG_USER_ONLY) 5835 GEN_PRIV; 5836 #else 5837 CHK_SV; 5838 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5839 #endif /* defined(CONFIG_USER_ONLY) */ 5840 } 5841 5842 /* tlbli */ 5843 static void gen_tlbli_6xx(DisasContext *ctx) 5844 { 5845 #if defined(CONFIG_USER_ONLY) 5846 GEN_PRIV; 5847 #else 5848 CHK_SV; 5849 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5850 #endif /* defined(CONFIG_USER_ONLY) */ 5851 } 5852 5853 /* 74xx TLB management */ 5854 5855 /* tlbld */ 5856 static void gen_tlbld_74xx(DisasContext *ctx) 5857 { 5858 #if defined(CONFIG_USER_ONLY) 5859 GEN_PRIV; 5860 #else 5861 CHK_SV; 5862 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5863 #endif /* defined(CONFIG_USER_ONLY) */ 5864 } 5865 5866 /* tlbli */ 5867 static void gen_tlbli_74xx(DisasContext *ctx) 5868 { 5869 #if defined(CONFIG_USER_ONLY) 5870 GEN_PRIV; 5871 #else 5872 CHK_SV; 5873 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5874 #endif /* defined(CONFIG_USER_ONLY) */ 5875 } 5876 5877 /* POWER instructions not in PowerPC 601 */ 5878 5879 /* clf */ 5880 static void gen_clf(DisasContext *ctx) 5881 { 5882 /* Cache line flush: implemented as no-op */ 5883 } 5884 5885 /* cli */ 5886 static void gen_cli(DisasContext *ctx) 5887 { 5888 #if defined(CONFIG_USER_ONLY) 5889 GEN_PRIV; 5890 #else 5891 /* Cache line invalidate: privileged and treated as no-op */ 5892 CHK_SV; 5893 #endif /* defined(CONFIG_USER_ONLY) */ 5894 } 5895 5896 /* dclst */ 5897 static void gen_dclst(DisasContext *ctx) 5898 { 5899 /* Data cache line store: treated as no-op */ 5900 } 5901 5902 static void gen_mfsri(DisasContext *ctx) 5903 { 5904 #if defined(CONFIG_USER_ONLY) 5905 GEN_PRIV; 5906 #else 5907 int ra = rA(ctx->opcode); 5908 int rd = rD(ctx->opcode); 5909 TCGv t0; 5910 5911 CHK_SV; 5912 t0 = tcg_temp_new(); 5913 gen_addr_reg_index(ctx, t0); 5914 tcg_gen_extract_tl(t0, t0, 28, 4); 5915 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5916 tcg_temp_free(t0); 5917 if (ra != 0 && ra != rd) { 5918 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5919 } 5920 #endif /* defined(CONFIG_USER_ONLY) */ 5921 } 5922 5923 static void gen_rac(DisasContext *ctx) 5924 { 5925 #if defined(CONFIG_USER_ONLY) 5926 GEN_PRIV; 5927 #else 5928 TCGv t0; 5929 5930 CHK_SV; 5931 t0 = tcg_temp_new(); 5932 gen_addr_reg_index(ctx, t0); 5933 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5934 tcg_temp_free(t0); 5935 #endif /* defined(CONFIG_USER_ONLY) */ 5936 } 5937 5938 static void gen_rfsvc(DisasContext *ctx) 5939 { 5940 #if defined(CONFIG_USER_ONLY) 5941 GEN_PRIV; 5942 #else 5943 CHK_SV; 5944 5945 gen_helper_rfsvc(cpu_env); 5946 gen_sync_exception(ctx); 5947 #endif /* defined(CONFIG_USER_ONLY) */ 5948 } 5949 5950 /* svc is not implemented for now */ 5951 5952 /* BookE specific instructions */ 5953 5954 /* XXX: not implemented on 440 ? */ 5955 static void gen_mfapidi(DisasContext *ctx) 5956 { 5957 /* XXX: TODO */ 5958 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5959 } 5960 5961 /* XXX: not implemented on 440 ? */ 5962 static void gen_tlbiva(DisasContext *ctx) 5963 { 5964 #if defined(CONFIG_USER_ONLY) 5965 GEN_PRIV; 5966 #else 5967 TCGv t0; 5968 5969 CHK_SV; 5970 t0 = tcg_temp_new(); 5971 gen_addr_reg_index(ctx, t0); 5972 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5973 tcg_temp_free(t0); 5974 #endif /* defined(CONFIG_USER_ONLY) */ 5975 } 5976 5977 /* All 405 MAC instructions are translated here */ 5978 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5979 int ra, int rb, int rt, int Rc) 5980 { 5981 TCGv t0, t1; 5982 5983 t0 = tcg_temp_local_new(); 5984 t1 = tcg_temp_local_new(); 5985 5986 switch (opc3 & 0x0D) { 5987 case 0x05: 5988 /* macchw - macchw. - macchwo - macchwo. */ 5989 /* macchws - macchws. - macchwso - macchwso. */ 5990 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5991 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5992 /* mulchw - mulchw. */ 5993 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5994 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5995 tcg_gen_ext16s_tl(t1, t1); 5996 break; 5997 case 0x04: 5998 /* macchwu - macchwu. - macchwuo - macchwuo. */ 5999 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6000 /* mulchwu - mulchwu. */ 6001 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6002 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6003 tcg_gen_ext16u_tl(t1, t1); 6004 break; 6005 case 0x01: 6006 /* machhw - machhw. - machhwo - machhwo. */ 6007 /* machhws - machhws. - machhwso - machhwso. */ 6008 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6009 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6010 /* mulhhw - mulhhw. */ 6011 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6012 tcg_gen_ext16s_tl(t0, t0); 6013 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6014 tcg_gen_ext16s_tl(t1, t1); 6015 break; 6016 case 0x00: 6017 /* machhwu - machhwu. - machhwuo - machhwuo. */ 6018 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6019 /* mulhhwu - mulhhwu. */ 6020 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6021 tcg_gen_ext16u_tl(t0, t0); 6022 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6023 tcg_gen_ext16u_tl(t1, t1); 6024 break; 6025 case 0x0D: 6026 /* maclhw - maclhw. - maclhwo - maclhwo. */ 6027 /* maclhws - maclhws. - maclhwso - maclhwso. */ 6028 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 6029 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 6030 /* mullhw - mullhw. */ 6031 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6032 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 6033 break; 6034 case 0x0C: 6035 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 6036 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 6037 /* mullhwu - mullhwu. */ 6038 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6039 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 6040 break; 6041 } 6042 if (opc2 & 0x04) { 6043 /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 6044 tcg_gen_mul_tl(t1, t0, t1); 6045 if (opc2 & 0x02) { 6046 /* nmultiply-and-accumulate (0x0E) */ 6047 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 6048 } else { 6049 /* multiply-and-accumulate (0x0C) */ 6050 tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 6051 } 6052 6053 if (opc3 & 0x12) { 6054 /* Check overflow and/or saturate */ 6055 TCGLabel *l1 = gen_new_label(); 6056 6057 if (opc3 & 0x10) { 6058 /* Start with XER OV disabled, the most likely case */ 6059 tcg_gen_movi_tl(cpu_ov, 0); 6060 } 6061 if (opc3 & 0x01) { 6062 /* Signed */ 6063 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6064 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6065 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6066 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6067 if (opc3 & 0x02) { 6068 /* Saturate */ 6069 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6070 tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6071 } 6072 } else { 6073 /* Unsigned */ 6074 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6075 if (opc3 & 0x02) { 6076 /* Saturate */ 6077 tcg_gen_movi_tl(t0, UINT32_MAX); 6078 } 6079 } 6080 if (opc3 & 0x10) { 6081 /* Check overflow */ 6082 tcg_gen_movi_tl(cpu_ov, 1); 6083 tcg_gen_movi_tl(cpu_so, 1); 6084 } 6085 gen_set_label(l1); 6086 tcg_gen_mov_tl(cpu_gpr[rt], t0); 6087 } 6088 } else { 6089 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6090 } 6091 tcg_temp_free(t0); 6092 tcg_temp_free(t1); 6093 if (unlikely(Rc) != 0) { 6094 /* Update Rc0 */ 6095 gen_set_Rc0(ctx, cpu_gpr[rt]); 6096 } 6097 } 6098 6099 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6100 static void glue(gen_, name)(DisasContext *ctx) \ 6101 { \ 6102 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6103 rD(ctx->opcode), Rc(ctx->opcode)); \ 6104 } 6105 6106 /* macchw - macchw. */ 6107 GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6108 /* macchwo - macchwo. */ 6109 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6110 /* macchws - macchws. */ 6111 GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6112 /* macchwso - macchwso. */ 6113 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6114 /* macchwsu - macchwsu. */ 6115 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6116 /* macchwsuo - macchwsuo. */ 6117 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6118 /* macchwu - macchwu. */ 6119 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6120 /* macchwuo - macchwuo. */ 6121 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6122 /* machhw - machhw. */ 6123 GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6124 /* machhwo - machhwo. */ 6125 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6126 /* machhws - machhws. */ 6127 GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6128 /* machhwso - machhwso. */ 6129 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6130 /* machhwsu - machhwsu. */ 6131 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6132 /* machhwsuo - machhwsuo. */ 6133 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6134 /* machhwu - machhwu. */ 6135 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6136 /* machhwuo - machhwuo. */ 6137 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6138 /* maclhw - maclhw. */ 6139 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6140 /* maclhwo - maclhwo. */ 6141 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6142 /* maclhws - maclhws. */ 6143 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6144 /* maclhwso - maclhwso. */ 6145 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6146 /* maclhwu - maclhwu. */ 6147 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6148 /* maclhwuo - maclhwuo. */ 6149 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6150 /* maclhwsu - maclhwsu. */ 6151 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6152 /* maclhwsuo - maclhwsuo. */ 6153 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6154 /* nmacchw - nmacchw. */ 6155 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6156 /* nmacchwo - nmacchwo. */ 6157 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6158 /* nmacchws - nmacchws. */ 6159 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6160 /* nmacchwso - nmacchwso. */ 6161 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6162 /* nmachhw - nmachhw. */ 6163 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6164 /* nmachhwo - nmachhwo. */ 6165 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6166 /* nmachhws - nmachhws. */ 6167 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6168 /* nmachhwso - nmachhwso. */ 6169 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6170 /* nmaclhw - nmaclhw. */ 6171 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6172 /* nmaclhwo - nmaclhwo. */ 6173 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6174 /* nmaclhws - nmaclhws. */ 6175 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6176 /* nmaclhwso - nmaclhwso. */ 6177 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6178 6179 /* mulchw - mulchw. */ 6180 GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6181 /* mulchwu - mulchwu. */ 6182 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6183 /* mulhhw - mulhhw. */ 6184 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6185 /* mulhhwu - mulhhwu. */ 6186 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6187 /* mullhw - mullhw. */ 6188 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6189 /* mullhwu - mullhwu. */ 6190 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6191 6192 /* mfdcr */ 6193 static void gen_mfdcr(DisasContext *ctx) 6194 { 6195 #if defined(CONFIG_USER_ONLY) 6196 GEN_PRIV; 6197 #else 6198 TCGv dcrn; 6199 6200 CHK_SV; 6201 dcrn = tcg_const_tl(SPR(ctx->opcode)); 6202 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6203 tcg_temp_free(dcrn); 6204 #endif /* defined(CONFIG_USER_ONLY) */ 6205 } 6206 6207 /* mtdcr */ 6208 static void gen_mtdcr(DisasContext *ctx) 6209 { 6210 #if defined(CONFIG_USER_ONLY) 6211 GEN_PRIV; 6212 #else 6213 TCGv dcrn; 6214 6215 CHK_SV; 6216 dcrn = tcg_const_tl(SPR(ctx->opcode)); 6217 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6218 tcg_temp_free(dcrn); 6219 #endif /* defined(CONFIG_USER_ONLY) */ 6220 } 6221 6222 /* mfdcrx */ 6223 /* XXX: not implemented on 440 ? */ 6224 static void gen_mfdcrx(DisasContext *ctx) 6225 { 6226 #if defined(CONFIG_USER_ONLY) 6227 GEN_PRIV; 6228 #else 6229 CHK_SV; 6230 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6231 cpu_gpr[rA(ctx->opcode)]); 6232 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6233 #endif /* defined(CONFIG_USER_ONLY) */ 6234 } 6235 6236 /* mtdcrx */ 6237 /* XXX: not implemented on 440 ? */ 6238 static void gen_mtdcrx(DisasContext *ctx) 6239 { 6240 #if defined(CONFIG_USER_ONLY) 6241 GEN_PRIV; 6242 #else 6243 CHK_SV; 6244 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6245 cpu_gpr[rS(ctx->opcode)]); 6246 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6247 #endif /* defined(CONFIG_USER_ONLY) */ 6248 } 6249 6250 /* mfdcrux (PPC 460) : user-mode access to DCR */ 6251 static void gen_mfdcrux(DisasContext *ctx) 6252 { 6253 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6254 cpu_gpr[rA(ctx->opcode)]); 6255 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6256 } 6257 6258 /* mtdcrux (PPC 460) : user-mode access to DCR */ 6259 static void gen_mtdcrux(DisasContext *ctx) 6260 { 6261 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6262 cpu_gpr[rS(ctx->opcode)]); 6263 /* Note: Rc update flag set leads to undefined state of Rc0 */ 6264 } 6265 6266 /* dccci */ 6267 static void gen_dccci(DisasContext *ctx) 6268 { 6269 CHK_SV; 6270 /* interpreted as no-op */ 6271 } 6272 6273 /* dcread */ 6274 static void gen_dcread(DisasContext *ctx) 6275 { 6276 #if defined(CONFIG_USER_ONLY) 6277 GEN_PRIV; 6278 #else 6279 TCGv EA, val; 6280 6281 CHK_SV; 6282 gen_set_access_type(ctx, ACCESS_CACHE); 6283 EA = tcg_temp_new(); 6284 gen_addr_reg_index(ctx, EA); 6285 val = tcg_temp_new(); 6286 gen_qemu_ld32u(ctx, val, EA); 6287 tcg_temp_free(val); 6288 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6289 tcg_temp_free(EA); 6290 #endif /* defined(CONFIG_USER_ONLY) */ 6291 } 6292 6293 /* icbt */ 6294 static void gen_icbt_40x(DisasContext *ctx) 6295 { 6296 /* 6297 * interpreted as no-op 6298 * XXX: specification say this is treated as a load by the MMU but 6299 * does not generate any exception 6300 */ 6301 } 6302 6303 /* iccci */ 6304 static void gen_iccci(DisasContext *ctx) 6305 { 6306 CHK_SV; 6307 /* interpreted as no-op */ 6308 } 6309 6310 /* icread */ 6311 static void gen_icread(DisasContext *ctx) 6312 { 6313 CHK_SV; 6314 /* interpreted as no-op */ 6315 } 6316 6317 /* rfci (supervisor only) */ 6318 static void gen_rfci_40x(DisasContext *ctx) 6319 { 6320 #if defined(CONFIG_USER_ONLY) 6321 GEN_PRIV; 6322 #else 6323 CHK_SV; 6324 /* Restore CPU state */ 6325 gen_helper_40x_rfci(cpu_env); 6326 gen_sync_exception(ctx); 6327 #endif /* defined(CONFIG_USER_ONLY) */ 6328 } 6329 6330 static void gen_rfci(DisasContext *ctx) 6331 { 6332 #if defined(CONFIG_USER_ONLY) 6333 GEN_PRIV; 6334 #else 6335 CHK_SV; 6336 /* Restore CPU state */ 6337 gen_helper_rfci(cpu_env); 6338 gen_sync_exception(ctx); 6339 #endif /* defined(CONFIG_USER_ONLY) */ 6340 } 6341 6342 /* BookE specific */ 6343 6344 /* XXX: not implemented on 440 ? */ 6345 static void gen_rfdi(DisasContext *ctx) 6346 { 6347 #if defined(CONFIG_USER_ONLY) 6348 GEN_PRIV; 6349 #else 6350 CHK_SV; 6351 /* Restore CPU state */ 6352 gen_helper_rfdi(cpu_env); 6353 gen_sync_exception(ctx); 6354 #endif /* defined(CONFIG_USER_ONLY) */ 6355 } 6356 6357 /* XXX: not implemented on 440 ? */ 6358 static void gen_rfmci(DisasContext *ctx) 6359 { 6360 #if defined(CONFIG_USER_ONLY) 6361 GEN_PRIV; 6362 #else 6363 CHK_SV; 6364 /* Restore CPU state */ 6365 gen_helper_rfmci(cpu_env); 6366 gen_sync_exception(ctx); 6367 #endif /* defined(CONFIG_USER_ONLY) */ 6368 } 6369 6370 /* TLB management - PowerPC 405 implementation */ 6371 6372 /* tlbre */ 6373 static void gen_tlbre_40x(DisasContext *ctx) 6374 { 6375 #if defined(CONFIG_USER_ONLY) 6376 GEN_PRIV; 6377 #else 6378 CHK_SV; 6379 switch (rB(ctx->opcode)) { 6380 case 0: 6381 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6382 cpu_gpr[rA(ctx->opcode)]); 6383 break; 6384 case 1: 6385 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6386 cpu_gpr[rA(ctx->opcode)]); 6387 break; 6388 default: 6389 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6390 break; 6391 } 6392 #endif /* defined(CONFIG_USER_ONLY) */ 6393 } 6394 6395 /* tlbsx - tlbsx. */ 6396 static void gen_tlbsx_40x(DisasContext *ctx) 6397 { 6398 #if defined(CONFIG_USER_ONLY) 6399 GEN_PRIV; 6400 #else 6401 TCGv t0; 6402 6403 CHK_SV; 6404 t0 = tcg_temp_new(); 6405 gen_addr_reg_index(ctx, t0); 6406 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6407 tcg_temp_free(t0); 6408 if (Rc(ctx->opcode)) { 6409 TCGLabel *l1 = gen_new_label(); 6410 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6411 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6412 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6413 gen_set_label(l1); 6414 } 6415 #endif /* defined(CONFIG_USER_ONLY) */ 6416 } 6417 6418 /* tlbwe */ 6419 static void gen_tlbwe_40x(DisasContext *ctx) 6420 { 6421 #if defined(CONFIG_USER_ONLY) 6422 GEN_PRIV; 6423 #else 6424 CHK_SV; 6425 6426 switch (rB(ctx->opcode)) { 6427 case 0: 6428 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6429 cpu_gpr[rS(ctx->opcode)]); 6430 break; 6431 case 1: 6432 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6433 cpu_gpr[rS(ctx->opcode)]); 6434 break; 6435 default: 6436 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6437 break; 6438 } 6439 #endif /* defined(CONFIG_USER_ONLY) */ 6440 } 6441 6442 /* TLB management - PowerPC 440 implementation */ 6443 6444 /* tlbre */ 6445 static void gen_tlbre_440(DisasContext *ctx) 6446 { 6447 #if defined(CONFIG_USER_ONLY) 6448 GEN_PRIV; 6449 #else 6450 CHK_SV; 6451 6452 switch (rB(ctx->opcode)) { 6453 case 0: 6454 case 1: 6455 case 2: 6456 { 6457 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6458 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6459 t0, cpu_gpr[rA(ctx->opcode)]); 6460 tcg_temp_free_i32(t0); 6461 } 6462 break; 6463 default: 6464 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6465 break; 6466 } 6467 #endif /* defined(CONFIG_USER_ONLY) */ 6468 } 6469 6470 /* tlbsx - tlbsx. */ 6471 static void gen_tlbsx_440(DisasContext *ctx) 6472 { 6473 #if defined(CONFIG_USER_ONLY) 6474 GEN_PRIV; 6475 #else 6476 TCGv t0; 6477 6478 CHK_SV; 6479 t0 = tcg_temp_new(); 6480 gen_addr_reg_index(ctx, t0); 6481 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6482 tcg_temp_free(t0); 6483 if (Rc(ctx->opcode)) { 6484 TCGLabel *l1 = gen_new_label(); 6485 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6486 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6487 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6488 gen_set_label(l1); 6489 } 6490 #endif /* defined(CONFIG_USER_ONLY) */ 6491 } 6492 6493 /* tlbwe */ 6494 static void gen_tlbwe_440(DisasContext *ctx) 6495 { 6496 #if defined(CONFIG_USER_ONLY) 6497 GEN_PRIV; 6498 #else 6499 CHK_SV; 6500 switch (rB(ctx->opcode)) { 6501 case 0: 6502 case 1: 6503 case 2: 6504 { 6505 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6506 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6507 cpu_gpr[rS(ctx->opcode)]); 6508 tcg_temp_free_i32(t0); 6509 } 6510 break; 6511 default: 6512 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6513 break; 6514 } 6515 #endif /* defined(CONFIG_USER_ONLY) */ 6516 } 6517 6518 /* TLB management - PowerPC BookE 2.06 implementation */ 6519 6520 /* tlbre */ 6521 static void gen_tlbre_booke206(DisasContext *ctx) 6522 { 6523 #if defined(CONFIG_USER_ONLY) 6524 GEN_PRIV; 6525 #else 6526 CHK_SV; 6527 gen_helper_booke206_tlbre(cpu_env); 6528 #endif /* defined(CONFIG_USER_ONLY) */ 6529 } 6530 6531 /* tlbsx - tlbsx. */ 6532 static void gen_tlbsx_booke206(DisasContext *ctx) 6533 { 6534 #if defined(CONFIG_USER_ONLY) 6535 GEN_PRIV; 6536 #else 6537 TCGv t0; 6538 6539 CHK_SV; 6540 if (rA(ctx->opcode)) { 6541 t0 = tcg_temp_new(); 6542 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6543 } else { 6544 t0 = tcg_const_tl(0); 6545 } 6546 6547 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6548 gen_helper_booke206_tlbsx(cpu_env, t0); 6549 tcg_temp_free(t0); 6550 #endif /* defined(CONFIG_USER_ONLY) */ 6551 } 6552 6553 /* tlbwe */ 6554 static void gen_tlbwe_booke206(DisasContext *ctx) 6555 { 6556 #if defined(CONFIG_USER_ONLY) 6557 GEN_PRIV; 6558 #else 6559 CHK_SV; 6560 gen_helper_booke206_tlbwe(cpu_env); 6561 #endif /* defined(CONFIG_USER_ONLY) */ 6562 } 6563 6564 static void gen_tlbivax_booke206(DisasContext *ctx) 6565 { 6566 #if defined(CONFIG_USER_ONLY) 6567 GEN_PRIV; 6568 #else 6569 TCGv t0; 6570 6571 CHK_SV; 6572 t0 = tcg_temp_new(); 6573 gen_addr_reg_index(ctx, t0); 6574 gen_helper_booke206_tlbivax(cpu_env, t0); 6575 tcg_temp_free(t0); 6576 #endif /* defined(CONFIG_USER_ONLY) */ 6577 } 6578 6579 static void gen_tlbilx_booke206(DisasContext *ctx) 6580 { 6581 #if defined(CONFIG_USER_ONLY) 6582 GEN_PRIV; 6583 #else 6584 TCGv t0; 6585 6586 CHK_SV; 6587 t0 = tcg_temp_new(); 6588 gen_addr_reg_index(ctx, t0); 6589 6590 switch ((ctx->opcode >> 21) & 0x3) { 6591 case 0: 6592 gen_helper_booke206_tlbilx0(cpu_env, t0); 6593 break; 6594 case 1: 6595 gen_helper_booke206_tlbilx1(cpu_env, t0); 6596 break; 6597 case 3: 6598 gen_helper_booke206_tlbilx3(cpu_env, t0); 6599 break; 6600 default: 6601 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6602 break; 6603 } 6604 6605 tcg_temp_free(t0); 6606 #endif /* defined(CONFIG_USER_ONLY) */ 6607 } 6608 6609 6610 /* wrtee */ 6611 static void gen_wrtee(DisasContext *ctx) 6612 { 6613 #if defined(CONFIG_USER_ONLY) 6614 GEN_PRIV; 6615 #else 6616 TCGv t0; 6617 6618 CHK_SV; 6619 t0 = tcg_temp_new(); 6620 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6621 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6622 tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6623 tcg_temp_free(t0); 6624 /* 6625 * Stop translation to have a chance to raise an exception if we 6626 * just set msr_ee to 1 6627 */ 6628 gen_stop_exception(ctx); 6629 #endif /* defined(CONFIG_USER_ONLY) */ 6630 } 6631 6632 /* wrteei */ 6633 static void gen_wrteei(DisasContext *ctx) 6634 { 6635 #if defined(CONFIG_USER_ONLY) 6636 GEN_PRIV; 6637 #else 6638 CHK_SV; 6639 if (ctx->opcode & 0x00008000) { 6640 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6641 /* Stop translation to have a chance to raise an exception */ 6642 gen_stop_exception(ctx); 6643 } else { 6644 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6645 } 6646 #endif /* defined(CONFIG_USER_ONLY) */ 6647 } 6648 6649 /* PowerPC 440 specific instructions */ 6650 6651 /* dlmzb */ 6652 static void gen_dlmzb(DisasContext *ctx) 6653 { 6654 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6655 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6656 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6657 tcg_temp_free_i32(t0); 6658 } 6659 6660 /* mbar replaces eieio on 440 */ 6661 static void gen_mbar(DisasContext *ctx) 6662 { 6663 /* interpreted as no-op */ 6664 } 6665 6666 /* msync replaces sync on 440 */ 6667 static void gen_msync_4xx(DisasContext *ctx) 6668 { 6669 /* Only e500 seems to treat reserved bits as invalid */ 6670 if ((ctx->insns_flags2 & PPC2_BOOKE206) && 6671 (ctx->opcode & 0x03FFF801)) { 6672 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6673 } 6674 /* otherwise interpreted as no-op */ 6675 } 6676 6677 /* icbt */ 6678 static void gen_icbt_440(DisasContext *ctx) 6679 { 6680 /* 6681 * interpreted as no-op 6682 * XXX: specification say this is treated as a load by the MMU but 6683 * does not generate any exception 6684 */ 6685 } 6686 6687 /* Embedded.Processor Control */ 6688 6689 static void gen_msgclr(DisasContext *ctx) 6690 { 6691 #if defined(CONFIG_USER_ONLY) 6692 GEN_PRIV; 6693 #else 6694 CHK_HV; 6695 if (is_book3s_arch2x(ctx)) { 6696 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6697 } else { 6698 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6699 } 6700 #endif /* defined(CONFIG_USER_ONLY) */ 6701 } 6702 6703 static void gen_msgsnd(DisasContext *ctx) 6704 { 6705 #if defined(CONFIG_USER_ONLY) 6706 GEN_PRIV; 6707 #else 6708 CHK_HV; 6709 if (is_book3s_arch2x(ctx)) { 6710 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6711 } else { 6712 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6713 } 6714 #endif /* defined(CONFIG_USER_ONLY) */ 6715 } 6716 6717 #if defined(TARGET_PPC64) 6718 static void gen_msgclrp(DisasContext *ctx) 6719 { 6720 #if defined(CONFIG_USER_ONLY) 6721 GEN_PRIV; 6722 #else 6723 CHK_SV; 6724 gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6725 #endif /* defined(CONFIG_USER_ONLY) */ 6726 } 6727 6728 static void gen_msgsndp(DisasContext *ctx) 6729 { 6730 #if defined(CONFIG_USER_ONLY) 6731 GEN_PRIV; 6732 #else 6733 CHK_SV; 6734 gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6735 #endif /* defined(CONFIG_USER_ONLY) */ 6736 } 6737 #endif 6738 6739 static void gen_msgsync(DisasContext *ctx) 6740 { 6741 #if defined(CONFIG_USER_ONLY) 6742 GEN_PRIV; 6743 #else 6744 CHK_HV; 6745 #endif /* defined(CONFIG_USER_ONLY) */ 6746 /* interpreted as no-op */ 6747 } 6748 6749 #if defined(TARGET_PPC64) 6750 static void gen_maddld(DisasContext *ctx) 6751 { 6752 TCGv_i64 t1 = tcg_temp_new_i64(); 6753 6754 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6755 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6756 tcg_temp_free_i64(t1); 6757 } 6758 6759 /* maddhd maddhdu */ 6760 static void gen_maddhd_maddhdu(DisasContext *ctx) 6761 { 6762 TCGv_i64 lo = tcg_temp_new_i64(); 6763 TCGv_i64 hi = tcg_temp_new_i64(); 6764 TCGv_i64 t1 = tcg_temp_new_i64(); 6765 6766 if (Rc(ctx->opcode)) { 6767 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6768 cpu_gpr[rB(ctx->opcode)]); 6769 tcg_gen_movi_i64(t1, 0); 6770 } else { 6771 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6772 cpu_gpr[rB(ctx->opcode)]); 6773 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6774 } 6775 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6776 cpu_gpr[rC(ctx->opcode)], t1); 6777 tcg_temp_free_i64(lo); 6778 tcg_temp_free_i64(hi); 6779 tcg_temp_free_i64(t1); 6780 } 6781 #endif /* defined(TARGET_PPC64) */ 6782 6783 static void gen_tbegin(DisasContext *ctx) 6784 { 6785 if (unlikely(!ctx->tm_enabled)) { 6786 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6787 return; 6788 } 6789 gen_helper_tbegin(cpu_env); 6790 } 6791 6792 #define GEN_TM_NOOP(name) \ 6793 static inline void gen_##name(DisasContext *ctx) \ 6794 { \ 6795 if (unlikely(!ctx->tm_enabled)) { \ 6796 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6797 return; \ 6798 } \ 6799 /* \ 6800 * Because tbegin always fails in QEMU, these user \ 6801 * space instructions all have a simple implementation: \ 6802 * \ 6803 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6804 * = 0b0 || 0b00 || 0b0 \ 6805 */ \ 6806 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6807 } 6808 6809 GEN_TM_NOOP(tend); 6810 GEN_TM_NOOP(tabort); 6811 GEN_TM_NOOP(tabortwc); 6812 GEN_TM_NOOP(tabortwci); 6813 GEN_TM_NOOP(tabortdc); 6814 GEN_TM_NOOP(tabortdci); 6815 GEN_TM_NOOP(tsr); 6816 6817 static inline void gen_cp_abort(DisasContext *ctx) 6818 { 6819 /* Do Nothing */ 6820 } 6821 6822 #define GEN_CP_PASTE_NOOP(name) \ 6823 static inline void gen_##name(DisasContext *ctx) \ 6824 { \ 6825 /* \ 6826 * Generate invalid exception until we have an \ 6827 * implementation of the copy paste facility \ 6828 */ \ 6829 gen_invalid(ctx); \ 6830 } 6831 6832 GEN_CP_PASTE_NOOP(copy) 6833 GEN_CP_PASTE_NOOP(paste) 6834 6835 static void gen_tcheck(DisasContext *ctx) 6836 { 6837 if (unlikely(!ctx->tm_enabled)) { 6838 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6839 return; 6840 } 6841 /* 6842 * Because tbegin always fails, the tcheck implementation is 6843 * simple: 6844 * 6845 * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6846 * = 0b1 || 0b00 || 0b0 6847 */ 6848 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6849 } 6850 6851 #if defined(CONFIG_USER_ONLY) 6852 #define GEN_TM_PRIV_NOOP(name) \ 6853 static inline void gen_##name(DisasContext *ctx) \ 6854 { \ 6855 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6856 } 6857 6858 #else 6859 6860 #define GEN_TM_PRIV_NOOP(name) \ 6861 static inline void gen_##name(DisasContext *ctx) \ 6862 { \ 6863 CHK_SV; \ 6864 if (unlikely(!ctx->tm_enabled)) { \ 6865 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6866 return; \ 6867 } \ 6868 /* \ 6869 * Because tbegin always fails, the implementation is \ 6870 * simple: \ 6871 * \ 6872 * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6873 * = 0b0 || 0b00 | 0b0 \ 6874 */ \ 6875 tcg_gen_movi_i32(cpu_crf[0], 0); \ 6876 } 6877 6878 #endif 6879 6880 GEN_TM_PRIV_NOOP(treclaim); 6881 GEN_TM_PRIV_NOOP(trechkpt); 6882 6883 static inline void get_fpr(TCGv_i64 dst, int regno) 6884 { 6885 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 6886 } 6887 6888 static inline void set_fpr(int regno, TCGv_i64 src) 6889 { 6890 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 6891 } 6892 6893 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6894 { 6895 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6896 } 6897 6898 static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6899 { 6900 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6901 } 6902 6903 #include "translate/fp-impl.c.inc" 6904 6905 #include "translate/vmx-impl.c.inc" 6906 6907 #include "translate/vsx-impl.c.inc" 6908 6909 #include "translate/dfp-impl.c.inc" 6910 6911 #include "translate/spe-impl.c.inc" 6912 6913 /* Handles lfdp, lxsd, lxssp */ 6914 static void gen_dform39(DisasContext *ctx) 6915 { 6916 switch (ctx->opcode & 0x3) { 6917 case 0: /* lfdp */ 6918 if (ctx->insns_flags2 & PPC2_ISA205) { 6919 return gen_lfdp(ctx); 6920 } 6921 break; 6922 case 2: /* lxsd */ 6923 if (ctx->insns_flags2 & PPC2_ISA300) { 6924 return gen_lxsd(ctx); 6925 } 6926 break; 6927 case 3: /* lxssp */ 6928 if (ctx->insns_flags2 & PPC2_ISA300) { 6929 return gen_lxssp(ctx); 6930 } 6931 break; 6932 } 6933 return gen_invalid(ctx); 6934 } 6935 6936 /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6937 static void gen_dform3D(DisasContext *ctx) 6938 { 6939 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6940 switch (ctx->opcode & 0x7) { 6941 case 1: /* lxv */ 6942 if (ctx->insns_flags2 & PPC2_ISA300) { 6943 return gen_lxv(ctx); 6944 } 6945 break; 6946 case 5: /* stxv */ 6947 if (ctx->insns_flags2 & PPC2_ISA300) { 6948 return gen_stxv(ctx); 6949 } 6950 break; 6951 } 6952 } else { /* DS-FORM */ 6953 switch (ctx->opcode & 0x3) { 6954 case 0: /* stfdp */ 6955 if (ctx->insns_flags2 & PPC2_ISA205) { 6956 return gen_stfdp(ctx); 6957 } 6958 break; 6959 case 2: /* stxsd */ 6960 if (ctx->insns_flags2 & PPC2_ISA300) { 6961 return gen_stxsd(ctx); 6962 } 6963 break; 6964 case 3: /* stxssp */ 6965 if (ctx->insns_flags2 & PPC2_ISA300) { 6966 return gen_stxssp(ctx); 6967 } 6968 break; 6969 } 6970 } 6971 return gen_invalid(ctx); 6972 } 6973 6974 #if defined(TARGET_PPC64) 6975 /* brd */ 6976 static void gen_brd(DisasContext *ctx) 6977 { 6978 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6979 } 6980 6981 /* brw */ 6982 static void gen_brw(DisasContext *ctx) 6983 { 6984 tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 6985 tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 6986 6987 } 6988 6989 /* brh */ 6990 static void gen_brh(DisasContext *ctx) 6991 { 6992 TCGv_i64 t0 = tcg_temp_new_i64(); 6993 TCGv_i64 t1 = tcg_temp_new_i64(); 6994 TCGv_i64 t2 = tcg_temp_new_i64(); 6995 6996 tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); 6997 tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6998 tcg_gen_and_i64(t2, t1, t0); 6999 tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); 7000 tcg_gen_shli_i64(t1, t1, 8); 7001 tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 7002 7003 tcg_temp_free_i64(t0); 7004 tcg_temp_free_i64(t1); 7005 tcg_temp_free_i64(t2); 7006 } 7007 #endif 7008 7009 static opcode_t opcodes[] = { 7010 #if defined(TARGET_PPC64) 7011 GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 7012 GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 7013 GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 7014 #endif 7015 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7016 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 7017 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7018 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 7019 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7020 #if defined(TARGET_PPC64) 7021 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7022 #endif 7023 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 7024 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 7025 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 7026 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7027 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7028 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7029 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7030 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 7031 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 7032 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 7033 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 7034 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 7035 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7036 #if defined(TARGET_PPC64) 7037 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 7038 #endif 7039 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 7040 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 7041 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7042 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7043 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7044 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 7045 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 7046 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 7047 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7048 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 7049 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 7050 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 7051 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7052 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7053 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7054 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7055 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 7056 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 7057 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 7058 #if defined(TARGET_PPC64) 7059 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 7060 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 7061 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 7062 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 7063 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 7064 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 7065 #endif 7066 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7067 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7068 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7069 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 7070 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 7071 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 7072 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 7073 #if defined(TARGET_PPC64) 7074 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 7075 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 7076 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 7077 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 7078 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 7079 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 7080 PPC_NONE, PPC2_ISA300), 7081 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 7082 PPC_NONE, PPC2_ISA300), 7083 #endif 7084 #if defined(TARGET_PPC64) 7085 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 7086 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 7087 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 7088 #endif 7089 /* handles lfdp, lxsd, lxssp */ 7090 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7091 /* handles stfdp, lxv, stxsd, stxssp, stxv */ 7092 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7093 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7094 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7095 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 7096 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 7097 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 7098 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 7099 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 7100 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 7101 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7102 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7103 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 7104 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 7105 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 7106 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7107 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7108 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7109 #if defined(TARGET_PPC64) 7110 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7111 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7112 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7113 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7114 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7115 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7116 #endif 7117 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7118 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7119 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7120 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7121 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7122 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7123 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7124 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7125 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7126 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7127 #if defined(TARGET_PPC64) 7128 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 7129 #if !defined(CONFIG_USER_ONLY) 7130 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 7131 GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 7132 GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 7133 GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 7134 #endif 7135 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7136 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7137 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7138 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7139 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7140 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7141 #endif 7142 /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 7143 GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 7144 GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 7145 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7146 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7147 #if defined(TARGET_PPC64) 7148 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7149 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7150 #endif 7151 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7152 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7153 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7154 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7155 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7156 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7157 #if defined(TARGET_PPC64) 7158 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7159 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7160 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7161 #endif 7162 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7163 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7164 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 7165 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7166 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7167 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 7168 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7169 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 7170 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7171 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 7172 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7173 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7174 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 7175 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7176 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 7177 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7178 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7179 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 7180 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7181 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7182 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7183 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7184 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7185 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7186 #if defined(TARGET_PPC64) 7187 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7188 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7189 PPC_SEGMENT_64B), 7190 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7191 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7192 PPC_SEGMENT_64B), 7193 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7194 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7195 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7196 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7197 #endif 7198 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7199 /* 7200 * XXX Those instructions will need to be handled differently for 7201 * different ISA versions 7202 */ 7203 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7204 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7205 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 7206 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 7207 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 7208 #if defined(TARGET_PPC64) 7209 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 7210 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 7211 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 7212 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7213 #endif 7214 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 7215 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 7216 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 7217 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 7218 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 7219 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 7220 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 7221 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 7222 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 7223 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 7224 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 7225 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7226 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 7227 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 7228 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 7229 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 7230 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 7231 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 7232 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 7233 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7234 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 7235 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 7236 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 7237 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 7238 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 7239 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 7240 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 7241 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 7242 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 7243 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 7244 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 7245 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 7246 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 7247 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 7248 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 7249 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 7250 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7251 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7252 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7253 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7254 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7255 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 7256 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 7257 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7258 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7259 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7260 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7261 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7262 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7263 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7264 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7265 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7266 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7267 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7268 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7269 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7270 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7271 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7272 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7273 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7274 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7275 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7276 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7277 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7278 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7279 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7280 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7281 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7282 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7283 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7284 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7285 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7286 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7287 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7288 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7289 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7290 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7291 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7292 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7293 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7294 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7295 PPC_NONE, PPC2_BOOKE206), 7296 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7297 PPC_NONE, PPC2_BOOKE206), 7298 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7299 PPC_NONE, PPC2_BOOKE206), 7300 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7301 PPC_NONE, PPC2_BOOKE206), 7302 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7303 PPC_NONE, PPC2_BOOKE206), 7304 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7305 PPC_NONE, PPC2_PRCNTL), 7306 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7307 PPC_NONE, PPC2_PRCNTL), 7308 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 7309 PPC_NONE, PPC2_PRCNTL), 7310 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7311 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7312 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7313 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7314 PPC_BOOKE, PPC2_BOOKE206), 7315 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 7316 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7317 PPC_BOOKE, PPC2_BOOKE206), 7318 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 7319 PPC_440_SPEC), 7320 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7321 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7322 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7323 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7324 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7325 #if defined(TARGET_PPC64) 7326 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7327 PPC2_ISA300), 7328 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 7329 GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 7330 PPC_NONE, PPC2_ISA207S), 7331 GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 7332 PPC_NONE, PPC2_ISA207S), 7333 #endif 7334 7335 #undef GEN_INT_ARITH_ADD 7336 #undef GEN_INT_ARITH_ADD_CONST 7337 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7338 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7339 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7340 add_ca, compute_ca, compute_ov) \ 7341 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7342 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7343 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7344 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7345 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7346 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7347 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7348 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7349 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 7350 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7351 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7352 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7353 7354 #undef GEN_INT_ARITH_DIVW 7355 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7356 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7357 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7358 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7359 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7360 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7361 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7362 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7363 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7364 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7365 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7366 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7367 7368 #if defined(TARGET_PPC64) 7369 #undef GEN_INT_ARITH_DIVD 7370 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7371 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7372 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7373 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7374 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7375 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7376 7377 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7378 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7379 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7380 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7381 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7382 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7383 7384 #undef GEN_INT_ARITH_MUL_HELPER 7385 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 7386 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7387 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 7388 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 7389 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 7390 #endif 7391 7392 #undef GEN_INT_ARITH_SUBF 7393 #undef GEN_INT_ARITH_SUBF_CONST 7394 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 7395 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 7396 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 7397 add_ca, compute_ca, compute_ov) \ 7398 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 7399 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 7400 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7401 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7402 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7403 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7404 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7405 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7406 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7407 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7408 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7409 7410 #undef GEN_LOGICAL1 7411 #undef GEN_LOGICAL2 7412 #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7413 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7414 #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7415 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7416 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7417 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7418 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7419 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7420 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7421 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7422 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7423 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7424 #if defined(TARGET_PPC64) 7425 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 7426 #endif 7427 7428 #if defined(TARGET_PPC64) 7429 #undef GEN_PPC64_R2 7430 #undef GEN_PPC64_R4 7431 #define GEN_PPC64_R2(name, opc1, opc2) \ 7432 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7433 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7434 PPC_64B) 7435 #define GEN_PPC64_R4(name, opc1, opc2) \ 7436 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7437 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7438 PPC_64B), \ 7439 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7440 PPC_64B), \ 7441 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7442 PPC_64B) 7443 GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7444 GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7445 GEN_PPC64_R4(rldic, 0x1E, 0x04), 7446 GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7447 GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7448 GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7449 #endif 7450 7451 #undef GEN_LD 7452 #undef GEN_LDU 7453 #undef GEN_LDUX 7454 #undef GEN_LDX_E 7455 #undef GEN_LDS 7456 #define GEN_LD(name, ldop, opc, type) \ 7457 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7458 #define GEN_LDU(name, ldop, opc, type) \ 7459 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 7460 #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 7461 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7462 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7463 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7464 #define GEN_LDS(name, ldop, op, type) \ 7465 GEN_LD(name, ldop, op | 0x20, type) \ 7466 GEN_LDU(name, ldop, op | 0x21, type) \ 7467 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 7468 GEN_LDX(name, ldop, 0x17, op | 0x00, type) 7469 7470 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 7471 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 7472 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 7473 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 7474 #if defined(TARGET_PPC64) 7475 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 7476 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 7477 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 7478 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 7479 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7480 7481 /* HV/P7 and later only */ 7482 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7483 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7484 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7485 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7486 #endif 7487 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7488 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7489 7490 /* External PID based load */ 7491 #undef GEN_LDEPX 7492 #define GEN_LDEPX(name, ldop, opc2, opc3) \ 7493 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 7494 0x00000001, PPC_NONE, PPC2_BOOKE206), 7495 7496 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 7497 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 7498 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 7499 #if defined(TARGET_PPC64) 7500 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 7501 #endif 7502 7503 #undef GEN_ST 7504 #undef GEN_STU 7505 #undef GEN_STUX 7506 #undef GEN_STX_E 7507 #undef GEN_STS 7508 #define GEN_ST(name, stop, opc, type) \ 7509 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7510 #define GEN_STU(name, stop, opc, type) \ 7511 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 7512 #define GEN_STUX(name, stop, opc2, opc3, type) \ 7513 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7514 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 7515 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7516 #define GEN_STS(name, stop, op, type) \ 7517 GEN_ST(name, stop, op | 0x20, type) \ 7518 GEN_STU(name, stop, op | 0x21, type) \ 7519 GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 7520 GEN_STX(name, stop, 0x17, op | 0x00, type) 7521 7522 GEN_STS(stb, st8, 0x06, PPC_INTEGER) 7523 GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 7524 GEN_STS(stw, st32, 0x04, PPC_INTEGER) 7525 #if defined(TARGET_PPC64) 7526 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 7527 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 7528 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7529 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7530 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7531 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7532 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 7533 #endif 7534 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 7535 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 7536 7537 #undef GEN_STEPX 7538 #define GEN_STEPX(name, ldop, opc2, opc3) \ 7539 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 7540 0x00000001, PPC_NONE, PPC2_BOOKE206), 7541 7542 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 7543 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 7544 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 7545 #if defined(TARGET_PPC64) 7546 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 7547 #endif 7548 7549 #undef GEN_CRLOGIC 7550 #define GEN_CRLOGIC(name, tcg_op, opc) \ 7551 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 7552 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 7553 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 7554 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 7555 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 7556 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 7557 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 7558 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 7559 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 7560 7561 #undef GEN_MAC_HANDLER 7562 #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7563 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 7564 GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 7565 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 7566 GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 7567 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 7568 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 7569 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 7570 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 7571 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 7572 GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 7573 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 7574 GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 7575 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 7576 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 7577 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 7578 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 7579 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 7580 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 7581 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 7582 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 7583 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 7584 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 7585 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 7586 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 7587 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 7588 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 7589 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 7590 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 7591 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 7592 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 7593 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 7594 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 7595 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 7596 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 7597 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 7598 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 7599 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 7600 GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 7601 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 7602 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 7603 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 7604 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 7605 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 7606 7607 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 7608 PPC_NONE, PPC2_TM), 7609 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 7610 PPC_NONE, PPC2_TM), 7611 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 7612 PPC_NONE, PPC2_TM), 7613 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 7614 PPC_NONE, PPC2_TM), 7615 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 7616 PPC_NONE, PPC2_TM), 7617 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 7618 PPC_NONE, PPC2_TM), 7619 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 7620 PPC_NONE, PPC2_TM), 7621 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 7622 PPC_NONE, PPC2_TM), 7623 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 7624 PPC_NONE, PPC2_TM), 7625 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 7626 PPC_NONE, PPC2_TM), 7627 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 7628 PPC_NONE, PPC2_TM), 7629 7630 #include "translate/fp-ops.c.inc" 7631 7632 #include "translate/vmx-ops.c.inc" 7633 7634 #include "translate/vsx-ops.c.inc" 7635 7636 #include "translate/dfp-ops.c.inc" 7637 7638 #include "translate/spe-ops.c.inc" 7639 }; 7640 7641 #include "helper_regs.h" 7642 #include "translate_init.c.inc" 7643 7644 /*****************************************************************************/ 7645 /* Misc PowerPC helpers */ 7646 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7647 { 7648 #define RGPL 4 7649 #define RFPL 4 7650 7651 PowerPCCPU *cpu = POWERPC_CPU(cs); 7652 CPUPPCState *env = &cpu->env; 7653 int i; 7654 7655 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7656 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7657 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7658 cs->cpu_index); 7659 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7660 "%08x iidx %d didx %d\n", 7661 env->msr, env->spr[SPR_HID0], env->hflags, 7662 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 7663 #if !defined(NO_TIMER_DUMP) 7664 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7665 #if !defined(CONFIG_USER_ONLY) 7666 " DECR " TARGET_FMT_lu 7667 #endif 7668 "\n", 7669 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7670 #if !defined(CONFIG_USER_ONLY) 7671 , cpu_ppc_load_decr(env) 7672 #endif 7673 ); 7674 #endif 7675 for (i = 0; i < 32; i++) { 7676 if ((i & (RGPL - 1)) == 0) { 7677 qemu_fprintf(f, "GPR%02d", i); 7678 } 7679 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7680 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7681 qemu_fprintf(f, "\n"); 7682 } 7683 } 7684 qemu_fprintf(f, "CR "); 7685 for (i = 0; i < 8; i++) 7686 qemu_fprintf(f, "%01x", env->crf[i]); 7687 qemu_fprintf(f, " ["); 7688 for (i = 0; i < 8; i++) { 7689 char a = '-'; 7690 if (env->crf[i] & 0x08) { 7691 a = 'L'; 7692 } else if (env->crf[i] & 0x04) { 7693 a = 'G'; 7694 } else if (env->crf[i] & 0x02) { 7695 a = 'E'; 7696 } 7697 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7698 } 7699 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7700 env->reserve_addr); 7701 7702 if (flags & CPU_DUMP_FPU) { 7703 for (i = 0; i < 32; i++) { 7704 if ((i & (RFPL - 1)) == 0) { 7705 qemu_fprintf(f, "FPR%02d", i); 7706 } 7707 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7708 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7709 qemu_fprintf(f, "\n"); 7710 } 7711 } 7712 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7713 } 7714 7715 #if !defined(CONFIG_USER_ONLY) 7716 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7717 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7718 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7719 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7720 7721 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7722 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7723 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7724 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7725 7726 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7727 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7728 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7729 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7730 7731 #if defined(TARGET_PPC64) 7732 if (env->excp_model == POWERPC_EXCP_POWER7 || 7733 env->excp_model == POWERPC_EXCP_POWER8 || 7734 env->excp_model == POWERPC_EXCP_POWER9 || 7735 env->excp_model == POWERPC_EXCP_POWER10) { 7736 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7737 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7738 } 7739 #endif 7740 if (env->excp_model == POWERPC_EXCP_BOOKE) { 7741 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7742 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7743 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7744 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7745 7746 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7747 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7748 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7749 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7750 7751 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7752 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7753 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7754 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7755 7756 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7757 " EPR " TARGET_FMT_lx "\n", 7758 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7759 env->spr[SPR_BOOKE_EPR]); 7760 7761 /* FSL-specific */ 7762 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7763 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7764 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7765 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7766 7767 /* 7768 * IVORs are left out as they are large and do not change often -- 7769 * they can be read with "p $ivor0", "p $ivor1", etc. 7770 */ 7771 } 7772 7773 #if defined(TARGET_PPC64) 7774 if (env->flags & POWERPC_FLAG_CFAR) { 7775 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7776 } 7777 #endif 7778 7779 if (env->spr_cb[SPR_LPCR].name) { 7780 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7781 } 7782 7783 switch (env->mmu_model) { 7784 case POWERPC_MMU_32B: 7785 case POWERPC_MMU_601: 7786 case POWERPC_MMU_SOFT_6xx: 7787 case POWERPC_MMU_SOFT_74xx: 7788 #if defined(TARGET_PPC64) 7789 case POWERPC_MMU_64B: 7790 case POWERPC_MMU_2_03: 7791 case POWERPC_MMU_2_06: 7792 case POWERPC_MMU_2_07: 7793 case POWERPC_MMU_3_00: 7794 #endif 7795 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7796 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7797 } 7798 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 7799 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 7800 } 7801 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7802 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7803 break; 7804 case POWERPC_MMU_BOOKE206: 7805 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7806 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7807 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7808 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7809 7810 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7811 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7812 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7813 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7814 7815 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7816 " TLB1CFG " TARGET_FMT_lx "\n", 7817 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7818 env->spr[SPR_BOOKE_TLB1CFG]); 7819 break; 7820 default: 7821 break; 7822 } 7823 #endif 7824 7825 #undef RGPL 7826 #undef RFPL 7827 } 7828 7829 /*****************************************************************************/ 7830 /* Opcode types */ 7831 enum { 7832 PPC_DIRECT = 0, /* Opcode routine */ 7833 PPC_INDIRECT = 1, /* Indirect opcode table */ 7834 }; 7835 7836 #define PPC_OPCODE_MASK 0x3 7837 7838 static inline int is_indirect_opcode(void *handler) 7839 { 7840 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 7841 } 7842 7843 static inline opc_handler_t **ind_table(void *handler) 7844 { 7845 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 7846 } 7847 7848 /* Instruction table creation */ 7849 /* Opcodes tables creation */ 7850 static void fill_new_table(opc_handler_t **table, int len) 7851 { 7852 int i; 7853 7854 for (i = 0; i < len; i++) { 7855 table[i] = &invalid_handler; 7856 } 7857 } 7858 7859 static int create_new_table(opc_handler_t **table, unsigned char idx) 7860 { 7861 opc_handler_t **tmp; 7862 7863 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 7864 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 7865 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 7866 7867 return 0; 7868 } 7869 7870 static int insert_in_table(opc_handler_t **table, unsigned char idx, 7871 opc_handler_t *handler) 7872 { 7873 if (table[idx] != &invalid_handler) { 7874 return -1; 7875 } 7876 table[idx] = handler; 7877 7878 return 0; 7879 } 7880 7881 static int register_direct_insn(opc_handler_t **ppc_opcodes, 7882 unsigned char idx, opc_handler_t *handler) 7883 { 7884 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 7885 printf("*** ERROR: opcode %02x already assigned in main " 7886 "opcode table\n", idx); 7887 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 7888 printf(" Registered handler '%s' - new handler '%s'\n", 7889 ppc_opcodes[idx]->oname, handler->oname); 7890 #endif 7891 return -1; 7892 } 7893 7894 return 0; 7895 } 7896 7897 static int register_ind_in_table(opc_handler_t **table, 7898 unsigned char idx1, unsigned char idx2, 7899 opc_handler_t *handler) 7900 { 7901 if (table[idx1] == &invalid_handler) { 7902 if (create_new_table(table, idx1) < 0) { 7903 printf("*** ERROR: unable to create indirect table " 7904 "idx=%02x\n", idx1); 7905 return -1; 7906 } 7907 } else { 7908 if (!is_indirect_opcode(table[idx1])) { 7909 printf("*** ERROR: idx %02x already assigned to a direct " 7910 "opcode\n", idx1); 7911 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 7912 printf(" Registered handler '%s' - new handler '%s'\n", 7913 ind_table(table[idx1])[idx2]->oname, handler->oname); 7914 #endif 7915 return -1; 7916 } 7917 } 7918 if (handler != NULL && 7919 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 7920 printf("*** ERROR: opcode %02x already assigned in " 7921 "opcode table %02x\n", idx2, idx1); 7922 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 7923 printf(" Registered handler '%s' - new handler '%s'\n", 7924 ind_table(table[idx1])[idx2]->oname, handler->oname); 7925 #endif 7926 return -1; 7927 } 7928 7929 return 0; 7930 } 7931 7932 static int register_ind_insn(opc_handler_t **ppc_opcodes, 7933 unsigned char idx1, unsigned char idx2, 7934 opc_handler_t *handler) 7935 { 7936 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 7937 } 7938 7939 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 7940 unsigned char idx1, unsigned char idx2, 7941 unsigned char idx3, opc_handler_t *handler) 7942 { 7943 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 7944 printf("*** ERROR: unable to join indirect table idx " 7945 "[%02x-%02x]\n", idx1, idx2); 7946 return -1; 7947 } 7948 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 7949 handler) < 0) { 7950 printf("*** ERROR: unable to insert opcode " 7951 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 7952 return -1; 7953 } 7954 7955 return 0; 7956 } 7957 7958 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 7959 unsigned char idx1, unsigned char idx2, 7960 unsigned char idx3, unsigned char idx4, 7961 opc_handler_t *handler) 7962 { 7963 opc_handler_t **table; 7964 7965 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 7966 printf("*** ERROR: unable to join indirect table idx " 7967 "[%02x-%02x]\n", idx1, idx2); 7968 return -1; 7969 } 7970 table = ind_table(ppc_opcodes[idx1]); 7971 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 7972 printf("*** ERROR: unable to join 2nd-level indirect table idx " 7973 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 7974 return -1; 7975 } 7976 table = ind_table(table[idx2]); 7977 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 7978 printf("*** ERROR: unable to insert opcode " 7979 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 7980 return -1; 7981 } 7982 return 0; 7983 } 7984 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 7985 { 7986 if (insn->opc2 != 0xFF) { 7987 if (insn->opc3 != 0xFF) { 7988 if (insn->opc4 != 0xFF) { 7989 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7990 insn->opc3, insn->opc4, 7991 &insn->handler) < 0) { 7992 return -1; 7993 } 7994 } else { 7995 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 7996 insn->opc3, &insn->handler) < 0) { 7997 return -1; 7998 } 7999 } 8000 } else { 8001 if (register_ind_insn(ppc_opcodes, insn->opc1, 8002 insn->opc2, &insn->handler) < 0) { 8003 return -1; 8004 } 8005 } 8006 } else { 8007 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 8008 return -1; 8009 } 8010 } 8011 8012 return 0; 8013 } 8014 8015 static int test_opcode_table(opc_handler_t **table, int len) 8016 { 8017 int i, count, tmp; 8018 8019 for (i = 0, count = 0; i < len; i++) { 8020 /* Consistency fixup */ 8021 if (table[i] == NULL) { 8022 table[i] = &invalid_handler; 8023 } 8024 if (table[i] != &invalid_handler) { 8025 if (is_indirect_opcode(table[i])) { 8026 tmp = test_opcode_table(ind_table(table[i]), 8027 PPC_CPU_INDIRECT_OPCODES_LEN); 8028 if (tmp == 0) { 8029 free(table[i]); 8030 table[i] = &invalid_handler; 8031 } else { 8032 count++; 8033 } 8034 } else { 8035 count++; 8036 } 8037 } 8038 } 8039 8040 return count; 8041 } 8042 8043 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 8044 { 8045 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 8046 printf("*** WARNING: no opcode defined !\n"); 8047 } 8048 } 8049 8050 /*****************************************************************************/ 8051 void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 8052 { 8053 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8054 opcode_t *opc; 8055 8056 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 8057 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 8058 if (((opc->handler.type & pcc->insns_flags) != 0) || 8059 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 8060 if (register_insn(cpu->opcodes, opc) < 0) { 8061 error_setg(errp, "ERROR initializing PowerPC instruction " 8062 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 8063 opc->opc3); 8064 return; 8065 } 8066 } 8067 } 8068 fix_opcode_tables(cpu->opcodes); 8069 fflush(stdout); 8070 fflush(stderr); 8071 } 8072 8073 void destroy_ppc_opcodes(PowerPCCPU *cpu) 8074 { 8075 opc_handler_t **table, **table_2; 8076 int i, j, k; 8077 8078 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 8079 if (cpu->opcodes[i] == &invalid_handler) { 8080 continue; 8081 } 8082 if (is_indirect_opcode(cpu->opcodes[i])) { 8083 table = ind_table(cpu->opcodes[i]); 8084 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 8085 if (table[j] == &invalid_handler) { 8086 continue; 8087 } 8088 if (is_indirect_opcode(table[j])) { 8089 table_2 = ind_table(table[j]); 8090 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 8091 if (table_2[k] != &invalid_handler && 8092 is_indirect_opcode(table_2[k])) { 8093 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 8094 ~PPC_INDIRECT)); 8095 } 8096 } 8097 g_free((opc_handler_t *)((uintptr_t)table[j] & 8098 ~PPC_INDIRECT)); 8099 } 8100 } 8101 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 8102 ~PPC_INDIRECT)); 8103 } 8104 } 8105 } 8106 8107 #if defined(PPC_DUMP_CPU) 8108 static void dump_ppc_insns(CPUPPCState *env) 8109 { 8110 opc_handler_t **table, *handler; 8111 const char *p, *q; 8112 uint8_t opc1, opc2, opc3, opc4; 8113 8114 printf("Instructions set:\n"); 8115 /* opc1 is 6 bits long */ 8116 for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) { 8117 table = env->opcodes; 8118 handler = table[opc1]; 8119 if (is_indirect_opcode(handler)) { 8120 /* opc2 is 5 bits long */ 8121 for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) { 8122 table = env->opcodes; 8123 handler = env->opcodes[opc1]; 8124 table = ind_table(handler); 8125 handler = table[opc2]; 8126 if (is_indirect_opcode(handler)) { 8127 table = ind_table(handler); 8128 /* opc3 is 5 bits long */ 8129 for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN; 8130 opc3++) { 8131 handler = table[opc3]; 8132 if (is_indirect_opcode(handler)) { 8133 table = ind_table(handler); 8134 /* opc4 is 5 bits long */ 8135 for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN; 8136 opc4++) { 8137 handler = table[opc4]; 8138 if (handler->handler != &gen_invalid) { 8139 printf("INSN: %02x %02x %02x %02x -- " 8140 "(%02d %04d %02d) : %s\n", 8141 opc1, opc2, opc3, opc4, 8142 opc1, (opc3 << 5) | opc2, opc4, 8143 handler->oname); 8144 } 8145 } 8146 } else { 8147 if (handler->handler != &gen_invalid) { 8148 /* Special hack to properly dump SPE insns */ 8149 p = strchr(handler->oname, '_'); 8150 if (p == NULL) { 8151 printf("INSN: %02x %02x %02x (%02d %04d) : " 8152 "%s\n", 8153 opc1, opc2, opc3, opc1, 8154 (opc3 << 5) | opc2, 8155 handler->oname); 8156 } else { 8157 q = "speundef"; 8158 if ((p - handler->oname) != strlen(q) 8159 || (memcmp(handler->oname, q, strlen(q)) 8160 != 0)) { 8161 /* First instruction */ 8162 printf("INSN: %02x %02x %02x" 8163 "(%02d %04d) : %.*s\n", 8164 opc1, opc2 << 1, opc3, opc1, 8165 (opc3 << 6) | (opc2 << 1), 8166 (int)(p - handler->oname), 8167 handler->oname); 8168 } 8169 if (strcmp(p + 1, q) != 0) { 8170 /* Second instruction */ 8171 printf("INSN: %02x %02x %02x " 8172 "(%02d %04d) : %s\n", opc1, 8173 (opc2 << 1) | 1, opc3, opc1, 8174 (opc3 << 6) | (opc2 << 1) | 1, 8175 p + 1); 8176 } 8177 } 8178 } 8179 } 8180 } 8181 } else { 8182 if (handler->handler != &gen_invalid) { 8183 printf("INSN: %02x %02x -- (%02d %04d) : %s\n", 8184 opc1, opc2, opc1, opc2, handler->oname); 8185 } 8186 } 8187 } 8188 } else { 8189 if (handler->handler != &gen_invalid) { 8190 printf("INSN: %02x -- -- (%02d ----) : %s\n", 8191 opc1, opc1, handler->oname); 8192 } 8193 } 8194 } 8195 } 8196 #endif 8197 int ppc_fixup_cpu(PowerPCCPU *cpu) 8198 { 8199 CPUPPCState *env = &cpu->env; 8200 8201 /* 8202 * TCG doesn't (yet) emulate some groups of instructions that are 8203 * implemented on some otherwise supported CPUs (e.g. VSX and 8204 * decimal floating point instructions on POWER7). We remove 8205 * unsupported instruction groups from the cpu state's instruction 8206 * masks and hope the guest can cope. For at least the pseries 8207 * machine, the unavailability of these instructions can be 8208 * advertised to the guest via the device tree. 8209 */ 8210 if ((env->insns_flags & ~PPC_TCG_INSNS) 8211 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 8212 warn_report("Disabling some instructions which are not " 8213 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 8214 env->insns_flags & ~PPC_TCG_INSNS, 8215 env->insns_flags2 & ~PPC_TCG_INSNS2); 8216 } 8217 env->insns_flags &= PPC_TCG_INSNS; 8218 env->insns_flags2 &= PPC_TCG_INSNS2; 8219 return 0; 8220 } 8221 8222 8223 void ppc_cpu_dump_statistics(CPUState *cs, int flags) 8224 { 8225 #if defined(DO_PPC_STATISTICS) 8226 PowerPCCPU *cpu = POWERPC_CPU(cs); 8227 opc_handler_t **t1, **t2, **t3, *handler; 8228 int op1, op2, op3; 8229 8230 t1 = cpu->env.opcodes; 8231 for (op1 = 0; op1 < 64; op1++) { 8232 handler = t1[op1]; 8233 if (is_indirect_opcode(handler)) { 8234 t2 = ind_table(handler); 8235 for (op2 = 0; op2 < 32; op2++) { 8236 handler = t2[op2]; 8237 if (is_indirect_opcode(handler)) { 8238 t3 = ind_table(handler); 8239 for (op3 = 0; op3 < 32; op3++) { 8240 handler = t3[op3]; 8241 if (handler->count == 0) { 8242 continue; 8243 } 8244 qemu_printf("%02x %02x %02x (%02x %04d) %16s: " 8245 "%016" PRIx64 " %" PRId64 "\n", 8246 op1, op2, op3, op1, (op3 << 5) | op2, 8247 handler->oname, 8248 handler->count, handler->count); 8249 } 8250 } else { 8251 if (handler->count == 0) { 8252 continue; 8253 } 8254 qemu_printf("%02x %02x (%02x %04d) %16s: " 8255 "%016" PRIx64 " %" PRId64 "\n", 8256 op1, op2, op1, op2, handler->oname, 8257 handler->count, handler->count); 8258 } 8259 } 8260 } else { 8261 if (handler->count == 0) { 8262 continue; 8263 } 8264 qemu_printf("%02x (%02x ) %16s: %016" PRIx64 8265 " %" PRId64 "\n", 8266 op1, op1, handler->oname, 8267 handler->count, handler->count); 8268 } 8269 } 8270 #endif 8271 } 8272 8273 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 8274 { 8275 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8276 CPUPPCState *env = cs->env_ptr; 8277 uint32_t hflags = ctx->base.tb->flags; 8278 int bound; 8279 8280 ctx->exception = POWERPC_EXCP_NONE; 8281 ctx->spr_cb = env->spr_cb; 8282 ctx->pr = (hflags >> HFLAGS_PR) & 1; 8283 ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 8284 ctx->dr = (hflags >> HFLAGS_DR) & 1; 8285 ctx->hv = (hflags >> HFLAGS_HV) & 1; 8286 ctx->insns_flags = env->insns_flags; 8287 ctx->insns_flags2 = env->insns_flags2; 8288 ctx->access_type = -1; 8289 ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 8290 ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 8291 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 8292 ctx->flags = env->flags; 8293 #if defined(TARGET_PPC64) 8294 ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 8295 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 8296 #endif 8297 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 8298 || env->mmu_model == POWERPC_MMU_601 8299 || env->mmu_model & POWERPC_MMU_64; 8300 8301 ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 8302 ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 8303 ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 8304 ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 8305 ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 8306 ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 8307 8308 ctx->singlestep_enabled = 0; 8309 if ((hflags >> HFLAGS_SE) & 1) { 8310 ctx->singlestep_enabled |= CPU_SINGLE_STEP; 8311 } 8312 if ((hflags >> HFLAGS_BE) & 1) { 8313 ctx->singlestep_enabled |= CPU_BRANCH_STEP; 8314 } 8315 if (unlikely(ctx->base.singlestep_enabled)) { 8316 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 8317 } 8318 8319 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 8320 ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 8321 } 8322 8323 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 8324 { 8325 } 8326 8327 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 8328 { 8329 tcg_gen_insn_start(dcbase->pc_next); 8330 } 8331 8332 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 8333 const CPUBreakpoint *bp) 8334 { 8335 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8336 8337 gen_debug_exception(ctx); 8338 dcbase->is_jmp = DISAS_NORETURN; 8339 /* 8340 * The address covered by the breakpoint must be included in 8341 * [tb->pc, tb->pc + tb->size) in order to for it to be properly 8342 * cleared -- thus we increment the PC here so that the logic 8343 * setting tb->size below does the right thing. 8344 */ 8345 ctx->base.pc_next += 4; 8346 return true; 8347 } 8348 8349 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 8350 { 8351 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8352 PowerPCCPU *cpu = POWERPC_CPU(cs); 8353 CPUPPCState *env = cs->env_ptr; 8354 opc_handler_t **table, *handler; 8355 8356 LOG_DISAS("----------------\n"); 8357 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 8358 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 8359 8360 ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next, 8361 need_byteswap(ctx)); 8362 8363 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 8364 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), 8365 opc3(ctx->opcode), opc4(ctx->opcode), 8366 ctx->le_mode ? "little" : "big"); 8367 ctx->base.pc_next += 4; 8368 table = cpu->opcodes; 8369 handler = table[opc1(ctx->opcode)]; 8370 if (is_indirect_opcode(handler)) { 8371 table = ind_table(handler); 8372 handler = table[opc2(ctx->opcode)]; 8373 if (is_indirect_opcode(handler)) { 8374 table = ind_table(handler); 8375 handler = table[opc3(ctx->opcode)]; 8376 if (is_indirect_opcode(handler)) { 8377 table = ind_table(handler); 8378 handler = table[opc4(ctx->opcode)]; 8379 } 8380 } 8381 } 8382 /* Is opcode *REALLY* valid ? */ 8383 if (unlikely(handler->handler == &gen_invalid)) { 8384 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 8385 "%02x - %02x - %02x - %02x (%08x) " 8386 TARGET_FMT_lx " %d\n", 8387 opc1(ctx->opcode), opc2(ctx->opcode), 8388 opc3(ctx->opcode), opc4(ctx->opcode), 8389 ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); 8390 } else { 8391 uint32_t inval; 8392 8393 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 8394 && Rc(ctx->opcode))) { 8395 inval = handler->inval2; 8396 } else { 8397 inval = handler->inval1; 8398 } 8399 8400 if (unlikely((ctx->opcode & inval) != 0)) { 8401 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 8402 "%02x - %02x - %02x - %02x (%08x) " 8403 TARGET_FMT_lx "\n", ctx->opcode & inval, 8404 opc1(ctx->opcode), opc2(ctx->opcode), 8405 opc3(ctx->opcode), opc4(ctx->opcode), 8406 ctx->opcode, ctx->base.pc_next - 4); 8407 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 8408 ctx->base.is_jmp = DISAS_NORETURN; 8409 return; 8410 } 8411 } 8412 (*(handler->handler))(ctx); 8413 #if defined(DO_PPC_STATISTICS) 8414 handler->count++; 8415 #endif 8416 /* Check trace mode exceptions */ 8417 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 8418 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 8419 ctx->exception != POWERPC_SYSCALL && 8420 ctx->exception != POWERPC_EXCP_TRAP && 8421 ctx->exception != POWERPC_EXCP_BRANCH)) { 8422 uint32_t excp = gen_prep_dbgex(ctx); 8423 gen_exception_nip(ctx, excp, ctx->base.pc_next); 8424 } 8425 8426 if (tcg_check_temp_count()) { 8427 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 8428 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 8429 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 8430 } 8431 8432 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? 8433 DISAS_NEXT : DISAS_NORETURN; 8434 } 8435 8436 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 8437 { 8438 DisasContext *ctx = container_of(dcbase, DisasContext, base); 8439 8440 if (ctx->exception == POWERPC_EXCP_NONE) { 8441 gen_goto_tb(ctx, 0, ctx->base.pc_next); 8442 } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 8443 if (unlikely(ctx->base.singlestep_enabled)) { 8444 gen_debug_exception(ctx); 8445 } 8446 /* Generate the return instruction */ 8447 tcg_gen_exit_tb(NULL, 0); 8448 } 8449 } 8450 8451 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 8452 { 8453 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 8454 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 8455 } 8456 8457 static const TranslatorOps ppc_tr_ops = { 8458 .init_disas_context = ppc_tr_init_disas_context, 8459 .tb_start = ppc_tr_tb_start, 8460 .insn_start = ppc_tr_insn_start, 8461 .breakpoint_check = ppc_tr_breakpoint_check, 8462 .translate_insn = ppc_tr_translate_insn, 8463 .tb_stop = ppc_tr_tb_stop, 8464 .disas_log = ppc_tr_disas_log, 8465 }; 8466 8467 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 8468 { 8469 DisasContext ctx; 8470 8471 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 8472 } 8473 8474 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 8475 target_ulong *data) 8476 { 8477 env->nip = data[0]; 8478 } 8479