xref: /qemu/target/ppc/translate.c (revision ef291226)
1 /*
2  *  PowerPC emulation for qemu: main translation routines.
3  *
4  *  Copyright (c) 2003-2007 Jocelyn Mayer
5  *  Copyright (C) 2011 Freescale Semiconductor, Inc.
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg-op.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
29 
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32 
33 #include "trace-tcg.h"
34 #include "exec/log.h"
35 
36 
37 #define CPU_SINGLE_STEP 0x1
38 #define CPU_BRANCH_STEP 0x2
39 #define GDBSTUB_SINGLE_STEP 0x4
40 
41 /* Include definitions for instructions classes and implementations flags */
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44 
45 #ifdef PPC_DEBUG_DISAS
46 #  define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 #  define LOG_DISAS(...) do { } while (0)
49 #endif
50 /*****************************************************************************/
51 /* Code translation helpers                                                  */
52 
53 /* global register indexes */
54 static TCGv_env cpu_env;
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56     + 10*4 + 22*5 /* SPE GPRh */
57     + 10*4 + 22*5 /* FPR */
58     + 2*(10*6 + 22*7) /* AVRh, AVRl */
59     + 10*5 + 22*6 /* VSR */
60     + 8*5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 static TCGv cpu_gprh[32];
63 static TCGv_i64 cpu_fpr[32];
64 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
65 static TCGv_i64 cpu_vsr[32];
66 static TCGv_i32 cpu_crf[8];
67 static TCGv cpu_nip;
68 static TCGv cpu_msr;
69 static TCGv cpu_ctr;
70 static TCGv cpu_lr;
71 #if defined(TARGET_PPC64)
72 static TCGv cpu_cfar;
73 #endif
74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
75 static TCGv cpu_reserve;
76 static TCGv cpu_fpscr;
77 static TCGv_i32 cpu_access_type;
78 
79 #include "exec/gen-icount.h"
80 
81 void ppc_translate_init(void)
82 {
83     int i;
84     char* p;
85     size_t cpu_reg_names_size;
86     static int done_init = 0;
87 
88     if (done_init)
89         return;
90 
91     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
92     tcg_ctx.tcg_env = cpu_env;
93 
94     p = cpu_reg_names;
95     cpu_reg_names_size = sizeof(cpu_reg_names);
96 
97     for (i = 0; i < 8; i++) {
98         snprintf(p, cpu_reg_names_size, "crf%d", i);
99         cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
100                                             offsetof(CPUPPCState, crf[i]), p);
101         p += 5;
102         cpu_reg_names_size -= 5;
103     }
104 
105     for (i = 0; i < 32; i++) {
106         snprintf(p, cpu_reg_names_size, "r%d", i);
107         cpu_gpr[i] = tcg_global_mem_new(cpu_env,
108                                         offsetof(CPUPPCState, gpr[i]), p);
109         p += (i < 10) ? 3 : 4;
110         cpu_reg_names_size -= (i < 10) ? 3 : 4;
111         snprintf(p, cpu_reg_names_size, "r%dH", i);
112         cpu_gprh[i] = tcg_global_mem_new(cpu_env,
113                                          offsetof(CPUPPCState, gprh[i]), p);
114         p += (i < 10) ? 4 : 5;
115         cpu_reg_names_size -= (i < 10) ? 4 : 5;
116 
117         snprintf(p, cpu_reg_names_size, "fp%d", i);
118         cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
119                                             offsetof(CPUPPCState, fpr[i]), p);
120         p += (i < 10) ? 4 : 5;
121         cpu_reg_names_size -= (i < 10) ? 4 : 5;
122 
123         snprintf(p, cpu_reg_names_size, "avr%dH", i);
124 #ifdef HOST_WORDS_BIGENDIAN
125         cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
126                                              offsetof(CPUPPCState, avr[i].u64[0]), p);
127 #else
128         cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
129                                              offsetof(CPUPPCState, avr[i].u64[1]), p);
130 #endif
131         p += (i < 10) ? 6 : 7;
132         cpu_reg_names_size -= (i < 10) ? 6 : 7;
133 
134         snprintf(p, cpu_reg_names_size, "avr%dL", i);
135 #ifdef HOST_WORDS_BIGENDIAN
136         cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
137                                              offsetof(CPUPPCState, avr[i].u64[1]), p);
138 #else
139         cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
140                                              offsetof(CPUPPCState, avr[i].u64[0]), p);
141 #endif
142         p += (i < 10) ? 6 : 7;
143         cpu_reg_names_size -= (i < 10) ? 6 : 7;
144         snprintf(p, cpu_reg_names_size, "vsr%d", i);
145         cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
146                                             offsetof(CPUPPCState, vsr[i]), p);
147         p += (i < 10) ? 5 : 6;
148         cpu_reg_names_size -= (i < 10) ? 5 : 6;
149     }
150 
151     cpu_nip = tcg_global_mem_new(cpu_env,
152                                  offsetof(CPUPPCState, nip), "nip");
153 
154     cpu_msr = tcg_global_mem_new(cpu_env,
155                                  offsetof(CPUPPCState, msr), "msr");
156 
157     cpu_ctr = tcg_global_mem_new(cpu_env,
158                                  offsetof(CPUPPCState, ctr), "ctr");
159 
160     cpu_lr = tcg_global_mem_new(cpu_env,
161                                 offsetof(CPUPPCState, lr), "lr");
162 
163 #if defined(TARGET_PPC64)
164     cpu_cfar = tcg_global_mem_new(cpu_env,
165                                   offsetof(CPUPPCState, cfar), "cfar");
166 #endif
167 
168     cpu_xer = tcg_global_mem_new(cpu_env,
169                                  offsetof(CPUPPCState, xer), "xer");
170     cpu_so = tcg_global_mem_new(cpu_env,
171                                 offsetof(CPUPPCState, so), "SO");
172     cpu_ov = tcg_global_mem_new(cpu_env,
173                                 offsetof(CPUPPCState, ov), "OV");
174     cpu_ca = tcg_global_mem_new(cpu_env,
175                                 offsetof(CPUPPCState, ca), "CA");
176 
177     cpu_reserve = tcg_global_mem_new(cpu_env,
178                                      offsetof(CPUPPCState, reserve_addr),
179                                      "reserve_addr");
180 
181     cpu_fpscr = tcg_global_mem_new(cpu_env,
182                                    offsetof(CPUPPCState, fpscr), "fpscr");
183 
184     cpu_access_type = tcg_global_mem_new_i32(cpu_env,
185                                              offsetof(CPUPPCState, access_type), "access_type");
186 
187     done_init = 1;
188 }
189 
190 /* internal defines */
191 struct DisasContext {
192     struct TranslationBlock *tb;
193     target_ulong nip;
194     uint32_t opcode;
195     uint32_t exception;
196     /* Routine used to access memory */
197     bool pr, hv, dr, le_mode;
198     bool lazy_tlb_flush;
199     bool need_access_type;
200     int mem_idx;
201     int access_type;
202     /* Translation flags */
203     TCGMemOp default_tcg_memop_mask;
204 #if defined(TARGET_PPC64)
205     bool sf_mode;
206     bool has_cfar;
207 #endif
208     bool fpu_enabled;
209     bool altivec_enabled;
210     bool vsx_enabled;
211     bool spe_enabled;
212     bool tm_enabled;
213     ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
214     int singlestep_enabled;
215     uint64_t insns_flags;
216     uint64_t insns_flags2;
217 };
218 
219 /* Return true iff byteswap is needed in a scalar memop */
220 static inline bool need_byteswap(const DisasContext *ctx)
221 {
222 #if defined(TARGET_WORDS_BIGENDIAN)
223      return ctx->le_mode;
224 #else
225      return !ctx->le_mode;
226 #endif
227 }
228 
229 /* True when active word size < size of target_long.  */
230 #ifdef TARGET_PPC64
231 # define NARROW_MODE(C)  (!(C)->sf_mode)
232 #else
233 # define NARROW_MODE(C)  0
234 #endif
235 
236 struct opc_handler_t {
237     /* invalid bits for instruction 1 (Rc(opcode) == 0) */
238     uint32_t inval1;
239     /* invalid bits for instruction 2 (Rc(opcode) == 1) */
240     uint32_t inval2;
241     /* instruction type */
242     uint64_t type;
243     /* extended instruction type */
244     uint64_t type2;
245     /* handler */
246     void (*handler)(DisasContext *ctx);
247 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
248     const char *oname;
249 #endif
250 #if defined(DO_PPC_STATISTICS)
251     uint64_t count;
252 #endif
253 };
254 
255 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
256 {
257     if (ctx->need_access_type && ctx->access_type != access_type) {
258         tcg_gen_movi_i32(cpu_access_type, access_type);
259         ctx->access_type = access_type;
260     }
261 }
262 
263 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
264 {
265     if (NARROW_MODE(ctx)) {
266         nip = (uint32_t)nip;
267     }
268     tcg_gen_movi_tl(cpu_nip, nip);
269 }
270 
271 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
272 {
273     TCGv_i32 t0, t1;
274 
275     /* These are all synchronous exceptions, we set the PC back to
276      * the faulting instruction
277      */
278     if (ctx->exception == POWERPC_EXCP_NONE) {
279         gen_update_nip(ctx, ctx->nip - 4);
280     }
281     t0 = tcg_const_i32(excp);
282     t1 = tcg_const_i32(error);
283     gen_helper_raise_exception_err(cpu_env, t0, t1);
284     tcg_temp_free_i32(t0);
285     tcg_temp_free_i32(t1);
286     ctx->exception = (excp);
287 }
288 
289 static void gen_exception(DisasContext *ctx, uint32_t excp)
290 {
291     TCGv_i32 t0;
292 
293     /* These are all synchronous exceptions, we set the PC back to
294      * the faulting instruction
295      */
296     if (ctx->exception == POWERPC_EXCP_NONE) {
297         gen_update_nip(ctx, ctx->nip - 4);
298     }
299     t0 = tcg_const_i32(excp);
300     gen_helper_raise_exception(cpu_env, t0);
301     tcg_temp_free_i32(t0);
302     ctx->exception = (excp);
303 }
304 
305 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
306                               target_ulong nip)
307 {
308     TCGv_i32 t0;
309 
310     gen_update_nip(ctx, nip);
311     t0 = tcg_const_i32(excp);
312     gen_helper_raise_exception(cpu_env, t0);
313     tcg_temp_free_i32(t0);
314     ctx->exception = (excp);
315 }
316 
317 static void gen_debug_exception(DisasContext *ctx)
318 {
319     TCGv_i32 t0;
320 
321     /* These are all synchronous exceptions, we set the PC back to
322      * the faulting instruction
323      */
324     if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
325         (ctx->exception != POWERPC_EXCP_SYNC)) {
326         gen_update_nip(ctx, ctx->nip);
327     }
328     t0 = tcg_const_i32(EXCP_DEBUG);
329     gen_helper_raise_exception(cpu_env, t0);
330     tcg_temp_free_i32(t0);
331 }
332 
333 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
334 {
335     /* Will be converted to program check if needed */
336     gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
337 }
338 
339 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
340 {
341     gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
342 }
343 
344 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
345 {
346     /* Will be converted to program check if needed */
347     gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
348 }
349 
350 /* Stop translation */
351 static inline void gen_stop_exception(DisasContext *ctx)
352 {
353     gen_update_nip(ctx, ctx->nip);
354     ctx->exception = POWERPC_EXCP_STOP;
355 }
356 
357 #ifndef CONFIG_USER_ONLY
358 /* No need to update nip here, as execution flow will change */
359 static inline void gen_sync_exception(DisasContext *ctx)
360 {
361     ctx->exception = POWERPC_EXCP_SYNC;
362 }
363 #endif
364 
365 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
366 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
367 
368 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2)             \
369 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
370 
371 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
372 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
373 
374 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2)      \
375 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
376 
377 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2)     \
378 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
379 
380 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
381 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
382 
383 typedef struct opcode_t {
384     unsigned char opc1, opc2, opc3, opc4;
385 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
386     unsigned char pad[4];
387 #endif
388     opc_handler_t handler;
389     const char *oname;
390 } opcode_t;
391 
392 /* Helpers for priv. check */
393 #define GEN_PRIV                                                \
394     do {                                                        \
395         gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
396     } while (0)
397 
398 #if defined(CONFIG_USER_ONLY)
399 #define CHK_HV GEN_PRIV
400 #define CHK_SV GEN_PRIV
401 #define CHK_HVRM GEN_PRIV
402 #else
403 #define CHK_HV                                                          \
404     do {                                                                \
405         if (unlikely(ctx->pr || !ctx->hv)) {                            \
406             GEN_PRIV;                                                   \
407         }                                                               \
408     } while (0)
409 #define CHK_SV                   \
410     do {                         \
411         if (unlikely(ctx->pr)) { \
412             GEN_PRIV;            \
413         }                        \
414     } while (0)
415 #define CHK_HVRM                                            \
416     do {                                                    \
417         if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) {     \
418             GEN_PRIV;                                       \
419         }                                                   \
420     } while (0)
421 #endif
422 
423 #define CHK_NONE
424 
425 /*****************************************************************************/
426 /* PowerPC instructions table                                                */
427 
428 #if defined(DO_PPC_STATISTICS)
429 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2)                    \
430 {                                                                             \
431     .opc1 = op1,                                                              \
432     .opc2 = op2,                                                              \
433     .opc3 = op3,                                                              \
434     .opc4 = 0xff,                                                             \
435     .handler = {                                                              \
436         .inval1  = invl,                                                      \
437         .type = _typ,                                                         \
438         .type2 = _typ2,                                                       \
439         .handler = &gen_##name,                                               \
440         .oname = stringify(name),                                             \
441     },                                                                        \
442     .oname = stringify(name),                                                 \
443 }
444 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2)       \
445 {                                                                             \
446     .opc1 = op1,                                                              \
447     .opc2 = op2,                                                              \
448     .opc3 = op3,                                                              \
449     .opc4 = 0xff,                                                             \
450     .handler = {                                                              \
451         .inval1  = invl1,                                                     \
452         .inval2  = invl2,                                                     \
453         .type = _typ,                                                         \
454         .type2 = _typ2,                                                       \
455         .handler = &gen_##name,                                               \
456         .oname = stringify(name),                                             \
457     },                                                                        \
458     .oname = stringify(name),                                                 \
459 }
460 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2)             \
461 {                                                                             \
462     .opc1 = op1,                                                              \
463     .opc2 = op2,                                                              \
464     .opc3 = op3,                                                              \
465     .opc4 = 0xff,                                                             \
466     .handler = {                                                              \
467         .inval1  = invl,                                                      \
468         .type = _typ,                                                         \
469         .type2 = _typ2,                                                       \
470         .handler = &gen_##name,                                               \
471         .oname = onam,                                                        \
472     },                                                                        \
473     .oname = onam,                                                            \
474 }
475 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2)              \
476 {                                                                             \
477     .opc1 = op1,                                                              \
478     .opc2 = op2,                                                              \
479     .opc3 = op3,                                                              \
480     .opc4 = op4,                                                              \
481     .handler = {                                                              \
482         .inval1  = invl,                                                      \
483         .type = _typ,                                                         \
484         .type2 = _typ2,                                                       \
485         .handler = &gen_##name,                                               \
486         .oname = stringify(name),                                             \
487     },                                                                        \
488     .oname = stringify(name),                                                 \
489 }
490 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2)        \
491 {                                                                             \
492     .opc1 = op1,                                                              \
493     .opc2 = op2,                                                              \
494     .opc3 = op3,                                                              \
495     .opc4 = op4,                                                              \
496     .handler = {                                                              \
497         .inval1  = invl,                                                      \
498         .type = _typ,                                                         \
499         .type2 = _typ2,                                                       \
500         .handler = &gen_##name,                                               \
501         .oname = onam,                                                        \
502     },                                                                        \
503     .oname = onam,                                                            \
504 }
505 #else
506 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2)                    \
507 {                                                                             \
508     .opc1 = op1,                                                              \
509     .opc2 = op2,                                                              \
510     .opc3 = op3,                                                              \
511     .opc4 = 0xff,                                                             \
512     .handler = {                                                              \
513         .inval1  = invl,                                                      \
514         .type = _typ,                                                         \
515         .type2 = _typ2,                                                       \
516         .handler = &gen_##name,                                               \
517     },                                                                        \
518     .oname = stringify(name),                                                 \
519 }
520 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2)       \
521 {                                                                             \
522     .opc1 = op1,                                                              \
523     .opc2 = op2,                                                              \
524     .opc3 = op3,                                                              \
525     .opc4 = 0xff,                                                             \
526     .handler = {                                                              \
527         .inval1  = invl1,                                                     \
528         .inval2  = invl2,                                                     \
529         .type = _typ,                                                         \
530         .type2 = _typ2,                                                       \
531         .handler = &gen_##name,                                               \
532     },                                                                        \
533     .oname = stringify(name),                                                 \
534 }
535 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2)             \
536 {                                                                             \
537     .opc1 = op1,                                                              \
538     .opc2 = op2,                                                              \
539     .opc3 = op3,                                                              \
540     .opc4 = 0xff,                                                             \
541     .handler = {                                                              \
542         .inval1  = invl,                                                      \
543         .type = _typ,                                                         \
544         .type2 = _typ2,                                                       \
545         .handler = &gen_##name,                                               \
546     },                                                                        \
547     .oname = onam,                                                            \
548 }
549 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2)              \
550 {                                                                             \
551     .opc1 = op1,                                                              \
552     .opc2 = op2,                                                              \
553     .opc3 = op3,                                                              \
554     .opc4 = op4,                                                              \
555     .handler = {                                                              \
556         .inval1  = invl,                                                      \
557         .type = _typ,                                                         \
558         .type2 = _typ2,                                                       \
559         .handler = &gen_##name,                                               \
560     },                                                                        \
561     .oname = stringify(name),                                                 \
562 }
563 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2)        \
564 {                                                                             \
565     .opc1 = op1,                                                              \
566     .opc2 = op2,                                                              \
567     .opc3 = op3,                                                              \
568     .opc4 = op4,                                                              \
569     .handler = {                                                              \
570         .inval1  = invl,                                                      \
571         .type = _typ,                                                         \
572         .type2 = _typ2,                                                       \
573         .handler = &gen_##name,                                               \
574     },                                                                        \
575     .oname = onam,                                                            \
576 }
577 #endif
578 
579 /* SPR load/store helpers */
580 static inline void gen_load_spr(TCGv t, int reg)
581 {
582     tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
583 }
584 
585 static inline void gen_store_spr(int reg, TCGv t)
586 {
587     tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
588 }
589 
590 /* Invalid instruction */
591 static void gen_invalid(DisasContext *ctx)
592 {
593     gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
594 }
595 
596 static opc_handler_t invalid_handler = {
597     .inval1  = 0xFFFFFFFF,
598     .inval2  = 0xFFFFFFFF,
599     .type    = PPC_NONE,
600     .type2   = PPC_NONE,
601     .handler = gen_invalid,
602 };
603 
604 /***                           Integer comparison                          ***/
605 
606 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
607 {
608     TCGv t0 = tcg_temp_new();
609     TCGv_i32 t1 = tcg_temp_new_i32();
610 
611     tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
612 
613     tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
614     tcg_gen_trunc_tl_i32(t1, t0);
615     tcg_gen_shli_i32(t1, t1, CRF_LT_BIT);
616     tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
617 
618     tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
619     tcg_gen_trunc_tl_i32(t1, t0);
620     tcg_gen_shli_i32(t1, t1, CRF_GT_BIT);
621     tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
622 
623     tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
624     tcg_gen_trunc_tl_i32(t1, t0);
625     tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT);
626     tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
627 
628     tcg_temp_free(t0);
629     tcg_temp_free_i32(t1);
630 }
631 
632 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
633 {
634     TCGv t0 = tcg_const_tl(arg1);
635     gen_op_cmp(arg0, t0, s, crf);
636     tcg_temp_free(t0);
637 }
638 
639 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
640 {
641     TCGv t0, t1;
642     t0 = tcg_temp_new();
643     t1 = tcg_temp_new();
644     if (s) {
645         tcg_gen_ext32s_tl(t0, arg0);
646         tcg_gen_ext32s_tl(t1, arg1);
647     } else {
648         tcg_gen_ext32u_tl(t0, arg0);
649         tcg_gen_ext32u_tl(t1, arg1);
650     }
651     gen_op_cmp(t0, t1, s, crf);
652     tcg_temp_free(t1);
653     tcg_temp_free(t0);
654 }
655 
656 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
657 {
658     TCGv t0 = tcg_const_tl(arg1);
659     gen_op_cmp32(arg0, t0, s, crf);
660     tcg_temp_free(t0);
661 }
662 
663 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
664 {
665     if (NARROW_MODE(ctx)) {
666         gen_op_cmpi32(reg, 0, 1, 0);
667     } else {
668         gen_op_cmpi(reg, 0, 1, 0);
669     }
670 }
671 
672 /* cmp */
673 static void gen_cmp(DisasContext *ctx)
674 {
675     if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
676         gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
677                    1, crfD(ctx->opcode));
678     } else {
679         gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
680                      1, crfD(ctx->opcode));
681     }
682 }
683 
684 /* cmpi */
685 static void gen_cmpi(DisasContext *ctx)
686 {
687     if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
688         gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
689                     1, crfD(ctx->opcode));
690     } else {
691         gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
692                       1, crfD(ctx->opcode));
693     }
694 }
695 
696 /* cmpl */
697 static void gen_cmpl(DisasContext *ctx)
698 {
699     if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
700         gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
701                    0, crfD(ctx->opcode));
702     } else {
703         gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
704                      0, crfD(ctx->opcode));
705     }
706 }
707 
708 /* cmpli */
709 static void gen_cmpli(DisasContext *ctx)
710 {
711     if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
712         gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
713                     0, crfD(ctx->opcode));
714     } else {
715         gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
716                       0, crfD(ctx->opcode));
717     }
718 }
719 
720 /* cmprb - range comparison: isupper, isaplha, islower*/
721 static void gen_cmprb(DisasContext *ctx)
722 {
723     TCGv_i32 src1 = tcg_temp_new_i32();
724     TCGv_i32 src2 = tcg_temp_new_i32();
725     TCGv_i32 src2lo = tcg_temp_new_i32();
726     TCGv_i32 src2hi = tcg_temp_new_i32();
727     TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
728 
729     tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
730     tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
731 
732     tcg_gen_andi_i32(src1, src1, 0xFF);
733     tcg_gen_ext8u_i32(src2lo, src2);
734     tcg_gen_shri_i32(src2, src2, 8);
735     tcg_gen_ext8u_i32(src2hi, src2);
736 
737     tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
738     tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
739     tcg_gen_and_i32(crf, src2lo, src2hi);
740 
741     if (ctx->opcode & 0x00200000) {
742         tcg_gen_shri_i32(src2, src2, 8);
743         tcg_gen_ext8u_i32(src2lo, src2);
744         tcg_gen_shri_i32(src2, src2, 8);
745         tcg_gen_ext8u_i32(src2hi, src2);
746         tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
747         tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
748         tcg_gen_and_i32(src2lo, src2lo, src2hi);
749         tcg_gen_or_i32(crf, crf, src2lo);
750     }
751     tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
752     tcg_temp_free_i32(src1);
753     tcg_temp_free_i32(src2);
754     tcg_temp_free_i32(src2lo);
755     tcg_temp_free_i32(src2hi);
756 }
757 
758 #if defined(TARGET_PPC64)
759 /* cmpeqb */
760 static void gen_cmpeqb(DisasContext *ctx)
761 {
762     gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
763                       cpu_gpr[rB(ctx->opcode)]);
764 }
765 #endif
766 
767 /* isel (PowerPC 2.03 specification) */
768 static void gen_isel(DisasContext *ctx)
769 {
770     uint32_t bi = rC(ctx->opcode);
771     uint32_t mask = 0x08 >> (bi & 0x03);
772     TCGv t0 = tcg_temp_new();
773     TCGv zr;
774 
775     tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
776     tcg_gen_andi_tl(t0, t0, mask);
777 
778     zr = tcg_const_tl(0);
779     tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
780                        rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
781                        cpu_gpr[rB(ctx->opcode)]);
782     tcg_temp_free(zr);
783     tcg_temp_free(t0);
784 }
785 
786 /* cmpb: PowerPC 2.05 specification */
787 static void gen_cmpb(DisasContext *ctx)
788 {
789     gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
790                     cpu_gpr[rB(ctx->opcode)]);
791 }
792 
793 /***                           Integer arithmetic                          ***/
794 
795 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
796                                            TCGv arg1, TCGv arg2, int sub)
797 {
798     TCGv t0 = tcg_temp_new();
799 
800     tcg_gen_xor_tl(cpu_ov, arg0, arg2);
801     tcg_gen_xor_tl(t0, arg1, arg2);
802     if (sub) {
803         tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
804     } else {
805         tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
806     }
807     tcg_temp_free(t0);
808     if (NARROW_MODE(ctx)) {
809         tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
810     }
811     tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
812     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
813 }
814 
815 /* Common add function */
816 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
817                                     TCGv arg2, bool add_ca, bool compute_ca,
818                                     bool compute_ov, bool compute_rc0)
819 {
820     TCGv t0 = ret;
821 
822     if (compute_ca || compute_ov) {
823         t0 = tcg_temp_new();
824     }
825 
826     if (compute_ca) {
827         if (NARROW_MODE(ctx)) {
828             /* Caution: a non-obvious corner case of the spec is that we
829                must produce the *entire* 64-bit addition, but produce the
830                carry into bit 32.  */
831             TCGv t1 = tcg_temp_new();
832             tcg_gen_xor_tl(t1, arg1, arg2);        /* add without carry */
833             tcg_gen_add_tl(t0, arg1, arg2);
834             if (add_ca) {
835                 tcg_gen_add_tl(t0, t0, cpu_ca);
836             }
837             tcg_gen_xor_tl(cpu_ca, t0, t1);        /* bits changed w/ carry */
838             tcg_temp_free(t1);
839             tcg_gen_shri_tl(cpu_ca, cpu_ca, 32);   /* extract bit 32 */
840             tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
841         } else {
842             TCGv zero = tcg_const_tl(0);
843             if (add_ca) {
844                 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
845                 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
846             } else {
847                 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
848             }
849             tcg_temp_free(zero);
850         }
851     } else {
852         tcg_gen_add_tl(t0, arg1, arg2);
853         if (add_ca) {
854             tcg_gen_add_tl(t0, t0, cpu_ca);
855         }
856     }
857 
858     if (compute_ov) {
859         gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
860     }
861     if (unlikely(compute_rc0)) {
862         gen_set_Rc0(ctx, t0);
863     }
864 
865     if (!TCGV_EQUAL(t0, ret)) {
866         tcg_gen_mov_tl(ret, t0);
867         tcg_temp_free(t0);
868     }
869 }
870 /* Add functions with two operands */
871 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov)         \
872 static void glue(gen_, name)(DisasContext *ctx)                               \
873 {                                                                             \
874     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
875                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
876                      add_ca, compute_ca, compute_ov, Rc(ctx->opcode));        \
877 }
878 /* Add functions with one operand and one immediate */
879 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val,                        \
880                                 add_ca, compute_ca, compute_ov)               \
881 static void glue(gen_, name)(DisasContext *ctx)                               \
882 {                                                                             \
883     TCGv t0 = tcg_const_tl(const_val);                                        \
884     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
885                      cpu_gpr[rA(ctx->opcode)], t0,                            \
886                      add_ca, compute_ca, compute_ov, Rc(ctx->opcode));        \
887     tcg_temp_free(t0);                                                        \
888 }
889 
890 /* add  add.  addo  addo. */
891 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
892 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
893 /* addc  addc.  addco  addco. */
894 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
895 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
896 /* adde  adde.  addeo  addeo. */
897 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
898 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
899 /* addme  addme.  addmeo  addmeo.  */
900 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
901 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
902 /* addze  addze.  addzeo  addzeo.*/
903 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
904 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
905 /* addi */
906 static void gen_addi(DisasContext *ctx)
907 {
908     target_long simm = SIMM(ctx->opcode);
909 
910     if (rA(ctx->opcode) == 0) {
911         /* li case */
912         tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
913     } else {
914         tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
915                         cpu_gpr[rA(ctx->opcode)], simm);
916     }
917 }
918 /* addic  addic.*/
919 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
920 {
921     TCGv c = tcg_const_tl(SIMM(ctx->opcode));
922     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
923                      c, 0, 1, 0, compute_rc0);
924     tcg_temp_free(c);
925 }
926 
927 static void gen_addic(DisasContext *ctx)
928 {
929     gen_op_addic(ctx, 0);
930 }
931 
932 static void gen_addic_(DisasContext *ctx)
933 {
934     gen_op_addic(ctx, 1);
935 }
936 
937 /* addis */
938 static void gen_addis(DisasContext *ctx)
939 {
940     target_long simm = SIMM(ctx->opcode);
941 
942     if (rA(ctx->opcode) == 0) {
943         /* lis case */
944         tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
945     } else {
946         tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
947                         cpu_gpr[rA(ctx->opcode)], simm << 16);
948     }
949 }
950 
951 /* addpcis */
952 static void gen_addpcis(DisasContext *ctx)
953 {
954     target_long d = DX(ctx->opcode);
955 
956     tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
957 }
958 
959 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
960                                      TCGv arg2, int sign, int compute_ov)
961 {
962     TCGv_i32 t0 = tcg_temp_new_i32();
963     TCGv_i32 t1 = tcg_temp_new_i32();
964     TCGv_i32 t2 = tcg_temp_new_i32();
965     TCGv_i32 t3 = tcg_temp_new_i32();
966 
967     tcg_gen_trunc_tl_i32(t0, arg1);
968     tcg_gen_trunc_tl_i32(t1, arg2);
969     if (sign) {
970         tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
971         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
972         tcg_gen_and_i32(t2, t2, t3);
973         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
974         tcg_gen_or_i32(t2, t2, t3);
975         tcg_gen_movi_i32(t3, 0);
976         tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
977         tcg_gen_div_i32(t3, t0, t1);
978         tcg_gen_extu_i32_tl(ret, t3);
979     } else {
980         tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
981         tcg_gen_movi_i32(t3, 0);
982         tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
983         tcg_gen_divu_i32(t3, t0, t1);
984         tcg_gen_extu_i32_tl(ret, t3);
985     }
986     if (compute_ov) {
987         tcg_gen_extu_i32_tl(cpu_ov, t2);
988         tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
989     }
990     tcg_temp_free_i32(t0);
991     tcg_temp_free_i32(t1);
992     tcg_temp_free_i32(t2);
993     tcg_temp_free_i32(t3);
994 
995     if (unlikely(Rc(ctx->opcode) != 0))
996         gen_set_Rc0(ctx, ret);
997 }
998 /* Div functions */
999 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \
1000 static void glue(gen_, name)(DisasContext *ctx)                                       \
1001 {                                                                             \
1002     gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1003                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
1004                      sign, compute_ov);                                       \
1005 }
1006 /* divwu  divwu.  divwuo  divwuo.   */
1007 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1008 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1009 /* divw  divw.  divwo  divwo.   */
1010 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1011 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1012 
1013 /* div[wd]eu[o][.] */
1014 #define GEN_DIVE(name, hlpr, compute_ov)                                      \
1015 static void gen_##name(DisasContext *ctx)                                     \
1016 {                                                                             \
1017     TCGv_i32 t0 = tcg_const_i32(compute_ov);                                  \
1018     gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env,                      \
1019                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1020     tcg_temp_free_i32(t0);                                                    \
1021     if (unlikely(Rc(ctx->opcode) != 0)) {                                     \
1022         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);                           \
1023     }                                                                         \
1024 }
1025 
1026 GEN_DIVE(divweu, divweu, 0);
1027 GEN_DIVE(divweuo, divweu, 1);
1028 GEN_DIVE(divwe, divwe, 0);
1029 GEN_DIVE(divweo, divwe, 1);
1030 
1031 #if defined(TARGET_PPC64)
1032 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1033                                      TCGv arg2, int sign, int compute_ov)
1034 {
1035     TCGv_i64 t0 = tcg_temp_new_i64();
1036     TCGv_i64 t1 = tcg_temp_new_i64();
1037     TCGv_i64 t2 = tcg_temp_new_i64();
1038     TCGv_i64 t3 = tcg_temp_new_i64();
1039 
1040     tcg_gen_mov_i64(t0, arg1);
1041     tcg_gen_mov_i64(t1, arg2);
1042     if (sign) {
1043         tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1044         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1045         tcg_gen_and_i64(t2, t2, t3);
1046         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1047         tcg_gen_or_i64(t2, t2, t3);
1048         tcg_gen_movi_i64(t3, 0);
1049         tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1050         tcg_gen_div_i64(ret, t0, t1);
1051     } else {
1052         tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1053         tcg_gen_movi_i64(t3, 0);
1054         tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1055         tcg_gen_divu_i64(ret, t0, t1);
1056     }
1057     if (compute_ov) {
1058         tcg_gen_mov_tl(cpu_ov, t2);
1059         tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1060     }
1061     tcg_temp_free_i64(t0);
1062     tcg_temp_free_i64(t1);
1063     tcg_temp_free_i64(t2);
1064     tcg_temp_free_i64(t3);
1065 
1066     if (unlikely(Rc(ctx->opcode) != 0))
1067         gen_set_Rc0(ctx, ret);
1068 }
1069 
1070 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov)                      \
1071 static void glue(gen_, name)(DisasContext *ctx)                                       \
1072 {                                                                             \
1073     gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1074                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1075                       sign, compute_ov);                                      \
1076 }
1077 /* divwu  divwu.  divwuo  divwuo.   */
1078 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1079 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1080 /* divw  divw.  divwo  divwo.   */
1081 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1082 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1083 
1084 GEN_DIVE(divdeu, divdeu, 0);
1085 GEN_DIVE(divdeuo, divdeu, 1);
1086 GEN_DIVE(divde, divde, 0);
1087 GEN_DIVE(divdeo, divde, 1);
1088 #endif
1089 
1090 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1091                                      TCGv arg2, int sign)
1092 {
1093     TCGv_i32 t0 = tcg_temp_new_i32();
1094     TCGv_i32 t1 = tcg_temp_new_i32();
1095 
1096     tcg_gen_trunc_tl_i32(t0, arg1);
1097     tcg_gen_trunc_tl_i32(t1, arg2);
1098     if (sign) {
1099         TCGv_i32 t2 = tcg_temp_new_i32();
1100         TCGv_i32 t3 = tcg_temp_new_i32();
1101         tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1102         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1103         tcg_gen_and_i32(t2, t2, t3);
1104         tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1105         tcg_gen_or_i32(t2, t2, t3);
1106         tcg_gen_movi_i32(t3, 0);
1107         tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1108         tcg_gen_rem_i32(t3, t0, t1);
1109         tcg_gen_ext_i32_tl(ret, t3);
1110         tcg_temp_free_i32(t2);
1111         tcg_temp_free_i32(t3);
1112     } else {
1113         TCGv_i32 t2 = tcg_const_i32(1);
1114         TCGv_i32 t3 = tcg_const_i32(0);
1115         tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1116         tcg_gen_remu_i32(t3, t0, t1);
1117         tcg_gen_extu_i32_tl(ret, t3);
1118         tcg_temp_free_i32(t2);
1119         tcg_temp_free_i32(t3);
1120     }
1121     tcg_temp_free_i32(t0);
1122     tcg_temp_free_i32(t1);
1123 }
1124 
1125 #define GEN_INT_ARITH_MODW(name, opc3, sign)                                \
1126 static void glue(gen_, name)(DisasContext *ctx)                             \
1127 {                                                                           \
1128     gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)],                        \
1129                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],   \
1130                       sign);                                                \
1131 }
1132 
1133 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1134 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1135 
1136 #if defined(TARGET_PPC64)
1137 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1138                                      TCGv arg2, int sign)
1139 {
1140     TCGv_i64 t0 = tcg_temp_new_i64();
1141     TCGv_i64 t1 = tcg_temp_new_i64();
1142 
1143     tcg_gen_mov_i64(t0, arg1);
1144     tcg_gen_mov_i64(t1, arg2);
1145     if (sign) {
1146         TCGv_i64 t2 = tcg_temp_new_i64();
1147         TCGv_i64 t3 = tcg_temp_new_i64();
1148         tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1149         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1150         tcg_gen_and_i64(t2, t2, t3);
1151         tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1152         tcg_gen_or_i64(t2, t2, t3);
1153         tcg_gen_movi_i64(t3, 0);
1154         tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1155         tcg_gen_rem_i64(ret, t0, t1);
1156         tcg_temp_free_i64(t2);
1157         tcg_temp_free_i64(t3);
1158     } else {
1159         TCGv_i64 t2 = tcg_const_i64(1);
1160         TCGv_i64 t3 = tcg_const_i64(0);
1161         tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1162         tcg_gen_remu_i64(ret, t0, t1);
1163         tcg_temp_free_i64(t2);
1164         tcg_temp_free_i64(t3);
1165     }
1166     tcg_temp_free_i64(t0);
1167     tcg_temp_free_i64(t1);
1168 }
1169 
1170 #define GEN_INT_ARITH_MODD(name, opc3, sign)                            \
1171 static void glue(gen_, name)(DisasContext *ctx)                           \
1172 {                                                                         \
1173   gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)],                        \
1174                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],   \
1175                     sign);                                                \
1176 }
1177 
1178 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1179 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1180 #endif
1181 
1182 /* mulhw  mulhw. */
1183 static void gen_mulhw(DisasContext *ctx)
1184 {
1185     TCGv_i32 t0 = tcg_temp_new_i32();
1186     TCGv_i32 t1 = tcg_temp_new_i32();
1187 
1188     tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1189     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1190     tcg_gen_muls2_i32(t0, t1, t0, t1);
1191     tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1192     tcg_temp_free_i32(t0);
1193     tcg_temp_free_i32(t1);
1194     if (unlikely(Rc(ctx->opcode) != 0))
1195         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1196 }
1197 
1198 /* mulhwu  mulhwu.  */
1199 static void gen_mulhwu(DisasContext *ctx)
1200 {
1201     TCGv_i32 t0 = tcg_temp_new_i32();
1202     TCGv_i32 t1 = tcg_temp_new_i32();
1203 
1204     tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1205     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1206     tcg_gen_mulu2_i32(t0, t1, t0, t1);
1207     tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1208     tcg_temp_free_i32(t0);
1209     tcg_temp_free_i32(t1);
1210     if (unlikely(Rc(ctx->opcode) != 0))
1211         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1212 }
1213 
1214 /* mullw  mullw. */
1215 static void gen_mullw(DisasContext *ctx)
1216 {
1217 #if defined(TARGET_PPC64)
1218     TCGv_i64 t0, t1;
1219     t0 = tcg_temp_new_i64();
1220     t1 = tcg_temp_new_i64();
1221     tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1222     tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1223     tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1224     tcg_temp_free(t0);
1225     tcg_temp_free(t1);
1226 #else
1227     tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1228                     cpu_gpr[rB(ctx->opcode)]);
1229 #endif
1230     if (unlikely(Rc(ctx->opcode) != 0))
1231         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1232 }
1233 
1234 /* mullwo  mullwo. */
1235 static void gen_mullwo(DisasContext *ctx)
1236 {
1237     TCGv_i32 t0 = tcg_temp_new_i32();
1238     TCGv_i32 t1 = tcg_temp_new_i32();
1239 
1240     tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1241     tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1242     tcg_gen_muls2_i32(t0, t1, t0, t1);
1243 #if defined(TARGET_PPC64)
1244     tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1245 #else
1246     tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1247 #endif
1248 
1249     tcg_gen_sari_i32(t0, t0, 31);
1250     tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1251     tcg_gen_extu_i32_tl(cpu_ov, t0);
1252     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1253 
1254     tcg_temp_free_i32(t0);
1255     tcg_temp_free_i32(t1);
1256     if (unlikely(Rc(ctx->opcode) != 0))
1257         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1258 }
1259 
1260 /* mulli */
1261 static void gen_mulli(DisasContext *ctx)
1262 {
1263     tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1264                     SIMM(ctx->opcode));
1265 }
1266 
1267 #if defined(TARGET_PPC64)
1268 /* mulhd  mulhd. */
1269 static void gen_mulhd(DisasContext *ctx)
1270 {
1271     TCGv lo = tcg_temp_new();
1272     tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1273                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1274     tcg_temp_free(lo);
1275     if (unlikely(Rc(ctx->opcode) != 0)) {
1276         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1277     }
1278 }
1279 
1280 /* mulhdu  mulhdu. */
1281 static void gen_mulhdu(DisasContext *ctx)
1282 {
1283     TCGv lo = tcg_temp_new();
1284     tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1285                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1286     tcg_temp_free(lo);
1287     if (unlikely(Rc(ctx->opcode) != 0)) {
1288         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1289     }
1290 }
1291 
1292 /* mulld  mulld. */
1293 static void gen_mulld(DisasContext *ctx)
1294 {
1295     tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1296                    cpu_gpr[rB(ctx->opcode)]);
1297     if (unlikely(Rc(ctx->opcode) != 0))
1298         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1299 }
1300 
1301 /* mulldo  mulldo. */
1302 static void gen_mulldo(DisasContext *ctx)
1303 {
1304     TCGv_i64 t0 = tcg_temp_new_i64();
1305     TCGv_i64 t1 = tcg_temp_new_i64();
1306 
1307     tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1308                       cpu_gpr[rB(ctx->opcode)]);
1309     tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1310 
1311     tcg_gen_sari_i64(t0, t0, 63);
1312     tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1313     tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1314 
1315     tcg_temp_free_i64(t0);
1316     tcg_temp_free_i64(t1);
1317 
1318     if (unlikely(Rc(ctx->opcode) != 0)) {
1319         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1320     }
1321 }
1322 #endif
1323 
1324 /* Common subf function */
1325 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1326                                      TCGv arg2, bool add_ca, bool compute_ca,
1327                                      bool compute_ov, bool compute_rc0)
1328 {
1329     TCGv t0 = ret;
1330 
1331     if (compute_ca || compute_ov) {
1332         t0 = tcg_temp_new();
1333     }
1334 
1335     if (compute_ca) {
1336         /* dest = ~arg1 + arg2 [+ ca].  */
1337         if (NARROW_MODE(ctx)) {
1338             /* Caution: a non-obvious corner case of the spec is that we
1339                must produce the *entire* 64-bit addition, but produce the
1340                carry into bit 32.  */
1341             TCGv inv1 = tcg_temp_new();
1342             TCGv t1 = tcg_temp_new();
1343             tcg_gen_not_tl(inv1, arg1);
1344             if (add_ca) {
1345                 tcg_gen_add_tl(t0, arg2, cpu_ca);
1346             } else {
1347                 tcg_gen_addi_tl(t0, arg2, 1);
1348             }
1349             tcg_gen_xor_tl(t1, arg2, inv1);         /* add without carry */
1350             tcg_gen_add_tl(t0, t0, inv1);
1351             tcg_temp_free(inv1);
1352             tcg_gen_xor_tl(cpu_ca, t0, t1);         /* bits changes w/ carry */
1353             tcg_temp_free(t1);
1354             tcg_gen_shri_tl(cpu_ca, cpu_ca, 32);    /* extract bit 32 */
1355             tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1356         } else if (add_ca) {
1357             TCGv zero, inv1 = tcg_temp_new();
1358             tcg_gen_not_tl(inv1, arg1);
1359             zero = tcg_const_tl(0);
1360             tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1361             tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1362             tcg_temp_free(zero);
1363             tcg_temp_free(inv1);
1364         } else {
1365             tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1366             tcg_gen_sub_tl(t0, arg2, arg1);
1367         }
1368     } else if (add_ca) {
1369         /* Since we're ignoring carry-out, we can simplify the
1370            standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.  */
1371         tcg_gen_sub_tl(t0, arg2, arg1);
1372         tcg_gen_add_tl(t0, t0, cpu_ca);
1373         tcg_gen_subi_tl(t0, t0, 1);
1374     } else {
1375         tcg_gen_sub_tl(t0, arg2, arg1);
1376     }
1377 
1378     if (compute_ov) {
1379         gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1380     }
1381     if (unlikely(compute_rc0)) {
1382         gen_set_Rc0(ctx, t0);
1383     }
1384 
1385     if (!TCGV_EQUAL(t0, ret)) {
1386         tcg_gen_mov_tl(ret, t0);
1387         tcg_temp_free(t0);
1388     }
1389 }
1390 /* Sub functions with Two operands functions */
1391 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov)        \
1392 static void glue(gen_, name)(DisasContext *ctx)                               \
1393 {                                                                             \
1394     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1395                       cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1396                       add_ca, compute_ca, compute_ov, Rc(ctx->opcode));       \
1397 }
1398 /* Sub functions with one operand and one immediate */
1399 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val,                       \
1400                                 add_ca, compute_ca, compute_ov)               \
1401 static void glue(gen_, name)(DisasContext *ctx)                               \
1402 {                                                                             \
1403     TCGv t0 = tcg_const_tl(const_val);                                        \
1404     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1405                       cpu_gpr[rA(ctx->opcode)], t0,                           \
1406                       add_ca, compute_ca, compute_ov, Rc(ctx->opcode));       \
1407     tcg_temp_free(t0);                                                        \
1408 }
1409 /* subf  subf.  subfo  subfo. */
1410 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1411 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1412 /* subfc  subfc.  subfco  subfco. */
1413 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1414 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1415 /* subfe  subfe.  subfeo  subfo. */
1416 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1417 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1418 /* subfme  subfme.  subfmeo  subfmeo.  */
1419 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1420 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1421 /* subfze  subfze.  subfzeo  subfzeo.*/
1422 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1423 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1424 
1425 /* subfic */
1426 static void gen_subfic(DisasContext *ctx)
1427 {
1428     TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1429     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1430                       c, 0, 1, 0, 0);
1431     tcg_temp_free(c);
1432 }
1433 
1434 /* neg neg. nego nego. */
1435 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1436 {
1437     TCGv zero = tcg_const_tl(0);
1438     gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1439                       zero, 0, 0, compute_ov, Rc(ctx->opcode));
1440     tcg_temp_free(zero);
1441 }
1442 
1443 static void gen_neg(DisasContext *ctx)
1444 {
1445     gen_op_arith_neg(ctx, 0);
1446 }
1447 
1448 static void gen_nego(DisasContext *ctx)
1449 {
1450     gen_op_arith_neg(ctx, 1);
1451 }
1452 
1453 /***                            Integer logical                            ***/
1454 #define GEN_LOGICAL2(name, tcg_op, opc, type)                                 \
1455 static void glue(gen_, name)(DisasContext *ctx)                                       \
1456 {                                                                             \
1457     tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],                \
1458        cpu_gpr[rB(ctx->opcode)]);                                             \
1459     if (unlikely(Rc(ctx->opcode) != 0))                                       \
1460         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
1461 }
1462 
1463 #define GEN_LOGICAL1(name, tcg_op, opc, type)                                 \
1464 static void glue(gen_, name)(DisasContext *ctx)                                       \
1465 {                                                                             \
1466     tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);               \
1467     if (unlikely(Rc(ctx->opcode) != 0))                                       \
1468         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
1469 }
1470 
1471 /* and & and. */
1472 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1473 /* andc & andc. */
1474 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1475 
1476 /* andi. */
1477 static void gen_andi_(DisasContext *ctx)
1478 {
1479     tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1480     gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1481 }
1482 
1483 /* andis. */
1484 static void gen_andis_(DisasContext *ctx)
1485 {
1486     tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1487     gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1488 }
1489 
1490 /* cntlzw */
1491 static void gen_cntlzw(DisasContext *ctx)
1492 {
1493     TCGv_i32 t = tcg_temp_new_i32();
1494 
1495     tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1496     tcg_gen_clzi_i32(t, t, 32);
1497     tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1498     tcg_temp_free_i32(t);
1499 
1500     if (unlikely(Rc(ctx->opcode) != 0))
1501         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1502 }
1503 
1504 /* cnttzw */
1505 static void gen_cnttzw(DisasContext *ctx)
1506 {
1507     TCGv_i32 t = tcg_temp_new_i32();
1508 
1509     tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1510     tcg_gen_ctzi_i32(t, t, 32);
1511     tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1512     tcg_temp_free_i32(t);
1513 
1514     if (unlikely(Rc(ctx->opcode) != 0)) {
1515         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1516     }
1517 }
1518 
1519 /* eqv & eqv. */
1520 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1521 /* extsb & extsb. */
1522 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1523 /* extsh & extsh. */
1524 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1525 /* nand & nand. */
1526 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1527 /* nor & nor. */
1528 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1529 
1530 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1531 static void gen_pause(DisasContext *ctx)
1532 {
1533     TCGv_i32 t0 = tcg_const_i32(0);
1534     tcg_gen_st_i32(t0, cpu_env,
1535                    -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1536     tcg_temp_free_i32(t0);
1537 
1538     /* Stop translation, this gives other CPUs a chance to run */
1539     gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1540 }
1541 #endif /* defined(TARGET_PPC64) */
1542 
1543 /* or & or. */
1544 static void gen_or(DisasContext *ctx)
1545 {
1546     int rs, ra, rb;
1547 
1548     rs = rS(ctx->opcode);
1549     ra = rA(ctx->opcode);
1550     rb = rB(ctx->opcode);
1551     /* Optimisation for mr. ri case */
1552     if (rs != ra || rs != rb) {
1553         if (rs != rb)
1554             tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1555         else
1556             tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1557         if (unlikely(Rc(ctx->opcode) != 0))
1558             gen_set_Rc0(ctx, cpu_gpr[ra]);
1559     } else if (unlikely(Rc(ctx->opcode) != 0)) {
1560         gen_set_Rc0(ctx, cpu_gpr[rs]);
1561 #if defined(TARGET_PPC64)
1562     } else if (rs != 0) { /* 0 is nop */
1563         int prio = 0;
1564 
1565         switch (rs) {
1566         case 1:
1567             /* Set process priority to low */
1568             prio = 2;
1569             break;
1570         case 6:
1571             /* Set process priority to medium-low */
1572             prio = 3;
1573             break;
1574         case 2:
1575             /* Set process priority to normal */
1576             prio = 4;
1577             break;
1578 #if !defined(CONFIG_USER_ONLY)
1579         case 31:
1580             if (!ctx->pr) {
1581                 /* Set process priority to very low */
1582                 prio = 1;
1583             }
1584             break;
1585         case 5:
1586             if (!ctx->pr) {
1587                 /* Set process priority to medium-hight */
1588                 prio = 5;
1589             }
1590             break;
1591         case 3:
1592             if (!ctx->pr) {
1593                 /* Set process priority to high */
1594                 prio = 6;
1595             }
1596             break;
1597         case 7:
1598             if (ctx->hv && !ctx->pr) {
1599                 /* Set process priority to very high */
1600                 prio = 7;
1601             }
1602             break;
1603 #endif
1604         default:
1605             break;
1606         }
1607         if (prio) {
1608             TCGv t0 = tcg_temp_new();
1609             gen_load_spr(t0, SPR_PPR);
1610             tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1611             tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1612             gen_store_spr(SPR_PPR, t0);
1613             tcg_temp_free(t0);
1614         }
1615 #if !defined(CONFIG_USER_ONLY)
1616         /* Pause out of TCG otherwise spin loops with smt_low eat too much
1617          * CPU and the kernel hangs.  This applies to all encodings other
1618          * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1619          * and all currently undefined.
1620          */
1621         gen_pause(ctx);
1622 #endif
1623 #endif
1624     }
1625 }
1626 /* orc & orc. */
1627 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1628 
1629 /* xor & xor. */
1630 static void gen_xor(DisasContext *ctx)
1631 {
1632     /* Optimisation for "set to zero" case */
1633     if (rS(ctx->opcode) != rB(ctx->opcode))
1634         tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1635     else
1636         tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1637     if (unlikely(Rc(ctx->opcode) != 0))
1638         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1639 }
1640 
1641 /* ori */
1642 static void gen_ori(DisasContext *ctx)
1643 {
1644     target_ulong uimm = UIMM(ctx->opcode);
1645 
1646     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1647         return;
1648     }
1649     tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1650 }
1651 
1652 /* oris */
1653 static void gen_oris(DisasContext *ctx)
1654 {
1655     target_ulong uimm = UIMM(ctx->opcode);
1656 
1657     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1658         /* NOP */
1659         return;
1660     }
1661     tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1662 }
1663 
1664 /* xori */
1665 static void gen_xori(DisasContext *ctx)
1666 {
1667     target_ulong uimm = UIMM(ctx->opcode);
1668 
1669     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1670         /* NOP */
1671         return;
1672     }
1673     tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1674 }
1675 
1676 /* xoris */
1677 static void gen_xoris(DisasContext *ctx)
1678 {
1679     target_ulong uimm = UIMM(ctx->opcode);
1680 
1681     if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1682         /* NOP */
1683         return;
1684     }
1685     tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1686 }
1687 
1688 /* popcntb : PowerPC 2.03 specification */
1689 static void gen_popcntb(DisasContext *ctx)
1690 {
1691     gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1692 }
1693 
1694 static void gen_popcntw(DisasContext *ctx)
1695 {
1696 #if defined(TARGET_PPC64)
1697     gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1698 #else
1699     tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1700 #endif
1701 }
1702 
1703 #if defined(TARGET_PPC64)
1704 /* popcntd: PowerPC 2.06 specification */
1705 static void gen_popcntd(DisasContext *ctx)
1706 {
1707     tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1708 }
1709 #endif
1710 
1711 /* prtyw: PowerPC 2.05 specification */
1712 static void gen_prtyw(DisasContext *ctx)
1713 {
1714     TCGv ra = cpu_gpr[rA(ctx->opcode)];
1715     TCGv rs = cpu_gpr[rS(ctx->opcode)];
1716     TCGv t0 = tcg_temp_new();
1717     tcg_gen_shri_tl(t0, rs, 16);
1718     tcg_gen_xor_tl(ra, rs, t0);
1719     tcg_gen_shri_tl(t0, ra, 8);
1720     tcg_gen_xor_tl(ra, ra, t0);
1721     tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1722     tcg_temp_free(t0);
1723 }
1724 
1725 #if defined(TARGET_PPC64)
1726 /* prtyd: PowerPC 2.05 specification */
1727 static void gen_prtyd(DisasContext *ctx)
1728 {
1729     TCGv ra = cpu_gpr[rA(ctx->opcode)];
1730     TCGv rs = cpu_gpr[rS(ctx->opcode)];
1731     TCGv t0 = tcg_temp_new();
1732     tcg_gen_shri_tl(t0, rs, 32);
1733     tcg_gen_xor_tl(ra, rs, t0);
1734     tcg_gen_shri_tl(t0, ra, 16);
1735     tcg_gen_xor_tl(ra, ra, t0);
1736     tcg_gen_shri_tl(t0, ra, 8);
1737     tcg_gen_xor_tl(ra, ra, t0);
1738     tcg_gen_andi_tl(ra, ra, 1);
1739     tcg_temp_free(t0);
1740 }
1741 #endif
1742 
1743 #if defined(TARGET_PPC64)
1744 /* bpermd */
1745 static void gen_bpermd(DisasContext *ctx)
1746 {
1747     gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1748                       cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1749 }
1750 #endif
1751 
1752 #if defined(TARGET_PPC64)
1753 /* extsw & extsw. */
1754 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1755 
1756 /* cntlzd */
1757 static void gen_cntlzd(DisasContext *ctx)
1758 {
1759     tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1760     if (unlikely(Rc(ctx->opcode) != 0))
1761         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1762 }
1763 
1764 /* cnttzd */
1765 static void gen_cnttzd(DisasContext *ctx)
1766 {
1767     tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1768     if (unlikely(Rc(ctx->opcode) != 0)) {
1769         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1770     }
1771 }
1772 
1773 /* darn */
1774 static void gen_darn(DisasContext *ctx)
1775 {
1776     int l = L(ctx->opcode);
1777 
1778     if (l == 0) {
1779         gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1780     } else if (l <= 2) {
1781         /* Return 64-bit random for both CRN and RRN */
1782         gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1783     } else {
1784         tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1785     }
1786 }
1787 #endif
1788 
1789 /***                             Integer rotate                            ***/
1790 
1791 /* rlwimi & rlwimi. */
1792 static void gen_rlwimi(DisasContext *ctx)
1793 {
1794     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1795     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1796     uint32_t sh = SH(ctx->opcode);
1797     uint32_t mb = MB(ctx->opcode);
1798     uint32_t me = ME(ctx->opcode);
1799 
1800     if (sh == (31-me) && mb <= me) {
1801         tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1802     } else {
1803         target_ulong mask;
1804         TCGv t1;
1805 
1806 #if defined(TARGET_PPC64)
1807         mb += 32;
1808         me += 32;
1809 #endif
1810         mask = MASK(mb, me);
1811 
1812         t1 = tcg_temp_new();
1813         if (mask <= 0xffffffffu) {
1814             TCGv_i32 t0 = tcg_temp_new_i32();
1815             tcg_gen_trunc_tl_i32(t0, t_rs);
1816             tcg_gen_rotli_i32(t0, t0, sh);
1817             tcg_gen_extu_i32_tl(t1, t0);
1818             tcg_temp_free_i32(t0);
1819         } else {
1820 #if defined(TARGET_PPC64)
1821             tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1822             tcg_gen_rotli_i64(t1, t1, sh);
1823 #else
1824             g_assert_not_reached();
1825 #endif
1826         }
1827 
1828         tcg_gen_andi_tl(t1, t1, mask);
1829         tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1830         tcg_gen_or_tl(t_ra, t_ra, t1);
1831         tcg_temp_free(t1);
1832     }
1833     if (unlikely(Rc(ctx->opcode) != 0)) {
1834         gen_set_Rc0(ctx, t_ra);
1835     }
1836 }
1837 
1838 /* rlwinm & rlwinm. */
1839 static void gen_rlwinm(DisasContext *ctx)
1840 {
1841     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1842     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1843     int sh = SH(ctx->opcode);
1844     int mb = MB(ctx->opcode);
1845     int me = ME(ctx->opcode);
1846     int len = me - mb + 1;
1847     int rsh = (32 - sh) & 31;
1848 
1849     if (sh != 0 && len > 0 && me == (31 - sh)) {
1850         tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1851     } else if (me == 31 && rsh + len <= 32) {
1852         tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1853     } else {
1854         target_ulong mask;
1855 #if defined(TARGET_PPC64)
1856         mb += 32;
1857         me += 32;
1858 #endif
1859         mask = MASK(mb, me);
1860         if (sh == 0) {
1861             tcg_gen_andi_tl(t_ra, t_rs, mask);
1862         } else if (mask <= 0xffffffffu) {
1863             TCGv_i32 t0 = tcg_temp_new_i32();
1864             tcg_gen_trunc_tl_i32(t0, t_rs);
1865             tcg_gen_rotli_i32(t0, t0, sh);
1866             tcg_gen_andi_i32(t0, t0, mask);
1867             tcg_gen_extu_i32_tl(t_ra, t0);
1868             tcg_temp_free_i32(t0);
1869         } else {
1870 #if defined(TARGET_PPC64)
1871             tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1872             tcg_gen_rotli_i64(t_ra, t_ra, sh);
1873             tcg_gen_andi_i64(t_ra, t_ra, mask);
1874 #else
1875             g_assert_not_reached();
1876 #endif
1877         }
1878     }
1879     if (unlikely(Rc(ctx->opcode) != 0)) {
1880         gen_set_Rc0(ctx, t_ra);
1881     }
1882 }
1883 
1884 /* rlwnm & rlwnm. */
1885 static void gen_rlwnm(DisasContext *ctx)
1886 {
1887     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1888     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1889     TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1890     uint32_t mb = MB(ctx->opcode);
1891     uint32_t me = ME(ctx->opcode);
1892     target_ulong mask;
1893 
1894 #if defined(TARGET_PPC64)
1895     mb += 32;
1896     me += 32;
1897 #endif
1898     mask = MASK(mb, me);
1899 
1900     if (mask <= 0xffffffffu) {
1901         TCGv_i32 t0 = tcg_temp_new_i32();
1902         TCGv_i32 t1 = tcg_temp_new_i32();
1903         tcg_gen_trunc_tl_i32(t0, t_rb);
1904         tcg_gen_trunc_tl_i32(t1, t_rs);
1905         tcg_gen_andi_i32(t0, t0, 0x1f);
1906         tcg_gen_rotl_i32(t1, t1, t0);
1907         tcg_gen_extu_i32_tl(t_ra, t1);
1908         tcg_temp_free_i32(t0);
1909         tcg_temp_free_i32(t1);
1910     } else {
1911 #if defined(TARGET_PPC64)
1912         TCGv_i64 t0 = tcg_temp_new_i64();
1913         tcg_gen_andi_i64(t0, t_rb, 0x1f);
1914         tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1915         tcg_gen_rotl_i64(t_ra, t_ra, t0);
1916         tcg_temp_free_i64(t0);
1917 #else
1918         g_assert_not_reached();
1919 #endif
1920     }
1921 
1922     tcg_gen_andi_tl(t_ra, t_ra, mask);
1923 
1924     if (unlikely(Rc(ctx->opcode) != 0)) {
1925         gen_set_Rc0(ctx, t_ra);
1926     }
1927 }
1928 
1929 #if defined(TARGET_PPC64)
1930 #define GEN_PPC64_R2(name, opc1, opc2)                                        \
1931 static void glue(gen_, name##0)(DisasContext *ctx)                            \
1932 {                                                                             \
1933     gen_##name(ctx, 0);                                                       \
1934 }                                                                             \
1935                                                                               \
1936 static void glue(gen_, name##1)(DisasContext *ctx)                            \
1937 {                                                                             \
1938     gen_##name(ctx, 1);                                                       \
1939 }
1940 #define GEN_PPC64_R4(name, opc1, opc2)                                        \
1941 static void glue(gen_, name##0)(DisasContext *ctx)                            \
1942 {                                                                             \
1943     gen_##name(ctx, 0, 0);                                                    \
1944 }                                                                             \
1945                                                                               \
1946 static void glue(gen_, name##1)(DisasContext *ctx)                            \
1947 {                                                                             \
1948     gen_##name(ctx, 0, 1);                                                    \
1949 }                                                                             \
1950                                                                               \
1951 static void glue(gen_, name##2)(DisasContext *ctx)                            \
1952 {                                                                             \
1953     gen_##name(ctx, 1, 0);                                                    \
1954 }                                                                             \
1955                                                                               \
1956 static void glue(gen_, name##3)(DisasContext *ctx)                            \
1957 {                                                                             \
1958     gen_##name(ctx, 1, 1);                                                    \
1959 }
1960 
1961 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
1962 {
1963     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1964     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1965     int len = me - mb + 1;
1966     int rsh = (64 - sh) & 63;
1967 
1968     if (sh != 0 && len > 0 && me == (63 - sh)) {
1969         tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1970     } else if (me == 63 && rsh + len <= 64) {
1971         tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1972     } else {
1973         tcg_gen_rotli_tl(t_ra, t_rs, sh);
1974         tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1975     }
1976     if (unlikely(Rc(ctx->opcode) != 0)) {
1977         gen_set_Rc0(ctx, t_ra);
1978     }
1979 }
1980 
1981 /* rldicl - rldicl. */
1982 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1983 {
1984     uint32_t sh, mb;
1985 
1986     sh = SH(ctx->opcode) | (shn << 5);
1987     mb = MB(ctx->opcode) | (mbn << 5);
1988     gen_rldinm(ctx, mb, 63, sh);
1989 }
1990 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1991 
1992 /* rldicr - rldicr. */
1993 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1994 {
1995     uint32_t sh, me;
1996 
1997     sh = SH(ctx->opcode) | (shn << 5);
1998     me = MB(ctx->opcode) | (men << 5);
1999     gen_rldinm(ctx, 0, me, sh);
2000 }
2001 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2002 
2003 /* rldic - rldic. */
2004 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2005 {
2006     uint32_t sh, mb;
2007 
2008     sh = SH(ctx->opcode) | (shn << 5);
2009     mb = MB(ctx->opcode) | (mbn << 5);
2010     gen_rldinm(ctx, mb, 63 - sh, sh);
2011 }
2012 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2013 
2014 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2015 {
2016     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2017     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2018     TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2019     TCGv t0;
2020 
2021     t0 = tcg_temp_new();
2022     tcg_gen_andi_tl(t0, t_rb, 0x3f);
2023     tcg_gen_rotl_tl(t_ra, t_rs, t0);
2024     tcg_temp_free(t0);
2025 
2026     tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2027     if (unlikely(Rc(ctx->opcode) != 0)) {
2028         gen_set_Rc0(ctx, t_ra);
2029     }
2030 }
2031 
2032 /* rldcl - rldcl. */
2033 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2034 {
2035     uint32_t mb;
2036 
2037     mb = MB(ctx->opcode) | (mbn << 5);
2038     gen_rldnm(ctx, mb, 63);
2039 }
2040 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2041 
2042 /* rldcr - rldcr. */
2043 static inline void gen_rldcr(DisasContext *ctx, int men)
2044 {
2045     uint32_t me;
2046 
2047     me = MB(ctx->opcode) | (men << 5);
2048     gen_rldnm(ctx, 0, me);
2049 }
2050 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2051 
2052 /* rldimi - rldimi. */
2053 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2054 {
2055     TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2056     TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2057     uint32_t sh = SH(ctx->opcode) | (shn << 5);
2058     uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2059     uint32_t me = 63 - sh;
2060 
2061     if (mb <= me) {
2062         tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2063     } else {
2064         target_ulong mask = MASK(mb, me);
2065         TCGv t1 = tcg_temp_new();
2066 
2067         tcg_gen_rotli_tl(t1, t_rs, sh);
2068         tcg_gen_andi_tl(t1, t1, mask);
2069         tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2070         tcg_gen_or_tl(t_ra, t_ra, t1);
2071         tcg_temp_free(t1);
2072     }
2073     if (unlikely(Rc(ctx->opcode) != 0)) {
2074         gen_set_Rc0(ctx, t_ra);
2075     }
2076 }
2077 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2078 #endif
2079 
2080 /***                             Integer shift                             ***/
2081 
2082 /* slw & slw. */
2083 static void gen_slw(DisasContext *ctx)
2084 {
2085     TCGv t0, t1;
2086 
2087     t0 = tcg_temp_new();
2088     /* AND rS with a mask that is 0 when rB >= 0x20 */
2089 #if defined(TARGET_PPC64)
2090     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2091     tcg_gen_sari_tl(t0, t0, 0x3f);
2092 #else
2093     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2094     tcg_gen_sari_tl(t0, t0, 0x1f);
2095 #endif
2096     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2097     t1 = tcg_temp_new();
2098     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2099     tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2100     tcg_temp_free(t1);
2101     tcg_temp_free(t0);
2102     tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2103     if (unlikely(Rc(ctx->opcode) != 0))
2104         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2105 }
2106 
2107 /* sraw & sraw. */
2108 static void gen_sraw(DisasContext *ctx)
2109 {
2110     gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2111                     cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2112     if (unlikely(Rc(ctx->opcode) != 0))
2113         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2114 }
2115 
2116 /* srawi & srawi. */
2117 static void gen_srawi(DisasContext *ctx)
2118 {
2119     int sh = SH(ctx->opcode);
2120     TCGv dst = cpu_gpr[rA(ctx->opcode)];
2121     TCGv src = cpu_gpr[rS(ctx->opcode)];
2122     if (sh == 0) {
2123         tcg_gen_ext32s_tl(dst, src);
2124         tcg_gen_movi_tl(cpu_ca, 0);
2125     } else {
2126         TCGv t0;
2127         tcg_gen_ext32s_tl(dst, src);
2128         tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2129         t0 = tcg_temp_new();
2130         tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2131         tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2132         tcg_temp_free(t0);
2133         tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2134         tcg_gen_sari_tl(dst, dst, sh);
2135     }
2136     if (unlikely(Rc(ctx->opcode) != 0)) {
2137         gen_set_Rc0(ctx, dst);
2138     }
2139 }
2140 
2141 /* srw & srw. */
2142 static void gen_srw(DisasContext *ctx)
2143 {
2144     TCGv t0, t1;
2145 
2146     t0 = tcg_temp_new();
2147     /* AND rS with a mask that is 0 when rB >= 0x20 */
2148 #if defined(TARGET_PPC64)
2149     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2150     tcg_gen_sari_tl(t0, t0, 0x3f);
2151 #else
2152     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2153     tcg_gen_sari_tl(t0, t0, 0x1f);
2154 #endif
2155     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2156     tcg_gen_ext32u_tl(t0, t0);
2157     t1 = tcg_temp_new();
2158     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2159     tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2160     tcg_temp_free(t1);
2161     tcg_temp_free(t0);
2162     if (unlikely(Rc(ctx->opcode) != 0))
2163         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2164 }
2165 
2166 #if defined(TARGET_PPC64)
2167 /* sld & sld. */
2168 static void gen_sld(DisasContext *ctx)
2169 {
2170     TCGv t0, t1;
2171 
2172     t0 = tcg_temp_new();
2173     /* AND rS with a mask that is 0 when rB >= 0x40 */
2174     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2175     tcg_gen_sari_tl(t0, t0, 0x3f);
2176     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2177     t1 = tcg_temp_new();
2178     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2179     tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2180     tcg_temp_free(t1);
2181     tcg_temp_free(t0);
2182     if (unlikely(Rc(ctx->opcode) != 0))
2183         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2184 }
2185 
2186 /* srad & srad. */
2187 static void gen_srad(DisasContext *ctx)
2188 {
2189     gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2190                     cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2191     if (unlikely(Rc(ctx->opcode) != 0))
2192         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2193 }
2194 /* sradi & sradi. */
2195 static inline void gen_sradi(DisasContext *ctx, int n)
2196 {
2197     int sh = SH(ctx->opcode) + (n << 5);
2198     TCGv dst = cpu_gpr[rA(ctx->opcode)];
2199     TCGv src = cpu_gpr[rS(ctx->opcode)];
2200     if (sh == 0) {
2201         tcg_gen_mov_tl(dst, src);
2202         tcg_gen_movi_tl(cpu_ca, 0);
2203     } else {
2204         TCGv t0;
2205         tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2206         t0 = tcg_temp_new();
2207         tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2208         tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2209         tcg_temp_free(t0);
2210         tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2211         tcg_gen_sari_tl(dst, src, sh);
2212     }
2213     if (unlikely(Rc(ctx->opcode) != 0)) {
2214         gen_set_Rc0(ctx, dst);
2215     }
2216 }
2217 
2218 static void gen_sradi0(DisasContext *ctx)
2219 {
2220     gen_sradi(ctx, 0);
2221 }
2222 
2223 static void gen_sradi1(DisasContext *ctx)
2224 {
2225     gen_sradi(ctx, 1);
2226 }
2227 
2228 /* extswsli & extswsli. */
2229 static inline void gen_extswsli(DisasContext *ctx, int n)
2230 {
2231     int sh = SH(ctx->opcode) + (n << 5);
2232     TCGv dst = cpu_gpr[rA(ctx->opcode)];
2233     TCGv src = cpu_gpr[rS(ctx->opcode)];
2234 
2235     tcg_gen_ext32s_tl(dst, src);
2236     tcg_gen_shli_tl(dst, dst, sh);
2237     if (unlikely(Rc(ctx->opcode) != 0)) {
2238         gen_set_Rc0(ctx, dst);
2239     }
2240 }
2241 
2242 static void gen_extswsli0(DisasContext *ctx)
2243 {
2244     gen_extswsli(ctx, 0);
2245 }
2246 
2247 static void gen_extswsli1(DisasContext *ctx)
2248 {
2249     gen_extswsli(ctx, 1);
2250 }
2251 
2252 /* srd & srd. */
2253 static void gen_srd(DisasContext *ctx)
2254 {
2255     TCGv t0, t1;
2256 
2257     t0 = tcg_temp_new();
2258     /* AND rS with a mask that is 0 when rB >= 0x40 */
2259     tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2260     tcg_gen_sari_tl(t0, t0, 0x3f);
2261     tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2262     t1 = tcg_temp_new();
2263     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2264     tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2265     tcg_temp_free(t1);
2266     tcg_temp_free(t0);
2267     if (unlikely(Rc(ctx->opcode) != 0))
2268         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2269 }
2270 #endif
2271 
2272 /***                           Addressing modes                            ***/
2273 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2274 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2275                                       target_long maskl)
2276 {
2277     target_long simm = SIMM(ctx->opcode);
2278 
2279     simm &= ~maskl;
2280     if (rA(ctx->opcode) == 0) {
2281         if (NARROW_MODE(ctx)) {
2282             simm = (uint32_t)simm;
2283         }
2284         tcg_gen_movi_tl(EA, simm);
2285     } else if (likely(simm != 0)) {
2286         tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2287         if (NARROW_MODE(ctx)) {
2288             tcg_gen_ext32u_tl(EA, EA);
2289         }
2290     } else {
2291         if (NARROW_MODE(ctx)) {
2292             tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2293         } else {
2294             tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2295         }
2296     }
2297 }
2298 
2299 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2300 {
2301     if (rA(ctx->opcode) == 0) {
2302         if (NARROW_MODE(ctx)) {
2303             tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2304         } else {
2305             tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2306         }
2307     } else {
2308         tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2309         if (NARROW_MODE(ctx)) {
2310             tcg_gen_ext32u_tl(EA, EA);
2311         }
2312     }
2313 }
2314 
2315 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2316 {
2317     if (rA(ctx->opcode) == 0) {
2318         tcg_gen_movi_tl(EA, 0);
2319     } else if (NARROW_MODE(ctx)) {
2320         tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2321     } else {
2322         tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2323     }
2324 }
2325 
2326 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2327                                 target_long val)
2328 {
2329     tcg_gen_addi_tl(ret, arg1, val);
2330     if (NARROW_MODE(ctx)) {
2331         tcg_gen_ext32u_tl(ret, ret);
2332     }
2333 }
2334 
2335 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2336 {
2337     TCGLabel *l1 = gen_new_label();
2338     TCGv t0 = tcg_temp_new();
2339     TCGv_i32 t1, t2;
2340     tcg_gen_andi_tl(t0, EA, mask);
2341     tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2342     t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2343     t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2344     gen_update_nip(ctx, ctx->nip - 4);
2345     gen_helper_raise_exception_err(cpu_env, t1, t2);
2346     tcg_temp_free_i32(t1);
2347     tcg_temp_free_i32(t2);
2348     gen_set_label(l1);
2349     tcg_temp_free(t0);
2350 }
2351 
2352 static inline void gen_align_no_le(DisasContext *ctx)
2353 {
2354     gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2355                       (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2356 }
2357 
2358 /***                             Integer load                              ***/
2359 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2360 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2361 
2362 #define GEN_QEMU_LOAD_TL(ldop, op)                                      \
2363 static void glue(gen_qemu_, ldop)(DisasContext *ctx,                    \
2364                                   TCGv val,                             \
2365                                   TCGv addr)                            \
2366 {                                                                       \
2367     tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op);                    \
2368 }
2369 
2370 GEN_QEMU_LOAD_TL(ld8u,  DEF_MEMOP(MO_UB))
2371 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2372 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2373 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2374 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2375 
2376 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2377 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2378 
2379 #define GEN_QEMU_LOAD_64(ldop, op)                                  \
2380 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx,    \
2381                                              TCGv_i64 val,          \
2382                                              TCGv addr)             \
2383 {                                                                   \
2384     tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op);               \
2385 }
2386 
2387 GEN_QEMU_LOAD_64(ld8u,  DEF_MEMOP(MO_UB))
2388 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2389 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2390 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2391 GEN_QEMU_LOAD_64(ld64,  DEF_MEMOP(MO_Q))
2392 
2393 #if defined(TARGET_PPC64)
2394 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2395 #endif
2396 
2397 #define GEN_QEMU_STORE_TL(stop, op)                                     \
2398 static void glue(gen_qemu_, stop)(DisasContext *ctx,                    \
2399                                   TCGv val,                             \
2400                                   TCGv addr)                            \
2401 {                                                                       \
2402     tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op);                    \
2403 }
2404 
2405 GEN_QEMU_STORE_TL(st8,  DEF_MEMOP(MO_UB))
2406 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2407 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2408 
2409 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2410 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2411 
2412 #define GEN_QEMU_STORE_64(stop, op)                               \
2413 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx,  \
2414                                               TCGv_i64 val,       \
2415                                               TCGv addr)          \
2416 {                                                                 \
2417     tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op);             \
2418 }
2419 
2420 GEN_QEMU_STORE_64(st8,  DEF_MEMOP(MO_UB))
2421 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2422 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2423 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2424 
2425 #if defined(TARGET_PPC64)
2426 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2427 #endif
2428 
2429 #define GEN_LD(name, ldop, opc, type)                                         \
2430 static void glue(gen_, name)(DisasContext *ctx)                                       \
2431 {                                                                             \
2432     TCGv EA;                                                                  \
2433     gen_set_access_type(ctx, ACCESS_INT);                                     \
2434     EA = tcg_temp_new();                                                      \
2435     gen_addr_imm_index(ctx, EA, 0);                                           \
2436     gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2437     tcg_temp_free(EA);                                                        \
2438 }
2439 
2440 #define GEN_LDU(name, ldop, opc, type)                                        \
2441 static void glue(gen_, name##u)(DisasContext *ctx)                                    \
2442 {                                                                             \
2443     TCGv EA;                                                                  \
2444     if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2445                  rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2446         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2447         return;                                                               \
2448     }                                                                         \
2449     gen_set_access_type(ctx, ACCESS_INT);                                     \
2450     EA = tcg_temp_new();                                                      \
2451     if (type == PPC_64B)                                                      \
2452         gen_addr_imm_index(ctx, EA, 0x03);                                    \
2453     else                                                                      \
2454         gen_addr_imm_index(ctx, EA, 0);                                       \
2455     gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2456     tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2457     tcg_temp_free(EA);                                                        \
2458 }
2459 
2460 #define GEN_LDUX(name, ldop, opc2, opc3, type)                                \
2461 static void glue(gen_, name##ux)(DisasContext *ctx)                                   \
2462 {                                                                             \
2463     TCGv EA;                                                                  \
2464     if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2465                  rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2466         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2467         return;                                                               \
2468     }                                                                         \
2469     gen_set_access_type(ctx, ACCESS_INT);                                     \
2470     EA = tcg_temp_new();                                                      \
2471     gen_addr_reg_index(ctx, EA);                                              \
2472     gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2473     tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2474     tcg_temp_free(EA);                                                        \
2475 }
2476 
2477 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk)                   \
2478 static void glue(gen_, name##x)(DisasContext *ctx)                            \
2479 {                                                                             \
2480     TCGv EA;                                                                  \
2481     chk;                                                                      \
2482     gen_set_access_type(ctx, ACCESS_INT);                                     \
2483     EA = tcg_temp_new();                                                      \
2484     gen_addr_reg_index(ctx, EA);                                              \
2485     gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2486     tcg_temp_free(EA);                                                        \
2487 }
2488 
2489 #define GEN_LDX(name, ldop, opc2, opc3, type)                                 \
2490     GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2491 
2492 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type)                            \
2493     GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2494 
2495 #define GEN_LDS(name, ldop, op, type)                                         \
2496 GEN_LD(name, ldop, op | 0x20, type);                                          \
2497 GEN_LDU(name, ldop, op | 0x21, type);                                         \
2498 GEN_LDUX(name, ldop, 0x17, op | 0x01, type);                                  \
2499 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2500 
2501 /* lbz lbzu lbzux lbzx */
2502 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2503 /* lha lhau lhaux lhax */
2504 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2505 /* lhz lhzu lhzux lhzx */
2506 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2507 /* lwz lwzu lwzux lwzx */
2508 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2509 #if defined(TARGET_PPC64)
2510 /* lwaux */
2511 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2512 /* lwax */
2513 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2514 /* ldux */
2515 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2516 /* ldx */
2517 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2518 
2519 /* CI load/store variants */
2520 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2521 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2522 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2523 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2524 
2525 static void gen_ld(DisasContext *ctx)
2526 {
2527     TCGv EA;
2528     if (Rc(ctx->opcode)) {
2529         if (unlikely(rA(ctx->opcode) == 0 ||
2530                      rA(ctx->opcode) == rD(ctx->opcode))) {
2531             gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2532             return;
2533         }
2534     }
2535     gen_set_access_type(ctx, ACCESS_INT);
2536     EA = tcg_temp_new();
2537     gen_addr_imm_index(ctx, EA, 0x03);
2538     if (ctx->opcode & 0x02) {
2539         /* lwa (lwau is undefined) */
2540         gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2541     } else {
2542         /* ld - ldu */
2543         gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2544     }
2545     if (Rc(ctx->opcode))
2546         tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2547     tcg_temp_free(EA);
2548 }
2549 
2550 /* lq */
2551 static void gen_lq(DisasContext *ctx)
2552 {
2553     int ra, rd;
2554     TCGv EA;
2555 
2556     /* lq is a legal user mode instruction starting in ISA 2.07 */
2557     bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2558     bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2559 
2560     if (!legal_in_user_mode && ctx->pr) {
2561         gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2562         return;
2563     }
2564 
2565     if (!le_is_supported && ctx->le_mode) {
2566         gen_align_no_le(ctx);
2567         return;
2568     }
2569     ra = rA(ctx->opcode);
2570     rd = rD(ctx->opcode);
2571     if (unlikely((rd & 1) || rd == ra)) {
2572         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2573         return;
2574     }
2575 
2576     gen_set_access_type(ctx, ACCESS_INT);
2577     EA = tcg_temp_new();
2578     gen_addr_imm_index(ctx, EA, 0x0F);
2579 
2580     /* We only need to swap high and low halves. gen_qemu_ld64_i64 does
2581        necessary 64-bit byteswap already. */
2582     if (unlikely(ctx->le_mode)) {
2583         gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2584         gen_addr_add(ctx, EA, EA, 8);
2585         gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2586     } else {
2587         gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2588         gen_addr_add(ctx, EA, EA, 8);
2589         gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2590     }
2591     tcg_temp_free(EA);
2592 }
2593 #endif
2594 
2595 /***                              Integer store                            ***/
2596 #define GEN_ST(name, stop, opc, type)                                         \
2597 static void glue(gen_, name)(DisasContext *ctx)                                       \
2598 {                                                                             \
2599     TCGv EA;                                                                  \
2600     gen_set_access_type(ctx, ACCESS_INT);                                     \
2601     EA = tcg_temp_new();                                                      \
2602     gen_addr_imm_index(ctx, EA, 0);                                           \
2603     gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2604     tcg_temp_free(EA);                                                        \
2605 }
2606 
2607 #define GEN_STU(name, stop, opc, type)                                        \
2608 static void glue(gen_, stop##u)(DisasContext *ctx)                                    \
2609 {                                                                             \
2610     TCGv EA;                                                                  \
2611     if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2612         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2613         return;                                                               \
2614     }                                                                         \
2615     gen_set_access_type(ctx, ACCESS_INT);                                     \
2616     EA = tcg_temp_new();                                                      \
2617     if (type == PPC_64B)                                                      \
2618         gen_addr_imm_index(ctx, EA, 0x03);                                    \
2619     else                                                                      \
2620         gen_addr_imm_index(ctx, EA, 0);                                       \
2621     gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2622     tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2623     tcg_temp_free(EA);                                                        \
2624 }
2625 
2626 #define GEN_STUX(name, stop, opc2, opc3, type)                                \
2627 static void glue(gen_, name##ux)(DisasContext *ctx)                                   \
2628 {                                                                             \
2629     TCGv EA;                                                                  \
2630     if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2631         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2632         return;                                                               \
2633     }                                                                         \
2634     gen_set_access_type(ctx, ACCESS_INT);                                     \
2635     EA = tcg_temp_new();                                                      \
2636     gen_addr_reg_index(ctx, EA);                                              \
2637     gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2638     tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2639     tcg_temp_free(EA);                                                        \
2640 }
2641 
2642 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk)                   \
2643 static void glue(gen_, name##x)(DisasContext *ctx)                            \
2644 {                                                                             \
2645     TCGv EA;                                                                  \
2646     chk;                                                                      \
2647     gen_set_access_type(ctx, ACCESS_INT);                                     \
2648     EA = tcg_temp_new();                                                      \
2649     gen_addr_reg_index(ctx, EA);                                              \
2650     gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2651     tcg_temp_free(EA);                                                        \
2652 }
2653 #define GEN_STX(name, stop, opc2, opc3, type)                                 \
2654     GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2655 
2656 #define GEN_STX_HVRM(name, stop, opc2, opc3, type)                            \
2657     GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2658 
2659 #define GEN_STS(name, stop, op, type)                                         \
2660 GEN_ST(name, stop, op | 0x20, type);                                          \
2661 GEN_STU(name, stop, op | 0x21, type);                                         \
2662 GEN_STUX(name, stop, 0x17, op | 0x01, type);                                  \
2663 GEN_STX(name, stop, 0x17, op | 0x00, type)
2664 
2665 /* stb stbu stbux stbx */
2666 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2667 /* sth sthu sthux sthx */
2668 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2669 /* stw stwu stwux stwx */
2670 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2671 #if defined(TARGET_PPC64)
2672 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2673 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2674 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2675 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2676 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2677 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2678 
2679 static void gen_std(DisasContext *ctx)
2680 {
2681     int rs;
2682     TCGv EA;
2683 
2684     rs = rS(ctx->opcode);
2685     if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2686         bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2687         bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2688 
2689         if (!(ctx->insns_flags & PPC_64BX)) {
2690             gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2691         }
2692 
2693         if (!legal_in_user_mode && ctx->pr) {
2694             gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2695             return;
2696         }
2697 
2698         if (!le_is_supported && ctx->le_mode) {
2699             gen_align_no_le(ctx);
2700             return;
2701         }
2702 
2703         if (unlikely(rs & 1)) {
2704             gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2705             return;
2706         }
2707         gen_set_access_type(ctx, ACCESS_INT);
2708         EA = tcg_temp_new();
2709         gen_addr_imm_index(ctx, EA, 0x03);
2710 
2711         /* We only need to swap high and low halves. gen_qemu_st64_i64 does
2712            necessary 64-bit byteswap already. */
2713         if (unlikely(ctx->le_mode)) {
2714             gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2715             gen_addr_add(ctx, EA, EA, 8);
2716             gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2717         } else {
2718             gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2719             gen_addr_add(ctx, EA, EA, 8);
2720             gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2721         }
2722         tcg_temp_free(EA);
2723     } else {
2724         /* std / stdu*/
2725         if (Rc(ctx->opcode)) {
2726             if (unlikely(rA(ctx->opcode) == 0)) {
2727                 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2728                 return;
2729             }
2730         }
2731         gen_set_access_type(ctx, ACCESS_INT);
2732         EA = tcg_temp_new();
2733         gen_addr_imm_index(ctx, EA, 0x03);
2734         gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2735         if (Rc(ctx->opcode))
2736             tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2737         tcg_temp_free(EA);
2738     }
2739 }
2740 #endif
2741 /***                Integer load and store with byte reverse               ***/
2742 
2743 /* lhbrx */
2744 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2745 
2746 /* lwbrx */
2747 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2748 
2749 #if defined(TARGET_PPC64)
2750 /* ldbrx */
2751 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2752 /* stdbrx */
2753 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2754 #endif  /* TARGET_PPC64 */
2755 
2756 /* sthbrx */
2757 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2758 /* stwbrx */
2759 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2760 
2761 /***                    Integer load and store multiple                    ***/
2762 
2763 /* lmw */
2764 static void gen_lmw(DisasContext *ctx)
2765 {
2766     TCGv t0;
2767     TCGv_i32 t1;
2768 
2769     if (ctx->le_mode) {
2770         gen_align_no_le(ctx);
2771         return;
2772     }
2773     gen_set_access_type(ctx, ACCESS_INT);
2774     t0 = tcg_temp_new();
2775     t1 = tcg_const_i32(rD(ctx->opcode));
2776     gen_addr_imm_index(ctx, t0, 0);
2777     gen_helper_lmw(cpu_env, t0, t1);
2778     tcg_temp_free(t0);
2779     tcg_temp_free_i32(t1);
2780 }
2781 
2782 /* stmw */
2783 static void gen_stmw(DisasContext *ctx)
2784 {
2785     TCGv t0;
2786     TCGv_i32 t1;
2787 
2788     if (ctx->le_mode) {
2789         gen_align_no_le(ctx);
2790         return;
2791     }
2792     gen_set_access_type(ctx, ACCESS_INT);
2793     t0 = tcg_temp_new();
2794     t1 = tcg_const_i32(rS(ctx->opcode));
2795     gen_addr_imm_index(ctx, t0, 0);
2796     gen_helper_stmw(cpu_env, t0, t1);
2797     tcg_temp_free(t0);
2798     tcg_temp_free_i32(t1);
2799 }
2800 
2801 /***                    Integer load and store strings                     ***/
2802 
2803 /* lswi */
2804 /* PowerPC32 specification says we must generate an exception if
2805  * rA is in the range of registers to be loaded.
2806  * In an other hand, IBM says this is valid, but rA won't be loaded.
2807  * For now, I'll follow the spec...
2808  */
2809 static void gen_lswi(DisasContext *ctx)
2810 {
2811     TCGv t0;
2812     TCGv_i32 t1, t2;
2813     int nb = NB(ctx->opcode);
2814     int start = rD(ctx->opcode);
2815     int ra = rA(ctx->opcode);
2816     int nr;
2817 
2818     if (ctx->le_mode) {
2819         gen_align_no_le(ctx);
2820         return;
2821     }
2822     if (nb == 0)
2823         nb = 32;
2824     nr = (nb + 3) / 4;
2825     if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2826         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2827         return;
2828     }
2829     gen_set_access_type(ctx, ACCESS_INT);
2830     t0 = tcg_temp_new();
2831     gen_addr_register(ctx, t0);
2832     t1 = tcg_const_i32(nb);
2833     t2 = tcg_const_i32(start);
2834     gen_helper_lsw(cpu_env, t0, t1, t2);
2835     tcg_temp_free(t0);
2836     tcg_temp_free_i32(t1);
2837     tcg_temp_free_i32(t2);
2838 }
2839 
2840 /* lswx */
2841 static void gen_lswx(DisasContext *ctx)
2842 {
2843     TCGv t0;
2844     TCGv_i32 t1, t2, t3;
2845 
2846     if (ctx->le_mode) {
2847         gen_align_no_le(ctx);
2848         return;
2849     }
2850     gen_set_access_type(ctx, ACCESS_INT);
2851     t0 = tcg_temp_new();
2852     gen_addr_reg_index(ctx, t0);
2853     t1 = tcg_const_i32(rD(ctx->opcode));
2854     t2 = tcg_const_i32(rA(ctx->opcode));
2855     t3 = tcg_const_i32(rB(ctx->opcode));
2856     gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2857     tcg_temp_free(t0);
2858     tcg_temp_free_i32(t1);
2859     tcg_temp_free_i32(t2);
2860     tcg_temp_free_i32(t3);
2861 }
2862 
2863 /* stswi */
2864 static void gen_stswi(DisasContext *ctx)
2865 {
2866     TCGv t0;
2867     TCGv_i32 t1, t2;
2868     int nb = NB(ctx->opcode);
2869 
2870     if (ctx->le_mode) {
2871         gen_align_no_le(ctx);
2872         return;
2873     }
2874     gen_set_access_type(ctx, ACCESS_INT);
2875     t0 = tcg_temp_new();
2876     gen_addr_register(ctx, t0);
2877     if (nb == 0)
2878         nb = 32;
2879     t1 = tcg_const_i32(nb);
2880     t2 = tcg_const_i32(rS(ctx->opcode));
2881     gen_helper_stsw(cpu_env, t0, t1, t2);
2882     tcg_temp_free(t0);
2883     tcg_temp_free_i32(t1);
2884     tcg_temp_free_i32(t2);
2885 }
2886 
2887 /* stswx */
2888 static void gen_stswx(DisasContext *ctx)
2889 {
2890     TCGv t0;
2891     TCGv_i32 t1, t2;
2892 
2893     if (ctx->le_mode) {
2894         gen_align_no_le(ctx);
2895         return;
2896     }
2897     gen_set_access_type(ctx, ACCESS_INT);
2898     t0 = tcg_temp_new();
2899     gen_addr_reg_index(ctx, t0);
2900     t1 = tcg_temp_new_i32();
2901     tcg_gen_trunc_tl_i32(t1, cpu_xer);
2902     tcg_gen_andi_i32(t1, t1, 0x7F);
2903     t2 = tcg_const_i32(rS(ctx->opcode));
2904     gen_helper_stsw(cpu_env, t0, t1, t2);
2905     tcg_temp_free(t0);
2906     tcg_temp_free_i32(t1);
2907     tcg_temp_free_i32(t2);
2908 }
2909 
2910 /***                        Memory synchronisation                         ***/
2911 /* eieio */
2912 static void gen_eieio(DisasContext *ctx)
2913 {
2914 }
2915 
2916 #if !defined(CONFIG_USER_ONLY)
2917 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
2918 {
2919     TCGv_i32 t;
2920     TCGLabel *l;
2921 
2922     if (!ctx->lazy_tlb_flush) {
2923         return;
2924     }
2925     l = gen_new_label();
2926     t = tcg_temp_new_i32();
2927     tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
2928     tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
2929     if (global) {
2930         gen_helper_check_tlb_flush_global(cpu_env);
2931     } else {
2932         gen_helper_check_tlb_flush_local(cpu_env);
2933     }
2934     gen_set_label(l);
2935     tcg_temp_free_i32(t);
2936 }
2937 #else
2938 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
2939 #endif
2940 
2941 /* isync */
2942 static void gen_isync(DisasContext *ctx)
2943 {
2944     /*
2945      * We need to check for a pending TLB flush. This can only happen in
2946      * kernel mode however so check MSR_PR
2947      */
2948     if (!ctx->pr) {
2949         gen_check_tlb_flush(ctx, false);
2950     }
2951     gen_stop_exception(ctx);
2952 }
2953 
2954 #define MEMOP_GET_SIZE(x)  (1 << ((x) & MO_SIZE))
2955 
2956 #define LARX(name, memop)                                            \
2957 static void gen_##name(DisasContext *ctx)                            \
2958 {                                                                    \
2959     TCGv t0;                                                         \
2960     TCGv gpr = cpu_gpr[rD(ctx->opcode)];                             \
2961     int len = MEMOP_GET_SIZE(memop);                                 \
2962     gen_set_access_type(ctx, ACCESS_RES);                            \
2963     t0 = tcg_temp_local_new();                                       \
2964     gen_addr_reg_index(ctx, t0);                                     \
2965     if ((len) > 1) {                                                 \
2966         gen_check_align(ctx, t0, (len)-1);                           \
2967     }                                                                \
2968     tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop);                \
2969     tcg_gen_mov_tl(cpu_reserve, t0);                                 \
2970     tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
2971     tcg_temp_free(t0);                                               \
2972 }
2973 
2974 /* lwarx */
2975 LARX(lbarx, DEF_MEMOP(MO_UB))
2976 LARX(lharx, DEF_MEMOP(MO_UW))
2977 LARX(lwarx, DEF_MEMOP(MO_UL))
2978 
2979 #if defined(CONFIG_USER_ONLY)
2980 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
2981                                   int reg, int memop)
2982 {
2983     TCGv t0 = tcg_temp_new();
2984 
2985     tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
2986     tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
2987     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
2988     tcg_temp_free(t0);
2989     gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
2990 }
2991 #else
2992 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
2993                                   int reg, int memop)
2994 {
2995     TCGLabel *l1;
2996 
2997     tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
2998     l1 = gen_new_label();
2999     tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3000     tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3001     tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop);
3002     gen_set_label(l1);
3003     tcg_gen_movi_tl(cpu_reserve, -1);
3004 }
3005 #endif
3006 
3007 #define STCX(name, memop)                                   \
3008 static void gen_##name(DisasContext *ctx)                   \
3009 {                                                           \
3010     TCGv t0;                                                \
3011     int len = MEMOP_GET_SIZE(memop);                        \
3012     gen_set_access_type(ctx, ACCESS_RES);                   \
3013     t0 = tcg_temp_local_new();                              \
3014     gen_addr_reg_index(ctx, t0);                            \
3015     if (len > 1) {                                          \
3016         gen_check_align(ctx, t0, (len) - 1);                \
3017     }                                                       \
3018     gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
3019     tcg_temp_free(t0);                                      \
3020 }
3021 
3022 STCX(stbcx_, DEF_MEMOP(MO_UB))
3023 STCX(sthcx_, DEF_MEMOP(MO_UW))
3024 STCX(stwcx_, DEF_MEMOP(MO_UL))
3025 
3026 #if defined(TARGET_PPC64)
3027 /* ldarx */
3028 LARX(ldarx, DEF_MEMOP(MO_Q))
3029 /* stdcx. */
3030 STCX(stdcx_, DEF_MEMOP(MO_Q))
3031 
3032 /* lqarx */
3033 static void gen_lqarx(DisasContext *ctx)
3034 {
3035     TCGv EA;
3036     int rd = rD(ctx->opcode);
3037     TCGv gpr1, gpr2;
3038 
3039     if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3040                  (rd == rB(ctx->opcode)))) {
3041         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3042         return;
3043     }
3044 
3045     gen_set_access_type(ctx, ACCESS_RES);
3046     EA = tcg_temp_local_new();
3047     gen_addr_reg_index(ctx, EA);
3048     gen_check_align(ctx, EA, 15);
3049     if (unlikely(ctx->le_mode)) {
3050         gpr1 = cpu_gpr[rd+1];
3051         gpr2 = cpu_gpr[rd];
3052     } else {
3053         gpr1 = cpu_gpr[rd];
3054         gpr2 = cpu_gpr[rd+1];
3055     }
3056     tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3057     tcg_gen_mov_tl(cpu_reserve, EA);
3058     gen_addr_add(ctx, EA, EA, 8);
3059     tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3060 
3061     tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3062     tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3063     tcg_temp_free(EA);
3064 }
3065 
3066 /* stqcx. */
3067 static void gen_stqcx_(DisasContext *ctx)
3068 {
3069     TCGv EA;
3070     int reg = rS(ctx->opcode);
3071     int len = 16;
3072 #if !defined(CONFIG_USER_ONLY)
3073     TCGLabel *l1;
3074     TCGv gpr1, gpr2;
3075 #endif
3076 
3077     if (unlikely((rD(ctx->opcode) & 1))) {
3078         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3079         return;
3080     }
3081     gen_set_access_type(ctx, ACCESS_RES);
3082     EA = tcg_temp_local_new();
3083     gen_addr_reg_index(ctx, EA);
3084     if (len > 1) {
3085         gen_check_align(ctx, EA, (len) - 1);
3086     }
3087 
3088 #if defined(CONFIG_USER_ONLY)
3089     gen_conditional_store(ctx, EA, reg, 16);
3090 #else
3091     tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3092     l1 = gen_new_label();
3093     tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3094     tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3095 
3096     if (unlikely(ctx->le_mode)) {
3097         gpr1 = cpu_gpr[reg + 1];
3098         gpr2 = cpu_gpr[reg];
3099     } else {
3100         gpr1 = cpu_gpr[reg];
3101         gpr2 = cpu_gpr[reg + 1];
3102     }
3103     tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3104     gen_addr_add(ctx, EA, EA, 8);
3105     tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3106 
3107     gen_set_label(l1);
3108     tcg_gen_movi_tl(cpu_reserve, -1);
3109 #endif
3110     tcg_temp_free(EA);
3111 }
3112 
3113 #endif /* defined(TARGET_PPC64) */
3114 
3115 /* sync */
3116 static void gen_sync(DisasContext *ctx)
3117 {
3118     uint32_t l = (ctx->opcode >> 21) & 3;
3119 
3120     /*
3121      * We may need to check for a pending TLB flush.
3122      *
3123      * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3124      *
3125      * Additionally, this can only happen in kernel mode however so
3126      * check MSR_PR as well.
3127      */
3128     if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3129         gen_check_tlb_flush(ctx, true);
3130     }
3131 }
3132 
3133 /* wait */
3134 static void gen_wait(DisasContext *ctx)
3135 {
3136     TCGv_i32 t0 = tcg_const_i32(1);
3137     tcg_gen_st_i32(t0, cpu_env,
3138                    -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3139     tcg_temp_free_i32(t0);
3140     /* Stop translation, as the CPU is supposed to sleep from now */
3141     gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3142 }
3143 
3144 #if defined(TARGET_PPC64)
3145 static void gen_doze(DisasContext *ctx)
3146 {
3147 #if defined(CONFIG_USER_ONLY)
3148     GEN_PRIV;
3149 #else
3150     TCGv_i32 t;
3151 
3152     CHK_HV;
3153     t = tcg_const_i32(PPC_PM_DOZE);
3154     gen_helper_pminsn(cpu_env, t);
3155     tcg_temp_free_i32(t);
3156     gen_stop_exception(ctx);
3157 #endif /* defined(CONFIG_USER_ONLY) */
3158 }
3159 
3160 static void gen_nap(DisasContext *ctx)
3161 {
3162 #if defined(CONFIG_USER_ONLY)
3163     GEN_PRIV;
3164 #else
3165     TCGv_i32 t;
3166 
3167     CHK_HV;
3168     t = tcg_const_i32(PPC_PM_NAP);
3169     gen_helper_pminsn(cpu_env, t);
3170     tcg_temp_free_i32(t);
3171     gen_stop_exception(ctx);
3172 #endif /* defined(CONFIG_USER_ONLY) */
3173 }
3174 
3175 static void gen_stop(DisasContext *ctx)
3176 {
3177     gen_nap(ctx);
3178 }
3179 
3180 static void gen_sleep(DisasContext *ctx)
3181 {
3182 #if defined(CONFIG_USER_ONLY)
3183     GEN_PRIV;
3184 #else
3185     TCGv_i32 t;
3186 
3187     CHK_HV;
3188     t = tcg_const_i32(PPC_PM_SLEEP);
3189     gen_helper_pminsn(cpu_env, t);
3190     tcg_temp_free_i32(t);
3191     gen_stop_exception(ctx);
3192 #endif /* defined(CONFIG_USER_ONLY) */
3193 }
3194 
3195 static void gen_rvwinkle(DisasContext *ctx)
3196 {
3197 #if defined(CONFIG_USER_ONLY)
3198     GEN_PRIV;
3199 #else
3200     TCGv_i32 t;
3201 
3202     CHK_HV;
3203     t = tcg_const_i32(PPC_PM_RVWINKLE);
3204     gen_helper_pminsn(cpu_env, t);
3205     tcg_temp_free_i32(t);
3206     gen_stop_exception(ctx);
3207 #endif /* defined(CONFIG_USER_ONLY) */
3208 }
3209 #endif /* #if defined(TARGET_PPC64) */
3210 
3211 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3212 {
3213 #if defined(TARGET_PPC64)
3214     if (ctx->has_cfar)
3215         tcg_gen_movi_tl(cpu_cfar, nip);
3216 #endif
3217 }
3218 
3219 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3220 {
3221     if (unlikely(ctx->singlestep_enabled)) {
3222         return false;
3223     }
3224 
3225 #ifndef CONFIG_USER_ONLY
3226     return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3227 #else
3228     return true;
3229 #endif
3230 }
3231 
3232 /***                                Branch                                 ***/
3233 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3234 {
3235     if (NARROW_MODE(ctx)) {
3236         dest = (uint32_t) dest;
3237     }
3238     if (use_goto_tb(ctx, dest)) {
3239         tcg_gen_goto_tb(n);
3240         tcg_gen_movi_tl(cpu_nip, dest & ~3);
3241         tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3242     } else {
3243         tcg_gen_movi_tl(cpu_nip, dest & ~3);
3244         if (unlikely(ctx->singlestep_enabled)) {
3245             if ((ctx->singlestep_enabled &
3246                 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3247                 (ctx->exception == POWERPC_EXCP_BRANCH ||
3248                  ctx->exception == POWERPC_EXCP_TRACE)) {
3249                 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3250             }
3251             if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3252                 gen_debug_exception(ctx);
3253             }
3254         }
3255         tcg_gen_exit_tb(0);
3256     }
3257 }
3258 
3259 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3260 {
3261     if (NARROW_MODE(ctx)) {
3262         nip = (uint32_t)nip;
3263     }
3264     tcg_gen_movi_tl(cpu_lr, nip);
3265 }
3266 
3267 /* b ba bl bla */
3268 static void gen_b(DisasContext *ctx)
3269 {
3270     target_ulong li, target;
3271 
3272     ctx->exception = POWERPC_EXCP_BRANCH;
3273     /* sign extend LI */
3274     li = LI(ctx->opcode);
3275     li = (li ^ 0x02000000) - 0x02000000;
3276     if (likely(AA(ctx->opcode) == 0)) {
3277         target = ctx->nip + li - 4;
3278     } else {
3279         target = li;
3280     }
3281     if (LK(ctx->opcode)) {
3282         gen_setlr(ctx, ctx->nip);
3283     }
3284     gen_update_cfar(ctx, ctx->nip - 4);
3285     gen_goto_tb(ctx, 0, target);
3286 }
3287 
3288 #define BCOND_IM  0
3289 #define BCOND_LR  1
3290 #define BCOND_CTR 2
3291 #define BCOND_TAR 3
3292 
3293 static inline void gen_bcond(DisasContext *ctx, int type)
3294 {
3295     uint32_t bo = BO(ctx->opcode);
3296     TCGLabel *l1;
3297     TCGv target;
3298 
3299     ctx->exception = POWERPC_EXCP_BRANCH;
3300     if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3301         target = tcg_temp_local_new();
3302         if (type == BCOND_CTR)
3303             tcg_gen_mov_tl(target, cpu_ctr);
3304         else if (type == BCOND_TAR)
3305             gen_load_spr(target, SPR_TAR);
3306         else
3307             tcg_gen_mov_tl(target, cpu_lr);
3308     } else {
3309         TCGV_UNUSED(target);
3310     }
3311     if (LK(ctx->opcode))
3312         gen_setlr(ctx, ctx->nip);
3313     l1 = gen_new_label();
3314     if ((bo & 0x4) == 0) {
3315         /* Decrement and test CTR */
3316         TCGv temp = tcg_temp_new();
3317         if (unlikely(type == BCOND_CTR)) {
3318             gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3319             return;
3320         }
3321         tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3322         if (NARROW_MODE(ctx)) {
3323             tcg_gen_ext32u_tl(temp, cpu_ctr);
3324         } else {
3325             tcg_gen_mov_tl(temp, cpu_ctr);
3326         }
3327         if (bo & 0x2) {
3328             tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3329         } else {
3330             tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3331         }
3332         tcg_temp_free(temp);
3333     }
3334     if ((bo & 0x10) == 0) {
3335         /* Test CR */
3336         uint32_t bi = BI(ctx->opcode);
3337         uint32_t mask = 0x08 >> (bi & 0x03);
3338         TCGv_i32 temp = tcg_temp_new_i32();
3339 
3340         if (bo & 0x8) {
3341             tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3342             tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3343         } else {
3344             tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3345             tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3346         }
3347         tcg_temp_free_i32(temp);
3348     }
3349     gen_update_cfar(ctx, ctx->nip - 4);
3350     if (type == BCOND_IM) {
3351         target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3352         if (likely(AA(ctx->opcode) == 0)) {
3353             gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3354         } else {
3355             gen_goto_tb(ctx, 0, li);
3356         }
3357         if ((bo & 0x14) != 0x14) {
3358             gen_set_label(l1);
3359             gen_goto_tb(ctx, 1, ctx->nip);
3360         }
3361     } else {
3362         if (NARROW_MODE(ctx)) {
3363             tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3364         } else {
3365             tcg_gen_andi_tl(cpu_nip, target, ~3);
3366         }
3367         tcg_gen_exit_tb(0);
3368         if ((bo & 0x14) != 0x14) {
3369             gen_set_label(l1);
3370             gen_update_nip(ctx, ctx->nip);
3371             tcg_gen_exit_tb(0);
3372         }
3373     }
3374     if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3375         tcg_temp_free(target);
3376     }
3377 }
3378 
3379 static void gen_bc(DisasContext *ctx)
3380 {
3381     gen_bcond(ctx, BCOND_IM);
3382 }
3383 
3384 static void gen_bcctr(DisasContext *ctx)
3385 {
3386     gen_bcond(ctx, BCOND_CTR);
3387 }
3388 
3389 static void gen_bclr(DisasContext *ctx)
3390 {
3391     gen_bcond(ctx, BCOND_LR);
3392 }
3393 
3394 static void gen_bctar(DisasContext *ctx)
3395 {
3396     gen_bcond(ctx, BCOND_TAR);
3397 }
3398 
3399 /***                      Condition register logical                       ***/
3400 #define GEN_CRLOGIC(name, tcg_op, opc)                                        \
3401 static void glue(gen_, name)(DisasContext *ctx)                                       \
3402 {                                                                             \
3403     uint8_t bitmask;                                                          \
3404     int sh;                                                                   \
3405     TCGv_i32 t0, t1;                                                          \
3406     sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
3407     t0 = tcg_temp_new_i32();                                                  \
3408     if (sh > 0)                                                               \
3409         tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh);            \
3410     else if (sh < 0)                                                          \
3411         tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh);           \
3412     else                                                                      \
3413         tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]);                 \
3414     t1 = tcg_temp_new_i32();                                                  \
3415     sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
3416     if (sh > 0)                                                               \
3417         tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh);            \
3418     else if (sh < 0)                                                          \
3419         tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh);           \
3420     else                                                                      \
3421         tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]);                 \
3422     tcg_op(t0, t0, t1);                                                       \
3423     bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03);                             \
3424     tcg_gen_andi_i32(t0, t0, bitmask);                                        \
3425     tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask);          \
3426     tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1);                  \
3427     tcg_temp_free_i32(t0);                                                    \
3428     tcg_temp_free_i32(t1);                                                    \
3429 }
3430 
3431 /* crand */
3432 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3433 /* crandc */
3434 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3435 /* creqv */
3436 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3437 /* crnand */
3438 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3439 /* crnor */
3440 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3441 /* cror */
3442 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3443 /* crorc */
3444 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3445 /* crxor */
3446 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3447 
3448 /* mcrf */
3449 static void gen_mcrf(DisasContext *ctx)
3450 {
3451     tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3452 }
3453 
3454 /***                           System linkage                              ***/
3455 
3456 /* rfi (supervisor only) */
3457 static void gen_rfi(DisasContext *ctx)
3458 {
3459 #if defined(CONFIG_USER_ONLY)
3460     GEN_PRIV;
3461 #else
3462     /* This instruction doesn't exist anymore on 64-bit server
3463      * processors compliant with arch 2.x
3464      */
3465     if (ctx->insns_flags & PPC_SEGMENT_64B) {
3466         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3467         return;
3468     }
3469     /* Restore CPU state */
3470     CHK_SV;
3471     gen_update_cfar(ctx, ctx->nip - 4);
3472     gen_helper_rfi(cpu_env);
3473     gen_sync_exception(ctx);
3474 #endif
3475 }
3476 
3477 #if defined(TARGET_PPC64)
3478 static void gen_rfid(DisasContext *ctx)
3479 {
3480 #if defined(CONFIG_USER_ONLY)
3481     GEN_PRIV;
3482 #else
3483     /* Restore CPU state */
3484     CHK_SV;
3485     gen_update_cfar(ctx, ctx->nip - 4);
3486     gen_helper_rfid(cpu_env);
3487     gen_sync_exception(ctx);
3488 #endif
3489 }
3490 
3491 static void gen_hrfid(DisasContext *ctx)
3492 {
3493 #if defined(CONFIG_USER_ONLY)
3494     GEN_PRIV;
3495 #else
3496     /* Restore CPU state */
3497     CHK_HV;
3498     gen_helper_hrfid(cpu_env);
3499     gen_sync_exception(ctx);
3500 #endif
3501 }
3502 #endif
3503 
3504 /* sc */
3505 #if defined(CONFIG_USER_ONLY)
3506 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3507 #else
3508 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3509 #endif
3510 static void gen_sc(DisasContext *ctx)
3511 {
3512     uint32_t lev;
3513 
3514     lev = (ctx->opcode >> 5) & 0x7F;
3515     gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3516 }
3517 
3518 /***                                Trap                                   ***/
3519 
3520 /* Check for unconditional traps (always or never) */
3521 static bool check_unconditional_trap(DisasContext *ctx)
3522 {
3523     /* Trap never */
3524     if (TO(ctx->opcode) == 0) {
3525         return true;
3526     }
3527     /* Trap always */
3528     if (TO(ctx->opcode) == 31) {
3529         gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3530         return true;
3531     }
3532     return false;
3533 }
3534 
3535 /* tw */
3536 static void gen_tw(DisasContext *ctx)
3537 {
3538     TCGv_i32 t0;
3539 
3540     if (check_unconditional_trap(ctx)) {
3541         return;
3542     }
3543     t0 = tcg_const_i32(TO(ctx->opcode));
3544     gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3545                   t0);
3546     tcg_temp_free_i32(t0);
3547 }
3548 
3549 /* twi */
3550 static void gen_twi(DisasContext *ctx)
3551 {
3552     TCGv t0;
3553     TCGv_i32 t1;
3554 
3555     if (check_unconditional_trap(ctx)) {
3556         return;
3557     }
3558     t0 = tcg_const_tl(SIMM(ctx->opcode));
3559     t1 = tcg_const_i32(TO(ctx->opcode));
3560     gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3561     tcg_temp_free(t0);
3562     tcg_temp_free_i32(t1);
3563 }
3564 
3565 #if defined(TARGET_PPC64)
3566 /* td */
3567 static void gen_td(DisasContext *ctx)
3568 {
3569     TCGv_i32 t0;
3570 
3571     if (check_unconditional_trap(ctx)) {
3572         return;
3573     }
3574     t0 = tcg_const_i32(TO(ctx->opcode));
3575     gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3576                   t0);
3577     tcg_temp_free_i32(t0);
3578 }
3579 
3580 /* tdi */
3581 static void gen_tdi(DisasContext *ctx)
3582 {
3583     TCGv t0;
3584     TCGv_i32 t1;
3585 
3586     if (check_unconditional_trap(ctx)) {
3587         return;
3588     }
3589     t0 = tcg_const_tl(SIMM(ctx->opcode));
3590     t1 = tcg_const_i32(TO(ctx->opcode));
3591     gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3592     tcg_temp_free(t0);
3593     tcg_temp_free_i32(t1);
3594 }
3595 #endif
3596 
3597 /***                          Processor control                            ***/
3598 
3599 static void gen_read_xer(TCGv dst)
3600 {
3601     TCGv t0 = tcg_temp_new();
3602     TCGv t1 = tcg_temp_new();
3603     TCGv t2 = tcg_temp_new();
3604     tcg_gen_mov_tl(dst, cpu_xer);
3605     tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3606     tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3607     tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3608     tcg_gen_or_tl(t0, t0, t1);
3609     tcg_gen_or_tl(dst, dst, t2);
3610     tcg_gen_or_tl(dst, dst, t0);
3611     tcg_temp_free(t0);
3612     tcg_temp_free(t1);
3613     tcg_temp_free(t2);
3614 }
3615 
3616 static void gen_write_xer(TCGv src)
3617 {
3618     tcg_gen_andi_tl(cpu_xer, src,
3619                     ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3620     tcg_gen_shri_tl(cpu_so, src, XER_SO);
3621     tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3622     tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3623     tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3624     tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3625     tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3626 }
3627 
3628 /* mcrxr */
3629 static void gen_mcrxr(DisasContext *ctx)
3630 {
3631     TCGv_i32 t0 = tcg_temp_new_i32();
3632     TCGv_i32 t1 = tcg_temp_new_i32();
3633     TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3634 
3635     tcg_gen_trunc_tl_i32(t0, cpu_so);
3636     tcg_gen_trunc_tl_i32(t1, cpu_ov);
3637     tcg_gen_trunc_tl_i32(dst, cpu_ca);
3638     tcg_gen_shli_i32(t0, t0, 3);
3639     tcg_gen_shli_i32(t1, t1, 2);
3640     tcg_gen_shli_i32(dst, dst, 1);
3641     tcg_gen_or_i32(dst, dst, t0);
3642     tcg_gen_or_i32(dst, dst, t1);
3643     tcg_temp_free_i32(t0);
3644     tcg_temp_free_i32(t1);
3645 
3646     tcg_gen_movi_tl(cpu_so, 0);
3647     tcg_gen_movi_tl(cpu_ov, 0);
3648     tcg_gen_movi_tl(cpu_ca, 0);
3649 }
3650 
3651 /* mfcr mfocrf */
3652 static void gen_mfcr(DisasContext *ctx)
3653 {
3654     uint32_t crm, crn;
3655 
3656     if (likely(ctx->opcode & 0x00100000)) {
3657         crm = CRM(ctx->opcode);
3658         if (likely(crm && ((crm & (crm - 1)) == 0))) {
3659             crn = ctz32 (crm);
3660             tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3661             tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3662                             cpu_gpr[rD(ctx->opcode)], crn * 4);
3663         }
3664     } else {
3665         TCGv_i32 t0 = tcg_temp_new_i32();
3666         tcg_gen_mov_i32(t0, cpu_crf[0]);
3667         tcg_gen_shli_i32(t0, t0, 4);
3668         tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3669         tcg_gen_shli_i32(t0, t0, 4);
3670         tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3671         tcg_gen_shli_i32(t0, t0, 4);
3672         tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3673         tcg_gen_shli_i32(t0, t0, 4);
3674         tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3675         tcg_gen_shli_i32(t0, t0, 4);
3676         tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3677         tcg_gen_shli_i32(t0, t0, 4);
3678         tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3679         tcg_gen_shli_i32(t0, t0, 4);
3680         tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3681         tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3682         tcg_temp_free_i32(t0);
3683     }
3684 }
3685 
3686 /* mfmsr */
3687 static void gen_mfmsr(DisasContext *ctx)
3688 {
3689     CHK_SV;
3690     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3691 }
3692 
3693 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3694 {
3695 #if 0
3696     sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3697     printf("ERROR: try to access SPR %d !\n", sprn);
3698 #endif
3699 }
3700 #define SPR_NOACCESS (&spr_noaccess)
3701 
3702 /* mfspr */
3703 static inline void gen_op_mfspr(DisasContext *ctx)
3704 {
3705     void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3706     uint32_t sprn = SPR(ctx->opcode);
3707 
3708 #if defined(CONFIG_USER_ONLY)
3709     read_cb = ctx->spr_cb[sprn].uea_read;
3710 #else
3711     if (ctx->pr) {
3712         read_cb = ctx->spr_cb[sprn].uea_read;
3713     } else if (ctx->hv) {
3714         read_cb = ctx->spr_cb[sprn].hea_read;
3715     } else {
3716         read_cb = ctx->spr_cb[sprn].oea_read;
3717     }
3718 #endif
3719     if (likely(read_cb != NULL)) {
3720         if (likely(read_cb != SPR_NOACCESS)) {
3721             (*read_cb)(ctx, rD(ctx->opcode), sprn);
3722         } else {
3723             /* Privilege exception */
3724             /* This is a hack to avoid warnings when running Linux:
3725              * this OS breaks the PowerPC virtualisation model,
3726              * allowing userland application to read the PVR
3727              */
3728             if (sprn != SPR_PVR) {
3729                 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3730                         TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3731                 if (qemu_log_separate()) {
3732                     qemu_log("Trying to read privileged spr %d (0x%03x) at "
3733                              TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3734                 }
3735             }
3736             gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3737         }
3738     } else {
3739         /* ISA 2.07 defines these as no-ops */
3740         if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3741             (sprn >= 808 && sprn <= 811)) {
3742             /* This is a nop */
3743             return;
3744         }
3745         /* Not defined */
3746         fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3747                 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3748         if (qemu_log_separate()) {
3749             qemu_log("Trying to read invalid spr %d (0x%03x) at "
3750                      TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3751         }
3752 
3753         /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3754          * it can generate a priv, a hv emu or a no-op
3755          */
3756         if (sprn & 0x10) {
3757             if (ctx->pr) {
3758                 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3759             }
3760         } else {
3761             if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3762                 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3763             }
3764         }
3765     }
3766 }
3767 
3768 static void gen_mfspr(DisasContext *ctx)
3769 {
3770     gen_op_mfspr(ctx);
3771 }
3772 
3773 /* mftb */
3774 static void gen_mftb(DisasContext *ctx)
3775 {
3776     gen_op_mfspr(ctx);
3777 }
3778 
3779 /* mtcrf mtocrf*/
3780 static void gen_mtcrf(DisasContext *ctx)
3781 {
3782     uint32_t crm, crn;
3783 
3784     crm = CRM(ctx->opcode);
3785     if (likely((ctx->opcode & 0x00100000))) {
3786         if (crm && ((crm & (crm - 1)) == 0)) {
3787             TCGv_i32 temp = tcg_temp_new_i32();
3788             crn = ctz32 (crm);
3789             tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3790             tcg_gen_shri_i32(temp, temp, crn * 4);
3791             tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3792             tcg_temp_free_i32(temp);
3793         }
3794     } else {
3795         TCGv_i32 temp = tcg_temp_new_i32();
3796         tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3797         for (crn = 0 ; crn < 8 ; crn++) {
3798             if (crm & (1 << crn)) {
3799                     tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3800                     tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3801             }
3802         }
3803         tcg_temp_free_i32(temp);
3804     }
3805 }
3806 
3807 /* mtmsr */
3808 #if defined(TARGET_PPC64)
3809 static void gen_mtmsrd(DisasContext *ctx)
3810 {
3811     CHK_SV;
3812 
3813 #if !defined(CONFIG_USER_ONLY)
3814     if (ctx->opcode & 0x00010000) {
3815         /* Special form that does not need any synchronisation */
3816         TCGv t0 = tcg_temp_new();
3817         tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3818         tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3819         tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3820         tcg_temp_free(t0);
3821     } else {
3822         /* XXX: we need to update nip before the store
3823          *      if we enter power saving mode, we will exit the loop
3824          *      directly from ppc_store_msr
3825          */
3826         gen_update_nip(ctx, ctx->nip);
3827         gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3828         /* Must stop the translation as machine state (may have) changed */
3829         /* Note that mtmsr is not always defined as context-synchronizing */
3830         gen_stop_exception(ctx);
3831     }
3832 #endif /* !defined(CONFIG_USER_ONLY) */
3833 }
3834 #endif /* defined(TARGET_PPC64) */
3835 
3836 static void gen_mtmsr(DisasContext *ctx)
3837 {
3838     CHK_SV;
3839 
3840 #if !defined(CONFIG_USER_ONLY)
3841    if (ctx->opcode & 0x00010000) {
3842         /* Special form that does not need any synchronisation */
3843         TCGv t0 = tcg_temp_new();
3844         tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3845         tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3846         tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3847         tcg_temp_free(t0);
3848     } else {
3849         TCGv msr = tcg_temp_new();
3850 
3851         /* XXX: we need to update nip before the store
3852          *      if we enter power saving mode, we will exit the loop
3853          *      directly from ppc_store_msr
3854          */
3855         gen_update_nip(ctx, ctx->nip);
3856 #if defined(TARGET_PPC64)
3857         tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3858 #else
3859         tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3860 #endif
3861         gen_helper_store_msr(cpu_env, msr);
3862         tcg_temp_free(msr);
3863         /* Must stop the translation as machine state (may have) changed */
3864         /* Note that mtmsr is not always defined as context-synchronizing */
3865         gen_stop_exception(ctx);
3866     }
3867 #endif
3868 }
3869 
3870 /* mtspr */
3871 static void gen_mtspr(DisasContext *ctx)
3872 {
3873     void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
3874     uint32_t sprn = SPR(ctx->opcode);
3875 
3876 #if defined(CONFIG_USER_ONLY)
3877     write_cb = ctx->spr_cb[sprn].uea_write;
3878 #else
3879     if (ctx->pr) {
3880         write_cb = ctx->spr_cb[sprn].uea_write;
3881     } else if (ctx->hv) {
3882         write_cb = ctx->spr_cb[sprn].hea_write;
3883     } else {
3884         write_cb = ctx->spr_cb[sprn].oea_write;
3885     }
3886 #endif
3887     if (likely(write_cb != NULL)) {
3888         if (likely(write_cb != SPR_NOACCESS)) {
3889             (*write_cb)(ctx, sprn, rS(ctx->opcode));
3890         } else {
3891             /* Privilege exception */
3892             fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
3893                     TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3894             if (qemu_log_separate()) {
3895                 qemu_log("Trying to write privileged spr %d (0x%03x) at "
3896                          TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3897             }
3898             gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3899         }
3900     } else {
3901         /* ISA 2.07 defines these as no-ops */
3902         if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3903             (sprn >= 808 && sprn <= 811)) {
3904             /* This is a nop */
3905             return;
3906         }
3907 
3908         /* Not defined */
3909         if (qemu_log_separate()) {
3910             qemu_log("Trying to write invalid spr %d (0x%03x) at "
3911                      TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3912         }
3913         fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
3914                 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3915 
3916 
3917         /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3918          * it can generate a priv, a hv emu or a no-op
3919          */
3920         if (sprn & 0x10) {
3921             if (ctx->pr) {
3922                 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3923             }
3924         } else {
3925             if (ctx->pr || sprn == 0) {
3926                 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3927             }
3928         }
3929     }
3930 }
3931 
3932 #if defined(TARGET_PPC64)
3933 /* setb */
3934 static void gen_setb(DisasContext *ctx)
3935 {
3936     TCGv_i32 t0 = tcg_temp_new_i32();
3937     TCGv_i32 t8 = tcg_temp_new_i32();
3938     TCGv_i32 tm1 = tcg_temp_new_i32();
3939     int crf = crfS(ctx->opcode);
3940 
3941     tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
3942     tcg_gen_movi_i32(t8, 8);
3943     tcg_gen_movi_i32(tm1, -1);
3944     tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
3945     tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3946 
3947     tcg_temp_free_i32(t0);
3948     tcg_temp_free_i32(t8);
3949     tcg_temp_free_i32(tm1);
3950 }
3951 #endif
3952 
3953 /***                         Cache management                              ***/
3954 
3955 /* dcbf */
3956 static void gen_dcbf(DisasContext *ctx)
3957 {
3958     /* XXX: specification says this is treated as a load by the MMU */
3959     TCGv t0;
3960     gen_set_access_type(ctx, ACCESS_CACHE);
3961     t0 = tcg_temp_new();
3962     gen_addr_reg_index(ctx, t0);
3963     gen_qemu_ld8u(ctx, t0, t0);
3964     tcg_temp_free(t0);
3965 }
3966 
3967 /* dcbi (Supervisor only) */
3968 static void gen_dcbi(DisasContext *ctx)
3969 {
3970 #if defined(CONFIG_USER_ONLY)
3971     GEN_PRIV;
3972 #else
3973     TCGv EA, val;
3974 
3975     CHK_SV;
3976     EA = tcg_temp_new();
3977     gen_set_access_type(ctx, ACCESS_CACHE);
3978     gen_addr_reg_index(ctx, EA);
3979     val = tcg_temp_new();
3980     /* XXX: specification says this should be treated as a store by the MMU */
3981     gen_qemu_ld8u(ctx, val, EA);
3982     gen_qemu_st8(ctx, val, EA);
3983     tcg_temp_free(val);
3984     tcg_temp_free(EA);
3985 #endif /* defined(CONFIG_USER_ONLY) */
3986 }
3987 
3988 /* dcdst */
3989 static void gen_dcbst(DisasContext *ctx)
3990 {
3991     /* XXX: specification say this is treated as a load by the MMU */
3992     TCGv t0;
3993     gen_set_access_type(ctx, ACCESS_CACHE);
3994     t0 = tcg_temp_new();
3995     gen_addr_reg_index(ctx, t0);
3996     gen_qemu_ld8u(ctx, t0, t0);
3997     tcg_temp_free(t0);
3998 }
3999 
4000 /* dcbt */
4001 static void gen_dcbt(DisasContext *ctx)
4002 {
4003     /* interpreted as no-op */
4004     /* XXX: specification say this is treated as a load by the MMU
4005      *      but does not generate any exception
4006      */
4007 }
4008 
4009 /* dcbtst */
4010 static void gen_dcbtst(DisasContext *ctx)
4011 {
4012     /* interpreted as no-op */
4013     /* XXX: specification say this is treated as a load by the MMU
4014      *      but does not generate any exception
4015      */
4016 }
4017 
4018 /* dcbtls */
4019 static void gen_dcbtls(DisasContext *ctx)
4020 {
4021     /* Always fails locking the cache */
4022     TCGv t0 = tcg_temp_new();
4023     gen_load_spr(t0, SPR_Exxx_L1CSR0);
4024     tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4025     gen_store_spr(SPR_Exxx_L1CSR0, t0);
4026     tcg_temp_free(t0);
4027 }
4028 
4029 /* dcbz */
4030 static void gen_dcbz(DisasContext *ctx)
4031 {
4032     TCGv tcgv_addr;
4033     TCGv_i32 tcgv_op;
4034 
4035     gen_set_access_type(ctx, ACCESS_CACHE);
4036     tcgv_addr = tcg_temp_new();
4037     tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4038     gen_addr_reg_index(ctx, tcgv_addr);
4039     gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4040     tcg_temp_free(tcgv_addr);
4041     tcg_temp_free_i32(tcgv_op);
4042 }
4043 
4044 /* dst / dstt */
4045 static void gen_dst(DisasContext *ctx)
4046 {
4047     if (rA(ctx->opcode) == 0) {
4048         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4049     } else {
4050         /* interpreted as no-op */
4051     }
4052 }
4053 
4054 /* dstst /dststt */
4055 static void gen_dstst(DisasContext *ctx)
4056 {
4057     if (rA(ctx->opcode) == 0) {
4058         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4059     } else {
4060         /* interpreted as no-op */
4061     }
4062 
4063 }
4064 
4065 /* dss / dssall */
4066 static void gen_dss(DisasContext *ctx)
4067 {
4068     /* interpreted as no-op */
4069 }
4070 
4071 /* icbi */
4072 static void gen_icbi(DisasContext *ctx)
4073 {
4074     TCGv t0;
4075     gen_set_access_type(ctx, ACCESS_CACHE);
4076     t0 = tcg_temp_new();
4077     gen_addr_reg_index(ctx, t0);
4078     gen_helper_icbi(cpu_env, t0);
4079     tcg_temp_free(t0);
4080 }
4081 
4082 /* Optional: */
4083 /* dcba */
4084 static void gen_dcba(DisasContext *ctx)
4085 {
4086     /* interpreted as no-op */
4087     /* XXX: specification say this is treated as a store by the MMU
4088      *      but does not generate any exception
4089      */
4090 }
4091 
4092 /***                    Segment register manipulation                      ***/
4093 /* Supervisor only: */
4094 
4095 /* mfsr */
4096 static void gen_mfsr(DisasContext *ctx)
4097 {
4098 #if defined(CONFIG_USER_ONLY)
4099     GEN_PRIV;
4100 #else
4101     TCGv t0;
4102 
4103     CHK_SV;
4104     t0 = tcg_const_tl(SR(ctx->opcode));
4105     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4106     tcg_temp_free(t0);
4107 #endif /* defined(CONFIG_USER_ONLY) */
4108 }
4109 
4110 /* mfsrin */
4111 static void gen_mfsrin(DisasContext *ctx)
4112 {
4113 #if defined(CONFIG_USER_ONLY)
4114     GEN_PRIV;
4115 #else
4116     TCGv t0;
4117 
4118     CHK_SV;
4119     t0 = tcg_temp_new();
4120     tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4121     tcg_gen_andi_tl(t0, t0, 0xF);
4122     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4123     tcg_temp_free(t0);
4124 #endif /* defined(CONFIG_USER_ONLY) */
4125 }
4126 
4127 /* mtsr */
4128 static void gen_mtsr(DisasContext *ctx)
4129 {
4130 #if defined(CONFIG_USER_ONLY)
4131     GEN_PRIV;
4132 #else
4133     TCGv t0;
4134 
4135     CHK_SV;
4136     t0 = tcg_const_tl(SR(ctx->opcode));
4137     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4138     tcg_temp_free(t0);
4139 #endif /* defined(CONFIG_USER_ONLY) */
4140 }
4141 
4142 /* mtsrin */
4143 static void gen_mtsrin(DisasContext *ctx)
4144 {
4145 #if defined(CONFIG_USER_ONLY)
4146     GEN_PRIV;
4147 #else
4148     TCGv t0;
4149     CHK_SV;
4150 
4151     t0 = tcg_temp_new();
4152     tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4153     tcg_gen_andi_tl(t0, t0, 0xF);
4154     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4155     tcg_temp_free(t0);
4156 #endif /* defined(CONFIG_USER_ONLY) */
4157 }
4158 
4159 #if defined(TARGET_PPC64)
4160 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4161 
4162 /* mfsr */
4163 static void gen_mfsr_64b(DisasContext *ctx)
4164 {
4165 #if defined(CONFIG_USER_ONLY)
4166     GEN_PRIV;
4167 #else
4168     TCGv t0;
4169 
4170     CHK_SV;
4171     t0 = tcg_const_tl(SR(ctx->opcode));
4172     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4173     tcg_temp_free(t0);
4174 #endif /* defined(CONFIG_USER_ONLY) */
4175 }
4176 
4177 /* mfsrin */
4178 static void gen_mfsrin_64b(DisasContext *ctx)
4179 {
4180 #if defined(CONFIG_USER_ONLY)
4181     GEN_PRIV;
4182 #else
4183     TCGv t0;
4184 
4185     CHK_SV;
4186     t0 = tcg_temp_new();
4187     tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4188     tcg_gen_andi_tl(t0, t0, 0xF);
4189     gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4190     tcg_temp_free(t0);
4191 #endif /* defined(CONFIG_USER_ONLY) */
4192 }
4193 
4194 /* mtsr */
4195 static void gen_mtsr_64b(DisasContext *ctx)
4196 {
4197 #if defined(CONFIG_USER_ONLY)
4198     GEN_PRIV;
4199 #else
4200     TCGv t0;
4201 
4202     CHK_SV;
4203     t0 = tcg_const_tl(SR(ctx->opcode));
4204     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4205     tcg_temp_free(t0);
4206 #endif /* defined(CONFIG_USER_ONLY) */
4207 }
4208 
4209 /* mtsrin */
4210 static void gen_mtsrin_64b(DisasContext *ctx)
4211 {
4212 #if defined(CONFIG_USER_ONLY)
4213     GEN_PRIV;
4214 #else
4215     TCGv t0;
4216 
4217     CHK_SV;
4218     t0 = tcg_temp_new();
4219     tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4220     tcg_gen_andi_tl(t0, t0, 0xF);
4221     gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4222     tcg_temp_free(t0);
4223 #endif /* defined(CONFIG_USER_ONLY) */
4224 }
4225 
4226 /* slbmte */
4227 static void gen_slbmte(DisasContext *ctx)
4228 {
4229 #if defined(CONFIG_USER_ONLY)
4230     GEN_PRIV;
4231 #else
4232     CHK_SV;
4233 
4234     gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4235                          cpu_gpr[rS(ctx->opcode)]);
4236 #endif /* defined(CONFIG_USER_ONLY) */
4237 }
4238 
4239 static void gen_slbmfee(DisasContext *ctx)
4240 {
4241 #if defined(CONFIG_USER_ONLY)
4242     GEN_PRIV;
4243 #else
4244     CHK_SV;
4245 
4246     gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4247                              cpu_gpr[rB(ctx->opcode)]);
4248 #endif /* defined(CONFIG_USER_ONLY) */
4249 }
4250 
4251 static void gen_slbmfev(DisasContext *ctx)
4252 {
4253 #if defined(CONFIG_USER_ONLY)
4254     GEN_PRIV;
4255 #else
4256     CHK_SV;
4257 
4258     gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4259                              cpu_gpr[rB(ctx->opcode)]);
4260 #endif /* defined(CONFIG_USER_ONLY) */
4261 }
4262 
4263 static void gen_slbfee_(DisasContext *ctx)
4264 {
4265 #if defined(CONFIG_USER_ONLY)
4266     gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4267 #else
4268     TCGLabel *l1, *l2;
4269 
4270     if (unlikely(ctx->pr)) {
4271         gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4272         return;
4273     }
4274     gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4275                              cpu_gpr[rB(ctx->opcode)]);
4276     l1 = gen_new_label();
4277     l2 = gen_new_label();
4278     tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4279     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4280     tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4281     tcg_gen_br(l2);
4282     gen_set_label(l1);
4283     tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4284     gen_set_label(l2);
4285 #endif
4286 }
4287 #endif /* defined(TARGET_PPC64) */
4288 
4289 /***                      Lookaside buffer management                      ***/
4290 /* Optional & supervisor only: */
4291 
4292 /* tlbia */
4293 static void gen_tlbia(DisasContext *ctx)
4294 {
4295 #if defined(CONFIG_USER_ONLY)
4296     GEN_PRIV;
4297 #else
4298     CHK_HV;
4299 
4300     gen_helper_tlbia(cpu_env);
4301 #endif  /* defined(CONFIG_USER_ONLY) */
4302 }
4303 
4304 /* tlbiel */
4305 static void gen_tlbiel(DisasContext *ctx)
4306 {
4307 #if defined(CONFIG_USER_ONLY)
4308     GEN_PRIV;
4309 #else
4310     CHK_SV;
4311 
4312     gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4313 #endif /* defined(CONFIG_USER_ONLY) */
4314 }
4315 
4316 /* tlbie */
4317 static void gen_tlbie(DisasContext *ctx)
4318 {
4319 #if defined(CONFIG_USER_ONLY)
4320     GEN_PRIV;
4321 #else
4322     TCGv_i32 t1;
4323     CHK_HV;
4324 
4325     if (NARROW_MODE(ctx)) {
4326         TCGv t0 = tcg_temp_new();
4327         tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4328         gen_helper_tlbie(cpu_env, t0);
4329         tcg_temp_free(t0);
4330     } else {
4331         gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4332     }
4333     t1 = tcg_temp_new_i32();
4334     tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4335     tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4336     tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4337     tcg_temp_free_i32(t1);
4338 #endif /* defined(CONFIG_USER_ONLY) */
4339 }
4340 
4341 /* tlbsync */
4342 static void gen_tlbsync(DisasContext *ctx)
4343 {
4344 #if defined(CONFIG_USER_ONLY)
4345     GEN_PRIV;
4346 #else
4347     CHK_HV;
4348 
4349     /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4350     if (ctx->insns_flags & PPC_BOOKE) {
4351         gen_check_tlb_flush(ctx, true);
4352     }
4353 #endif /* defined(CONFIG_USER_ONLY) */
4354 }
4355 
4356 #if defined(TARGET_PPC64)
4357 /* slbia */
4358 static void gen_slbia(DisasContext *ctx)
4359 {
4360 #if defined(CONFIG_USER_ONLY)
4361     GEN_PRIV;
4362 #else
4363     CHK_SV;
4364 
4365     gen_helper_slbia(cpu_env);
4366 #endif /* defined(CONFIG_USER_ONLY) */
4367 }
4368 
4369 /* slbie */
4370 static void gen_slbie(DisasContext *ctx)
4371 {
4372 #if defined(CONFIG_USER_ONLY)
4373     GEN_PRIV;
4374 #else
4375     CHK_SV;
4376 
4377     gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4378 #endif /* defined(CONFIG_USER_ONLY) */
4379 }
4380 #endif  /* defined(TARGET_PPC64) */
4381 
4382 /***                              External control                         ***/
4383 /* Optional: */
4384 
4385 /* eciwx */
4386 static void gen_eciwx(DisasContext *ctx)
4387 {
4388     TCGv t0;
4389     /* Should check EAR[E] ! */
4390     gen_set_access_type(ctx, ACCESS_EXT);
4391     t0 = tcg_temp_new();
4392     gen_addr_reg_index(ctx, t0);
4393     gen_check_align(ctx, t0, 0x03);
4394     gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4395     tcg_temp_free(t0);
4396 }
4397 
4398 /* ecowx */
4399 static void gen_ecowx(DisasContext *ctx)
4400 {
4401     TCGv t0;
4402     /* Should check EAR[E] ! */
4403     gen_set_access_type(ctx, ACCESS_EXT);
4404     t0 = tcg_temp_new();
4405     gen_addr_reg_index(ctx, t0);
4406     gen_check_align(ctx, t0, 0x03);
4407     gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4408     tcg_temp_free(t0);
4409 }
4410 
4411 /* PowerPC 601 specific instructions */
4412 
4413 /* abs - abs. */
4414 static void gen_abs(DisasContext *ctx)
4415 {
4416     TCGLabel *l1 = gen_new_label();
4417     TCGLabel *l2 = gen_new_label();
4418     tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4419     tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4420     tcg_gen_br(l2);
4421     gen_set_label(l1);
4422     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4423     gen_set_label(l2);
4424     if (unlikely(Rc(ctx->opcode) != 0))
4425         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4426 }
4427 
4428 /* abso - abso. */
4429 static void gen_abso(DisasContext *ctx)
4430 {
4431     TCGLabel *l1 = gen_new_label();
4432     TCGLabel *l2 = gen_new_label();
4433     TCGLabel *l3 = gen_new_label();
4434     /* Start with XER OV disabled, the most likely case */
4435     tcg_gen_movi_tl(cpu_ov, 0);
4436     tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4437     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4438     tcg_gen_movi_tl(cpu_ov, 1);
4439     tcg_gen_movi_tl(cpu_so, 1);
4440     tcg_gen_br(l2);
4441     gen_set_label(l1);
4442     tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4443     tcg_gen_br(l3);
4444     gen_set_label(l2);
4445     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4446     gen_set_label(l3);
4447     if (unlikely(Rc(ctx->opcode) != 0))
4448         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4449 }
4450 
4451 /* clcs */
4452 static void gen_clcs(DisasContext *ctx)
4453 {
4454     TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4455     gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4456     tcg_temp_free_i32(t0);
4457     /* Rc=1 sets CR0 to an undefined state */
4458 }
4459 
4460 /* div - div. */
4461 static void gen_div(DisasContext *ctx)
4462 {
4463     gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4464                    cpu_gpr[rB(ctx->opcode)]);
4465     if (unlikely(Rc(ctx->opcode) != 0))
4466         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4467 }
4468 
4469 /* divo - divo. */
4470 static void gen_divo(DisasContext *ctx)
4471 {
4472     gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4473                     cpu_gpr[rB(ctx->opcode)]);
4474     if (unlikely(Rc(ctx->opcode) != 0))
4475         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4476 }
4477 
4478 /* divs - divs. */
4479 static void gen_divs(DisasContext *ctx)
4480 {
4481     gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4482                     cpu_gpr[rB(ctx->opcode)]);
4483     if (unlikely(Rc(ctx->opcode) != 0))
4484         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4485 }
4486 
4487 /* divso - divso. */
4488 static void gen_divso(DisasContext *ctx)
4489 {
4490     gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4491                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4492     if (unlikely(Rc(ctx->opcode) != 0))
4493         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4494 }
4495 
4496 /* doz - doz. */
4497 static void gen_doz(DisasContext *ctx)
4498 {
4499     TCGLabel *l1 = gen_new_label();
4500     TCGLabel *l2 = gen_new_label();
4501     tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4502     tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4503     tcg_gen_br(l2);
4504     gen_set_label(l1);
4505     tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4506     gen_set_label(l2);
4507     if (unlikely(Rc(ctx->opcode) != 0))
4508         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4509 }
4510 
4511 /* dozo - dozo. */
4512 static void gen_dozo(DisasContext *ctx)
4513 {
4514     TCGLabel *l1 = gen_new_label();
4515     TCGLabel *l2 = gen_new_label();
4516     TCGv t0 = tcg_temp_new();
4517     TCGv t1 = tcg_temp_new();
4518     TCGv t2 = tcg_temp_new();
4519     /* Start with XER OV disabled, the most likely case */
4520     tcg_gen_movi_tl(cpu_ov, 0);
4521     tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4522     tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4523     tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4524     tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4525     tcg_gen_andc_tl(t1, t1, t2);
4526     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4527     tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4528     tcg_gen_movi_tl(cpu_ov, 1);
4529     tcg_gen_movi_tl(cpu_so, 1);
4530     tcg_gen_br(l2);
4531     gen_set_label(l1);
4532     tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4533     gen_set_label(l2);
4534     tcg_temp_free(t0);
4535     tcg_temp_free(t1);
4536     tcg_temp_free(t2);
4537     if (unlikely(Rc(ctx->opcode) != 0))
4538         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4539 }
4540 
4541 /* dozi */
4542 static void gen_dozi(DisasContext *ctx)
4543 {
4544     target_long simm = SIMM(ctx->opcode);
4545     TCGLabel *l1 = gen_new_label();
4546     TCGLabel *l2 = gen_new_label();
4547     tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4548     tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4549     tcg_gen_br(l2);
4550     gen_set_label(l1);
4551     tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4552     gen_set_label(l2);
4553     if (unlikely(Rc(ctx->opcode) != 0))
4554         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4555 }
4556 
4557 /* lscbx - lscbx. */
4558 static void gen_lscbx(DisasContext *ctx)
4559 {
4560     TCGv t0 = tcg_temp_new();
4561     TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4562     TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4563     TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4564 
4565     gen_addr_reg_index(ctx, t0);
4566     gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4567     tcg_temp_free_i32(t1);
4568     tcg_temp_free_i32(t2);
4569     tcg_temp_free_i32(t3);
4570     tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4571     tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4572     if (unlikely(Rc(ctx->opcode) != 0))
4573         gen_set_Rc0(ctx, t0);
4574     tcg_temp_free(t0);
4575 }
4576 
4577 /* maskg - maskg. */
4578 static void gen_maskg(DisasContext *ctx)
4579 {
4580     TCGLabel *l1 = gen_new_label();
4581     TCGv t0 = tcg_temp_new();
4582     TCGv t1 = tcg_temp_new();
4583     TCGv t2 = tcg_temp_new();
4584     TCGv t3 = tcg_temp_new();
4585     tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4586     tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4587     tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4588     tcg_gen_addi_tl(t2, t0, 1);
4589     tcg_gen_shr_tl(t2, t3, t2);
4590     tcg_gen_shr_tl(t3, t3, t1);
4591     tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4592     tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4593     tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4594     gen_set_label(l1);
4595     tcg_temp_free(t0);
4596     tcg_temp_free(t1);
4597     tcg_temp_free(t2);
4598     tcg_temp_free(t3);
4599     if (unlikely(Rc(ctx->opcode) != 0))
4600         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4601 }
4602 
4603 /* maskir - maskir. */
4604 static void gen_maskir(DisasContext *ctx)
4605 {
4606     TCGv t0 = tcg_temp_new();
4607     TCGv t1 = tcg_temp_new();
4608     tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4609     tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4610     tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4611     tcg_temp_free(t0);
4612     tcg_temp_free(t1);
4613     if (unlikely(Rc(ctx->opcode) != 0))
4614         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4615 }
4616 
4617 /* mul - mul. */
4618 static void gen_mul(DisasContext *ctx)
4619 {
4620     TCGv_i64 t0 = tcg_temp_new_i64();
4621     TCGv_i64 t1 = tcg_temp_new_i64();
4622     TCGv t2 = tcg_temp_new();
4623     tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4624     tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4625     tcg_gen_mul_i64(t0, t0, t1);
4626     tcg_gen_trunc_i64_tl(t2, t0);
4627     gen_store_spr(SPR_MQ, t2);
4628     tcg_gen_shri_i64(t1, t0, 32);
4629     tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4630     tcg_temp_free_i64(t0);
4631     tcg_temp_free_i64(t1);
4632     tcg_temp_free(t2);
4633     if (unlikely(Rc(ctx->opcode) != 0))
4634         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4635 }
4636 
4637 /* mulo - mulo. */
4638 static void gen_mulo(DisasContext *ctx)
4639 {
4640     TCGLabel *l1 = gen_new_label();
4641     TCGv_i64 t0 = tcg_temp_new_i64();
4642     TCGv_i64 t1 = tcg_temp_new_i64();
4643     TCGv t2 = tcg_temp_new();
4644     /* Start with XER OV disabled, the most likely case */
4645     tcg_gen_movi_tl(cpu_ov, 0);
4646     tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4647     tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4648     tcg_gen_mul_i64(t0, t0, t1);
4649     tcg_gen_trunc_i64_tl(t2, t0);
4650     gen_store_spr(SPR_MQ, t2);
4651     tcg_gen_shri_i64(t1, t0, 32);
4652     tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4653     tcg_gen_ext32s_i64(t1, t0);
4654     tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4655     tcg_gen_movi_tl(cpu_ov, 1);
4656     tcg_gen_movi_tl(cpu_so, 1);
4657     gen_set_label(l1);
4658     tcg_temp_free_i64(t0);
4659     tcg_temp_free_i64(t1);
4660     tcg_temp_free(t2);
4661     if (unlikely(Rc(ctx->opcode) != 0))
4662         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4663 }
4664 
4665 /* nabs - nabs. */
4666 static void gen_nabs(DisasContext *ctx)
4667 {
4668     TCGLabel *l1 = gen_new_label();
4669     TCGLabel *l2 = gen_new_label();
4670     tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4671     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4672     tcg_gen_br(l2);
4673     gen_set_label(l1);
4674     tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4675     gen_set_label(l2);
4676     if (unlikely(Rc(ctx->opcode) != 0))
4677         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4678 }
4679 
4680 /* nabso - nabso. */
4681 static void gen_nabso(DisasContext *ctx)
4682 {
4683     TCGLabel *l1 = gen_new_label();
4684     TCGLabel *l2 = gen_new_label();
4685     tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4686     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4687     tcg_gen_br(l2);
4688     gen_set_label(l1);
4689     tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4690     gen_set_label(l2);
4691     /* nabs never overflows */
4692     tcg_gen_movi_tl(cpu_ov, 0);
4693     if (unlikely(Rc(ctx->opcode) != 0))
4694         gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4695 }
4696 
4697 /* rlmi - rlmi. */
4698 static void gen_rlmi(DisasContext *ctx)
4699 {
4700     uint32_t mb = MB(ctx->opcode);
4701     uint32_t me = ME(ctx->opcode);
4702     TCGv t0 = tcg_temp_new();
4703     tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4704     tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4705     tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4706     tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4707     tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4708     tcg_temp_free(t0);
4709     if (unlikely(Rc(ctx->opcode) != 0))
4710         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4711 }
4712 
4713 /* rrib - rrib. */
4714 static void gen_rrib(DisasContext *ctx)
4715 {
4716     TCGv t0 = tcg_temp_new();
4717     TCGv t1 = tcg_temp_new();
4718     tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4719     tcg_gen_movi_tl(t1, 0x80000000);
4720     tcg_gen_shr_tl(t1, t1, t0);
4721     tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4722     tcg_gen_and_tl(t0, t0, t1);
4723     tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4724     tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4725     tcg_temp_free(t0);
4726     tcg_temp_free(t1);
4727     if (unlikely(Rc(ctx->opcode) != 0))
4728         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4729 }
4730 
4731 /* sle - sle. */
4732 static void gen_sle(DisasContext *ctx)
4733 {
4734     TCGv t0 = tcg_temp_new();
4735     TCGv t1 = tcg_temp_new();
4736     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4737     tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4738     tcg_gen_subfi_tl(t1, 32, t1);
4739     tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4740     tcg_gen_or_tl(t1, t0, t1);
4741     tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4742     gen_store_spr(SPR_MQ, t1);
4743     tcg_temp_free(t0);
4744     tcg_temp_free(t1);
4745     if (unlikely(Rc(ctx->opcode) != 0))
4746         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4747 }
4748 
4749 /* sleq - sleq. */
4750 static void gen_sleq(DisasContext *ctx)
4751 {
4752     TCGv t0 = tcg_temp_new();
4753     TCGv t1 = tcg_temp_new();
4754     TCGv t2 = tcg_temp_new();
4755     tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4756     tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4757     tcg_gen_shl_tl(t2, t2, t0);
4758     tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4759     gen_load_spr(t1, SPR_MQ);
4760     gen_store_spr(SPR_MQ, t0);
4761     tcg_gen_and_tl(t0, t0, t2);
4762     tcg_gen_andc_tl(t1, t1, t2);
4763     tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4764     tcg_temp_free(t0);
4765     tcg_temp_free(t1);
4766     tcg_temp_free(t2);
4767     if (unlikely(Rc(ctx->opcode) != 0))
4768         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4769 }
4770 
4771 /* sliq - sliq. */
4772 static void gen_sliq(DisasContext *ctx)
4773 {
4774     int sh = SH(ctx->opcode);
4775     TCGv t0 = tcg_temp_new();
4776     TCGv t1 = tcg_temp_new();
4777     tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4778     tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4779     tcg_gen_or_tl(t1, t0, t1);
4780     tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4781     gen_store_spr(SPR_MQ, t1);
4782     tcg_temp_free(t0);
4783     tcg_temp_free(t1);
4784     if (unlikely(Rc(ctx->opcode) != 0))
4785         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4786 }
4787 
4788 /* slliq - slliq. */
4789 static void gen_slliq(DisasContext *ctx)
4790 {
4791     int sh = SH(ctx->opcode);
4792     TCGv t0 = tcg_temp_new();
4793     TCGv t1 = tcg_temp_new();
4794     tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4795     gen_load_spr(t1, SPR_MQ);
4796     gen_store_spr(SPR_MQ, t0);
4797     tcg_gen_andi_tl(t0, t0,  (0xFFFFFFFFU << sh));
4798     tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4799     tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4800     tcg_temp_free(t0);
4801     tcg_temp_free(t1);
4802     if (unlikely(Rc(ctx->opcode) != 0))
4803         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4804 }
4805 
4806 /* sllq - sllq. */
4807 static void gen_sllq(DisasContext *ctx)
4808 {
4809     TCGLabel *l1 = gen_new_label();
4810     TCGLabel *l2 = gen_new_label();
4811     TCGv t0 = tcg_temp_local_new();
4812     TCGv t1 = tcg_temp_local_new();
4813     TCGv t2 = tcg_temp_local_new();
4814     tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4815     tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4816     tcg_gen_shl_tl(t1, t1, t2);
4817     tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4818     tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4819     gen_load_spr(t0, SPR_MQ);
4820     tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4821     tcg_gen_br(l2);
4822     gen_set_label(l1);
4823     tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4824     gen_load_spr(t2, SPR_MQ);
4825     tcg_gen_andc_tl(t1, t2, t1);
4826     tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4827     gen_set_label(l2);
4828     tcg_temp_free(t0);
4829     tcg_temp_free(t1);
4830     tcg_temp_free(t2);
4831     if (unlikely(Rc(ctx->opcode) != 0))
4832         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4833 }
4834 
4835 /* slq - slq. */
4836 static void gen_slq(DisasContext *ctx)
4837 {
4838     TCGLabel *l1 = gen_new_label();
4839     TCGv t0 = tcg_temp_new();
4840     TCGv t1 = tcg_temp_new();
4841     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4842     tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4843     tcg_gen_subfi_tl(t1, 32, t1);
4844     tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4845     tcg_gen_or_tl(t1, t0, t1);
4846     gen_store_spr(SPR_MQ, t1);
4847     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4848     tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4849     tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4850     tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4851     gen_set_label(l1);
4852     tcg_temp_free(t0);
4853     tcg_temp_free(t1);
4854     if (unlikely(Rc(ctx->opcode) != 0))
4855         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4856 }
4857 
4858 /* sraiq - sraiq. */
4859 static void gen_sraiq(DisasContext *ctx)
4860 {
4861     int sh = SH(ctx->opcode);
4862     TCGLabel *l1 = gen_new_label();
4863     TCGv t0 = tcg_temp_new();
4864     TCGv t1 = tcg_temp_new();
4865     tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4866     tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4867     tcg_gen_or_tl(t0, t0, t1);
4868     gen_store_spr(SPR_MQ, t0);
4869     tcg_gen_movi_tl(cpu_ca, 0);
4870     tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4871     tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4872     tcg_gen_movi_tl(cpu_ca, 1);
4873     gen_set_label(l1);
4874     tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4875     tcg_temp_free(t0);
4876     tcg_temp_free(t1);
4877     if (unlikely(Rc(ctx->opcode) != 0))
4878         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4879 }
4880 
4881 /* sraq - sraq. */
4882 static void gen_sraq(DisasContext *ctx)
4883 {
4884     TCGLabel *l1 = gen_new_label();
4885     TCGLabel *l2 = gen_new_label();
4886     TCGv t0 = tcg_temp_new();
4887     TCGv t1 = tcg_temp_local_new();
4888     TCGv t2 = tcg_temp_local_new();
4889     tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4890     tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4891     tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4892     tcg_gen_subfi_tl(t2, 32, t2);
4893     tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4894     tcg_gen_or_tl(t0, t0, t2);
4895     gen_store_spr(SPR_MQ, t0);
4896     tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4897     tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4898     tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4899     tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4900     gen_set_label(l1);
4901     tcg_temp_free(t0);
4902     tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4903     tcg_gen_movi_tl(cpu_ca, 0);
4904     tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4905     tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4906     tcg_gen_movi_tl(cpu_ca, 1);
4907     gen_set_label(l2);
4908     tcg_temp_free(t1);
4909     tcg_temp_free(t2);
4910     if (unlikely(Rc(ctx->opcode) != 0))
4911         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4912 }
4913 
4914 /* sre - sre. */
4915 static void gen_sre(DisasContext *ctx)
4916 {
4917     TCGv t0 = tcg_temp_new();
4918     TCGv t1 = tcg_temp_new();
4919     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4920     tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4921     tcg_gen_subfi_tl(t1, 32, t1);
4922     tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4923     tcg_gen_or_tl(t1, t0, t1);
4924     tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4925     gen_store_spr(SPR_MQ, t1);
4926     tcg_temp_free(t0);
4927     tcg_temp_free(t1);
4928     if (unlikely(Rc(ctx->opcode) != 0))
4929         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4930 }
4931 
4932 /* srea - srea. */
4933 static void gen_srea(DisasContext *ctx)
4934 {
4935     TCGv t0 = tcg_temp_new();
4936     TCGv t1 = tcg_temp_new();
4937     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4938     tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4939     gen_store_spr(SPR_MQ, t0);
4940     tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4941     tcg_temp_free(t0);
4942     tcg_temp_free(t1);
4943     if (unlikely(Rc(ctx->opcode) != 0))
4944         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4945 }
4946 
4947 /* sreq */
4948 static void gen_sreq(DisasContext *ctx)
4949 {
4950     TCGv t0 = tcg_temp_new();
4951     TCGv t1 = tcg_temp_new();
4952     TCGv t2 = tcg_temp_new();
4953     tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4954     tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4955     tcg_gen_shr_tl(t1, t1, t0);
4956     tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4957     gen_load_spr(t2, SPR_MQ);
4958     gen_store_spr(SPR_MQ, t0);
4959     tcg_gen_and_tl(t0, t0, t1);
4960     tcg_gen_andc_tl(t2, t2, t1);
4961     tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4962     tcg_temp_free(t0);
4963     tcg_temp_free(t1);
4964     tcg_temp_free(t2);
4965     if (unlikely(Rc(ctx->opcode) != 0))
4966         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4967 }
4968 
4969 /* sriq */
4970 static void gen_sriq(DisasContext *ctx)
4971 {
4972     int sh = SH(ctx->opcode);
4973     TCGv t0 = tcg_temp_new();
4974     TCGv t1 = tcg_temp_new();
4975     tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4976     tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4977     tcg_gen_or_tl(t1, t0, t1);
4978     tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4979     gen_store_spr(SPR_MQ, t1);
4980     tcg_temp_free(t0);
4981     tcg_temp_free(t1);
4982     if (unlikely(Rc(ctx->opcode) != 0))
4983         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4984 }
4985 
4986 /* srliq */
4987 static void gen_srliq(DisasContext *ctx)
4988 {
4989     int sh = SH(ctx->opcode);
4990     TCGv t0 = tcg_temp_new();
4991     TCGv t1 = tcg_temp_new();
4992     tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4993     gen_load_spr(t1, SPR_MQ);
4994     gen_store_spr(SPR_MQ, t0);
4995     tcg_gen_andi_tl(t0, t0,  (0xFFFFFFFFU >> sh));
4996     tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
4997     tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4998     tcg_temp_free(t0);
4999     tcg_temp_free(t1);
5000     if (unlikely(Rc(ctx->opcode) != 0))
5001         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5002 }
5003 
5004 /* srlq */
5005 static void gen_srlq(DisasContext *ctx)
5006 {
5007     TCGLabel *l1 = gen_new_label();
5008     TCGLabel *l2 = gen_new_label();
5009     TCGv t0 = tcg_temp_local_new();
5010     TCGv t1 = tcg_temp_local_new();
5011     TCGv t2 = tcg_temp_local_new();
5012     tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5013     tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5014     tcg_gen_shr_tl(t2, t1, t2);
5015     tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5016     tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5017     gen_load_spr(t0, SPR_MQ);
5018     tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5019     tcg_gen_br(l2);
5020     gen_set_label(l1);
5021     tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5022     tcg_gen_and_tl(t0, t0, t2);
5023     gen_load_spr(t1, SPR_MQ);
5024     tcg_gen_andc_tl(t1, t1, t2);
5025     tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5026     gen_set_label(l2);
5027     tcg_temp_free(t0);
5028     tcg_temp_free(t1);
5029     tcg_temp_free(t2);
5030     if (unlikely(Rc(ctx->opcode) != 0))
5031         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5032 }
5033 
5034 /* srq */
5035 static void gen_srq(DisasContext *ctx)
5036 {
5037     TCGLabel *l1 = gen_new_label();
5038     TCGv t0 = tcg_temp_new();
5039     TCGv t1 = tcg_temp_new();
5040     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5041     tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5042     tcg_gen_subfi_tl(t1, 32, t1);
5043     tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5044     tcg_gen_or_tl(t1, t0, t1);
5045     gen_store_spr(SPR_MQ, t1);
5046     tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5047     tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5048     tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5049     tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5050     gen_set_label(l1);
5051     tcg_temp_free(t0);
5052     tcg_temp_free(t1);
5053     if (unlikely(Rc(ctx->opcode) != 0))
5054         gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5055 }
5056 
5057 /* PowerPC 602 specific instructions */
5058 
5059 /* dsa  */
5060 static void gen_dsa(DisasContext *ctx)
5061 {
5062     /* XXX: TODO */
5063     gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5064 }
5065 
5066 /* esa */
5067 static void gen_esa(DisasContext *ctx)
5068 {
5069     /* XXX: TODO */
5070     gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5071 }
5072 
5073 /* mfrom */
5074 static void gen_mfrom(DisasContext *ctx)
5075 {
5076 #if defined(CONFIG_USER_ONLY)
5077     GEN_PRIV;
5078 #else
5079     CHK_SV;
5080     gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5081 #endif /* defined(CONFIG_USER_ONLY) */
5082 }
5083 
5084 /* 602 - 603 - G2 TLB management */
5085 
5086 /* tlbld */
5087 static void gen_tlbld_6xx(DisasContext *ctx)
5088 {
5089 #if defined(CONFIG_USER_ONLY)
5090     GEN_PRIV;
5091 #else
5092     CHK_SV;
5093     gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5094 #endif /* defined(CONFIG_USER_ONLY) */
5095 }
5096 
5097 /* tlbli */
5098 static void gen_tlbli_6xx(DisasContext *ctx)
5099 {
5100 #if defined(CONFIG_USER_ONLY)
5101     GEN_PRIV;
5102 #else
5103     CHK_SV;
5104     gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5105 #endif /* defined(CONFIG_USER_ONLY) */
5106 }
5107 
5108 /* 74xx TLB management */
5109 
5110 /* tlbld */
5111 static void gen_tlbld_74xx(DisasContext *ctx)
5112 {
5113 #if defined(CONFIG_USER_ONLY)
5114     GEN_PRIV;
5115 #else
5116     CHK_SV;
5117     gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5118 #endif /* defined(CONFIG_USER_ONLY) */
5119 }
5120 
5121 /* tlbli */
5122 static void gen_tlbli_74xx(DisasContext *ctx)
5123 {
5124 #if defined(CONFIG_USER_ONLY)
5125     GEN_PRIV;
5126 #else
5127     CHK_SV;
5128     gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5129 #endif /* defined(CONFIG_USER_ONLY) */
5130 }
5131 
5132 /* POWER instructions not in PowerPC 601 */
5133 
5134 /* clf */
5135 static void gen_clf(DisasContext *ctx)
5136 {
5137     /* Cache line flush: implemented as no-op */
5138 }
5139 
5140 /* cli */
5141 static void gen_cli(DisasContext *ctx)
5142 {
5143 #if defined(CONFIG_USER_ONLY)
5144     GEN_PRIV;
5145 #else
5146     /* Cache line invalidate: privileged and treated as no-op */
5147     CHK_SV;
5148 #endif /* defined(CONFIG_USER_ONLY) */
5149 }
5150 
5151 /* dclst */
5152 static void gen_dclst(DisasContext *ctx)
5153 {
5154     /* Data cache line store: treated as no-op */
5155 }
5156 
5157 static void gen_mfsri(DisasContext *ctx)
5158 {
5159 #if defined(CONFIG_USER_ONLY)
5160     GEN_PRIV;
5161 #else
5162     int ra = rA(ctx->opcode);
5163     int rd = rD(ctx->opcode);
5164     TCGv t0;
5165 
5166     CHK_SV;
5167     t0 = tcg_temp_new();
5168     gen_addr_reg_index(ctx, t0);
5169     tcg_gen_shri_tl(t0, t0, 28);
5170     tcg_gen_andi_tl(t0, t0, 0xF);
5171     gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5172     tcg_temp_free(t0);
5173     if (ra != 0 && ra != rd)
5174         tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5175 #endif /* defined(CONFIG_USER_ONLY) */
5176 }
5177 
5178 static void gen_rac(DisasContext *ctx)
5179 {
5180 #if defined(CONFIG_USER_ONLY)
5181     GEN_PRIV;
5182 #else
5183     TCGv t0;
5184 
5185     CHK_SV;
5186     t0 = tcg_temp_new();
5187     gen_addr_reg_index(ctx, t0);
5188     gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5189     tcg_temp_free(t0);
5190 #endif /* defined(CONFIG_USER_ONLY) */
5191 }
5192 
5193 static void gen_rfsvc(DisasContext *ctx)
5194 {
5195 #if defined(CONFIG_USER_ONLY)
5196     GEN_PRIV;
5197 #else
5198     CHK_SV;
5199 
5200     gen_helper_rfsvc(cpu_env);
5201     gen_sync_exception(ctx);
5202 #endif /* defined(CONFIG_USER_ONLY) */
5203 }
5204 
5205 /* svc is not implemented for now */
5206 
5207 /* BookE specific instructions */
5208 
5209 /* XXX: not implemented on 440 ? */
5210 static void gen_mfapidi(DisasContext *ctx)
5211 {
5212     /* XXX: TODO */
5213     gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5214 }
5215 
5216 /* XXX: not implemented on 440 ? */
5217 static void gen_tlbiva(DisasContext *ctx)
5218 {
5219 #if defined(CONFIG_USER_ONLY)
5220     GEN_PRIV;
5221 #else
5222     TCGv t0;
5223 
5224     CHK_SV;
5225     t0 = tcg_temp_new();
5226     gen_addr_reg_index(ctx, t0);
5227     gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5228     tcg_temp_free(t0);
5229 #endif /* defined(CONFIG_USER_ONLY) */
5230 }
5231 
5232 /* All 405 MAC instructions are translated here */
5233 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5234                                         int ra, int rb, int rt, int Rc)
5235 {
5236     TCGv t0, t1;
5237 
5238     t0 = tcg_temp_local_new();
5239     t1 = tcg_temp_local_new();
5240 
5241     switch (opc3 & 0x0D) {
5242     case 0x05:
5243         /* macchw    - macchw.    - macchwo   - macchwo.   */
5244         /* macchws   - macchws.   - macchwso  - macchwso.  */
5245         /* nmacchw   - nmacchw.   - nmacchwo  - nmacchwo.  */
5246         /* nmacchws  - nmacchws.  - nmacchwso - nmacchwso. */
5247         /* mulchw - mulchw. */
5248         tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5249         tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5250         tcg_gen_ext16s_tl(t1, t1);
5251         break;
5252     case 0x04:
5253         /* macchwu   - macchwu.   - macchwuo  - macchwuo.  */
5254         /* macchwsu  - macchwsu.  - macchwsuo - macchwsuo. */
5255         /* mulchwu - mulchwu. */
5256         tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5257         tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5258         tcg_gen_ext16u_tl(t1, t1);
5259         break;
5260     case 0x01:
5261         /* machhw    - machhw.    - machhwo   - machhwo.   */
5262         /* machhws   - machhws.   - machhwso  - machhwso.  */
5263         /* nmachhw   - nmachhw.   - nmachhwo  - nmachhwo.  */
5264         /* nmachhws  - nmachhws.  - nmachhwso - nmachhwso. */
5265         /* mulhhw - mulhhw. */
5266         tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5267         tcg_gen_ext16s_tl(t0, t0);
5268         tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5269         tcg_gen_ext16s_tl(t1, t1);
5270         break;
5271     case 0x00:
5272         /* machhwu   - machhwu.   - machhwuo  - machhwuo.  */
5273         /* machhwsu  - machhwsu.  - machhwsuo - machhwsuo. */
5274         /* mulhhwu - mulhhwu. */
5275         tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5276         tcg_gen_ext16u_tl(t0, t0);
5277         tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5278         tcg_gen_ext16u_tl(t1, t1);
5279         break;
5280     case 0x0D:
5281         /* maclhw    - maclhw.    - maclhwo   - maclhwo.   */
5282         /* maclhws   - maclhws.   - maclhwso  - maclhwso.  */
5283         /* nmaclhw   - nmaclhw.   - nmaclhwo  - nmaclhwo.  */
5284         /* nmaclhws  - nmaclhws.  - nmaclhwso - nmaclhwso. */
5285         /* mullhw - mullhw. */
5286         tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5287         tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5288         break;
5289     case 0x0C:
5290         /* maclhwu   - maclhwu.   - maclhwuo  - maclhwuo.  */
5291         /* maclhwsu  - maclhwsu.  - maclhwsuo - maclhwsuo. */
5292         /* mullhwu - mullhwu. */
5293         tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5294         tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5295         break;
5296     }
5297     if (opc2 & 0x04) {
5298         /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5299         tcg_gen_mul_tl(t1, t0, t1);
5300         if (opc2 & 0x02) {
5301             /* nmultiply-and-accumulate (0x0E) */
5302             tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5303         } else {
5304             /* multiply-and-accumulate (0x0C) */
5305             tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5306         }
5307 
5308         if (opc3 & 0x12) {
5309             /* Check overflow and/or saturate */
5310             TCGLabel *l1 = gen_new_label();
5311 
5312             if (opc3 & 0x10) {
5313                 /* Start with XER OV disabled, the most likely case */
5314                 tcg_gen_movi_tl(cpu_ov, 0);
5315             }
5316             if (opc3 & 0x01) {
5317                 /* Signed */
5318                 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5319                 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5320                 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5321                 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5322                 if (opc3 & 0x02) {
5323                     /* Saturate */
5324                     tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5325                     tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5326                 }
5327             } else {
5328                 /* Unsigned */
5329                 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5330                 if (opc3 & 0x02) {
5331                     /* Saturate */
5332                     tcg_gen_movi_tl(t0, UINT32_MAX);
5333                 }
5334             }
5335             if (opc3 & 0x10) {
5336                 /* Check overflow */
5337                 tcg_gen_movi_tl(cpu_ov, 1);
5338                 tcg_gen_movi_tl(cpu_so, 1);
5339             }
5340             gen_set_label(l1);
5341             tcg_gen_mov_tl(cpu_gpr[rt], t0);
5342         }
5343     } else {
5344         tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5345     }
5346     tcg_temp_free(t0);
5347     tcg_temp_free(t1);
5348     if (unlikely(Rc) != 0) {
5349         /* Update Rc0 */
5350         gen_set_Rc0(ctx, cpu_gpr[rt]);
5351     }
5352 }
5353 
5354 #define GEN_MAC_HANDLER(name, opc2, opc3)                                     \
5355 static void glue(gen_, name)(DisasContext *ctx)                               \
5356 {                                                                             \
5357     gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode),   \
5358                          rD(ctx->opcode), Rc(ctx->opcode));                   \
5359 }
5360 
5361 /* macchw    - macchw.    */
5362 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5363 /* macchwo   - macchwo.   */
5364 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5365 /* macchws   - macchws.   */
5366 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5367 /* macchwso  - macchwso.  */
5368 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5369 /* macchwsu  - macchwsu.  */
5370 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5371 /* macchwsuo - macchwsuo. */
5372 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5373 /* macchwu   - macchwu.   */
5374 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5375 /* macchwuo  - macchwuo.  */
5376 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5377 /* machhw    - machhw.    */
5378 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5379 /* machhwo   - machhwo.   */
5380 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5381 /* machhws   - machhws.   */
5382 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5383 /* machhwso  - machhwso.  */
5384 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5385 /* machhwsu  - machhwsu.  */
5386 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5387 /* machhwsuo - machhwsuo. */
5388 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5389 /* machhwu   - machhwu.   */
5390 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5391 /* machhwuo  - machhwuo.  */
5392 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5393 /* maclhw    - maclhw.    */
5394 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5395 /* maclhwo   - maclhwo.   */
5396 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5397 /* maclhws   - maclhws.   */
5398 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5399 /* maclhwso  - maclhwso.  */
5400 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5401 /* maclhwu   - maclhwu.   */
5402 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5403 /* maclhwuo  - maclhwuo.  */
5404 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5405 /* maclhwsu  - maclhwsu.  */
5406 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5407 /* maclhwsuo - maclhwsuo. */
5408 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5409 /* nmacchw   - nmacchw.   */
5410 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5411 /* nmacchwo  - nmacchwo.  */
5412 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5413 /* nmacchws  - nmacchws.  */
5414 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5415 /* nmacchwso - nmacchwso. */
5416 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5417 /* nmachhw   - nmachhw.   */
5418 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5419 /* nmachhwo  - nmachhwo.  */
5420 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5421 /* nmachhws  - nmachhws.  */
5422 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5423 /* nmachhwso - nmachhwso. */
5424 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5425 /* nmaclhw   - nmaclhw.   */
5426 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5427 /* nmaclhwo  - nmaclhwo.  */
5428 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5429 /* nmaclhws  - nmaclhws.  */
5430 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5431 /* nmaclhwso - nmaclhwso. */
5432 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5433 
5434 /* mulchw  - mulchw.  */
5435 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5436 /* mulchwu - mulchwu. */
5437 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5438 /* mulhhw  - mulhhw.  */
5439 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5440 /* mulhhwu - mulhhwu. */
5441 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5442 /* mullhw  - mullhw.  */
5443 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5444 /* mullhwu - mullhwu. */
5445 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5446 
5447 /* mfdcr */
5448 static void gen_mfdcr(DisasContext *ctx)
5449 {
5450 #if defined(CONFIG_USER_ONLY)
5451     GEN_PRIV;
5452 #else
5453     TCGv dcrn;
5454 
5455     CHK_SV;
5456     dcrn = tcg_const_tl(SPR(ctx->opcode));
5457     gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5458     tcg_temp_free(dcrn);
5459 #endif /* defined(CONFIG_USER_ONLY) */
5460 }
5461 
5462 /* mtdcr */
5463 static void gen_mtdcr(DisasContext *ctx)
5464 {
5465 #if defined(CONFIG_USER_ONLY)
5466     GEN_PRIV;
5467 #else
5468     TCGv dcrn;
5469 
5470     CHK_SV;
5471     dcrn = tcg_const_tl(SPR(ctx->opcode));
5472     gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5473     tcg_temp_free(dcrn);
5474 #endif /* defined(CONFIG_USER_ONLY) */
5475 }
5476 
5477 /* mfdcrx */
5478 /* XXX: not implemented on 440 ? */
5479 static void gen_mfdcrx(DisasContext *ctx)
5480 {
5481 #if defined(CONFIG_USER_ONLY)
5482     GEN_PRIV;
5483 #else
5484     CHK_SV;
5485     gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5486                         cpu_gpr[rA(ctx->opcode)]);
5487     /* Note: Rc update flag set leads to undefined state of Rc0 */
5488 #endif /* defined(CONFIG_USER_ONLY) */
5489 }
5490 
5491 /* mtdcrx */
5492 /* XXX: not implemented on 440 ? */
5493 static void gen_mtdcrx(DisasContext *ctx)
5494 {
5495 #if defined(CONFIG_USER_ONLY)
5496     GEN_PRIV;
5497 #else
5498     CHK_SV;
5499     gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5500                          cpu_gpr[rS(ctx->opcode)]);
5501     /* Note: Rc update flag set leads to undefined state of Rc0 */
5502 #endif /* defined(CONFIG_USER_ONLY) */
5503 }
5504 
5505 /* mfdcrux (PPC 460) : user-mode access to DCR */
5506 static void gen_mfdcrux(DisasContext *ctx)
5507 {
5508     gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5509                         cpu_gpr[rA(ctx->opcode)]);
5510     /* Note: Rc update flag set leads to undefined state of Rc0 */
5511 }
5512 
5513 /* mtdcrux (PPC 460) : user-mode access to DCR */
5514 static void gen_mtdcrux(DisasContext *ctx)
5515 {
5516     gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5517                          cpu_gpr[rS(ctx->opcode)]);
5518     /* Note: Rc update flag set leads to undefined state of Rc0 */
5519 }
5520 
5521 /* dccci */
5522 static void gen_dccci(DisasContext *ctx)
5523 {
5524     CHK_SV;
5525     /* interpreted as no-op */
5526 }
5527 
5528 /* dcread */
5529 static void gen_dcread(DisasContext *ctx)
5530 {
5531 #if defined(CONFIG_USER_ONLY)
5532     GEN_PRIV;
5533 #else
5534     TCGv EA, val;
5535 
5536     CHK_SV;
5537     gen_set_access_type(ctx, ACCESS_CACHE);
5538     EA = tcg_temp_new();
5539     gen_addr_reg_index(ctx, EA);
5540     val = tcg_temp_new();
5541     gen_qemu_ld32u(ctx, val, EA);
5542     tcg_temp_free(val);
5543     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5544     tcg_temp_free(EA);
5545 #endif /* defined(CONFIG_USER_ONLY) */
5546 }
5547 
5548 /* icbt */
5549 static void gen_icbt_40x(DisasContext *ctx)
5550 {
5551     /* interpreted as no-op */
5552     /* XXX: specification say this is treated as a load by the MMU
5553      *      but does not generate any exception
5554      */
5555 }
5556 
5557 /* iccci */
5558 static void gen_iccci(DisasContext *ctx)
5559 {
5560     CHK_SV;
5561     /* interpreted as no-op */
5562 }
5563 
5564 /* icread */
5565 static void gen_icread(DisasContext *ctx)
5566 {
5567     CHK_SV;
5568     /* interpreted as no-op */
5569 }
5570 
5571 /* rfci (supervisor only) */
5572 static void gen_rfci_40x(DisasContext *ctx)
5573 {
5574 #if defined(CONFIG_USER_ONLY)
5575     GEN_PRIV;
5576 #else
5577     CHK_SV;
5578     /* Restore CPU state */
5579     gen_helper_40x_rfci(cpu_env);
5580     gen_sync_exception(ctx);
5581 #endif /* defined(CONFIG_USER_ONLY) */
5582 }
5583 
5584 static void gen_rfci(DisasContext *ctx)
5585 {
5586 #if defined(CONFIG_USER_ONLY)
5587     GEN_PRIV;
5588 #else
5589     CHK_SV;
5590     /* Restore CPU state */
5591     gen_helper_rfci(cpu_env);
5592     gen_sync_exception(ctx);
5593 #endif /* defined(CONFIG_USER_ONLY) */
5594 }
5595 
5596 /* BookE specific */
5597 
5598 /* XXX: not implemented on 440 ? */
5599 static void gen_rfdi(DisasContext *ctx)
5600 {
5601 #if defined(CONFIG_USER_ONLY)
5602     GEN_PRIV;
5603 #else
5604     CHK_SV;
5605     /* Restore CPU state */
5606     gen_helper_rfdi(cpu_env);
5607     gen_sync_exception(ctx);
5608 #endif /* defined(CONFIG_USER_ONLY) */
5609 }
5610 
5611 /* XXX: not implemented on 440 ? */
5612 static void gen_rfmci(DisasContext *ctx)
5613 {
5614 #if defined(CONFIG_USER_ONLY)
5615     GEN_PRIV;
5616 #else
5617     CHK_SV;
5618     /* Restore CPU state */
5619     gen_helper_rfmci(cpu_env);
5620     gen_sync_exception(ctx);
5621 #endif /* defined(CONFIG_USER_ONLY) */
5622 }
5623 
5624 /* TLB management - PowerPC 405 implementation */
5625 
5626 /* tlbre */
5627 static void gen_tlbre_40x(DisasContext *ctx)
5628 {
5629 #if defined(CONFIG_USER_ONLY)
5630     GEN_PRIV;
5631 #else
5632     CHK_SV;
5633     switch (rB(ctx->opcode)) {
5634     case 0:
5635         gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5636                                 cpu_gpr[rA(ctx->opcode)]);
5637         break;
5638     case 1:
5639         gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5640                                 cpu_gpr[rA(ctx->opcode)]);
5641         break;
5642     default:
5643         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5644         break;
5645     }
5646 #endif /* defined(CONFIG_USER_ONLY) */
5647 }
5648 
5649 /* tlbsx - tlbsx. */
5650 static void gen_tlbsx_40x(DisasContext *ctx)
5651 {
5652 #if defined(CONFIG_USER_ONLY)
5653     GEN_PRIV;
5654 #else
5655     TCGv t0;
5656 
5657     CHK_SV;
5658     t0 = tcg_temp_new();
5659     gen_addr_reg_index(ctx, t0);
5660     gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5661     tcg_temp_free(t0);
5662     if (Rc(ctx->opcode)) {
5663         TCGLabel *l1 = gen_new_label();
5664         tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5665         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5666         tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5667         gen_set_label(l1);
5668     }
5669 #endif /* defined(CONFIG_USER_ONLY) */
5670 }
5671 
5672 /* tlbwe */
5673 static void gen_tlbwe_40x(DisasContext *ctx)
5674 {
5675 #if defined(CONFIG_USER_ONLY)
5676     GEN_PRIV;
5677 #else
5678     CHK_SV;
5679 
5680     switch (rB(ctx->opcode)) {
5681     case 0:
5682         gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5683                                 cpu_gpr[rS(ctx->opcode)]);
5684         break;
5685     case 1:
5686         gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5687                                 cpu_gpr[rS(ctx->opcode)]);
5688         break;
5689     default:
5690         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5691         break;
5692     }
5693 #endif /* defined(CONFIG_USER_ONLY) */
5694 }
5695 
5696 /* TLB management - PowerPC 440 implementation */
5697 
5698 /* tlbre */
5699 static void gen_tlbre_440(DisasContext *ctx)
5700 {
5701 #if defined(CONFIG_USER_ONLY)
5702     GEN_PRIV;
5703 #else
5704     CHK_SV;
5705 
5706     switch (rB(ctx->opcode)) {
5707     case 0:
5708     case 1:
5709     case 2:
5710         {
5711             TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5712             gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5713                                  t0, cpu_gpr[rA(ctx->opcode)]);
5714             tcg_temp_free_i32(t0);
5715         }
5716         break;
5717     default:
5718         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5719         break;
5720     }
5721 #endif /* defined(CONFIG_USER_ONLY) */
5722 }
5723 
5724 /* tlbsx - tlbsx. */
5725 static void gen_tlbsx_440(DisasContext *ctx)
5726 {
5727 #if defined(CONFIG_USER_ONLY)
5728     GEN_PRIV;
5729 #else
5730     TCGv t0;
5731 
5732     CHK_SV;
5733     t0 = tcg_temp_new();
5734     gen_addr_reg_index(ctx, t0);
5735     gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5736     tcg_temp_free(t0);
5737     if (Rc(ctx->opcode)) {
5738         TCGLabel *l1 = gen_new_label();
5739         tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5740         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5741         tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5742         gen_set_label(l1);
5743     }
5744 #endif /* defined(CONFIG_USER_ONLY) */
5745 }
5746 
5747 /* tlbwe */
5748 static void gen_tlbwe_440(DisasContext *ctx)
5749 {
5750 #if defined(CONFIG_USER_ONLY)
5751     GEN_PRIV;
5752 #else
5753     CHK_SV;
5754     switch (rB(ctx->opcode)) {
5755     case 0:
5756     case 1:
5757     case 2:
5758         {
5759             TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5760             gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5761                                  cpu_gpr[rS(ctx->opcode)]);
5762             tcg_temp_free_i32(t0);
5763         }
5764         break;
5765     default:
5766         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5767         break;
5768     }
5769 #endif /* defined(CONFIG_USER_ONLY) */
5770 }
5771 
5772 /* TLB management - PowerPC BookE 2.06 implementation */
5773 
5774 /* tlbre */
5775 static void gen_tlbre_booke206(DisasContext *ctx)
5776 {
5777  #if defined(CONFIG_USER_ONLY)
5778     GEN_PRIV;
5779 #else
5780    CHK_SV;
5781     gen_helper_booke206_tlbre(cpu_env);
5782 #endif /* defined(CONFIG_USER_ONLY) */
5783 }
5784 
5785 /* tlbsx - tlbsx. */
5786 static void gen_tlbsx_booke206(DisasContext *ctx)
5787 {
5788 #if defined(CONFIG_USER_ONLY)
5789     GEN_PRIV;
5790 #else
5791     TCGv t0;
5792 
5793     CHK_SV;
5794     if (rA(ctx->opcode)) {
5795         t0 = tcg_temp_new();
5796         tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
5797     } else {
5798         t0 = tcg_const_tl(0);
5799     }
5800 
5801     tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
5802     gen_helper_booke206_tlbsx(cpu_env, t0);
5803     tcg_temp_free(t0);
5804 #endif /* defined(CONFIG_USER_ONLY) */
5805 }
5806 
5807 /* tlbwe */
5808 static void gen_tlbwe_booke206(DisasContext *ctx)
5809 {
5810 #if defined(CONFIG_USER_ONLY)
5811     GEN_PRIV;
5812 #else
5813     CHK_SV;
5814     gen_helper_booke206_tlbwe(cpu_env);
5815 #endif /* defined(CONFIG_USER_ONLY) */
5816 }
5817 
5818 static void gen_tlbivax_booke206(DisasContext *ctx)
5819 {
5820 #if defined(CONFIG_USER_ONLY)
5821     GEN_PRIV;
5822 #else
5823     TCGv t0;
5824 
5825     CHK_SV;
5826     t0 = tcg_temp_new();
5827     gen_addr_reg_index(ctx, t0);
5828     gen_helper_booke206_tlbivax(cpu_env, t0);
5829     tcg_temp_free(t0);
5830 #endif /* defined(CONFIG_USER_ONLY) */
5831 }
5832 
5833 static void gen_tlbilx_booke206(DisasContext *ctx)
5834 {
5835 #if defined(CONFIG_USER_ONLY)
5836     GEN_PRIV;
5837 #else
5838     TCGv t0;
5839 
5840     CHK_SV;
5841     t0 = tcg_temp_new();
5842     gen_addr_reg_index(ctx, t0);
5843 
5844     switch((ctx->opcode >> 21) & 0x3) {
5845     case 0:
5846         gen_helper_booke206_tlbilx0(cpu_env, t0);
5847         break;
5848     case 1:
5849         gen_helper_booke206_tlbilx1(cpu_env, t0);
5850         break;
5851     case 3:
5852         gen_helper_booke206_tlbilx3(cpu_env, t0);
5853         break;
5854     default:
5855         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5856         break;
5857     }
5858 
5859     tcg_temp_free(t0);
5860 #endif /* defined(CONFIG_USER_ONLY) */
5861 }
5862 
5863 
5864 /* wrtee */
5865 static void gen_wrtee(DisasContext *ctx)
5866 {
5867 #if defined(CONFIG_USER_ONLY)
5868     GEN_PRIV;
5869 #else
5870     TCGv t0;
5871 
5872     CHK_SV;
5873     t0 = tcg_temp_new();
5874     tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
5875     tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5876     tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
5877     tcg_temp_free(t0);
5878     /* Stop translation to have a chance to raise an exception
5879      * if we just set msr_ee to 1
5880      */
5881     gen_stop_exception(ctx);
5882 #endif /* defined(CONFIG_USER_ONLY) */
5883 }
5884 
5885 /* wrteei */
5886 static void gen_wrteei(DisasContext *ctx)
5887 {
5888 #if defined(CONFIG_USER_ONLY)
5889     GEN_PRIV;
5890 #else
5891     CHK_SV;
5892     if (ctx->opcode & 0x00008000) {
5893         tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
5894         /* Stop translation to have a chance to raise an exception */
5895         gen_stop_exception(ctx);
5896     } else {
5897         tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5898     }
5899 #endif /* defined(CONFIG_USER_ONLY) */
5900 }
5901 
5902 /* PowerPC 440 specific instructions */
5903 
5904 /* dlmzb */
5905 static void gen_dlmzb(DisasContext *ctx)
5906 {
5907     TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
5908     gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
5909                      cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
5910     tcg_temp_free_i32(t0);
5911 }
5912 
5913 /* mbar replaces eieio on 440 */
5914 static void gen_mbar(DisasContext *ctx)
5915 {
5916     /* interpreted as no-op */
5917 }
5918 
5919 /* msync replaces sync on 440 */
5920 static void gen_msync_4xx(DisasContext *ctx)
5921 {
5922     /* interpreted as no-op */
5923 }
5924 
5925 /* icbt */
5926 static void gen_icbt_440(DisasContext *ctx)
5927 {
5928     /* interpreted as no-op */
5929     /* XXX: specification say this is treated as a load by the MMU
5930      *      but does not generate any exception
5931      */
5932 }
5933 
5934 /* Embedded.Processor Control */
5935 
5936 static void gen_msgclr(DisasContext *ctx)
5937 {
5938 #if defined(CONFIG_USER_ONLY)
5939     GEN_PRIV;
5940 #else
5941     CHK_SV;
5942     gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5943 #endif /* defined(CONFIG_USER_ONLY) */
5944 }
5945 
5946 static void gen_msgsnd(DisasContext *ctx)
5947 {
5948 #if defined(CONFIG_USER_ONLY)
5949     GEN_PRIV;
5950 #else
5951     CHK_SV;
5952     gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
5953 #endif /* defined(CONFIG_USER_ONLY) */
5954 }
5955 
5956 
5957 #if defined(TARGET_PPC64)
5958 static void gen_maddld(DisasContext *ctx)
5959 {
5960     TCGv_i64 t1 = tcg_temp_new_i64();
5961 
5962     tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5963     tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
5964     tcg_temp_free_i64(t1);
5965 }
5966 
5967 /* maddhd maddhdu */
5968 static void gen_maddhd_maddhdu(DisasContext *ctx)
5969 {
5970     TCGv_i64 lo = tcg_temp_new_i64();
5971     TCGv_i64 hi = tcg_temp_new_i64();
5972     TCGv_i64 t1 = tcg_temp_new_i64();
5973 
5974     if (Rc(ctx->opcode)) {
5975         tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
5976                           cpu_gpr[rB(ctx->opcode)]);
5977         tcg_gen_movi_i64(t1, 0);
5978     } else {
5979         tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
5980                           cpu_gpr[rB(ctx->opcode)]);
5981         tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
5982     }
5983     tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
5984                      cpu_gpr[rC(ctx->opcode)], t1);
5985     tcg_temp_free_i64(lo);
5986     tcg_temp_free_i64(hi);
5987     tcg_temp_free_i64(t1);
5988 }
5989 #endif /* defined(TARGET_PPC64) */
5990 
5991 static void gen_tbegin(DisasContext *ctx)
5992 {
5993     if (unlikely(!ctx->tm_enabled)) {
5994         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
5995         return;
5996     }
5997     gen_helper_tbegin(cpu_env);
5998 }
5999 
6000 #define GEN_TM_NOOP(name)                                      \
6001 static inline void gen_##name(DisasContext *ctx)               \
6002 {                                                              \
6003     if (unlikely(!ctx->tm_enabled)) {                          \
6004         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);   \
6005         return;                                                \
6006     }                                                          \
6007     /* Because tbegin always fails in QEMU, these user         \
6008      * space instructions all have a simple implementation:    \
6009      *                                                         \
6010      *     CR[0] = 0b0 || MSR[TS] || 0b0                       \
6011      *           = 0b0 || 0b00    || 0b0                       \
6012      */                                                        \
6013     tcg_gen_movi_i32(cpu_crf[0], 0);                           \
6014 }
6015 
6016 GEN_TM_NOOP(tend);
6017 GEN_TM_NOOP(tabort);
6018 GEN_TM_NOOP(tabortwc);
6019 GEN_TM_NOOP(tabortwci);
6020 GEN_TM_NOOP(tabortdc);
6021 GEN_TM_NOOP(tabortdci);
6022 GEN_TM_NOOP(tsr);
6023 
6024 static void gen_tcheck(DisasContext *ctx)
6025 {
6026     if (unlikely(!ctx->tm_enabled)) {
6027         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6028         return;
6029     }
6030     /* Because tbegin always fails, the tcheck implementation
6031      * is simple:
6032      *
6033      * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6034      *         = 0b1 || 0b00 || 0b0
6035      */
6036     tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6037 }
6038 
6039 #if defined(CONFIG_USER_ONLY)
6040 #define GEN_TM_PRIV_NOOP(name)                                 \
6041 static inline void gen_##name(DisasContext *ctx)               \
6042 {                                                              \
6043     gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);           \
6044 }
6045 
6046 #else
6047 
6048 #define GEN_TM_PRIV_NOOP(name)                                 \
6049 static inline void gen_##name(DisasContext *ctx)               \
6050 {                                                              \
6051     CHK_SV;                                                    \
6052     if (unlikely(!ctx->tm_enabled)) {                          \
6053         gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);   \
6054         return;                                                \
6055     }                                                          \
6056     /* Because tbegin always fails, the implementation is      \
6057      * simple:                                                 \
6058      *                                                         \
6059      *   CR[0] = 0b0 || MSR[TS] || 0b0                         \
6060      *         = 0b0 || 0b00 | 0b0                             \
6061      */                                                        \
6062     tcg_gen_movi_i32(cpu_crf[0], 0);                           \
6063 }
6064 
6065 #endif
6066 
6067 GEN_TM_PRIV_NOOP(treclaim);
6068 GEN_TM_PRIV_NOOP(trechkpt);
6069 
6070 #include "translate/fp-impl.inc.c"
6071 
6072 #include "translate/vmx-impl.inc.c"
6073 
6074 #include "translate/vsx-impl.inc.c"
6075 
6076 #include "translate/dfp-impl.inc.c"
6077 
6078 #include "translate/spe-impl.inc.c"
6079 
6080 /* Handles lfdp, lxsd, lxssp */
6081 static void gen_dform39(DisasContext *ctx)
6082 {
6083     switch (ctx->opcode & 0x3) {
6084     case 0: /* lfdp */
6085         if (ctx->insns_flags2 & PPC2_ISA205) {
6086             return gen_lfdp(ctx);
6087         }
6088         break;
6089     case 2: /* lxsd */
6090         if (ctx->insns_flags2 & PPC2_ISA300) {
6091             return gen_lxsd(ctx);
6092         }
6093         break;
6094     case 3: /* lxssp */
6095         if (ctx->insns_flags2 & PPC2_ISA300) {
6096             return gen_lxssp(ctx);
6097         }
6098         break;
6099     }
6100     return gen_invalid(ctx);
6101 }
6102 
6103 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6104 static void gen_dform3D(DisasContext *ctx)
6105 {
6106     if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
6107         switch (ctx->opcode & 0x7) {
6108         case 1: /* lxv */
6109             if (ctx->insns_flags2 & PPC2_ISA300) {
6110                 return gen_lxv(ctx);
6111             }
6112             break;
6113         case 5: /* stxv */
6114             if (ctx->insns_flags2 & PPC2_ISA300) {
6115                 return gen_stxv(ctx);
6116             }
6117             break;
6118         }
6119     } else { /* DS-FORM */
6120         switch (ctx->opcode & 0x3) {
6121         case 0: /* stfdp */
6122             if (ctx->insns_flags2 & PPC2_ISA205) {
6123                 return gen_stfdp(ctx);
6124             }
6125             break;
6126         case 2: /* stxsd */
6127             if (ctx->insns_flags2 & PPC2_ISA300) {
6128                 return gen_stxsd(ctx);
6129             }
6130             break;
6131         case 3: /* stxssp */
6132             if (ctx->insns_flags2 & PPC2_ISA300) {
6133                 return gen_stxssp(ctx);
6134             }
6135             break;
6136         }
6137     }
6138     return gen_invalid(ctx);
6139 }
6140 
6141 static opcode_t opcodes[] = {
6142 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6143 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6144 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6145 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6146 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6147 #if defined(TARGET_PPC64)
6148 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6149 #endif
6150 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6151 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6152 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6153 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6154 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6155 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6156 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6157 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6158 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6159 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6160 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6161 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6162 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6163 #if defined(TARGET_PPC64)
6164 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6165 #endif
6166 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6167 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6168 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6169 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6170 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6171 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6172 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6173 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6174 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6175 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6176 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6177 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6178 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6179 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6180 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6181 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6182 #if defined(TARGET_PPC64)
6183 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6184 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6185 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6186 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6187 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6188 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6189 #endif
6190 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6191 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6192 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6193 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6194 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6195 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6196 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6197 #if defined(TARGET_PPC64)
6198 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6199 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6200 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6201 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6202 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6203 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6204                PPC_NONE, PPC2_ISA300),
6205 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6206                PPC_NONE, PPC2_ISA300),
6207 #endif
6208 #if defined(TARGET_PPC64)
6209 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6210 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6211 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6212 #endif
6213 /* handles lfdp, lxsd, lxssp */
6214 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6215 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6216 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6217 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6218 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6219 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6220 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6221 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6222 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6223 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6224 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6225 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6226 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6227 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6228 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6229 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6230 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6231 #if defined(TARGET_PPC64)
6232 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6233 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6234 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6235 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6236 #endif
6237 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6238 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6239 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6240 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6241 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6242 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6243 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6244 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6245 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6246 #if defined(TARGET_PPC64)
6247 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6248 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6249 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6250 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6251 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6252 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6253 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6254 #endif
6255 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6256 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6257 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6258 #if defined(TARGET_PPC64)
6259 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6260 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6261 #endif
6262 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6263 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6264 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6265 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6266 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6267 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6268 #if defined(TARGET_PPC64)
6269 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6270 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6271 #endif
6272 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6273 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6274 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6275 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6276 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6277 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6278 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6279 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6280 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6281 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6282 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6283 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6284 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6285 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6286 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6287 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6288 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6289 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6290 #if defined(TARGET_PPC64)
6291 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6292 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6293              PPC_SEGMENT_64B),
6294 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6295 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6296              PPC_SEGMENT_64B),
6297 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6298 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6299 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6300 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6301 #endif
6302 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6303 /* XXX Those instructions will need to be handled differently for
6304  * different ISA versions */
6305 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6306 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6307 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6308 #if defined(TARGET_PPC64)
6309 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6310 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6311 #endif
6312 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6313 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6314 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6315 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6316 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6317 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6318 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6319 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6320 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6321 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6322 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6323 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6324 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6325 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6326 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6327 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6328 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6329 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6330 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6331 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6332 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6333 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6334 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6335 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6336 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6337 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6338 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6339 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6340 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6341 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6342 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6343 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6344 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6345 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6346 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6347 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6348 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6349 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6350 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6351 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6352 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6353 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6354 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6355 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6356 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6357 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6358 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6359 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6360 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6361 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6362 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6363 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6364 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6365 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6366 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6367 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6368 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6369 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6370 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6371 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6372 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6373 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6374 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6375 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6376 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6377 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6378 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6379 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6380 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6381 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6382 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6383 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6384 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6385 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6386 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6387 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6388 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6389 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6390 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6391 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6392 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6393                PPC_NONE, PPC2_BOOKE206),
6394 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6395                PPC_NONE, PPC2_BOOKE206),
6396 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6397                PPC_NONE, PPC2_BOOKE206),
6398 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6399                PPC_NONE, PPC2_BOOKE206),
6400 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6401                PPC_NONE, PPC2_BOOKE206),
6402 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6403                PPC_NONE, PPC2_PRCNTL),
6404 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6405                PPC_NONE, PPC2_PRCNTL),
6406 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6407 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6408 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6409 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6410               PPC_BOOKE, PPC2_BOOKE206),
6411 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6412 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6413                PPC_BOOKE, PPC2_BOOKE206),
6414 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6415 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6416 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6417 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6418 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6419 #if defined(TARGET_PPC64)
6420 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6421               PPC2_ISA300),
6422 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6423 #endif
6424 
6425 #undef GEN_INT_ARITH_ADD
6426 #undef GEN_INT_ARITH_ADD_CONST
6427 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov)         \
6428 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6429 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val,                        \
6430                                 add_ca, compute_ca, compute_ov)               \
6431 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6432 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6433 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6434 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6435 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6436 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6437 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6438 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6439 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6440 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6441 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6442 
6443 #undef GEN_INT_ARITH_DIVW
6444 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \
6445 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6446 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6447 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6448 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6449 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6450 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6451 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6452 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6453 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6454 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6455 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6456 
6457 #if defined(TARGET_PPC64)
6458 #undef GEN_INT_ARITH_DIVD
6459 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov)                      \
6460 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6461 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6462 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6463 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6464 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6465 
6466 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6467 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6468 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6469 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6470 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6471 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6472 
6473 #undef GEN_INT_ARITH_MUL_HELPER
6474 #define GEN_INT_ARITH_MUL_HELPER(name, opc3)                                  \
6475 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6476 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6477 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6478 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6479 #endif
6480 
6481 #undef GEN_INT_ARITH_SUBF
6482 #undef GEN_INT_ARITH_SUBF_CONST
6483 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov)        \
6484 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6485 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val,                       \
6486                                 add_ca, compute_ca, compute_ov)               \
6487 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6488 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6489 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6490 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6491 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6492 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6493 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6494 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6495 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6496 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6497 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6498 
6499 #undef GEN_LOGICAL1
6500 #undef GEN_LOGICAL2
6501 #define GEN_LOGICAL2(name, tcg_op, opc, type)                                 \
6502 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6503 #define GEN_LOGICAL1(name, tcg_op, opc, type)                                 \
6504 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6505 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6506 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6507 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6508 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6509 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6510 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6511 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6512 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6513 #if defined(TARGET_PPC64)
6514 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6515 #endif
6516 
6517 #if defined(TARGET_PPC64)
6518 #undef GEN_PPC64_R2
6519 #undef GEN_PPC64_R4
6520 #define GEN_PPC64_R2(name, opc1, opc2)                                        \
6521 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6522 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
6523              PPC_64B)
6524 #define GEN_PPC64_R4(name, opc1, opc2)                                        \
6525 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6526 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000,   \
6527              PPC_64B),                                                        \
6528 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
6529              PPC_64B),                                                        \
6530 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000,   \
6531              PPC_64B)
6532 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6533 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6534 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6535 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6536 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6537 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6538 #endif
6539 
6540 #undef GEN_LD
6541 #undef GEN_LDU
6542 #undef GEN_LDUX
6543 #undef GEN_LDX_E
6544 #undef GEN_LDS
6545 #define GEN_LD(name, ldop, opc, type)                                         \
6546 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6547 #define GEN_LDU(name, ldop, opc, type)                                        \
6548 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6549 #define GEN_LDUX(name, ldop, opc2, opc3, type)                                \
6550 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6551 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk)                   \
6552 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6553 #define GEN_LDS(name, ldop, op, type)                                         \
6554 GEN_LD(name, ldop, op | 0x20, type)                                           \
6555 GEN_LDU(name, ldop, op | 0x21, type)                                          \
6556 GEN_LDUX(name, ldop, 0x17, op | 0x01, type)                                   \
6557 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6558 
6559 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6560 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6561 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6562 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6563 #if defined(TARGET_PPC64)
6564 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6565 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6566 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
6567 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
6568 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6569 
6570 /* HV/P7 and later only */
6571 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6572 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6573 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6574 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6575 #endif
6576 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6577 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6578 
6579 #undef GEN_ST
6580 #undef GEN_STU
6581 #undef GEN_STUX
6582 #undef GEN_STX_E
6583 #undef GEN_STS
6584 #define GEN_ST(name, stop, opc, type)                                         \
6585 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6586 #define GEN_STU(name, stop, opc, type)                                        \
6587 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6588 #define GEN_STUX(name, stop, opc2, opc3, type)                                \
6589 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6590 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk)                   \
6591 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6592 #define GEN_STS(name, stop, op, type)                                         \
6593 GEN_ST(name, stop, op | 0x20, type)                                           \
6594 GEN_STU(name, stop, op | 0x21, type)                                          \
6595 GEN_STUX(name, stop, 0x17, op | 0x01, type)                                   \
6596 GEN_STX(name, stop, 0x17, op | 0x00, type)
6597 
6598 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6599 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6600 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6601 #if defined(TARGET_PPC64)
6602 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
6603 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
6604 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6605 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6606 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6607 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6608 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6609 #endif
6610 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6611 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6612 
6613 #undef GEN_CRLOGIC
6614 #define GEN_CRLOGIC(name, tcg_op, opc)                                        \
6615 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6616 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6617 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6618 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6619 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6620 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6621 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6622 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6623 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6624 
6625 #undef GEN_MAC_HANDLER
6626 #define GEN_MAC_HANDLER(name, opc2, opc3)                                     \
6627 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6628 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6629 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6630 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6631 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6632 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6633 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6634 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6635 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6636 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6637 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6638 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6639 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6640 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6641 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6642 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6643 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6644 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6645 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6646 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6647 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6648 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6649 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6650 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6651 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6652 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6653 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6654 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6655 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6656 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6657 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6658 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6659 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6660 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6661 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6662 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6663 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6664 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6665 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6666 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6667 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6668 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6669 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6670 
6671 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6672                PPC_NONE, PPC2_TM),
6673 GEN_HANDLER2_E(tend,   "tend",   0x1F, 0x0E, 0x15, 0x01FFF800, \
6674                PPC_NONE, PPC2_TM),
6675 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6676                PPC_NONE, PPC2_TM),
6677 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6678                PPC_NONE, PPC2_TM),
6679 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6680                PPC_NONE, PPC2_TM),
6681 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6682                PPC_NONE, PPC2_TM),
6683 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6684                PPC_NONE, PPC2_TM),
6685 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6686                PPC_NONE, PPC2_TM),
6687 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6688                PPC_NONE, PPC2_TM),
6689 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6690                PPC_NONE, PPC2_TM),
6691 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6692                PPC_NONE, PPC2_TM),
6693 
6694 #include "translate/fp-ops.inc.c"
6695 
6696 #include "translate/vmx-ops.inc.c"
6697 
6698 #include "translate/vsx-ops.inc.c"
6699 
6700 #include "translate/dfp-ops.inc.c"
6701 
6702 #include "translate/spe-ops.inc.c"
6703 };
6704 
6705 #include "helper_regs.h"
6706 #include "translate_init.c"
6707 
6708 /*****************************************************************************/
6709 /* Misc PowerPC helpers */
6710 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6711                         int flags)
6712 {
6713 #define RGPL  4
6714 #define RFPL  4
6715 
6716     PowerPCCPU *cpu = POWERPC_CPU(cs);
6717     CPUPPCState *env = &cpu->env;
6718     int i;
6719 
6720     cpu_fprintf(f, "NIP " TARGET_FMT_lx "   LR " TARGET_FMT_lx " CTR "
6721                 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6722                 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6723                 cs->cpu_index);
6724     cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx "  HF "
6725                 TARGET_FMT_lx " iidx %d didx %d\n",
6726                 env->msr, env->spr[SPR_HID0],
6727                 env->hflags, env->immu_idx, env->dmmu_idx);
6728 #if !defined(NO_TIMER_DUMP)
6729     cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
6730 #if !defined(CONFIG_USER_ONLY)
6731                 " DECR %08" PRIu32
6732 #endif
6733                 "\n",
6734                 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6735 #if !defined(CONFIG_USER_ONLY)
6736                 , cpu_ppc_load_decr(env)
6737 #endif
6738                 );
6739 #endif
6740     for (i = 0; i < 32; i++) {
6741         if ((i & (RGPL - 1)) == 0)
6742             cpu_fprintf(f, "GPR%02d", i);
6743         cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
6744         if ((i & (RGPL - 1)) == (RGPL - 1))
6745             cpu_fprintf(f, "\n");
6746     }
6747     cpu_fprintf(f, "CR ");
6748     for (i = 0; i < 8; i++)
6749         cpu_fprintf(f, "%01x", env->crf[i]);
6750     cpu_fprintf(f, "  [");
6751     for (i = 0; i < 8; i++) {
6752         char a = '-';
6753         if (env->crf[i] & 0x08)
6754             a = 'L';
6755         else if (env->crf[i] & 0x04)
6756             a = 'G';
6757         else if (env->crf[i] & 0x02)
6758             a = 'E';
6759         cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6760     }
6761     cpu_fprintf(f, " ]             RES " TARGET_FMT_lx "\n",
6762                 env->reserve_addr);
6763     for (i = 0; i < 32; i++) {
6764         if ((i & (RFPL - 1)) == 0)
6765             cpu_fprintf(f, "FPR%02d", i);
6766         cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6767         if ((i & (RFPL - 1)) == (RFPL - 1))
6768             cpu_fprintf(f, "\n");
6769     }
6770     cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
6771 #if !defined(CONFIG_USER_ONLY)
6772     cpu_fprintf(f, " SRR0 " TARGET_FMT_lx "  SRR1 " TARGET_FMT_lx
6773                    "    PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
6774                 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
6775                 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
6776 
6777     cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
6778                    "  SPRG2 " TARGET_FMT_lx "  SPRG3 " TARGET_FMT_lx "\n",
6779                 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
6780                 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
6781 
6782     cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
6783                    "  SPRG6 " TARGET_FMT_lx "  SPRG7 " TARGET_FMT_lx "\n",
6784                 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
6785                 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
6786 
6787 #if defined(TARGET_PPC64)
6788     if (env->excp_model == POWERPC_EXCP_POWER7 ||
6789         env->excp_model == POWERPC_EXCP_POWER8) {
6790         cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
6791                     env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
6792     }
6793 #endif
6794     if (env->excp_model == POWERPC_EXCP_BOOKE) {
6795         cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
6796                        " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
6797                     env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
6798                     env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
6799 
6800         cpu_fprintf(f, "  TCR " TARGET_FMT_lx "   TSR " TARGET_FMT_lx
6801                        "    ESR " TARGET_FMT_lx "   DEAR " TARGET_FMT_lx "\n",
6802                     env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
6803                     env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
6804 
6805         cpu_fprintf(f, "  PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
6806                        "   IVPR " TARGET_FMT_lx "   EPCR " TARGET_FMT_lx "\n",
6807                     env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
6808                     env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
6809 
6810         cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
6811                        "    EPR " TARGET_FMT_lx "\n",
6812                     env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
6813                     env->spr[SPR_BOOKE_EPR]);
6814 
6815         /* FSL-specific */
6816         cpu_fprintf(f, " MCAR " TARGET_FMT_lx "  PID1 " TARGET_FMT_lx
6817                        "   PID2 " TARGET_FMT_lx "    SVR " TARGET_FMT_lx "\n",
6818                     env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
6819                     env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
6820 
6821         /*
6822          * IVORs are left out as they are large and do not change often --
6823          * they can be read with "p $ivor0", "p $ivor1", etc.
6824          */
6825     }
6826 
6827 #if defined(TARGET_PPC64)
6828     if (env->flags & POWERPC_FLAG_CFAR) {
6829         cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
6830     }
6831 #endif
6832 
6833     switch (env->mmu_model) {
6834     case POWERPC_MMU_32B:
6835     case POWERPC_MMU_601:
6836     case POWERPC_MMU_SOFT_6xx:
6837     case POWERPC_MMU_SOFT_74xx:
6838 #if defined(TARGET_PPC64)
6839     case POWERPC_MMU_64B:
6840     case POWERPC_MMU_2_03:
6841     case POWERPC_MMU_2_06:
6842     case POWERPC_MMU_2_06a:
6843     case POWERPC_MMU_2_07:
6844     case POWERPC_MMU_2_07a:
6845 #endif
6846         cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "   DAR " TARGET_FMT_lx
6847                        "  DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
6848                     env->spr[SPR_DAR], env->spr[SPR_DSISR]);
6849         break;
6850     case POWERPC_MMU_BOOKE206:
6851         cpu_fprintf(f, " MAS0 " TARGET_FMT_lx "  MAS1 " TARGET_FMT_lx
6852                        "   MAS2 " TARGET_FMT_lx "   MAS3 " TARGET_FMT_lx "\n",
6853                     env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
6854                     env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
6855 
6856         cpu_fprintf(f, " MAS4 " TARGET_FMT_lx "  MAS6 " TARGET_FMT_lx
6857                        "   MAS7 " TARGET_FMT_lx "    PID " TARGET_FMT_lx "\n",
6858                     env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
6859                     env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
6860 
6861         cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
6862                        " TLB1CFG " TARGET_FMT_lx "\n",
6863                     env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
6864                     env->spr[SPR_BOOKE_TLB1CFG]);
6865         break;
6866     default:
6867         break;
6868     }
6869 #endif
6870 
6871 #undef RGPL
6872 #undef RFPL
6873 }
6874 
6875 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
6876                              fprintf_function cpu_fprintf, int flags)
6877 {
6878 #if defined(DO_PPC_STATISTICS)
6879     PowerPCCPU *cpu = POWERPC_CPU(cs);
6880     opc_handler_t **t1, **t2, **t3, *handler;
6881     int op1, op2, op3;
6882 
6883     t1 = cpu->env.opcodes;
6884     for (op1 = 0; op1 < 64; op1++) {
6885         handler = t1[op1];
6886         if (is_indirect_opcode(handler)) {
6887             t2 = ind_table(handler);
6888             for (op2 = 0; op2 < 32; op2++) {
6889                 handler = t2[op2];
6890                 if (is_indirect_opcode(handler)) {
6891                     t3 = ind_table(handler);
6892                     for (op3 = 0; op3 < 32; op3++) {
6893                         handler = t3[op3];
6894                         if (handler->count == 0)
6895                             continue;
6896                         cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6897                                     "%016" PRIx64 " %" PRId64 "\n",
6898                                     op1, op2, op3, op1, (op3 << 5) | op2,
6899                                     handler->oname,
6900                                     handler->count, handler->count);
6901                     }
6902                 } else {
6903                     if (handler->count == 0)
6904                         continue;
6905                     cpu_fprintf(f, "%02x %02x    (%02x %04d) %16s: "
6906                                 "%016" PRIx64 " %" PRId64 "\n",
6907                                 op1, op2, op1, op2, handler->oname,
6908                                 handler->count, handler->count);
6909                 }
6910             }
6911         } else {
6912             if (handler->count == 0)
6913                 continue;
6914             cpu_fprintf(f, "%02x       (%02x     ) %16s: %016" PRIx64
6915                         " %" PRId64 "\n",
6916                         op1, op1, handler->oname,
6917                         handler->count, handler->count);
6918         }
6919     }
6920 #endif
6921 }
6922 
6923 /*****************************************************************************/
6924 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
6925 {
6926     PowerPCCPU *cpu = ppc_env_get_cpu(env);
6927     CPUState *cs = CPU(cpu);
6928     DisasContext ctx, *ctxp = &ctx;
6929     opc_handler_t **table, *handler;
6930     target_ulong pc_start;
6931     int num_insns;
6932     int max_insns;
6933 
6934     pc_start = tb->pc;
6935     ctx.nip = pc_start;
6936     ctx.tb = tb;
6937     ctx.exception = POWERPC_EXCP_NONE;
6938     ctx.spr_cb = env->spr_cb;
6939     ctx.pr = msr_pr;
6940     ctx.mem_idx = env->dmmu_idx;
6941     ctx.dr = msr_dr;
6942 #if !defined(CONFIG_USER_ONLY)
6943     ctx.hv = msr_hv || !env->has_hv_mode;
6944 #endif
6945     ctx.insns_flags = env->insns_flags;
6946     ctx.insns_flags2 = env->insns_flags2;
6947     ctx.access_type = -1;
6948     ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
6949     ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
6950     ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
6951 #if defined(TARGET_PPC64)
6952     ctx.sf_mode = msr_is_64bit(env, env->msr);
6953     ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
6954 #endif
6955     if (env->mmu_model == POWERPC_MMU_32B ||
6956         env->mmu_model == POWERPC_MMU_601 ||
6957         (env->mmu_model & POWERPC_MMU_64B))
6958             ctx.lazy_tlb_flush = true;
6959 
6960     ctx.fpu_enabled = !!msr_fp;
6961     if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6962         ctx.spe_enabled = !!msr_spe;
6963     else
6964         ctx.spe_enabled = false;
6965     if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6966         ctx.altivec_enabled = !!msr_vr;
6967     else
6968         ctx.altivec_enabled = false;
6969     if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
6970         ctx.vsx_enabled = !!msr_vsx;
6971     } else {
6972         ctx.vsx_enabled = false;
6973     }
6974 #if defined(TARGET_PPC64)
6975     if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
6976         ctx.tm_enabled = !!msr_tm;
6977     } else {
6978         ctx.tm_enabled = false;
6979     }
6980 #endif
6981     if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6982         ctx.singlestep_enabled = CPU_SINGLE_STEP;
6983     else
6984         ctx.singlestep_enabled = 0;
6985     if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6986         ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6987     if (unlikely(cs->singlestep_enabled)) {
6988         ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
6989     }
6990 #if defined (DO_SINGLE_STEP) && 0
6991     /* Single step trace mode */
6992     msr_se = 1;
6993 #endif
6994     num_insns = 0;
6995     max_insns = tb->cflags & CF_COUNT_MASK;
6996     if (max_insns == 0) {
6997         max_insns = CF_COUNT_MASK;
6998     }
6999     if (max_insns > TCG_MAX_INSNS) {
7000         max_insns = TCG_MAX_INSNS;
7001     }
7002 
7003     gen_tb_start(tb);
7004     tcg_clear_temp_count();
7005     /* Set env in case of segfault during code fetch */
7006     while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
7007         tcg_gen_insn_start(ctx.nip);
7008         num_insns++;
7009 
7010         if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
7011             gen_debug_exception(ctxp);
7012             /* The address covered by the breakpoint must be included in
7013                [tb->pc, tb->pc + tb->size) in order to for it to be
7014                properly cleared -- thus we increment the PC here so that
7015                the logic setting tb->size below does the right thing.  */
7016             ctx.nip += 4;
7017             break;
7018         }
7019 
7020         LOG_DISAS("----------------\n");
7021         LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7022                   ctx.nip, ctx.mem_idx, (int)msr_ir);
7023         if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7024             gen_io_start();
7025         if (unlikely(need_byteswap(&ctx))) {
7026             ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7027         } else {
7028             ctx.opcode = cpu_ldl_code(env, ctx.nip);
7029         }
7030         LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7031                   ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7032                   opc3(ctx.opcode), opc4(ctx.opcode),
7033                   ctx.le_mode ? "little" : "big");
7034         ctx.nip += 4;
7035         table = env->opcodes;
7036         handler = table[opc1(ctx.opcode)];
7037         if (is_indirect_opcode(handler)) {
7038             table = ind_table(handler);
7039             handler = table[opc2(ctx.opcode)];
7040             if (is_indirect_opcode(handler)) {
7041                 table = ind_table(handler);
7042                 handler = table[opc3(ctx.opcode)];
7043                 if (is_indirect_opcode(handler)) {
7044                     table = ind_table(handler);
7045                     handler = table[opc4(ctx.opcode)];
7046                 }
7047             }
7048         }
7049         /* Is opcode *REALLY* valid ? */
7050         if (unlikely(handler->handler == &gen_invalid)) {
7051             qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7052                           "%02x - %02x - %02x - %02x (%08x) "
7053                           TARGET_FMT_lx " %d\n",
7054                           opc1(ctx.opcode), opc2(ctx.opcode),
7055                           opc3(ctx.opcode), opc4(ctx.opcode),
7056                           ctx.opcode, ctx.nip - 4, (int)msr_ir);
7057         } else {
7058             uint32_t inval;
7059 
7060             if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7061                 inval = handler->inval2;
7062             } else {
7063                 inval = handler->inval1;
7064             }
7065 
7066             if (unlikely((ctx.opcode & inval) != 0)) {
7067                 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7068                               "%02x - %02x - %02x - %02x (%08x) "
7069                               TARGET_FMT_lx "\n", ctx.opcode & inval,
7070                               opc1(ctx.opcode), opc2(ctx.opcode),
7071                               opc3(ctx.opcode), opc4(ctx.opcode),
7072                               ctx.opcode, ctx.nip - 4);
7073                 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7074                 break;
7075             }
7076         }
7077         (*(handler->handler))(&ctx);
7078 #if defined(DO_PPC_STATISTICS)
7079         handler->count++;
7080 #endif
7081         /* Check trace mode exceptions */
7082         if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7083                      (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7084                      ctx.exception != POWERPC_SYSCALL &&
7085                      ctx.exception != POWERPC_EXCP_TRAP &&
7086                      ctx.exception != POWERPC_EXCP_BRANCH)) {
7087             gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7088         } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7089                             (cs->singlestep_enabled) ||
7090                             singlestep ||
7091                             num_insns >= max_insns)) {
7092             /* if we reach a page boundary or are single stepping, stop
7093              * generation
7094              */
7095             break;
7096         }
7097         if (tcg_check_temp_count()) {
7098             fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7099                     "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7100                     opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7101             exit(1);
7102         }
7103     }
7104     if (tb->cflags & CF_LAST_IO)
7105         gen_io_end();
7106     if (ctx.exception == POWERPC_EXCP_NONE) {
7107         gen_goto_tb(&ctx, 0, ctx.nip);
7108     } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7109         if (unlikely(cs->singlestep_enabled)) {
7110             gen_debug_exception(ctxp);
7111         }
7112         /* Generate the return instruction */
7113         tcg_gen_exit_tb(0);
7114     }
7115     gen_tb_end(tb, num_insns);
7116 
7117     tb->size = ctx.nip - pc_start;
7118     tb->icount = num_insns;
7119 
7120 #if defined(DEBUG_DISAS)
7121     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7122         && qemu_log_in_addr_range(pc_start)) {
7123         int flags;
7124         flags = env->bfd_mach;
7125         flags |= ctx.le_mode << 16;
7126         qemu_log_lock();
7127         qemu_log("IN: %s\n", lookup_symbol(pc_start));
7128         log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7129         qemu_log("\n");
7130         qemu_log_unlock();
7131     }
7132 #endif
7133 }
7134 
7135 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7136                           target_ulong *data)
7137 {
7138     env->nip = data[0];
7139 }
7140