1 /* 2 * Target-specific parts of semihosting/arm-compat-semi.c. 3 * 4 * Copyright (c) 2005, 2007 CodeSourcery. 5 * Copyright (c) 2019, 2022 Linaro 6 * Copyright © 2020 by Keith Packard <keithp@keithp.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0-or-later 9 */ 10 11 #ifndef TARGET_RISCV_COMMON_SEMI_TARGET_H 12 #define TARGET_RISCV_COMMON_SEMI_TARGET_H 13 14 static inline target_ulong common_semi_arg(CPUState *cs, int argno) 15 { 16 RISCVCPU *cpu = RISCV_CPU(cs); 17 CPURISCVState *env = &cpu->env; 18 return env->gpr[xA0 + argno]; 19 } 20 21 static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) 22 { 23 RISCVCPU *cpu = RISCV_CPU(cs); 24 CPURISCVState *env = &cpu->env; 25 env->gpr[xA0] = ret; 26 } 27 28 static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr) 29 { 30 return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8); 31 } 32 33 static inline bool is_64bit_semihosting(CPUArchState *env) 34 { 35 return riscv_cpu_mxl(env) != MXL_RV32; 36 } 37 38 static inline target_ulong common_semi_stack_bottom(CPUState *cs) 39 { 40 RISCVCPU *cpu = RISCV_CPU(cs); 41 CPURISCVState *env = &cpu->env; 42 return env->gpr[xSP]; 43 } 44 45 static inline bool common_semi_has_synccache(CPUArchState *env) 46 { 47 return true; 48 } 49 50 #endif 51