1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "internals.h" 27 #include "exec/exec-all.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "qemu/error-report.h" 31 #include "hw/qdev-properties.h" 32 #include "migration/vmstate.h" 33 #include "fpu/softfloat-helpers.h" 34 #include "sysemu/kvm.h" 35 #include "sysemu/tcg.h" 36 #include "kvm/kvm_riscv.h" 37 #include "tcg/tcg-cpu.h" 38 #include "tcg/tcg.h" 39 40 /* RISC-V CPU definitions */ 41 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 42 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, 43 RVC, RVS, RVU, RVH, RVJ, RVG, 0}; 44 45 /* 46 * From vector_helper.c 47 * Note that vector data is stored in host-endian 64-bit chunks, 48 * so addressing bytes needs a host-endian fixup. 49 */ 50 #if HOST_BIG_ENDIAN 51 #define BYTE(x) ((x) ^ 7) 52 #else 53 #define BYTE(x) (x) 54 #endif 55 56 bool riscv_cpu_is_32bit(RISCVCPU *cpu) 57 { 58 return riscv_cpu_mxl(&cpu->env) == MXL_RV32; 59 } 60 61 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ 62 {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} 63 64 /* 65 * Here are the ordering rules of extension naming defined by RISC-V 66 * specification : 67 * 1. All extensions should be separated from other multi-letter extensions 68 * by an underscore. 69 * 2. The first letter following the 'Z' conventionally indicates the most 70 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 71 * If multiple 'Z' extensions are named, they should be ordered first 72 * by category, then alphabetically within a category. 73 * 3. Standard supervisor-level extensions (starts with 'S') should be 74 * listed after standard unprivileged extensions. If multiple 75 * supervisor-level extensions are listed, they should be ordered 76 * alphabetically. 77 * 4. Non-standard extensions (starts with 'X') must be listed after all 78 * standard extensions. They must be separated from other multi-letter 79 * extensions by an underscore. 80 * 81 * Single letter extensions are checked in riscv_cpu_validate_misa_priv() 82 * instead. 83 */ 84 const RISCVIsaExtData isa_edata_arr[] = { 85 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom), 86 ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop), 87 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz), 88 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), 89 ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr), 90 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr), 91 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei), 92 ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), 93 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), 94 ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm), 95 ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), 96 ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas), 97 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), 98 ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), 99 ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin), 100 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), 101 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), 102 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), 103 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), 104 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), 105 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), 106 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), 107 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), 108 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), 109 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), 110 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), 111 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), 112 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), 113 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), 114 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), 115 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), 116 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), 117 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), 118 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), 119 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), 120 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), 121 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), 122 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), 123 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), 124 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), 125 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), 126 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), 127 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), 128 ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb), 129 ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), 130 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), 131 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), 132 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), 133 ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin), 134 ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), 135 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), 136 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), 137 ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb), 138 ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), 139 ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn), 140 ISA_EXT_DATA_ENTRY(zvknc, PRIV_VERSION_1_12_0, ext_zvknc), 141 ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), 142 ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng), 143 ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), 144 ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), 145 ISA_EXT_DATA_ENTRY(zvks, PRIV_VERSION_1_12_0, ext_zvks), 146 ISA_EXT_DATA_ENTRY(zvksc, PRIV_VERSION_1_12_0, ext_zvksc), 147 ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), 148 ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg), 149 ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), 150 ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), 151 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), 152 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), 153 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), 154 ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), 155 ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), 156 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), 157 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), 158 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), 159 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), 160 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), 161 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), 162 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), 163 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), 164 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), 165 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), 166 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), 167 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 168 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 169 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), 170 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), 171 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 172 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair), 173 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), 174 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 175 176 DEFINE_PROP_END_OF_LIST(), 177 }; 178 179 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) 180 { 181 bool *ext_enabled = (void *)&cpu->cfg + ext_offset; 182 183 return *ext_enabled; 184 } 185 186 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en) 187 { 188 bool *ext_enabled = (void *)&cpu->cfg + ext_offset; 189 190 *ext_enabled = en; 191 } 192 193 const char * const riscv_int_regnames[] = { 194 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 195 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 196 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 197 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 198 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 199 }; 200 201 const char * const riscv_int_regnamesh[] = { 202 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 203 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 204 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 205 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 206 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 207 "x30h/t5h", "x31h/t6h" 208 }; 209 210 const char * const riscv_fpr_regnames[] = { 211 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 212 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 213 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 214 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 215 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 216 "f30/ft10", "f31/ft11" 217 }; 218 219 const char * const riscv_rvv_regnames[] = { 220 "v0", "v1", "v2", "v3", "v4", "v5", "v6", 221 "v7", "v8", "v9", "v10", "v11", "v12", "v13", 222 "v14", "v15", "v16", "v17", "v18", "v19", "v20", 223 "v21", "v22", "v23", "v24", "v25", "v26", "v27", 224 "v28", "v29", "v30", "v31" 225 }; 226 227 static const char * const riscv_excp_names[] = { 228 "misaligned_fetch", 229 "fault_fetch", 230 "illegal_instruction", 231 "breakpoint", 232 "misaligned_load", 233 "fault_load", 234 "misaligned_store", 235 "fault_store", 236 "user_ecall", 237 "supervisor_ecall", 238 "hypervisor_ecall", 239 "machine_ecall", 240 "exec_page_fault", 241 "load_page_fault", 242 "reserved", 243 "store_page_fault", 244 "reserved", 245 "reserved", 246 "reserved", 247 "reserved", 248 "guest_exec_page_fault", 249 "guest_load_page_fault", 250 "reserved", 251 "guest_store_page_fault", 252 }; 253 254 static const char * const riscv_intr_names[] = { 255 "u_software", 256 "s_software", 257 "vs_software", 258 "m_software", 259 "u_timer", 260 "s_timer", 261 "vs_timer", 262 "m_timer", 263 "u_external", 264 "s_external", 265 "vs_external", 266 "m_external", 267 "reserved", 268 "reserved", 269 "reserved", 270 "reserved" 271 }; 272 273 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 274 { 275 if (async) { 276 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 277 riscv_intr_names[cause] : "(unknown)"; 278 } else { 279 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 280 riscv_excp_names[cause] : "(unknown)"; 281 } 282 } 283 284 void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 285 { 286 env->misa_mxl_max = env->misa_mxl = mxl; 287 env->misa_ext_mask = env->misa_ext = ext; 288 } 289 290 #ifndef CONFIG_USER_ONLY 291 static uint8_t satp_mode_from_str(const char *satp_mode_str) 292 { 293 if (!strncmp(satp_mode_str, "mbare", 5)) { 294 return VM_1_10_MBARE; 295 } 296 297 if (!strncmp(satp_mode_str, "sv32", 4)) { 298 return VM_1_10_SV32; 299 } 300 301 if (!strncmp(satp_mode_str, "sv39", 4)) { 302 return VM_1_10_SV39; 303 } 304 305 if (!strncmp(satp_mode_str, "sv48", 4)) { 306 return VM_1_10_SV48; 307 } 308 309 if (!strncmp(satp_mode_str, "sv57", 4)) { 310 return VM_1_10_SV57; 311 } 312 313 if (!strncmp(satp_mode_str, "sv64", 4)) { 314 return VM_1_10_SV64; 315 } 316 317 g_assert_not_reached(); 318 } 319 320 uint8_t satp_mode_max_from_map(uint32_t map) 321 { 322 /* 323 * 'map = 0' will make us return (31 - 32), which C will 324 * happily overflow to UINT_MAX. There's no good result to 325 * return if 'map = 0' (e.g. returning 0 will be ambiguous 326 * with the result for 'map = 1'). 327 * 328 * Assert out if map = 0. Callers will have to deal with 329 * it outside of this function. 330 */ 331 g_assert(map > 0); 332 333 /* map here has at least one bit set, so no problem with clz */ 334 return 31 - __builtin_clz(map); 335 } 336 337 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) 338 { 339 if (is_32_bit) { 340 switch (satp_mode) { 341 case VM_1_10_SV32: 342 return "sv32"; 343 case VM_1_10_MBARE: 344 return "none"; 345 } 346 } else { 347 switch (satp_mode) { 348 case VM_1_10_SV64: 349 return "sv64"; 350 case VM_1_10_SV57: 351 return "sv57"; 352 case VM_1_10_SV48: 353 return "sv48"; 354 case VM_1_10_SV39: 355 return "sv39"; 356 case VM_1_10_MBARE: 357 return "none"; 358 } 359 } 360 361 g_assert_not_reached(); 362 } 363 364 static void set_satp_mode_max_supported(RISCVCPU *cpu, 365 uint8_t satp_mode) 366 { 367 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 368 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; 369 370 for (int i = 0; i <= satp_mode; ++i) { 371 if (valid_vm[i]) { 372 cpu->cfg.satp_mode.supported |= (1 << i); 373 } 374 } 375 } 376 377 /* Set the satp mode to the max supported */ 378 static void set_satp_mode_default_map(RISCVCPU *cpu) 379 { 380 /* 381 * Bare CPUs do not default to the max available. 382 * Users must set a valid satp_mode in the command 383 * line. 384 */ 385 if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_BARE_CPU) != NULL) { 386 warn_report("No satp mode set. Defaulting to 'bare'"); 387 cpu->cfg.satp_mode.map = (1 << VM_1_10_MBARE); 388 return; 389 } 390 391 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; 392 } 393 #endif 394 395 static void riscv_any_cpu_init(Object *obj) 396 { 397 RISCVCPU *cpu = RISCV_CPU(obj); 398 CPURISCVState *env = &cpu->env; 399 #if defined(TARGET_RISCV32) 400 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 401 #elif defined(TARGET_RISCV64) 402 riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 403 #endif 404 405 #ifndef CONFIG_USER_ONLY 406 set_satp_mode_max_supported(RISCV_CPU(obj), 407 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? 408 VM_1_10_SV32 : VM_1_10_SV57); 409 #endif 410 411 env->priv_ver = PRIV_VERSION_LATEST; 412 413 /* inherited from parent obj via riscv_cpu_init() */ 414 cpu->cfg.ext_zifencei = true; 415 cpu->cfg.ext_zicsr = true; 416 cpu->cfg.mmu = true; 417 cpu->cfg.pmp = true; 418 } 419 420 static void riscv_max_cpu_init(Object *obj) 421 { 422 RISCVCPU *cpu = RISCV_CPU(obj); 423 CPURISCVState *env = &cpu->env; 424 RISCVMXL mlx = MXL_RV64; 425 426 #ifdef TARGET_RISCV32 427 mlx = MXL_RV32; 428 #endif 429 riscv_cpu_set_misa(env, mlx, 0); 430 env->priv_ver = PRIV_VERSION_LATEST; 431 #ifndef CONFIG_USER_ONLY 432 set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ? 433 VM_1_10_SV32 : VM_1_10_SV57); 434 #endif 435 } 436 437 #if defined(TARGET_RISCV64) 438 static void rv64_base_cpu_init(Object *obj) 439 { 440 CPURISCVState *env = &RISCV_CPU(obj)->env; 441 /* We set this in the realise function */ 442 riscv_cpu_set_misa(env, MXL_RV64, 0); 443 /* Set latest version of privileged specification */ 444 env->priv_ver = PRIV_VERSION_LATEST; 445 #ifndef CONFIG_USER_ONLY 446 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 447 #endif 448 } 449 450 static void rv64_sifive_u_cpu_init(Object *obj) 451 { 452 RISCVCPU *cpu = RISCV_CPU(obj); 453 CPURISCVState *env = &cpu->env; 454 riscv_cpu_set_misa(env, MXL_RV64, 455 RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 456 env->priv_ver = PRIV_VERSION_1_10_0; 457 #ifndef CONFIG_USER_ONLY 458 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); 459 #endif 460 461 /* inherited from parent obj via riscv_cpu_init() */ 462 cpu->cfg.ext_zifencei = true; 463 cpu->cfg.ext_zicsr = true; 464 cpu->cfg.mmu = true; 465 cpu->cfg.pmp = true; 466 } 467 468 static void rv64_sifive_e_cpu_init(Object *obj) 469 { 470 CPURISCVState *env = &RISCV_CPU(obj)->env; 471 RISCVCPU *cpu = RISCV_CPU(obj); 472 473 riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 474 env->priv_ver = PRIV_VERSION_1_10_0; 475 #ifndef CONFIG_USER_ONLY 476 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 477 #endif 478 479 /* inherited from parent obj via riscv_cpu_init() */ 480 cpu->cfg.ext_zifencei = true; 481 cpu->cfg.ext_zicsr = true; 482 cpu->cfg.pmp = true; 483 } 484 485 static void rv64_thead_c906_cpu_init(Object *obj) 486 { 487 CPURISCVState *env = &RISCV_CPU(obj)->env; 488 RISCVCPU *cpu = RISCV_CPU(obj); 489 490 riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); 491 env->priv_ver = PRIV_VERSION_1_11_0; 492 493 cpu->cfg.ext_zfa = true; 494 cpu->cfg.ext_zfh = true; 495 cpu->cfg.mmu = true; 496 cpu->cfg.ext_xtheadba = true; 497 cpu->cfg.ext_xtheadbb = true; 498 cpu->cfg.ext_xtheadbs = true; 499 cpu->cfg.ext_xtheadcmo = true; 500 cpu->cfg.ext_xtheadcondmov = true; 501 cpu->cfg.ext_xtheadfmemidx = true; 502 cpu->cfg.ext_xtheadmac = true; 503 cpu->cfg.ext_xtheadmemidx = true; 504 cpu->cfg.ext_xtheadmempair = true; 505 cpu->cfg.ext_xtheadsync = true; 506 507 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 508 #ifndef CONFIG_USER_ONLY 509 set_satp_mode_max_supported(cpu, VM_1_10_SV39); 510 #endif 511 512 /* inherited from parent obj via riscv_cpu_init() */ 513 cpu->cfg.pmp = true; 514 } 515 516 static void rv64_veyron_v1_cpu_init(Object *obj) 517 { 518 CPURISCVState *env = &RISCV_CPU(obj)->env; 519 RISCVCPU *cpu = RISCV_CPU(obj); 520 521 riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); 522 env->priv_ver = PRIV_VERSION_1_12_0; 523 524 /* Enable ISA extensions */ 525 cpu->cfg.mmu = true; 526 cpu->cfg.ext_zifencei = true; 527 cpu->cfg.ext_zicsr = true; 528 cpu->cfg.pmp = true; 529 cpu->cfg.ext_zicbom = true; 530 cpu->cfg.cbom_blocksize = 64; 531 cpu->cfg.cboz_blocksize = 64; 532 cpu->cfg.ext_zicboz = true; 533 cpu->cfg.ext_smaia = true; 534 cpu->cfg.ext_ssaia = true; 535 cpu->cfg.ext_sscofpmf = true; 536 cpu->cfg.ext_sstc = true; 537 cpu->cfg.ext_svinval = true; 538 cpu->cfg.ext_svnapot = true; 539 cpu->cfg.ext_svpbmt = true; 540 cpu->cfg.ext_smstateen = true; 541 cpu->cfg.ext_zba = true; 542 cpu->cfg.ext_zbb = true; 543 cpu->cfg.ext_zbc = true; 544 cpu->cfg.ext_zbs = true; 545 cpu->cfg.ext_XVentanaCondOps = true; 546 547 cpu->cfg.mvendorid = VEYRON_V1_MVENDORID; 548 cpu->cfg.marchid = VEYRON_V1_MARCHID; 549 cpu->cfg.mimpid = VEYRON_V1_MIMPID; 550 551 #ifndef CONFIG_USER_ONLY 552 set_satp_mode_max_supported(cpu, VM_1_10_SV48); 553 #endif 554 } 555 556 static void rv128_base_cpu_init(Object *obj) 557 { 558 if (qemu_tcg_mttcg_enabled()) { 559 /* Missing 128-bit aligned atomics */ 560 error_report("128-bit RISC-V currently does not work with Multi " 561 "Threaded TCG. Please use: -accel tcg,thread=single"); 562 exit(EXIT_FAILURE); 563 } 564 CPURISCVState *env = &RISCV_CPU(obj)->env; 565 /* We set this in the realise function */ 566 riscv_cpu_set_misa(env, MXL_RV128, 0); 567 /* Set latest version of privileged specification */ 568 env->priv_ver = PRIV_VERSION_LATEST; 569 #ifndef CONFIG_USER_ONLY 570 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 571 #endif 572 } 573 574 static void rv64i_bare_cpu_init(Object *obj) 575 { 576 CPURISCVState *env = &RISCV_CPU(obj)->env; 577 riscv_cpu_set_misa(env, MXL_RV64, RVI); 578 579 /* Remove the defaults from the parent class */ 580 RISCV_CPU(obj)->cfg.ext_zicntr = false; 581 RISCV_CPU(obj)->cfg.ext_zihpm = false; 582 583 /* Set to QEMU's first supported priv version */ 584 env->priv_ver = PRIV_VERSION_1_10_0; 585 586 /* 587 * Support all available satp_mode settings. The default 588 * value will be set to MBARE if the user doesn't set 589 * satp_mode manually (see set_satp_mode_default()). 590 */ 591 #ifndef CONFIG_USER_ONLY 592 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64); 593 #endif 594 } 595 #else 596 static void rv32_base_cpu_init(Object *obj) 597 { 598 CPURISCVState *env = &RISCV_CPU(obj)->env; 599 /* We set this in the realise function */ 600 riscv_cpu_set_misa(env, MXL_RV32, 0); 601 /* Set latest version of privileged specification */ 602 env->priv_ver = PRIV_VERSION_LATEST; 603 #ifndef CONFIG_USER_ONLY 604 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 605 #endif 606 } 607 608 static void rv32_sifive_u_cpu_init(Object *obj) 609 { 610 RISCVCPU *cpu = RISCV_CPU(obj); 611 CPURISCVState *env = &cpu->env; 612 riscv_cpu_set_misa(env, MXL_RV32, 613 RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 614 env->priv_ver = PRIV_VERSION_1_10_0; 615 #ifndef CONFIG_USER_ONLY 616 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 617 #endif 618 619 /* inherited from parent obj via riscv_cpu_init() */ 620 cpu->cfg.ext_zifencei = true; 621 cpu->cfg.ext_zicsr = true; 622 cpu->cfg.mmu = true; 623 cpu->cfg.pmp = true; 624 } 625 626 static void rv32_sifive_e_cpu_init(Object *obj) 627 { 628 CPURISCVState *env = &RISCV_CPU(obj)->env; 629 RISCVCPU *cpu = RISCV_CPU(obj); 630 631 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 632 env->priv_ver = PRIV_VERSION_1_10_0; 633 #ifndef CONFIG_USER_ONLY 634 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 635 #endif 636 637 /* inherited from parent obj via riscv_cpu_init() */ 638 cpu->cfg.ext_zifencei = true; 639 cpu->cfg.ext_zicsr = true; 640 cpu->cfg.pmp = true; 641 } 642 643 static void rv32_ibex_cpu_init(Object *obj) 644 { 645 CPURISCVState *env = &RISCV_CPU(obj)->env; 646 RISCVCPU *cpu = RISCV_CPU(obj); 647 648 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 649 env->priv_ver = PRIV_VERSION_1_12_0; 650 #ifndef CONFIG_USER_ONLY 651 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 652 #endif 653 /* inherited from parent obj via riscv_cpu_init() */ 654 cpu->cfg.ext_zifencei = true; 655 cpu->cfg.ext_zicsr = true; 656 cpu->cfg.pmp = true; 657 cpu->cfg.ext_smepmp = true; 658 } 659 660 static void rv32_imafcu_nommu_cpu_init(Object *obj) 661 { 662 CPURISCVState *env = &RISCV_CPU(obj)->env; 663 RISCVCPU *cpu = RISCV_CPU(obj); 664 665 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 666 env->priv_ver = PRIV_VERSION_1_10_0; 667 #ifndef CONFIG_USER_ONLY 668 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 669 #endif 670 671 /* inherited from parent obj via riscv_cpu_init() */ 672 cpu->cfg.ext_zifencei = true; 673 cpu->cfg.ext_zicsr = true; 674 cpu->cfg.pmp = true; 675 } 676 #endif 677 678 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 679 { 680 ObjectClass *oc; 681 char *typename; 682 char **cpuname; 683 684 cpuname = g_strsplit(cpu_model, ",", 1); 685 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 686 oc = object_class_by_name(typename); 687 g_strfreev(cpuname); 688 g_free(typename); 689 690 return oc; 691 } 692 693 char *riscv_cpu_get_name(RISCVCPU *cpu) 694 { 695 RISCVCPUClass *rcc = RISCV_CPU_GET_CLASS(cpu); 696 const char *typename = object_class_get_name(OBJECT_CLASS(rcc)); 697 698 g_assert(g_str_has_suffix(typename, RISCV_CPU_TYPE_SUFFIX)); 699 700 return cpu_model_from_type(typename); 701 } 702 703 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 704 { 705 RISCVCPU *cpu = RISCV_CPU(cs); 706 CPURISCVState *env = &cpu->env; 707 int i, j; 708 uint8_t *p; 709 710 #if !defined(CONFIG_USER_ONLY) 711 if (riscv_has_ext(env, RVH)) { 712 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); 713 } 714 #endif 715 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 716 #ifndef CONFIG_USER_ONLY 717 { 718 static const int dump_csrs[] = { 719 CSR_MHARTID, 720 CSR_MSTATUS, 721 CSR_MSTATUSH, 722 /* 723 * CSR_SSTATUS is intentionally omitted here as its value 724 * can be figured out by looking at CSR_MSTATUS 725 */ 726 CSR_HSTATUS, 727 CSR_VSSTATUS, 728 CSR_MIP, 729 CSR_MIE, 730 CSR_MIDELEG, 731 CSR_HIDELEG, 732 CSR_MEDELEG, 733 CSR_HEDELEG, 734 CSR_MTVEC, 735 CSR_STVEC, 736 CSR_VSTVEC, 737 CSR_MEPC, 738 CSR_SEPC, 739 CSR_VSEPC, 740 CSR_MCAUSE, 741 CSR_SCAUSE, 742 CSR_VSCAUSE, 743 CSR_MTVAL, 744 CSR_STVAL, 745 CSR_HTVAL, 746 CSR_MTVAL2, 747 CSR_MSCRATCH, 748 CSR_SSCRATCH, 749 CSR_SATP, 750 CSR_MMTE, 751 CSR_UPMBASE, 752 CSR_UPMMASK, 753 CSR_SPMBASE, 754 CSR_SPMMASK, 755 CSR_MPMBASE, 756 CSR_MPMMASK, 757 }; 758 759 for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 760 int csrno = dump_csrs[i]; 761 target_ulong val = 0; 762 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 763 764 /* 765 * Rely on the smode, hmode, etc, predicates within csr.c 766 * to do the filtering of the registers that are present. 767 */ 768 if (res == RISCV_EXCP_NONE) { 769 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 770 csr_ops[csrno].name, val); 771 } 772 } 773 } 774 #endif 775 776 for (i = 0; i < 32; i++) { 777 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 778 riscv_int_regnames[i], env->gpr[i]); 779 if ((i & 3) == 3) { 780 qemu_fprintf(f, "\n"); 781 } 782 } 783 if (flags & CPU_DUMP_FPU) { 784 for (i = 0; i < 32; i++) { 785 qemu_fprintf(f, " %-8s %016" PRIx64, 786 riscv_fpr_regnames[i], env->fpr[i]); 787 if ((i & 3) == 3) { 788 qemu_fprintf(f, "\n"); 789 } 790 } 791 } 792 if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) { 793 static const int dump_rvv_csrs[] = { 794 CSR_VSTART, 795 CSR_VXSAT, 796 CSR_VXRM, 797 CSR_VCSR, 798 CSR_VL, 799 CSR_VTYPE, 800 CSR_VLENB, 801 }; 802 for (i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) { 803 int csrno = dump_rvv_csrs[i]; 804 target_ulong val = 0; 805 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 806 807 /* 808 * Rely on the smode, hmode, etc, predicates within csr.c 809 * to do the filtering of the registers that are present. 810 */ 811 if (res == RISCV_EXCP_NONE) { 812 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 813 csr_ops[csrno].name, val); 814 } 815 } 816 uint16_t vlenb = cpu->cfg.vlen >> 3; 817 818 for (i = 0; i < 32; i++) { 819 qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]); 820 p = (uint8_t *)env->vreg; 821 for (j = vlenb - 1 ; j >= 0; j--) { 822 qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j))); 823 } 824 qemu_fprintf(f, "\n"); 825 } 826 } 827 } 828 829 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 830 { 831 RISCVCPU *cpu = RISCV_CPU(cs); 832 CPURISCVState *env = &cpu->env; 833 834 if (env->xl == MXL_RV32) { 835 env->pc = (int32_t)value; 836 } else { 837 env->pc = value; 838 } 839 } 840 841 static vaddr riscv_cpu_get_pc(CPUState *cs) 842 { 843 RISCVCPU *cpu = RISCV_CPU(cs); 844 CPURISCVState *env = &cpu->env; 845 846 /* Match cpu_get_tb_cpu_state. */ 847 if (env->xl == MXL_RV32) { 848 return env->pc & UINT32_MAX; 849 } 850 return env->pc; 851 } 852 853 static bool riscv_cpu_has_work(CPUState *cs) 854 { 855 #ifndef CONFIG_USER_ONLY 856 RISCVCPU *cpu = RISCV_CPU(cs); 857 CPURISCVState *env = &cpu->env; 858 /* 859 * Definition of the WFI instruction requires it to ignore the privilege 860 * mode and delegation registers, but respect individual enables 861 */ 862 return riscv_cpu_all_pending(env) != 0 || 863 riscv_cpu_sirq_pending(env) != RISCV_EXCP_NONE || 864 riscv_cpu_vsirq_pending(env) != RISCV_EXCP_NONE; 865 #else 866 return true; 867 #endif 868 } 869 870 static void riscv_cpu_reset_hold(Object *obj) 871 { 872 #ifndef CONFIG_USER_ONLY 873 uint8_t iprio; 874 int i, irq, rdzero; 875 #endif 876 CPUState *cs = CPU(obj); 877 RISCVCPU *cpu = RISCV_CPU(cs); 878 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 879 CPURISCVState *env = &cpu->env; 880 881 if (mcc->parent_phases.hold) { 882 mcc->parent_phases.hold(obj); 883 } 884 #ifndef CONFIG_USER_ONLY 885 env->misa_mxl = env->misa_mxl_max; 886 env->priv = PRV_M; 887 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 888 if (env->misa_mxl > MXL_RV32) { 889 /* 890 * The reset status of SXL/UXL is undefined, but mstatus is WARL 891 * and we must ensure that the value after init is valid for read. 892 */ 893 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 894 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 895 if (riscv_has_ext(env, RVH)) { 896 env->vsstatus = set_field(env->vsstatus, 897 MSTATUS64_SXL, env->misa_mxl); 898 env->vsstatus = set_field(env->vsstatus, 899 MSTATUS64_UXL, env->misa_mxl); 900 env->mstatus_hs = set_field(env->mstatus_hs, 901 MSTATUS64_SXL, env->misa_mxl); 902 env->mstatus_hs = set_field(env->mstatus_hs, 903 MSTATUS64_UXL, env->misa_mxl); 904 } 905 } 906 env->mcause = 0; 907 env->miclaim = MIP_SGEIP; 908 env->pc = env->resetvec; 909 env->bins = 0; 910 env->two_stage_lookup = false; 911 912 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | 913 (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); 914 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | 915 (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0); 916 917 /* Initialized default priorities of local interrupts. */ 918 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 919 iprio = riscv_cpu_default_priority(i); 920 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 921 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 922 env->hviprio[i] = 0; 923 } 924 i = 0; 925 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 926 if (!rdzero) { 927 env->hviprio[irq] = env->miprio[irq]; 928 } 929 i++; 930 } 931 /* mmte is supposed to have pm.current hardwired to 1 */ 932 env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); 933 934 /* 935 * Clear mseccfg and unlock all the PMP entries upon reset. 936 * This is allowed as per the priv and smepmp specifications 937 * and is needed to clear stale entries across reboots. 938 */ 939 if (riscv_cpu_cfg(env)->ext_smepmp) { 940 env->mseccfg = 0; 941 } 942 943 pmp_unlock_entries(env); 944 #endif 945 env->xl = riscv_cpu_mxl(env); 946 riscv_cpu_update_mask(env); 947 cs->exception_index = RISCV_EXCP_NONE; 948 env->load_res = -1; 949 set_default_nan_mode(1, &env->fp_status); 950 951 #ifndef CONFIG_USER_ONLY 952 if (cpu->cfg.debug) { 953 riscv_trigger_reset_hold(env); 954 } 955 956 if (kvm_enabled()) { 957 kvm_riscv_reset_vcpu(cpu); 958 } 959 #endif 960 } 961 962 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 963 { 964 RISCVCPU *cpu = RISCV_CPU(s); 965 CPURISCVState *env = &cpu->env; 966 info->target_info = &cpu->cfg; 967 968 switch (env->xl) { 969 case MXL_RV32: 970 info->print_insn = print_insn_riscv32; 971 break; 972 case MXL_RV64: 973 info->print_insn = print_insn_riscv64; 974 break; 975 case MXL_RV128: 976 info->print_insn = print_insn_riscv128; 977 break; 978 default: 979 g_assert_not_reached(); 980 } 981 } 982 983 #ifndef CONFIG_USER_ONLY 984 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) 985 { 986 bool rv32 = riscv_cpu_is_32bit(cpu); 987 uint8_t satp_mode_map_max, satp_mode_supported_max; 988 989 /* The CPU wants the OS to decide which satp mode to use */ 990 if (cpu->cfg.satp_mode.supported == 0) { 991 return; 992 } 993 994 satp_mode_supported_max = 995 satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 996 997 if (cpu->cfg.satp_mode.map == 0) { 998 if (cpu->cfg.satp_mode.init == 0) { 999 /* If unset by the user, we fallback to the default satp mode. */ 1000 set_satp_mode_default_map(cpu); 1001 } else { 1002 /* 1003 * Find the lowest level that was disabled and then enable the 1004 * first valid level below which can be found in 1005 * valid_vm_1_10_32/64. 1006 */ 1007 for (int i = 1; i < 16; ++i) { 1008 if ((cpu->cfg.satp_mode.init & (1 << i)) && 1009 (cpu->cfg.satp_mode.supported & (1 << i))) { 1010 for (int j = i - 1; j >= 0; --j) { 1011 if (cpu->cfg.satp_mode.supported & (1 << j)) { 1012 cpu->cfg.satp_mode.map |= (1 << j); 1013 break; 1014 } 1015 } 1016 break; 1017 } 1018 } 1019 } 1020 } 1021 1022 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 1023 1024 /* Make sure the user asked for a supported configuration (HW and qemu) */ 1025 if (satp_mode_map_max > satp_mode_supported_max) { 1026 error_setg(errp, "satp_mode %s is higher than hw max capability %s", 1027 satp_mode_str(satp_mode_map_max, rv32), 1028 satp_mode_str(satp_mode_supported_max, rv32)); 1029 return; 1030 } 1031 1032 /* 1033 * Make sure the user did not ask for an invalid configuration as per 1034 * the specification. 1035 */ 1036 if (!rv32) { 1037 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1038 if (!(cpu->cfg.satp_mode.map & (1 << i)) && 1039 (cpu->cfg.satp_mode.init & (1 << i)) && 1040 (cpu->cfg.satp_mode.supported & (1 << i))) { 1041 error_setg(errp, "cannot disable %s satp mode if %s " 1042 "is enabled", satp_mode_str(i, false), 1043 satp_mode_str(satp_mode_map_max, false)); 1044 return; 1045 } 1046 } 1047 } 1048 1049 /* Finally expand the map so that all valid modes are set */ 1050 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1051 if (cpu->cfg.satp_mode.supported & (1 << i)) { 1052 cpu->cfg.satp_mode.map |= (1 << i); 1053 } 1054 } 1055 } 1056 #endif 1057 1058 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1059 { 1060 Error *local_err = NULL; 1061 1062 #ifndef CONFIG_USER_ONLY 1063 riscv_cpu_satp_mode_finalize(cpu, &local_err); 1064 if (local_err != NULL) { 1065 error_propagate(errp, local_err); 1066 return; 1067 } 1068 #endif 1069 1070 /* 1071 * KVM accel does not have a specialized finalize() 1072 * callback because its extensions are validated 1073 * in the get()/set() callbacks of each property. 1074 */ 1075 if (tcg_enabled()) { 1076 riscv_tcg_cpu_finalize_features(cpu, &local_err); 1077 if (local_err != NULL) { 1078 error_propagate(errp, local_err); 1079 return; 1080 } 1081 } 1082 } 1083 1084 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 1085 { 1086 CPUState *cs = CPU(dev); 1087 RISCVCPU *cpu = RISCV_CPU(dev); 1088 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 1089 Error *local_err = NULL; 1090 1091 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_ANY) != NULL) { 1092 warn_report("The 'any' CPU is deprecated and will be " 1093 "removed in the future."); 1094 } 1095 1096 cpu_exec_realizefn(cs, &local_err); 1097 if (local_err != NULL) { 1098 error_propagate(errp, local_err); 1099 return; 1100 } 1101 1102 riscv_cpu_finalize_features(cpu, &local_err); 1103 if (local_err != NULL) { 1104 error_propagate(errp, local_err); 1105 return; 1106 } 1107 1108 riscv_cpu_register_gdb_regs_for_features(cs); 1109 1110 #ifndef CONFIG_USER_ONLY 1111 if (cpu->cfg.debug) { 1112 riscv_trigger_realize(&cpu->env); 1113 } 1114 #endif 1115 1116 qemu_init_vcpu(cs); 1117 cpu_reset(cs); 1118 1119 mcc->parent_realize(dev, errp); 1120 } 1121 1122 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu) 1123 { 1124 if (tcg_enabled()) { 1125 return riscv_cpu_tcg_compatible(cpu); 1126 } 1127 1128 return true; 1129 } 1130 1131 #ifndef CONFIG_USER_ONLY 1132 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, 1133 void *opaque, Error **errp) 1134 { 1135 RISCVSATPMap *satp_map = opaque; 1136 uint8_t satp = satp_mode_from_str(name); 1137 bool value; 1138 1139 value = satp_map->map & (1 << satp); 1140 1141 visit_type_bool(v, name, &value, errp); 1142 } 1143 1144 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, 1145 void *opaque, Error **errp) 1146 { 1147 RISCVSATPMap *satp_map = opaque; 1148 uint8_t satp = satp_mode_from_str(name); 1149 bool value; 1150 1151 if (!visit_type_bool(v, name, &value, errp)) { 1152 return; 1153 } 1154 1155 satp_map->map = deposit32(satp_map->map, satp, 1, value); 1156 satp_map->init |= 1 << satp; 1157 } 1158 1159 void riscv_add_satp_mode_properties(Object *obj) 1160 { 1161 RISCVCPU *cpu = RISCV_CPU(obj); 1162 1163 if (cpu->env.misa_mxl == MXL_RV32) { 1164 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, 1165 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1166 } else { 1167 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, 1168 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1169 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, 1170 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1171 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, 1172 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1173 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, 1174 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1175 } 1176 } 1177 1178 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1179 { 1180 RISCVCPU *cpu = RISCV_CPU(opaque); 1181 CPURISCVState *env = &cpu->env; 1182 1183 if (irq < IRQ_LOCAL_MAX) { 1184 switch (irq) { 1185 case IRQ_U_SOFT: 1186 case IRQ_S_SOFT: 1187 case IRQ_VS_SOFT: 1188 case IRQ_M_SOFT: 1189 case IRQ_U_TIMER: 1190 case IRQ_S_TIMER: 1191 case IRQ_VS_TIMER: 1192 case IRQ_M_TIMER: 1193 case IRQ_U_EXT: 1194 case IRQ_VS_EXT: 1195 case IRQ_M_EXT: 1196 if (kvm_enabled()) { 1197 kvm_riscv_set_irq(cpu, irq, level); 1198 } else { 1199 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); 1200 } 1201 break; 1202 case IRQ_S_EXT: 1203 if (kvm_enabled()) { 1204 kvm_riscv_set_irq(cpu, irq, level); 1205 } else { 1206 env->external_seip = level; 1207 riscv_cpu_update_mip(env, 1 << irq, 1208 BOOL_TO_MASK(level | env->software_seip)); 1209 } 1210 break; 1211 default: 1212 g_assert_not_reached(); 1213 } 1214 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1215 /* Require H-extension for handling guest local interrupts */ 1216 if (!riscv_has_ext(env, RVH)) { 1217 g_assert_not_reached(); 1218 } 1219 1220 /* Compute bit position in HGEIP CSR */ 1221 irq = irq - IRQ_LOCAL_MAX + 1; 1222 if (env->geilen < irq) { 1223 g_assert_not_reached(); 1224 } 1225 1226 /* Update HGEIP CSR */ 1227 env->hgeip &= ~((target_ulong)1 << irq); 1228 if (level) { 1229 env->hgeip |= (target_ulong)1 << irq; 1230 } 1231 1232 /* Update mip.SGEIP bit */ 1233 riscv_cpu_update_mip(env, MIP_SGEIP, 1234 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1235 } else { 1236 g_assert_not_reached(); 1237 } 1238 } 1239 #endif /* CONFIG_USER_ONLY */ 1240 1241 static bool riscv_cpu_is_dynamic(Object *cpu_obj) 1242 { 1243 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 1244 } 1245 1246 static void riscv_cpu_post_init(Object *obj) 1247 { 1248 accel_cpu_instance_init(CPU(obj)); 1249 } 1250 1251 static void riscv_cpu_init(Object *obj) 1252 { 1253 #ifndef CONFIG_USER_ONLY 1254 qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, 1255 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1256 #endif /* CONFIG_USER_ONLY */ 1257 1258 /* 1259 * The timer and performance counters extensions were supported 1260 * in QEMU before they were added as discrete extensions in the 1261 * ISA. To keep compatibility we'll always default them to 'true' 1262 * for all CPUs. Each accelerator will decide what to do when 1263 * users disable them. 1264 */ 1265 RISCV_CPU(obj)->cfg.ext_zicntr = true; 1266 RISCV_CPU(obj)->cfg.ext_zihpm = true; 1267 } 1268 1269 typedef struct misa_ext_info { 1270 const char *name; 1271 const char *description; 1272 } MISAExtInfo; 1273 1274 #define MISA_INFO_IDX(_bit) \ 1275 __builtin_ctz(_bit) 1276 1277 #define MISA_EXT_INFO(_bit, _propname, _descr) \ 1278 [MISA_INFO_IDX(_bit)] = {.name = _propname, .description = _descr} 1279 1280 static const MISAExtInfo misa_ext_info_arr[] = { 1281 MISA_EXT_INFO(RVA, "a", "Atomic instructions"), 1282 MISA_EXT_INFO(RVC, "c", "Compressed instructions"), 1283 MISA_EXT_INFO(RVD, "d", "Double-precision float point"), 1284 MISA_EXT_INFO(RVF, "f", "Single-precision float point"), 1285 MISA_EXT_INFO(RVI, "i", "Base integer instruction set"), 1286 MISA_EXT_INFO(RVE, "e", "Base integer instruction set (embedded)"), 1287 MISA_EXT_INFO(RVM, "m", "Integer multiplication and division"), 1288 MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"), 1289 MISA_EXT_INFO(RVU, "u", "User-level instructions"), 1290 MISA_EXT_INFO(RVH, "h", "Hypervisor"), 1291 MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"), 1292 MISA_EXT_INFO(RVV, "v", "Vector operations"), 1293 MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), 1294 }; 1295 1296 static int riscv_validate_misa_info_idx(uint32_t bit) 1297 { 1298 int idx; 1299 1300 /* 1301 * Our lowest valid input (RVA) is 1 and 1302 * __builtin_ctz() is UB with zero. 1303 */ 1304 g_assert(bit != 0); 1305 idx = MISA_INFO_IDX(bit); 1306 1307 g_assert(idx < ARRAY_SIZE(misa_ext_info_arr)); 1308 return idx; 1309 } 1310 1311 const char *riscv_get_misa_ext_name(uint32_t bit) 1312 { 1313 int idx = riscv_validate_misa_info_idx(bit); 1314 const char *val = misa_ext_info_arr[idx].name; 1315 1316 g_assert(val != NULL); 1317 return val; 1318 } 1319 1320 const char *riscv_get_misa_ext_description(uint32_t bit) 1321 { 1322 int idx = riscv_validate_misa_info_idx(bit); 1323 const char *val = misa_ext_info_arr[idx].description; 1324 1325 g_assert(val != NULL); 1326 return val; 1327 } 1328 1329 #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ 1330 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 1331 .enabled = _defval} 1332 1333 const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { 1334 /* Defaults for standard extensions */ 1335 MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), 1336 MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), 1337 MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), 1338 MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), 1339 MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true), 1340 MULTI_EXT_CFG_BOOL("zacas", ext_zacas, false), 1341 MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true), 1342 MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true), 1343 MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false), 1344 MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false), 1345 MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false), 1346 MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false), 1347 MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false), 1348 MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), 1349 1350 MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), 1351 MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), 1352 MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), 1353 MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), 1354 MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), 1355 MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), 1356 1357 MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true), 1358 MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true), 1359 1360 MULTI_EXT_CFG_BOOL("zba", ext_zba, true), 1361 MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true), 1362 MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true), 1363 MULTI_EXT_CFG_BOOL("zbkb", ext_zbkb, false), 1364 MULTI_EXT_CFG_BOOL("zbkc", ext_zbkc, false), 1365 MULTI_EXT_CFG_BOOL("zbkx", ext_zbkx, false), 1366 MULTI_EXT_CFG_BOOL("zbs", ext_zbs, true), 1367 MULTI_EXT_CFG_BOOL("zk", ext_zk, false), 1368 MULTI_EXT_CFG_BOOL("zkn", ext_zkn, false), 1369 MULTI_EXT_CFG_BOOL("zknd", ext_zknd, false), 1370 MULTI_EXT_CFG_BOOL("zkne", ext_zkne, false), 1371 MULTI_EXT_CFG_BOOL("zknh", ext_zknh, false), 1372 MULTI_EXT_CFG_BOOL("zkr", ext_zkr, false), 1373 MULTI_EXT_CFG_BOOL("zks", ext_zks, false), 1374 MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false), 1375 MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false), 1376 MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false), 1377 1378 MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false), 1379 MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false), 1380 MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false), 1381 MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false), 1382 1383 MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true), 1384 MULTI_EXT_CFG_BOOL("zicbop", ext_zicbop, true), 1385 MULTI_EXT_CFG_BOOL("zicboz", ext_zicboz, true), 1386 1387 MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false), 1388 1389 MULTI_EXT_CFG_BOOL("zca", ext_zca, false), 1390 MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false), 1391 MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false), 1392 MULTI_EXT_CFG_BOOL("zce", ext_zce, false), 1393 MULTI_EXT_CFG_BOOL("zcf", ext_zcf, false), 1394 MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false), 1395 MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false), 1396 MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false), 1397 1398 /* Vector cryptography extensions */ 1399 MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false), 1400 MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false), 1401 MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false), 1402 MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false), 1403 MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false), 1404 MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false), 1405 MULTI_EXT_CFG_BOOL("zvknhb", ext_zvknhb, false), 1406 MULTI_EXT_CFG_BOOL("zvksed", ext_zvksed, false), 1407 MULTI_EXT_CFG_BOOL("zvksh", ext_zvksh, false), 1408 MULTI_EXT_CFG_BOOL("zvkt", ext_zvkt, false), 1409 MULTI_EXT_CFG_BOOL("zvkn", ext_zvkn, false), 1410 MULTI_EXT_CFG_BOOL("zvknc", ext_zvknc, false), 1411 MULTI_EXT_CFG_BOOL("zvkng", ext_zvkng, false), 1412 MULTI_EXT_CFG_BOOL("zvks", ext_zvks, false), 1413 MULTI_EXT_CFG_BOOL("zvksc", ext_zvksc, false), 1414 MULTI_EXT_CFG_BOOL("zvksg", ext_zvksg, false), 1415 1416 DEFINE_PROP_END_OF_LIST(), 1417 }; 1418 1419 const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { 1420 MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false), 1421 MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false), 1422 MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false), 1423 MULTI_EXT_CFG_BOOL("xtheadcmo", ext_xtheadcmo, false), 1424 MULTI_EXT_CFG_BOOL("xtheadcondmov", ext_xtheadcondmov, false), 1425 MULTI_EXT_CFG_BOOL("xtheadfmemidx", ext_xtheadfmemidx, false), 1426 MULTI_EXT_CFG_BOOL("xtheadfmv", ext_xtheadfmv, false), 1427 MULTI_EXT_CFG_BOOL("xtheadmac", ext_xtheadmac, false), 1428 MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false), 1429 MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false), 1430 MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false), 1431 MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), 1432 1433 DEFINE_PROP_END_OF_LIST(), 1434 }; 1435 1436 /* These are experimental so mark with 'x-' */ 1437 const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { 1438 MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false), 1439 MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false), 1440 1441 MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false), 1442 MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false), 1443 1444 MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false), 1445 MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false), 1446 MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false), 1447 1448 DEFINE_PROP_END_OF_LIST(), 1449 }; 1450 1451 const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = { 1452 MULTI_EXT_CFG_BOOL("svade", svade, true), 1453 MULTI_EXT_CFG_BOOL("zic64b", zic64b, true), 1454 1455 DEFINE_PROP_END_OF_LIST(), 1456 }; 1457 1458 /* Deprecated entries marked for future removal */ 1459 const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = { 1460 MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true), 1461 MULTI_EXT_CFG_BOOL("Zicsr", ext_zicsr, true), 1462 MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true), 1463 MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true), 1464 MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true), 1465 MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true), 1466 MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false), 1467 MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false), 1468 MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false), 1469 MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false), 1470 MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false), 1471 1472 DEFINE_PROP_END_OF_LIST(), 1473 }; 1474 1475 static void prop_pmu_num_set(Object *obj, Visitor *v, const char *name, 1476 void *opaque, Error **errp) 1477 { 1478 RISCVCPU *cpu = RISCV_CPU(obj); 1479 uint8_t pmu_num; 1480 1481 visit_type_uint8(v, name, &pmu_num, errp); 1482 1483 if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { 1484 error_setg(errp, "Number of counters exceeds maximum available"); 1485 return; 1486 } 1487 1488 if (pmu_num == 0) { 1489 cpu->cfg.pmu_mask = 0; 1490 } else { 1491 cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, pmu_num); 1492 } 1493 1494 warn_report("\"pmu-num\" property is deprecated; use \"pmu-mask\""); 1495 } 1496 1497 static void prop_pmu_num_get(Object *obj, Visitor *v, const char *name, 1498 void *opaque, Error **errp) 1499 { 1500 RISCVCPU *cpu = RISCV_CPU(obj); 1501 uint8_t pmu_num = ctpop32(cpu->cfg.pmu_mask); 1502 1503 visit_type_uint8(v, name, &pmu_num, errp); 1504 } 1505 1506 const PropertyInfo prop_pmu_num = { 1507 .name = "pmu-num", 1508 .get = prop_pmu_num_get, 1509 .set = prop_pmu_num_set, 1510 }; 1511 1512 Property riscv_cpu_options[] = { 1513 DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask, MAKE_64BIT_MASK(3, 16)), 1514 {.name = "pmu-num", .info = &prop_pmu_num}, /* Deprecated */ 1515 1516 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1517 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1518 1519 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1520 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1521 1522 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1523 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1524 1525 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), 1526 DEFINE_PROP_UINT16("cbop_blocksize", RISCVCPU, cfg.cbop_blocksize, 64), 1527 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), 1528 1529 DEFINE_PROP_END_OF_LIST(), 1530 }; 1531 1532 /* 1533 * RVA22U64 defines some 'named features' or 'synthetic extensions' 1534 * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa 1535 * and Zicclsm. We do not implement caching in QEMU so we'll consider 1536 * all these named features as always enabled. 1537 * 1538 * There's no riscv,isa update for them (nor for zic64b, despite it 1539 * having a cfg offset) at this moment. 1540 */ 1541 static RISCVCPUProfile RVA22U64 = { 1542 .parent = NULL, 1543 .name = "rva22u64", 1544 .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU, 1545 .priv_spec = RISCV_PROFILE_ATTR_UNUSED, 1546 .satp_mode = RISCV_PROFILE_ATTR_UNUSED, 1547 .ext_offsets = { 1548 CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), 1549 CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), 1550 CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin), 1551 CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr), 1552 CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom), 1553 CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz), 1554 1555 /* mandatory named features for this profile */ 1556 CPU_CFG_OFFSET(zic64b), 1557 1558 RISCV_PROFILE_EXT_LIST_END 1559 } 1560 }; 1561 1562 /* 1563 * As with RVA22U64, RVA22S64 also defines 'named features'. 1564 * 1565 * Cache related features that we consider enabled since we don't 1566 * implement cache: Ssccptr 1567 * 1568 * Other named features that we already implement: Sstvecd, Sstvala, 1569 * Sscounterenw 1570 * 1571 * Named features that we need to enable: svade 1572 * 1573 * The remaining features/extensions comes from RVA22U64. 1574 */ 1575 static RISCVCPUProfile RVA22S64 = { 1576 .parent = &RVA22U64, 1577 .name = "rva22s64", 1578 .misa_ext = RVS, 1579 .priv_spec = PRIV_VERSION_1_12_0, 1580 .satp_mode = VM_1_10_SV39, 1581 .ext_offsets = { 1582 /* rva22s64 exts */ 1583 CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt), 1584 CPU_CFG_OFFSET(ext_svinval), 1585 1586 /* rva22s64 named features */ 1587 CPU_CFG_OFFSET(svade), 1588 1589 RISCV_PROFILE_EXT_LIST_END 1590 } 1591 }; 1592 1593 RISCVCPUProfile *riscv_profiles[] = { 1594 &RVA22U64, 1595 &RVA22S64, 1596 NULL, 1597 }; 1598 1599 static Property riscv_cpu_properties[] = { 1600 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1601 1602 #ifndef CONFIG_USER_ONLY 1603 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1604 #endif 1605 1606 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1607 1608 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1609 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1610 1611 /* 1612 * write_misa() is marked as experimental for now so mark 1613 * it with -x and default to 'false'. 1614 */ 1615 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), 1616 DEFINE_PROP_END_OF_LIST(), 1617 }; 1618 1619 #if defined(TARGET_RISCV64) 1620 static void rva22u64_profile_cpu_init(Object *obj) 1621 { 1622 rv64i_bare_cpu_init(obj); 1623 1624 RVA22U64.enabled = true; 1625 } 1626 1627 static void rva22s64_profile_cpu_init(Object *obj) 1628 { 1629 rv64i_bare_cpu_init(obj); 1630 1631 RVA22S64.enabled = true; 1632 } 1633 #endif 1634 1635 static const gchar *riscv_gdb_arch_name(CPUState *cs) 1636 { 1637 RISCVCPU *cpu = RISCV_CPU(cs); 1638 CPURISCVState *env = &cpu->env; 1639 1640 switch (riscv_cpu_mxl(env)) { 1641 case MXL_RV32: 1642 return "riscv:rv32"; 1643 case MXL_RV64: 1644 case MXL_RV128: 1645 return "riscv:rv64"; 1646 default: 1647 g_assert_not_reached(); 1648 } 1649 } 1650 1651 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1652 { 1653 RISCVCPU *cpu = RISCV_CPU(cs); 1654 1655 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1656 return cpu->dyn_csr_xml; 1657 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1658 return cpu->dyn_vreg_xml; 1659 } 1660 1661 return NULL; 1662 } 1663 1664 #ifndef CONFIG_USER_ONLY 1665 static int64_t riscv_get_arch_id(CPUState *cs) 1666 { 1667 RISCVCPU *cpu = RISCV_CPU(cs); 1668 1669 return cpu->env.mhartid; 1670 } 1671 1672 #include "hw/core/sysemu-cpu-ops.h" 1673 1674 static const struct SysemuCPUOps riscv_sysemu_ops = { 1675 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1676 .write_elf64_note = riscv_cpu_write_elf64_note, 1677 .write_elf32_note = riscv_cpu_write_elf32_note, 1678 .legacy_vmsd = &vmstate_riscv_cpu, 1679 }; 1680 #endif 1681 1682 static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name, 1683 void *opaque, Error **errp) 1684 { 1685 bool dynamic_cpu = riscv_cpu_is_dynamic(obj); 1686 RISCVCPU *cpu = RISCV_CPU(obj); 1687 uint32_t prev_val = cpu->cfg.mvendorid; 1688 uint32_t value; 1689 1690 if (!visit_type_uint32(v, name, &value, errp)) { 1691 return; 1692 } 1693 1694 if (!dynamic_cpu && prev_val != value) { 1695 error_setg(errp, "Unable to change %s mvendorid (0x%x)", 1696 object_get_typename(obj), prev_val); 1697 return; 1698 } 1699 1700 cpu->cfg.mvendorid = value; 1701 } 1702 1703 static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name, 1704 void *opaque, Error **errp) 1705 { 1706 uint32_t value = RISCV_CPU(obj)->cfg.mvendorid; 1707 1708 visit_type_uint32(v, name, &value, errp); 1709 } 1710 1711 static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, 1712 void *opaque, Error **errp) 1713 { 1714 bool dynamic_cpu = riscv_cpu_is_dynamic(obj); 1715 RISCVCPU *cpu = RISCV_CPU(obj); 1716 uint64_t prev_val = cpu->cfg.mimpid; 1717 uint64_t value; 1718 1719 if (!visit_type_uint64(v, name, &value, errp)) { 1720 return; 1721 } 1722 1723 if (!dynamic_cpu && prev_val != value) { 1724 error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")", 1725 object_get_typename(obj), prev_val); 1726 return; 1727 } 1728 1729 cpu->cfg.mimpid = value; 1730 } 1731 1732 static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name, 1733 void *opaque, Error **errp) 1734 { 1735 uint64_t value = RISCV_CPU(obj)->cfg.mimpid; 1736 1737 visit_type_uint64(v, name, &value, errp); 1738 } 1739 1740 static void cpu_set_marchid(Object *obj, Visitor *v, const char *name, 1741 void *opaque, Error **errp) 1742 { 1743 bool dynamic_cpu = riscv_cpu_is_dynamic(obj); 1744 RISCVCPU *cpu = RISCV_CPU(obj); 1745 uint64_t prev_val = cpu->cfg.marchid; 1746 uint64_t value, invalid_val; 1747 uint32_t mxlen = 0; 1748 1749 if (!visit_type_uint64(v, name, &value, errp)) { 1750 return; 1751 } 1752 1753 if (!dynamic_cpu && prev_val != value) { 1754 error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", 1755 object_get_typename(obj), prev_val); 1756 return; 1757 } 1758 1759 switch (riscv_cpu_mxl(&cpu->env)) { 1760 case MXL_RV32: 1761 mxlen = 32; 1762 break; 1763 case MXL_RV64: 1764 case MXL_RV128: 1765 mxlen = 64; 1766 break; 1767 default: 1768 g_assert_not_reached(); 1769 } 1770 1771 invalid_val = 1LL << (mxlen - 1); 1772 1773 if (value == invalid_val) { 1774 error_setg(errp, "Unable to set marchid with MSB (%u) bit set " 1775 "and the remaining bits zero", mxlen); 1776 return; 1777 } 1778 1779 cpu->cfg.marchid = value; 1780 } 1781 1782 static void cpu_get_marchid(Object *obj, Visitor *v, const char *name, 1783 void *opaque, Error **errp) 1784 { 1785 uint64_t value = RISCV_CPU(obj)->cfg.marchid; 1786 1787 visit_type_uint64(v, name, &value, errp); 1788 } 1789 1790 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1791 { 1792 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1793 CPUClass *cc = CPU_CLASS(c); 1794 DeviceClass *dc = DEVICE_CLASS(c); 1795 ResettableClass *rc = RESETTABLE_CLASS(c); 1796 1797 device_class_set_parent_realize(dc, riscv_cpu_realize, 1798 &mcc->parent_realize); 1799 1800 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1801 &mcc->parent_phases); 1802 1803 cc->class_by_name = riscv_cpu_class_by_name; 1804 cc->has_work = riscv_cpu_has_work; 1805 cc->dump_state = riscv_cpu_dump_state; 1806 cc->set_pc = riscv_cpu_set_pc; 1807 cc->get_pc = riscv_cpu_get_pc; 1808 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1809 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1810 cc->gdb_num_core_regs = 33; 1811 cc->gdb_stop_before_watchpoint = true; 1812 cc->disas_set_info = riscv_cpu_disas_set_info; 1813 #ifndef CONFIG_USER_ONLY 1814 cc->sysemu_ops = &riscv_sysemu_ops; 1815 cc->get_arch_id = riscv_get_arch_id; 1816 #endif 1817 cc->gdb_arch_name = riscv_gdb_arch_name; 1818 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1819 1820 object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, 1821 cpu_set_mvendorid, NULL, NULL); 1822 1823 object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, 1824 cpu_set_mimpid, NULL, NULL); 1825 1826 object_class_property_add(c, "marchid", "uint64", cpu_get_marchid, 1827 cpu_set_marchid, NULL, NULL); 1828 1829 device_class_set_props(dc, riscv_cpu_properties); 1830 } 1831 1832 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, 1833 int max_str_len) 1834 { 1835 const RISCVIsaExtData *edata; 1836 char *old = *isa_str; 1837 char *new = *isa_str; 1838 1839 for (edata = isa_edata_arr; edata && edata->name; edata++) { 1840 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) { 1841 new = g_strconcat(old, "_", edata->name, NULL); 1842 g_free(old); 1843 old = new; 1844 } 1845 } 1846 1847 *isa_str = new; 1848 } 1849 1850 char *riscv_isa_string(RISCVCPU *cpu) 1851 { 1852 int i; 1853 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1854 char *isa_str = g_new(char, maxlen); 1855 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1856 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1857 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1858 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1859 } 1860 } 1861 *p = '\0'; 1862 if (!cpu->cfg.short_isa_string) { 1863 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1864 } 1865 return isa_str; 1866 } 1867 1868 #define DEFINE_CPU(type_name, initfn) \ 1869 { \ 1870 .name = type_name, \ 1871 .parent = TYPE_RISCV_CPU, \ 1872 .instance_init = initfn \ 1873 } 1874 1875 #define DEFINE_DYNAMIC_CPU(type_name, initfn) \ 1876 { \ 1877 .name = type_name, \ 1878 .parent = TYPE_RISCV_DYNAMIC_CPU, \ 1879 .instance_init = initfn \ 1880 } 1881 1882 #define DEFINE_VENDOR_CPU(type_name, initfn) \ 1883 { \ 1884 .name = type_name, \ 1885 .parent = TYPE_RISCV_VENDOR_CPU, \ 1886 .instance_init = initfn \ 1887 } 1888 1889 #define DEFINE_BARE_CPU(type_name, initfn) \ 1890 { \ 1891 .name = type_name, \ 1892 .parent = TYPE_RISCV_BARE_CPU, \ 1893 .instance_init = initfn \ 1894 } 1895 1896 #define DEFINE_PROFILE_CPU(type_name, initfn) \ 1897 { \ 1898 .name = type_name, \ 1899 .parent = TYPE_RISCV_BARE_CPU, \ 1900 .instance_init = initfn \ 1901 } 1902 1903 static const TypeInfo riscv_cpu_type_infos[] = { 1904 { 1905 .name = TYPE_RISCV_CPU, 1906 .parent = TYPE_CPU, 1907 .instance_size = sizeof(RISCVCPU), 1908 .instance_align = __alignof(RISCVCPU), 1909 .instance_init = riscv_cpu_init, 1910 .instance_post_init = riscv_cpu_post_init, 1911 .abstract = true, 1912 .class_size = sizeof(RISCVCPUClass), 1913 .class_init = riscv_cpu_class_init, 1914 }, 1915 { 1916 .name = TYPE_RISCV_DYNAMIC_CPU, 1917 .parent = TYPE_RISCV_CPU, 1918 .abstract = true, 1919 }, 1920 { 1921 .name = TYPE_RISCV_VENDOR_CPU, 1922 .parent = TYPE_RISCV_CPU, 1923 .abstract = true, 1924 }, 1925 { 1926 .name = TYPE_RISCV_BARE_CPU, 1927 .parent = TYPE_RISCV_CPU, 1928 .abstract = true, 1929 }, 1930 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1931 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), 1932 #if defined(TARGET_RISCV32) 1933 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1934 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1935 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1936 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1937 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1938 #elif defined(TARGET_RISCV64) 1939 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1940 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1941 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1942 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1943 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1944 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), 1945 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1946 DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), 1947 DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init), 1948 DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init), 1949 #endif 1950 }; 1951 1952 DEFINE_TYPES(riscv_cpu_type_infos) 1953