1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qemu/error-report.h" 32 #include "hw/qdev-properties.h" 33 #include "migration/vmstate.h" 34 #include "fpu/softfloat-helpers.h" 35 #include "sysemu/kvm.h" 36 #include "kvm_riscv.h" 37 38 /* RISC-V CPU definitions */ 39 40 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 41 (QEMU_VERSION_MINOR << 8) | \ 42 (QEMU_VERSION_MICRO)) 43 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 44 45 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 46 47 struct isa_ext_data { 48 const char *name; 49 bool multi_letter; 50 int min_version; 51 int ext_enable_offset; 52 }; 53 54 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ 55 {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 56 57 /** 58 * Here are the ordering rules of extension naming defined by RISC-V 59 * specification : 60 * 1. All extensions should be separated from other multi-letter extensions 61 * by an underscore. 62 * 2. The first letter following the 'Z' conventionally indicates the most 63 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 64 * If multiple 'Z' extensions are named, they should be ordered first 65 * by category, then alphabetically within a category. 66 * 3. Standard supervisor-level extensions (starts with 'S') should be 67 * listed after standard unprivileged extensions. If multiple 68 * supervisor-level extensions are listed, they should be ordered 69 * alphabetically. 70 * 4. Non-standard extensions (starts with 'X') must be listed after all 71 * standard extensions. They must be separated from other multi-letter 72 * extensions by an underscore. 73 */ 74 static const struct isa_ext_data isa_edata_arr[] = { 75 ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), 76 ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), 77 ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), 78 ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), 79 ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), 80 ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), 81 ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), 82 ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), 83 ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), 84 ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), 85 ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), 86 ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), 87 ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), 88 ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), 89 ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), 90 ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), 91 ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), 92 ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), 93 ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), 94 ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), 95 ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), 96 ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), 97 ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), 98 ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), 99 ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), 100 ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), 101 ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), 102 ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), 103 ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), 104 ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), 105 ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), 106 ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), 107 ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), 108 ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), 109 ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), 110 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), 111 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), 112 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), 113 ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), 114 ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), 115 ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), 116 ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), 117 ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 118 ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 119 ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv), 120 ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), 121 ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 122 ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), 123 ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), 124 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 125 }; 126 127 static bool isa_ext_is_enabled(RISCVCPU *cpu, 128 const struct isa_ext_data *edata) 129 { 130 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 131 132 return *ext_enabled; 133 } 134 135 static void isa_ext_update_enabled(RISCVCPU *cpu, 136 const struct isa_ext_data *edata, bool en) 137 { 138 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 139 140 *ext_enabled = en; 141 } 142 143 const char * const riscv_int_regnames[] = { 144 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 145 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 146 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 147 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 148 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 149 }; 150 151 const char * const riscv_int_regnamesh[] = { 152 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 153 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 154 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 155 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 156 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 157 "x30h/t5h", "x31h/t6h" 158 }; 159 160 const char * const riscv_fpr_regnames[] = { 161 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 162 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 163 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 164 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 165 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 166 "f30/ft10", "f31/ft11" 167 }; 168 169 static const char * const riscv_excp_names[] = { 170 "misaligned_fetch", 171 "fault_fetch", 172 "illegal_instruction", 173 "breakpoint", 174 "misaligned_load", 175 "fault_load", 176 "misaligned_store", 177 "fault_store", 178 "user_ecall", 179 "supervisor_ecall", 180 "hypervisor_ecall", 181 "machine_ecall", 182 "exec_page_fault", 183 "load_page_fault", 184 "reserved", 185 "store_page_fault", 186 "reserved", 187 "reserved", 188 "reserved", 189 "reserved", 190 "guest_exec_page_fault", 191 "guest_load_page_fault", 192 "reserved", 193 "guest_store_page_fault", 194 }; 195 196 static const char * const riscv_intr_names[] = { 197 "u_software", 198 "s_software", 199 "vs_software", 200 "m_software", 201 "u_timer", 202 "s_timer", 203 "vs_timer", 204 "m_timer", 205 "u_external", 206 "s_external", 207 "vs_external", 208 "m_external", 209 "reserved", 210 "reserved", 211 "reserved", 212 "reserved" 213 }; 214 215 static void register_cpu_props(DeviceState *dev); 216 217 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 218 { 219 if (async) { 220 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 221 riscv_intr_names[cause] : "(unknown)"; 222 } else { 223 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 224 riscv_excp_names[cause] : "(unknown)"; 225 } 226 } 227 228 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 229 { 230 env->misa_mxl_max = env->misa_mxl = mxl; 231 env->misa_ext_mask = env->misa_ext = ext; 232 } 233 234 static void set_priv_version(CPURISCVState *env, int priv_ver) 235 { 236 env->priv_ver = priv_ver; 237 } 238 239 static void set_vext_version(CPURISCVState *env, int vext_ver) 240 { 241 env->vext_ver = vext_ver; 242 } 243 244 static void riscv_any_cpu_init(Object *obj) 245 { 246 CPURISCVState *env = &RISCV_CPU(obj)->env; 247 #if defined(TARGET_RISCV32) 248 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 249 #elif defined(TARGET_RISCV64) 250 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 251 #endif 252 set_priv_version(env, PRIV_VERSION_1_12_0); 253 register_cpu_props(DEVICE(obj)); 254 } 255 256 #if defined(TARGET_RISCV64) 257 static void rv64_base_cpu_init(Object *obj) 258 { 259 CPURISCVState *env = &RISCV_CPU(obj)->env; 260 /* We set this in the realise function */ 261 set_misa(env, MXL_RV64, 0); 262 register_cpu_props(DEVICE(obj)); 263 /* Set latest version of privileged specification */ 264 set_priv_version(env, PRIV_VERSION_1_12_0); 265 } 266 267 static void rv64_sifive_u_cpu_init(Object *obj) 268 { 269 CPURISCVState *env = &RISCV_CPU(obj)->env; 270 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 271 register_cpu_props(DEVICE(obj)); 272 set_priv_version(env, PRIV_VERSION_1_10_0); 273 } 274 275 static void rv64_sifive_e_cpu_init(Object *obj) 276 { 277 CPURISCVState *env = &RISCV_CPU(obj)->env; 278 RISCVCPU *cpu = RISCV_CPU(obj); 279 280 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 281 register_cpu_props(DEVICE(obj)); 282 set_priv_version(env, PRIV_VERSION_1_10_0); 283 cpu->cfg.mmu = false; 284 } 285 286 static void rv64_thead_c906_cpu_init(Object *obj) 287 { 288 CPURISCVState *env = &RISCV_CPU(obj)->env; 289 RISCVCPU *cpu = RISCV_CPU(obj); 290 291 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 292 set_priv_version(env, PRIV_VERSION_1_11_0); 293 294 cpu->cfg.ext_g = true; 295 cpu->cfg.ext_c = true; 296 cpu->cfg.ext_u = true; 297 cpu->cfg.ext_s = true; 298 cpu->cfg.ext_icsr = true; 299 cpu->cfg.ext_zfh = true; 300 cpu->cfg.mmu = true; 301 cpu->cfg.ext_xtheadba = true; 302 cpu->cfg.ext_xtheadbb = true; 303 cpu->cfg.ext_xtheadbs = true; 304 cpu->cfg.ext_xtheadcmo = true; 305 cpu->cfg.ext_xtheadcondmov = true; 306 cpu->cfg.ext_xtheadfmemidx = true; 307 cpu->cfg.ext_xtheadmac = true; 308 cpu->cfg.ext_xtheadmemidx = true; 309 cpu->cfg.ext_xtheadmempair = true; 310 cpu->cfg.ext_xtheadsync = true; 311 312 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 313 } 314 315 static void rv128_base_cpu_init(Object *obj) 316 { 317 if (qemu_tcg_mttcg_enabled()) { 318 /* Missing 128-bit aligned atomics */ 319 error_report("128-bit RISC-V currently does not work with Multi " 320 "Threaded TCG. Please use: -accel tcg,thread=single"); 321 exit(EXIT_FAILURE); 322 } 323 CPURISCVState *env = &RISCV_CPU(obj)->env; 324 /* We set this in the realise function */ 325 set_misa(env, MXL_RV128, 0); 326 register_cpu_props(DEVICE(obj)); 327 /* Set latest version of privileged specification */ 328 set_priv_version(env, PRIV_VERSION_1_12_0); 329 } 330 #else 331 static void rv32_base_cpu_init(Object *obj) 332 { 333 CPURISCVState *env = &RISCV_CPU(obj)->env; 334 /* We set this in the realise function */ 335 set_misa(env, MXL_RV32, 0); 336 register_cpu_props(DEVICE(obj)); 337 /* Set latest version of privileged specification */ 338 set_priv_version(env, PRIV_VERSION_1_12_0); 339 } 340 341 static void rv32_sifive_u_cpu_init(Object *obj) 342 { 343 CPURISCVState *env = &RISCV_CPU(obj)->env; 344 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 345 register_cpu_props(DEVICE(obj)); 346 set_priv_version(env, PRIV_VERSION_1_10_0); 347 } 348 349 static void rv32_sifive_e_cpu_init(Object *obj) 350 { 351 CPURISCVState *env = &RISCV_CPU(obj)->env; 352 RISCVCPU *cpu = RISCV_CPU(obj); 353 354 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 355 register_cpu_props(DEVICE(obj)); 356 set_priv_version(env, PRIV_VERSION_1_10_0); 357 cpu->cfg.mmu = false; 358 } 359 360 static void rv32_ibex_cpu_init(Object *obj) 361 { 362 CPURISCVState *env = &RISCV_CPU(obj)->env; 363 RISCVCPU *cpu = RISCV_CPU(obj); 364 365 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 366 register_cpu_props(DEVICE(obj)); 367 set_priv_version(env, PRIV_VERSION_1_11_0); 368 cpu->cfg.mmu = false; 369 cpu->cfg.epmp = true; 370 } 371 372 static void rv32_imafcu_nommu_cpu_init(Object *obj) 373 { 374 CPURISCVState *env = &RISCV_CPU(obj)->env; 375 RISCVCPU *cpu = RISCV_CPU(obj); 376 377 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 378 register_cpu_props(DEVICE(obj)); 379 set_priv_version(env, PRIV_VERSION_1_10_0); 380 cpu->cfg.mmu = false; 381 } 382 #endif 383 384 #if defined(CONFIG_KVM) 385 static void riscv_host_cpu_init(Object *obj) 386 { 387 CPURISCVState *env = &RISCV_CPU(obj)->env; 388 #if defined(TARGET_RISCV32) 389 set_misa(env, MXL_RV32, 0); 390 #elif defined(TARGET_RISCV64) 391 set_misa(env, MXL_RV64, 0); 392 #endif 393 register_cpu_props(DEVICE(obj)); 394 } 395 #endif 396 397 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 398 { 399 ObjectClass *oc; 400 char *typename; 401 char **cpuname; 402 403 cpuname = g_strsplit(cpu_model, ",", 1); 404 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 405 oc = object_class_by_name(typename); 406 g_strfreev(cpuname); 407 g_free(typename); 408 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 409 object_class_is_abstract(oc)) { 410 return NULL; 411 } 412 return oc; 413 } 414 415 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 416 { 417 RISCVCPU *cpu = RISCV_CPU(cs); 418 CPURISCVState *env = &cpu->env; 419 int i; 420 421 #if !defined(CONFIG_USER_ONLY) 422 if (riscv_has_ext(env, RVH)) { 423 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 424 } 425 #endif 426 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 427 #ifndef CONFIG_USER_ONLY 428 { 429 static const int dump_csrs[] = { 430 CSR_MHARTID, 431 CSR_MSTATUS, 432 CSR_MSTATUSH, 433 /* 434 * CSR_SSTATUS is intentionally omitted here as its value 435 * can be figured out by looking at CSR_MSTATUS 436 */ 437 CSR_HSTATUS, 438 CSR_VSSTATUS, 439 CSR_MIP, 440 CSR_MIE, 441 CSR_MIDELEG, 442 CSR_HIDELEG, 443 CSR_MEDELEG, 444 CSR_HEDELEG, 445 CSR_MTVEC, 446 CSR_STVEC, 447 CSR_VSTVEC, 448 CSR_MEPC, 449 CSR_SEPC, 450 CSR_VSEPC, 451 CSR_MCAUSE, 452 CSR_SCAUSE, 453 CSR_VSCAUSE, 454 CSR_MTVAL, 455 CSR_STVAL, 456 CSR_HTVAL, 457 CSR_MTVAL2, 458 CSR_MSCRATCH, 459 CSR_SSCRATCH, 460 CSR_SATP, 461 CSR_MMTE, 462 CSR_UPMBASE, 463 CSR_UPMMASK, 464 CSR_SPMBASE, 465 CSR_SPMMASK, 466 CSR_MPMBASE, 467 CSR_MPMMASK, 468 }; 469 470 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 471 int csrno = dump_csrs[i]; 472 target_ulong val = 0; 473 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 474 475 /* 476 * Rely on the smode, hmode, etc, predicates within csr.c 477 * to do the filtering of the registers that are present. 478 */ 479 if (res == RISCV_EXCP_NONE) { 480 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 481 csr_ops[csrno].name, val); 482 } 483 } 484 } 485 #endif 486 487 for (i = 0; i < 32; i++) { 488 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 489 riscv_int_regnames[i], env->gpr[i]); 490 if ((i & 3) == 3) { 491 qemu_fprintf(f, "\n"); 492 } 493 } 494 if (flags & CPU_DUMP_FPU) { 495 for (i = 0; i < 32; i++) { 496 qemu_fprintf(f, " %-8s %016" PRIx64, 497 riscv_fpr_regnames[i], env->fpr[i]); 498 if ((i & 3) == 3) { 499 qemu_fprintf(f, "\n"); 500 } 501 } 502 } 503 } 504 505 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 506 { 507 RISCVCPU *cpu = RISCV_CPU(cs); 508 CPURISCVState *env = &cpu->env; 509 510 if (env->xl == MXL_RV32) { 511 env->pc = (int32_t)value; 512 } else { 513 env->pc = value; 514 } 515 } 516 517 static vaddr riscv_cpu_get_pc(CPUState *cs) 518 { 519 RISCVCPU *cpu = RISCV_CPU(cs); 520 CPURISCVState *env = &cpu->env; 521 522 /* Match cpu_get_tb_cpu_state. */ 523 if (env->xl == MXL_RV32) { 524 return env->pc & UINT32_MAX; 525 } 526 return env->pc; 527 } 528 529 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 530 const TranslationBlock *tb) 531 { 532 RISCVCPU *cpu = RISCV_CPU(cs); 533 CPURISCVState *env = &cpu->env; 534 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 535 536 if (xl == MXL_RV32) { 537 env->pc = (int32_t)tb_pc(tb); 538 } else { 539 env->pc = tb_pc(tb); 540 } 541 } 542 543 static bool riscv_cpu_has_work(CPUState *cs) 544 { 545 #ifndef CONFIG_USER_ONLY 546 RISCVCPU *cpu = RISCV_CPU(cs); 547 CPURISCVState *env = &cpu->env; 548 /* 549 * Definition of the WFI instruction requires it to ignore the privilege 550 * mode and delegation registers, but respect individual enables 551 */ 552 return riscv_cpu_all_pending(env) != 0; 553 #else 554 return true; 555 #endif 556 } 557 558 static void riscv_restore_state_to_opc(CPUState *cs, 559 const TranslationBlock *tb, 560 const uint64_t *data) 561 { 562 RISCVCPU *cpu = RISCV_CPU(cs); 563 CPURISCVState *env = &cpu->env; 564 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 565 566 if (xl == MXL_RV32) { 567 env->pc = (int32_t)data[0]; 568 } else { 569 env->pc = data[0]; 570 } 571 env->bins = data[1]; 572 } 573 574 static void riscv_cpu_reset_hold(Object *obj) 575 { 576 #ifndef CONFIG_USER_ONLY 577 uint8_t iprio; 578 int i, irq, rdzero; 579 #endif 580 CPUState *cs = CPU(obj); 581 RISCVCPU *cpu = RISCV_CPU(cs); 582 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 583 CPURISCVState *env = &cpu->env; 584 585 if (mcc->parent_phases.hold) { 586 mcc->parent_phases.hold(obj); 587 } 588 #ifndef CONFIG_USER_ONLY 589 env->misa_mxl = env->misa_mxl_max; 590 env->priv = PRV_M; 591 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 592 if (env->misa_mxl > MXL_RV32) { 593 /* 594 * The reset status of SXL/UXL is undefined, but mstatus is WARL 595 * and we must ensure that the value after init is valid for read. 596 */ 597 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 598 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 599 if (riscv_has_ext(env, RVH)) { 600 env->vsstatus = set_field(env->vsstatus, 601 MSTATUS64_SXL, env->misa_mxl); 602 env->vsstatus = set_field(env->vsstatus, 603 MSTATUS64_UXL, env->misa_mxl); 604 env->mstatus_hs = set_field(env->mstatus_hs, 605 MSTATUS64_SXL, env->misa_mxl); 606 env->mstatus_hs = set_field(env->mstatus_hs, 607 MSTATUS64_UXL, env->misa_mxl); 608 } 609 } 610 env->mcause = 0; 611 env->miclaim = MIP_SGEIP; 612 env->pc = env->resetvec; 613 env->bins = 0; 614 env->two_stage_lookup = false; 615 616 /* Initialized default priorities of local interrupts. */ 617 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 618 iprio = riscv_cpu_default_priority(i); 619 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 620 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 621 env->hviprio[i] = 0; 622 } 623 i = 0; 624 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 625 if (!rdzero) { 626 env->hviprio[irq] = env->miprio[irq]; 627 } 628 i++; 629 } 630 /* mmte is supposed to have pm.current hardwired to 1 */ 631 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 632 #endif 633 env->xl = riscv_cpu_mxl(env); 634 riscv_cpu_update_mask(env); 635 cs->exception_index = RISCV_EXCP_NONE; 636 env->load_res = -1; 637 set_default_nan_mode(1, &env->fp_status); 638 639 #ifndef CONFIG_USER_ONLY 640 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 641 riscv_trigger_init(env); 642 } 643 644 if (kvm_enabled()) { 645 kvm_riscv_reset_vcpu(cpu); 646 } 647 #endif 648 } 649 650 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 651 { 652 RISCVCPU *cpu = RISCV_CPU(s); 653 654 switch (riscv_cpu_mxl(&cpu->env)) { 655 case MXL_RV32: 656 info->print_insn = print_insn_riscv32; 657 break; 658 case MXL_RV64: 659 info->print_insn = print_insn_riscv64; 660 break; 661 case MXL_RV128: 662 info->print_insn = print_insn_riscv128; 663 break; 664 default: 665 g_assert_not_reached(); 666 } 667 } 668 669 /* 670 * Check consistency between chosen extensions while setting 671 * cpu->cfg accordingly, doing a set_misa() in the end. 672 */ 673 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 674 { 675 CPURISCVState *env = &cpu->env; 676 uint32_t ext = 0; 677 678 /* Do some ISA extension error checking */ 679 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 680 cpu->cfg.ext_a && cpu->cfg.ext_f && 681 cpu->cfg.ext_d && 682 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 683 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 684 cpu->cfg.ext_i = true; 685 cpu->cfg.ext_m = true; 686 cpu->cfg.ext_a = true; 687 cpu->cfg.ext_f = true; 688 cpu->cfg.ext_d = true; 689 cpu->cfg.ext_icsr = true; 690 cpu->cfg.ext_ifencei = true; 691 } 692 693 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 694 error_setg(errp, 695 "I and E extensions are incompatible"); 696 return; 697 } 698 699 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 700 error_setg(errp, 701 "Either I or E extension must be set"); 702 return; 703 } 704 705 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { 706 error_setg(errp, 707 "Setting S extension without U extension is illegal"); 708 return; 709 } 710 711 if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { 712 error_setg(errp, 713 "H depends on an I base integer ISA with 32 x registers"); 714 return; 715 } 716 717 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { 718 error_setg(errp, "H extension implicitly requires S-mode"); 719 return; 720 } 721 722 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 723 error_setg(errp, "F extension requires Zicsr"); 724 return; 725 } 726 727 if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { 728 error_setg(errp, "Zawrs extension requires A extension"); 729 return; 730 } 731 732 if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { 733 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 734 return; 735 } 736 737 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 738 error_setg(errp, "D extension requires F extension"); 739 return; 740 } 741 742 if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { 743 error_setg(errp, "V extension requires D extension"); 744 return; 745 } 746 747 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 748 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 749 return; 750 } 751 752 /* Set the ISA extensions, checks should have happened above */ 753 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || 754 cpu->cfg.ext_zhinxmin) { 755 cpu->cfg.ext_zfinx = true; 756 } 757 758 if (cpu->cfg.ext_zfinx) { 759 if (!cpu->cfg.ext_icsr) { 760 error_setg(errp, "Zfinx extension requires Zicsr"); 761 return; 762 } 763 if (cpu->cfg.ext_f) { 764 error_setg(errp, 765 "Zfinx cannot be supported together with F extension"); 766 return; 767 } 768 } 769 770 if (cpu->cfg.ext_zk) { 771 cpu->cfg.ext_zkn = true; 772 cpu->cfg.ext_zkr = true; 773 cpu->cfg.ext_zkt = true; 774 } 775 776 if (cpu->cfg.ext_zkn) { 777 cpu->cfg.ext_zbkb = true; 778 cpu->cfg.ext_zbkc = true; 779 cpu->cfg.ext_zbkx = true; 780 cpu->cfg.ext_zkne = true; 781 cpu->cfg.ext_zknd = true; 782 cpu->cfg.ext_zknh = true; 783 } 784 785 if (cpu->cfg.ext_zks) { 786 cpu->cfg.ext_zbkb = true; 787 cpu->cfg.ext_zbkc = true; 788 cpu->cfg.ext_zbkx = true; 789 cpu->cfg.ext_zksed = true; 790 cpu->cfg.ext_zksh = true; 791 } 792 793 if (cpu->cfg.ext_i) { 794 ext |= RVI; 795 } 796 if (cpu->cfg.ext_e) { 797 ext |= RVE; 798 } 799 if (cpu->cfg.ext_m) { 800 ext |= RVM; 801 } 802 if (cpu->cfg.ext_a) { 803 ext |= RVA; 804 } 805 if (cpu->cfg.ext_f) { 806 ext |= RVF; 807 } 808 if (cpu->cfg.ext_d) { 809 ext |= RVD; 810 } 811 if (cpu->cfg.ext_c) { 812 ext |= RVC; 813 } 814 if (cpu->cfg.ext_s) { 815 ext |= RVS; 816 } 817 if (cpu->cfg.ext_u) { 818 ext |= RVU; 819 } 820 if (cpu->cfg.ext_h) { 821 ext |= RVH; 822 } 823 if (cpu->cfg.ext_v) { 824 int vext_version = VEXT_VERSION_1_00_0; 825 ext |= RVV; 826 if (!is_power_of_2(cpu->cfg.vlen)) { 827 error_setg(errp, 828 "Vector extension VLEN must be power of 2"); 829 return; 830 } 831 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 832 error_setg(errp, 833 "Vector extension implementation only supports VLEN " 834 "in the range [128, %d]", RV_VLEN_MAX); 835 return; 836 } 837 if (!is_power_of_2(cpu->cfg.elen)) { 838 error_setg(errp, 839 "Vector extension ELEN must be power of 2"); 840 return; 841 } 842 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 843 error_setg(errp, 844 "Vector extension implementation only supports ELEN " 845 "in the range [8, 64]"); 846 return; 847 } 848 if (cpu->cfg.vext_spec) { 849 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 850 vext_version = VEXT_VERSION_1_00_0; 851 } else { 852 error_setg(errp, 853 "Unsupported vector spec version '%s'", 854 cpu->cfg.vext_spec); 855 return; 856 } 857 } else { 858 qemu_log("vector version is not specified, " 859 "use the default value v1.0\n"); 860 } 861 set_vext_version(env, vext_version); 862 } 863 if (cpu->cfg.ext_j) { 864 ext |= RVJ; 865 } 866 867 set_misa(env, env->misa_mxl, ext); 868 } 869 870 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 871 { 872 CPUState *cs = CPU(dev); 873 RISCVCPU *cpu = RISCV_CPU(dev); 874 CPURISCVState *env = &cpu->env; 875 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 876 CPUClass *cc = CPU_CLASS(mcc); 877 int i, priv_version = -1; 878 Error *local_err = NULL; 879 880 cpu_exec_realizefn(cs, &local_err); 881 if (local_err != NULL) { 882 error_propagate(errp, local_err); 883 return; 884 } 885 886 if (cpu->cfg.priv_spec) { 887 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 888 priv_version = PRIV_VERSION_1_12_0; 889 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 890 priv_version = PRIV_VERSION_1_11_0; 891 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 892 priv_version = PRIV_VERSION_1_10_0; 893 } else { 894 error_setg(errp, 895 "Unsupported privilege spec version '%s'", 896 cpu->cfg.priv_spec); 897 return; 898 } 899 } 900 901 if (priv_version >= PRIV_VERSION_1_10_0) { 902 set_priv_version(env, priv_version); 903 } 904 905 /* Force disable extensions if priv spec version does not match */ 906 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 907 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 908 (env->priv_ver < isa_edata_arr[i].min_version)) { 909 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 910 #ifndef CONFIG_USER_ONLY 911 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 912 " because privilege spec version does not match", 913 isa_edata_arr[i].name, env->mhartid); 914 #else 915 warn_report("disabling %s extension because " 916 "privilege spec version does not match", 917 isa_edata_arr[i].name); 918 #endif 919 } 920 } 921 922 if (cpu->cfg.mmu) { 923 riscv_set_feature(env, RISCV_FEATURE_MMU); 924 } 925 926 if (cpu->cfg.pmp) { 927 riscv_set_feature(env, RISCV_FEATURE_PMP); 928 929 /* 930 * Enhanced PMP should only be available 931 * on harts with PMP support 932 */ 933 if (cpu->cfg.epmp) { 934 riscv_set_feature(env, RISCV_FEATURE_EPMP); 935 } 936 } 937 938 if (cpu->cfg.debug) { 939 riscv_set_feature(env, RISCV_FEATURE_DEBUG); 940 } 941 942 943 #ifndef CONFIG_USER_ONLY 944 if (cpu->cfg.ext_sstc) { 945 riscv_timer_init(cpu); 946 } 947 #endif /* CONFIG_USER_ONLY */ 948 949 /* Validate that MISA_MXL is set properly. */ 950 switch (env->misa_mxl_max) { 951 #ifdef TARGET_RISCV64 952 case MXL_RV64: 953 case MXL_RV128: 954 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 955 break; 956 #endif 957 case MXL_RV32: 958 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 959 break; 960 default: 961 g_assert_not_reached(); 962 } 963 assert(env->misa_mxl_max == env->misa_mxl); 964 965 riscv_cpu_validate_set_extensions(cpu, &local_err); 966 if (local_err != NULL) { 967 error_propagate(errp, local_err); 968 return; 969 } 970 971 #ifndef CONFIG_USER_ONLY 972 if (cpu->cfg.pmu_num) { 973 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 974 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 975 riscv_pmu_timer_cb, cpu); 976 } 977 } 978 #endif 979 980 riscv_cpu_register_gdb_regs_for_features(cs); 981 982 qemu_init_vcpu(cs); 983 cpu_reset(cs); 984 985 mcc->parent_realize(dev, errp); 986 } 987 988 #ifndef CONFIG_USER_ONLY 989 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 990 { 991 RISCVCPU *cpu = RISCV_CPU(opaque); 992 CPURISCVState *env = &cpu->env; 993 994 if (irq < IRQ_LOCAL_MAX) { 995 switch (irq) { 996 case IRQ_U_SOFT: 997 case IRQ_S_SOFT: 998 case IRQ_VS_SOFT: 999 case IRQ_M_SOFT: 1000 case IRQ_U_TIMER: 1001 case IRQ_S_TIMER: 1002 case IRQ_VS_TIMER: 1003 case IRQ_M_TIMER: 1004 case IRQ_U_EXT: 1005 case IRQ_VS_EXT: 1006 case IRQ_M_EXT: 1007 if (kvm_enabled()) { 1008 kvm_riscv_set_irq(cpu, irq, level); 1009 } else { 1010 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 1011 } 1012 break; 1013 case IRQ_S_EXT: 1014 if (kvm_enabled()) { 1015 kvm_riscv_set_irq(cpu, irq, level); 1016 } else { 1017 env->external_seip = level; 1018 riscv_cpu_update_mip(cpu, 1 << irq, 1019 BOOL_TO_MASK(level | env->software_seip)); 1020 } 1021 break; 1022 default: 1023 g_assert_not_reached(); 1024 } 1025 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1026 /* Require H-extension for handling guest local interrupts */ 1027 if (!riscv_has_ext(env, RVH)) { 1028 g_assert_not_reached(); 1029 } 1030 1031 /* Compute bit position in HGEIP CSR */ 1032 irq = irq - IRQ_LOCAL_MAX + 1; 1033 if (env->geilen < irq) { 1034 g_assert_not_reached(); 1035 } 1036 1037 /* Update HGEIP CSR */ 1038 env->hgeip &= ~((target_ulong)1 << irq); 1039 if (level) { 1040 env->hgeip |= (target_ulong)1 << irq; 1041 } 1042 1043 /* Update mip.SGEIP bit */ 1044 riscv_cpu_update_mip(cpu, MIP_SGEIP, 1045 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1046 } else { 1047 g_assert_not_reached(); 1048 } 1049 } 1050 #endif /* CONFIG_USER_ONLY */ 1051 1052 static void riscv_cpu_init(Object *obj) 1053 { 1054 RISCVCPU *cpu = RISCV_CPU(obj); 1055 1056 cpu->cfg.ext_ifencei = true; 1057 cpu->cfg.ext_icsr = true; 1058 cpu->cfg.mmu = true; 1059 cpu->cfg.pmp = true; 1060 1061 cpu_set_cpustate_pointers(cpu); 1062 1063 #ifndef CONFIG_USER_ONLY 1064 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1065 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1066 #endif /* CONFIG_USER_ONLY */ 1067 } 1068 1069 static Property riscv_cpu_extensions[] = { 1070 /* Defaults for standard extensions */ 1071 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 1072 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 1073 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 1074 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 1075 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 1076 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 1077 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 1078 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 1079 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 1080 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 1081 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1082 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1083 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1084 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1085 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1086 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1087 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1088 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1089 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1090 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1091 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1092 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1093 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1094 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1095 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1096 1097 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1098 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1099 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1100 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1101 1102 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1103 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1104 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1105 1106 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1107 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1108 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1109 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1110 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1111 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1112 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1113 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1114 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1115 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1116 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1117 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1118 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1119 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1120 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1121 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1122 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1123 1124 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1125 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1126 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1127 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1128 1129 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1130 1131 /* Vendor-specific custom extensions */ 1132 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1133 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1134 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1135 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1136 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1137 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1138 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1139 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1140 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1141 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1142 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1143 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1144 1145 /* These are experimental so mark with 'x-' */ 1146 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1147 /* ePMP 0.9.3 */ 1148 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1149 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1150 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1151 1152 DEFINE_PROP_END_OF_LIST(), 1153 }; 1154 1155 /* 1156 * Register CPU props based on env.misa_ext. If a non-zero 1157 * value was set, register only the required cpu->cfg.ext_* 1158 * properties and leave. env.misa_ext = 0 means that we want 1159 * all the default properties to be registered. 1160 */ 1161 static void register_cpu_props(DeviceState *dev) 1162 { 1163 RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); 1164 uint32_t misa_ext = cpu->env.misa_ext; 1165 Property *prop; 1166 1167 /* 1168 * If misa_ext is not zero, set cfg properties now to 1169 * allow them to be read during riscv_cpu_realize() 1170 * later on. 1171 */ 1172 if (cpu->env.misa_ext != 0) { 1173 cpu->cfg.ext_i = misa_ext & RVI; 1174 cpu->cfg.ext_e = misa_ext & RVE; 1175 cpu->cfg.ext_m = misa_ext & RVM; 1176 cpu->cfg.ext_a = misa_ext & RVA; 1177 cpu->cfg.ext_f = misa_ext & RVF; 1178 cpu->cfg.ext_d = misa_ext & RVD; 1179 cpu->cfg.ext_v = misa_ext & RVV; 1180 cpu->cfg.ext_c = misa_ext & RVC; 1181 cpu->cfg.ext_s = misa_ext & RVS; 1182 cpu->cfg.ext_u = misa_ext & RVU; 1183 cpu->cfg.ext_h = misa_ext & RVH; 1184 cpu->cfg.ext_j = misa_ext & RVJ; 1185 1186 /* 1187 * We don't want to set the default riscv_cpu_extensions 1188 * in this case. 1189 */ 1190 return; 1191 } 1192 1193 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1194 qdev_property_add_static(dev, prop); 1195 } 1196 } 1197 1198 static Property riscv_cpu_properties[] = { 1199 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1200 1201 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1202 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1203 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1204 1205 #ifndef CONFIG_USER_ONLY 1206 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1207 #endif 1208 1209 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1210 1211 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1212 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1213 DEFINE_PROP_END_OF_LIST(), 1214 }; 1215 1216 static gchar *riscv_gdb_arch_name(CPUState *cs) 1217 { 1218 RISCVCPU *cpu = RISCV_CPU(cs); 1219 CPURISCVState *env = &cpu->env; 1220 1221 switch (riscv_cpu_mxl(env)) { 1222 case MXL_RV32: 1223 return g_strdup("riscv:rv32"); 1224 case MXL_RV64: 1225 case MXL_RV128: 1226 return g_strdup("riscv:rv64"); 1227 default: 1228 g_assert_not_reached(); 1229 } 1230 } 1231 1232 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1233 { 1234 RISCVCPU *cpu = RISCV_CPU(cs); 1235 1236 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1237 return cpu->dyn_csr_xml; 1238 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1239 return cpu->dyn_vreg_xml; 1240 } 1241 1242 return NULL; 1243 } 1244 1245 #ifndef CONFIG_USER_ONLY 1246 #include "hw/core/sysemu-cpu-ops.h" 1247 1248 static const struct SysemuCPUOps riscv_sysemu_ops = { 1249 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1250 .write_elf64_note = riscv_cpu_write_elf64_note, 1251 .write_elf32_note = riscv_cpu_write_elf32_note, 1252 .legacy_vmsd = &vmstate_riscv_cpu, 1253 }; 1254 #endif 1255 1256 #include "hw/core/tcg-cpu-ops.h" 1257 1258 static const struct TCGCPUOps riscv_tcg_ops = { 1259 .initialize = riscv_translate_init, 1260 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1261 .restore_state_to_opc = riscv_restore_state_to_opc, 1262 1263 #ifndef CONFIG_USER_ONLY 1264 .tlb_fill = riscv_cpu_tlb_fill, 1265 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1266 .do_interrupt = riscv_cpu_do_interrupt, 1267 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1268 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1269 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1270 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1271 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1272 #endif /* !CONFIG_USER_ONLY */ 1273 }; 1274 1275 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1276 { 1277 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1278 CPUClass *cc = CPU_CLASS(c); 1279 DeviceClass *dc = DEVICE_CLASS(c); 1280 ResettableClass *rc = RESETTABLE_CLASS(c); 1281 1282 device_class_set_parent_realize(dc, riscv_cpu_realize, 1283 &mcc->parent_realize); 1284 1285 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1286 &mcc->parent_phases); 1287 1288 cc->class_by_name = riscv_cpu_class_by_name; 1289 cc->has_work = riscv_cpu_has_work; 1290 cc->dump_state = riscv_cpu_dump_state; 1291 cc->set_pc = riscv_cpu_set_pc; 1292 cc->get_pc = riscv_cpu_get_pc; 1293 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1294 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1295 cc->gdb_num_core_regs = 33; 1296 cc->gdb_stop_before_watchpoint = true; 1297 cc->disas_set_info = riscv_cpu_disas_set_info; 1298 #ifndef CONFIG_USER_ONLY 1299 cc->sysemu_ops = &riscv_sysemu_ops; 1300 #endif 1301 cc->gdb_arch_name = riscv_gdb_arch_name; 1302 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1303 cc->tcg_ops = &riscv_tcg_ops; 1304 1305 device_class_set_props(dc, riscv_cpu_properties); 1306 } 1307 1308 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 1309 { 1310 char *old = *isa_str; 1311 char *new = *isa_str; 1312 int i; 1313 1314 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1315 if (isa_edata_arr[i].multi_letter && 1316 isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1317 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1318 g_free(old); 1319 old = new; 1320 } 1321 } 1322 1323 *isa_str = new; 1324 } 1325 1326 char *riscv_isa_string(RISCVCPU *cpu) 1327 { 1328 int i; 1329 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1330 char *isa_str = g_new(char, maxlen); 1331 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1332 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1333 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1334 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1335 } 1336 } 1337 *p = '\0'; 1338 if (!cpu->cfg.short_isa_string) { 1339 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1340 } 1341 return isa_str; 1342 } 1343 1344 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1345 { 1346 ObjectClass *class_a = (ObjectClass *)a; 1347 ObjectClass *class_b = (ObjectClass *)b; 1348 const char *name_a, *name_b; 1349 1350 name_a = object_class_get_name(class_a); 1351 name_b = object_class_get_name(class_b); 1352 return strcmp(name_a, name_b); 1353 } 1354 1355 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1356 { 1357 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1358 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1359 1360 qemu_printf("%.*s\n", len, typename); 1361 } 1362 1363 void riscv_cpu_list(void) 1364 { 1365 GSList *list; 1366 1367 list = object_class_get_list(TYPE_RISCV_CPU, false); 1368 list = g_slist_sort(list, riscv_cpu_list_compare); 1369 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1370 g_slist_free(list); 1371 } 1372 1373 #define DEFINE_CPU(type_name, initfn) \ 1374 { \ 1375 .name = type_name, \ 1376 .parent = TYPE_RISCV_CPU, \ 1377 .instance_init = initfn \ 1378 } 1379 1380 static const TypeInfo riscv_cpu_type_infos[] = { 1381 { 1382 .name = TYPE_RISCV_CPU, 1383 .parent = TYPE_CPU, 1384 .instance_size = sizeof(RISCVCPU), 1385 .instance_align = __alignof__(RISCVCPU), 1386 .instance_init = riscv_cpu_init, 1387 .abstract = true, 1388 .class_size = sizeof(RISCVCPUClass), 1389 .class_init = riscv_cpu_class_init, 1390 }, 1391 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1392 #if defined(CONFIG_KVM) 1393 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1394 #endif 1395 #if defined(TARGET_RISCV32) 1396 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1397 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1398 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1399 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1400 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1401 #elif defined(TARGET_RISCV64) 1402 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1403 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1404 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1405 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1406 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1407 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1408 #endif 1409 }; 1410 1411 DEFINE_TYPES(riscv_cpu_type_infos) 1412