1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "qom/cpu.h" 24 #include "exec/cpu-defs.h" 25 #include "fpu/softfloat.h" 26 27 #define TCG_GUEST_DEFAULT_MO 0 28 29 #define TYPE_RISCV_CPU "riscv-cpu" 30 31 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 32 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 33 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 34 35 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 36 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 37 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 38 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") 39 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") 40 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu") 41 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") 42 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") 43 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu") 44 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 45 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 46 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 47 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 48 49 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 50 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 51 52 #if defined(TARGET_RISCV32) 53 #define RVXLEN RV32 54 #elif defined(TARGET_RISCV64) 55 #define RVXLEN RV64 56 #endif 57 58 #define RV(x) ((target_ulong)1 << (x - 'A')) 59 60 #define RVI RV('I') 61 #define RVE RV('E') /* E and I are mutually exclusive */ 62 #define RVM RV('M') 63 #define RVA RV('A') 64 #define RVF RV('F') 65 #define RVD RV('D') 66 #define RVC RV('C') 67 #define RVS RV('S') 68 #define RVU RV('U') 69 70 /* S extension denotes that Supervisor mode exists, however it is possible 71 to have a core that support S mode but does not have an MMU and there 72 is currently no bit in misa to indicate whether an MMU exists or not 73 so a cpu features bitfield is required, likewise for optional PMP support */ 74 enum { 75 RISCV_FEATURE_MMU, 76 RISCV_FEATURE_PMP, 77 RISCV_FEATURE_MISA 78 }; 79 80 #define USER_VERSION_2_02_0 0x00020200 81 #define PRIV_VERSION_1_09_1 0x00010901 82 #define PRIV_VERSION_1_10_0 0x00011000 83 84 #define TRANSLATE_FAIL 1 85 #define TRANSLATE_SUCCESS 0 86 #define MMU_USER_IDX 3 87 88 #define MAX_RISCV_PMPS (16) 89 90 typedef struct CPURISCVState CPURISCVState; 91 92 #include "pmp.h" 93 94 struct CPURISCVState { 95 target_ulong gpr[32]; 96 uint64_t fpr[32]; /* assume both F and D extensions */ 97 target_ulong pc; 98 target_ulong load_res; 99 target_ulong load_val; 100 101 target_ulong frm; 102 103 target_ulong badaddr; 104 105 target_ulong user_ver; 106 target_ulong priv_ver; 107 target_ulong misa; 108 target_ulong misa_mask; 109 110 uint32_t features; 111 112 #ifdef CONFIG_USER_ONLY 113 uint32_t elf_flags; 114 #endif 115 116 #ifndef CONFIG_USER_ONLY 117 target_ulong priv; 118 target_ulong resetvec; 119 120 target_ulong mhartid; 121 target_ulong mstatus; 122 123 /* 124 * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously 125 * by I/O threads. It should be read with atomic_read. It should be updated 126 * using riscv_cpu_update_mip with the iothread mutex held. The iothread 127 * mutex must be held because mip must be consistent with the CPU inturrept 128 * state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt 129 * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero. 130 * mip is 32-bits to allow atomic_read on 32-bit hosts. 131 */ 132 uint32_t mip; 133 uint32_t miclaim; 134 135 target_ulong mie; 136 target_ulong mideleg; 137 138 target_ulong sptbr; /* until: priv-1.9.1 */ 139 target_ulong satp; /* since: priv-1.10.0 */ 140 target_ulong sbadaddr; 141 target_ulong mbadaddr; 142 target_ulong medeleg; 143 144 target_ulong stvec; 145 target_ulong sepc; 146 target_ulong scause; 147 148 target_ulong mtvec; 149 target_ulong mepc; 150 target_ulong mcause; 151 target_ulong mtval; /* since: priv-1.10.0 */ 152 153 target_ulong scounteren; 154 target_ulong mcounteren; 155 156 target_ulong sscratch; 157 target_ulong mscratch; 158 159 /* temporary htif regs */ 160 uint64_t mfromhost; 161 uint64_t mtohost; 162 uint64_t timecmp; 163 164 /* physical memory protection */ 165 pmp_table_t pmp_state; 166 167 /* True if in debugger mode. */ 168 bool debugger; 169 #endif 170 171 float_status fp_status; 172 173 /* Fields from here on are preserved across CPU reset. */ 174 QEMUTimer *timer; /* Internal timer */ 175 }; 176 177 #define RISCV_CPU_CLASS(klass) \ 178 OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU) 179 #define RISCV_CPU(obj) \ 180 OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU) 181 #define RISCV_CPU_GET_CLASS(obj) \ 182 OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU) 183 184 /** 185 * RISCVCPUClass: 186 * @parent_realize: The parent class' realize handler. 187 * @parent_reset: The parent class' reset handler. 188 * 189 * A RISCV CPU model. 190 */ 191 typedef struct RISCVCPUClass { 192 /*< private >*/ 193 CPUClass parent_class; 194 /*< public >*/ 195 DeviceRealize parent_realize; 196 void (*parent_reset)(CPUState *cpu); 197 } RISCVCPUClass; 198 199 /** 200 * RISCVCPU: 201 * @env: #CPURISCVState 202 * 203 * A RISCV CPU. 204 */ 205 typedef struct RISCVCPU { 206 /*< private >*/ 207 CPUState parent_obj; 208 /*< public >*/ 209 CPUNegativeOffsetState neg; 210 CPURISCVState env; 211 212 /* Configuration Settings */ 213 struct { 214 char *priv_spec; 215 char *user_spec; 216 bool mmu; 217 bool pmp; 218 } cfg; 219 } RISCVCPU; 220 221 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 222 { 223 return (env->misa & ext) != 0; 224 } 225 226 static inline bool riscv_feature(CPURISCVState *env, int feature) 227 { 228 return env->features & (1ULL << feature); 229 } 230 231 #include "cpu_user.h" 232 #include "cpu_bits.h" 233 234 extern const char * const riscv_int_regnames[]; 235 extern const char * const riscv_fpr_regnames[]; 236 extern const char * const riscv_excp_names[]; 237 extern const char * const riscv_intr_names[]; 238 239 void riscv_cpu_do_interrupt(CPUState *cpu); 240 int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 241 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 242 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 243 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 244 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 245 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 246 MMUAccessType access_type, int mmu_idx, 247 uintptr_t retaddr); 248 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 249 MMUAccessType access_type, int mmu_idx, 250 bool probe, uintptr_t retaddr); 251 char *riscv_isa_string(RISCVCPU *cpu); 252 void riscv_cpu_list(void); 253 254 #define cpu_signal_handler riscv_cpu_signal_handler 255 #define cpu_list riscv_cpu_list 256 #define cpu_mmu_index riscv_cpu_mmu_index 257 258 #ifndef CONFIG_USER_ONLY 259 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 260 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 261 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 262 #endif 263 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 264 265 void riscv_translate_init(void); 266 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 267 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 268 uint32_t exception, uintptr_t pc); 269 270 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 271 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 272 273 #define TB_FLAGS_MMU_MASK 3 274 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 275 276 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 277 target_ulong *cs_base, uint32_t *flags) 278 { 279 *pc = env->pc; 280 *cs_base = 0; 281 #ifdef CONFIG_USER_ONLY 282 *flags = TB_FLAGS_MSTATUS_FS; 283 #else 284 *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); 285 #endif 286 } 287 288 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 289 target_ulong new_value, target_ulong write_mask); 290 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 291 target_ulong new_value, target_ulong write_mask); 292 293 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 294 target_ulong val) 295 { 296 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 297 } 298 299 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 300 { 301 target_ulong val = 0; 302 riscv_csrrw(env, csrno, &val, 0, 0); 303 return val; 304 } 305 306 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); 307 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 308 target_ulong *ret_value); 309 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 310 target_ulong new_value); 311 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 312 target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); 313 314 typedef struct { 315 riscv_csr_predicate_fn predicate; 316 riscv_csr_read_fn read; 317 riscv_csr_write_fn write; 318 riscv_csr_op_fn op; 319 } riscv_csr_operations; 320 321 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 322 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 323 324 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 325 326 typedef CPURISCVState CPUArchState; 327 typedef RISCVCPU ArchCPU; 328 329 #include "exec/cpu-all.h" 330 331 #endif /* RISCV_CPU_H */ 332