1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 #define TYPE_RISCV_CPU "riscv-cpu" 34 35 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 36 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 37 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 38 39 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 40 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 41 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 42 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 43 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 44 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 45 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 46 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 47 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 48 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 49 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 50 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 51 52 #if defined(TARGET_RISCV32) 53 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 54 #elif defined(TARGET_RISCV64) 55 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 56 #endif 57 58 #define RV(x) ((target_ulong)1 << (x - 'A')) 59 60 #define RVI RV('I') 61 #define RVE RV('E') /* E and I are mutually exclusive */ 62 #define RVM RV('M') 63 #define RVA RV('A') 64 #define RVF RV('F') 65 #define RVD RV('D') 66 #define RVV RV('V') 67 #define RVC RV('C') 68 #define RVS RV('S') 69 #define RVU RV('U') 70 #define RVH RV('H') 71 #define RVJ RV('J') 72 73 /* S extension denotes that Supervisor mode exists, however it is possible 74 to have a core that support S mode but does not have an MMU and there 75 is currently no bit in misa to indicate whether an MMU exists or not 76 so a cpu features bitfield is required, likewise for optional PMP support */ 77 enum { 78 RISCV_FEATURE_MMU, 79 RISCV_FEATURE_PMP, 80 RISCV_FEATURE_EPMP, 81 RISCV_FEATURE_MISA, 82 RISCV_FEATURE_AIA 83 }; 84 85 #define PRIV_VERSION_1_10_0 0x00011000 86 #define PRIV_VERSION_1_11_0 0x00011100 87 88 #define VEXT_VERSION_1_00_0 0x00010000 89 90 enum { 91 TRANSLATE_SUCCESS, 92 TRANSLATE_FAIL, 93 TRANSLATE_PMP_FAIL, 94 TRANSLATE_G_STAGE_FAIL 95 }; 96 97 #define MMU_USER_IDX 3 98 99 #define MAX_RISCV_PMPS (16) 100 101 typedef struct CPUArchState CPURISCVState; 102 103 #if !defined(CONFIG_USER_ONLY) 104 #include "pmp.h" 105 #endif 106 107 #define RV_VLEN_MAX 1024 108 109 FIELD(VTYPE, VLMUL, 0, 3) 110 FIELD(VTYPE, VSEW, 3, 3) 111 FIELD(VTYPE, VTA, 6, 1) 112 FIELD(VTYPE, VMA, 7, 1) 113 FIELD(VTYPE, VEDIV, 8, 2) 114 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 115 116 struct CPUArchState { 117 target_ulong gpr[32]; 118 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 119 uint64_t fpr[32]; /* assume both F and D extensions */ 120 121 /* vector coprocessor state. */ 122 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 123 target_ulong vxrm; 124 target_ulong vxsat; 125 target_ulong vl; 126 target_ulong vstart; 127 target_ulong vtype; 128 bool vill; 129 130 target_ulong pc; 131 target_ulong load_res; 132 target_ulong load_val; 133 134 target_ulong frm; 135 136 target_ulong badaddr; 137 uint32_t bins; 138 139 target_ulong guest_phys_fault_addr; 140 141 target_ulong priv_ver; 142 target_ulong bext_ver; 143 target_ulong vext_ver; 144 145 /* RISCVMXL, but uint32_t for vmstate migration */ 146 uint32_t misa_mxl; /* current mxl */ 147 uint32_t misa_mxl_max; /* max mxl for this cpu */ 148 uint32_t misa_ext; /* current extensions */ 149 uint32_t misa_ext_mask; /* max ext for this cpu */ 150 uint32_t xl; /* current xlen */ 151 152 /* 128-bit helpers upper part return value */ 153 target_ulong retxh; 154 155 uint32_t features; 156 157 #ifdef CONFIG_USER_ONLY 158 uint32_t elf_flags; 159 #endif 160 161 #ifndef CONFIG_USER_ONLY 162 target_ulong priv; 163 /* This contains QEMU specific information about the virt state. */ 164 target_ulong virt; 165 target_ulong geilen; 166 target_ulong resetvec; 167 168 target_ulong mhartid; 169 /* 170 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 171 * For RV64 this is a 64-bit mstatus. 172 */ 173 uint64_t mstatus; 174 175 uint64_t mip; 176 177 uint64_t miclaim; 178 179 uint64_t mie; 180 uint64_t mideleg; 181 182 target_ulong satp; /* since: priv-1.10.0 */ 183 target_ulong stval; 184 target_ulong medeleg; 185 186 target_ulong stvec; 187 target_ulong sepc; 188 target_ulong scause; 189 190 target_ulong mtvec; 191 target_ulong mepc; 192 target_ulong mcause; 193 target_ulong mtval; /* since: priv-1.10.0 */ 194 195 /* Machine and Supervisor interrupt priorities */ 196 uint8_t miprio[64]; 197 uint8_t siprio[64]; 198 199 /* AIA CSRs */ 200 target_ulong miselect; 201 target_ulong siselect; 202 203 /* Hypervisor CSRs */ 204 target_ulong hstatus; 205 target_ulong hedeleg; 206 uint64_t hideleg; 207 target_ulong hcounteren; 208 target_ulong htval; 209 target_ulong htinst; 210 target_ulong hgatp; 211 target_ulong hgeie; 212 target_ulong hgeip; 213 uint64_t htimedelta; 214 215 /* Hypervisor controlled virtual interrupt priorities */ 216 target_ulong hvictl; 217 uint8_t hviprio[64]; 218 219 /* Upper 64-bits of 128-bit CSRs */ 220 uint64_t mscratchh; 221 uint64_t sscratchh; 222 223 /* Virtual CSRs */ 224 /* 225 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 226 * For RV64 this is a 64-bit vsstatus. 227 */ 228 uint64_t vsstatus; 229 target_ulong vstvec; 230 target_ulong vsscratch; 231 target_ulong vsepc; 232 target_ulong vscause; 233 target_ulong vstval; 234 target_ulong vsatp; 235 236 /* AIA VS-mode CSRs */ 237 target_ulong vsiselect; 238 239 target_ulong mtval2; 240 target_ulong mtinst; 241 242 /* HS Backup CSRs */ 243 target_ulong stvec_hs; 244 target_ulong sscratch_hs; 245 target_ulong sepc_hs; 246 target_ulong scause_hs; 247 target_ulong stval_hs; 248 target_ulong satp_hs; 249 uint64_t mstatus_hs; 250 251 /* Signals whether the current exception occurred with two-stage address 252 translation active. */ 253 bool two_stage_lookup; 254 255 target_ulong scounteren; 256 target_ulong mcounteren; 257 258 target_ulong sscratch; 259 target_ulong mscratch; 260 261 /* temporary htif regs */ 262 uint64_t mfromhost; 263 uint64_t mtohost; 264 uint64_t timecmp; 265 266 /* physical memory protection */ 267 pmp_table_t pmp_state; 268 target_ulong mseccfg; 269 270 /* machine specific rdtime callback */ 271 uint64_t (*rdtime_fn)(uint32_t); 272 uint32_t rdtime_fn_arg; 273 274 /* machine specific AIA ireg read-modify-write callback */ 275 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 276 ((((__xlen) & 0xff) << 24) | \ 277 (((__vgein) & 0x3f) << 20) | \ 278 (((__virt) & 0x1) << 18) | \ 279 (((__priv) & 0x3) << 16) | \ 280 (__isel & 0xffff)) 281 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 282 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 283 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 284 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 285 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 286 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 287 target_ulong *val, target_ulong new_val, target_ulong write_mask); 288 void *aia_ireg_rmw_fn_arg[4]; 289 290 /* True if in debugger mode. */ 291 bool debugger; 292 293 /* 294 * CSRs for PointerMasking extension 295 */ 296 target_ulong mmte; 297 target_ulong mpmmask; 298 target_ulong mpmbase; 299 target_ulong spmmask; 300 target_ulong spmbase; 301 target_ulong upmmask; 302 target_ulong upmbase; 303 #endif 304 target_ulong cur_pmmask; 305 target_ulong cur_pmbase; 306 307 float_status fp_status; 308 309 /* Fields from here on are preserved across CPU reset. */ 310 QEMUTimer *timer; /* Internal timer */ 311 312 hwaddr kernel_addr; 313 hwaddr fdt_addr; 314 315 /* kvm timer */ 316 bool kvm_timer_dirty; 317 uint64_t kvm_timer_time; 318 uint64_t kvm_timer_compare; 319 uint64_t kvm_timer_state; 320 uint64_t kvm_timer_frequency; 321 }; 322 323 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 324 325 /** 326 * RISCVCPUClass: 327 * @parent_realize: The parent class' realize handler. 328 * @parent_reset: The parent class' reset handler. 329 * 330 * A RISCV CPU model. 331 */ 332 struct RISCVCPUClass { 333 /*< private >*/ 334 CPUClass parent_class; 335 /*< public >*/ 336 DeviceRealize parent_realize; 337 DeviceReset parent_reset; 338 }; 339 340 struct RISCVCPUConfig { 341 bool ext_i; 342 bool ext_e; 343 bool ext_g; 344 bool ext_m; 345 bool ext_a; 346 bool ext_f; 347 bool ext_d; 348 bool ext_c; 349 bool ext_s; 350 bool ext_u; 351 bool ext_h; 352 bool ext_j; 353 bool ext_v; 354 bool ext_zba; 355 bool ext_zbb; 356 bool ext_zbc; 357 bool ext_zbs; 358 bool ext_counters; 359 bool ext_ifencei; 360 bool ext_icsr; 361 bool ext_svinval; 362 bool ext_svnapot; 363 bool ext_svpbmt; 364 bool ext_zdinx; 365 bool ext_zfh; 366 bool ext_zfhmin; 367 bool ext_zfinx; 368 bool ext_zhinx; 369 bool ext_zhinxmin; 370 bool ext_zve32f; 371 bool ext_zve64f; 372 373 /* Vendor-specific custom extensions */ 374 bool ext_XVentanaCondOps; 375 376 char *priv_spec; 377 char *user_spec; 378 char *bext_spec; 379 char *vext_spec; 380 uint16_t vlen; 381 uint16_t elen; 382 bool mmu; 383 bool pmp; 384 bool epmp; 385 bool aia; 386 uint64_t resetvec; 387 }; 388 389 typedef struct RISCVCPUConfig RISCVCPUConfig; 390 391 /** 392 * RISCVCPU: 393 * @env: #CPURISCVState 394 * 395 * A RISCV CPU. 396 */ 397 struct ArchCPU { 398 /*< private >*/ 399 CPUState parent_obj; 400 /*< public >*/ 401 CPUNegativeOffsetState neg; 402 CPURISCVState env; 403 404 char *dyn_csr_xml; 405 char *dyn_vreg_xml; 406 407 /* Configuration Settings */ 408 RISCVCPUConfig cfg; 409 }; 410 411 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 412 { 413 return (env->misa_ext & ext) != 0; 414 } 415 416 static inline bool riscv_feature(CPURISCVState *env, int feature) 417 { 418 return env->features & (1ULL << feature); 419 } 420 421 static inline void riscv_set_feature(CPURISCVState *env, int feature) 422 { 423 env->features |= (1ULL << feature); 424 } 425 426 #include "cpu_user.h" 427 428 extern const char * const riscv_int_regnames[]; 429 extern const char * const riscv_int_regnamesh[]; 430 extern const char * const riscv_fpr_regnames[]; 431 432 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 433 void riscv_cpu_do_interrupt(CPUState *cpu); 434 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 435 int cpuid, void *opaque); 436 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 437 int cpuid, void *opaque); 438 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 439 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 440 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 441 uint8_t riscv_cpu_default_priority(int irq); 442 int riscv_cpu_mirq_pending(CPURISCVState *env); 443 int riscv_cpu_sirq_pending(CPURISCVState *env); 444 int riscv_cpu_vsirq_pending(CPURISCVState *env); 445 bool riscv_cpu_fp_enabled(CPURISCVState *env); 446 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 447 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 448 bool riscv_cpu_vector_enabled(CPURISCVState *env); 449 bool riscv_cpu_virt_enabled(CPURISCVState *env); 450 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 451 bool riscv_cpu_two_stage_lookup(int mmu_idx); 452 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 453 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 454 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 455 MMUAccessType access_type, int mmu_idx, 456 uintptr_t retaddr) QEMU_NORETURN; 457 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 458 MMUAccessType access_type, int mmu_idx, 459 bool probe, uintptr_t retaddr); 460 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 461 vaddr addr, unsigned size, 462 MMUAccessType access_type, 463 int mmu_idx, MemTxAttrs attrs, 464 MemTxResult response, uintptr_t retaddr); 465 char *riscv_isa_string(RISCVCPU *cpu); 466 void riscv_cpu_list(void); 467 468 #define cpu_list riscv_cpu_list 469 #define cpu_mmu_index riscv_cpu_mmu_index 470 471 #ifndef CONFIG_USER_ONLY 472 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 473 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 474 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 475 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 476 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 477 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 478 uint32_t arg); 479 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 480 int (*rmw_fn)(void *arg, 481 target_ulong reg, 482 target_ulong *val, 483 target_ulong new_val, 484 target_ulong write_mask), 485 void *rmw_fn_arg); 486 #endif 487 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 488 489 void riscv_translate_init(void); 490 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 491 uint32_t exception, uintptr_t pc); 492 493 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 494 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 495 496 #define TB_FLAGS_PRIV_MMU_MASK 3 497 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 498 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 499 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 500 501 #include "exec/cpu-all.h" 502 503 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 504 FIELD(TB_FLAGS, LMUL, 3, 3) 505 FIELD(TB_FLAGS, SEW, 6, 3) 506 /* Skip MSTATUS_VS (0x600) bits */ 507 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 508 FIELD(TB_FLAGS, VILL, 12, 1) 509 /* Skip MSTATUS_FS (0x6000) bits */ 510 /* Is a Hypervisor instruction load/store allowed? */ 511 FIELD(TB_FLAGS, HLSX, 15, 1) 512 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 513 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 514 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 515 FIELD(TB_FLAGS, XL, 20, 2) 516 /* If PointerMasking should be applied */ 517 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 518 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 519 520 #ifdef TARGET_RISCV32 521 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 522 #else 523 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 524 { 525 return env->misa_mxl; 526 } 527 #endif 528 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 529 530 #if defined(TARGET_RISCV32) 531 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 532 #else 533 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 534 { 535 RISCVMXL xl = env->misa_mxl; 536 #if !defined(CONFIG_USER_ONLY) 537 /* 538 * When emulating a 32-bit-only cpu, use RV32. 539 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 540 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 541 * back to RV64 for lower privs. 542 */ 543 if (xl != MXL_RV32) { 544 switch (env->priv) { 545 case PRV_M: 546 break; 547 case PRV_U: 548 xl = get_field(env->mstatus, MSTATUS64_UXL); 549 break; 550 default: /* PRV_S | PRV_H */ 551 xl = get_field(env->mstatus, MSTATUS64_SXL); 552 break; 553 } 554 } 555 #endif 556 return xl; 557 } 558 #endif 559 560 static inline int riscv_cpu_xlen(CPURISCVState *env) 561 { 562 return 16 << env->xl; 563 } 564 565 #ifdef TARGET_RISCV32 566 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 567 #else 568 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 569 { 570 #ifdef CONFIG_USER_ONLY 571 return env->misa_mxl; 572 #else 573 return get_field(env->mstatus, MSTATUS64_SXL); 574 #endif 575 } 576 #endif 577 578 /* 579 * Encode LMUL to lmul as follows: 580 * LMUL vlmul lmul 581 * 1 000 0 582 * 2 001 1 583 * 4 010 2 584 * 8 011 3 585 * - 100 - 586 * 1/8 101 -3 587 * 1/4 110 -2 588 * 1/2 111 -1 589 * 590 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 591 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 592 * => VLMAX = vlen >> (1 + 3 - (-3)) 593 * = 256 >> 7 594 * = 2 595 */ 596 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 597 { 598 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 599 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 600 return cpu->cfg.vlen >> (sew + 3 - lmul); 601 } 602 603 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 604 target_ulong *cs_base, uint32_t *pflags); 605 606 void riscv_cpu_update_mask(CPURISCVState *env); 607 608 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 609 target_ulong *ret_value, 610 target_ulong new_value, target_ulong write_mask); 611 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 612 target_ulong *ret_value, 613 target_ulong new_value, 614 target_ulong write_mask); 615 616 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 617 target_ulong val) 618 { 619 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 620 } 621 622 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 623 { 624 target_ulong val = 0; 625 riscv_csrrw(env, csrno, &val, 0, 0); 626 return val; 627 } 628 629 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 630 int csrno); 631 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 632 target_ulong *ret_value); 633 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 634 target_ulong new_value); 635 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 636 target_ulong *ret_value, 637 target_ulong new_value, 638 target_ulong write_mask); 639 640 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 641 Int128 *ret_value, 642 Int128 new_value, Int128 write_mask); 643 644 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 645 Int128 *ret_value); 646 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 647 Int128 new_value); 648 649 typedef struct { 650 const char *name; 651 riscv_csr_predicate_fn predicate; 652 riscv_csr_read_fn read; 653 riscv_csr_write_fn write; 654 riscv_csr_op_fn op; 655 riscv_csr_read128_fn read128; 656 riscv_csr_write128_fn write128; 657 } riscv_csr_operations; 658 659 /* CSR function table constants */ 660 enum { 661 CSR_TABLE_SIZE = 0x1000 662 }; 663 664 /* CSR function table */ 665 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 666 667 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 668 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 669 670 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 671 672 #endif /* RISCV_CPU_H */ 673