1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") 57 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 58 59 #if defined(TARGET_RISCV32) 60 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 61 #elif defined(TARGET_RISCV64) 62 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 63 #endif 64 65 #define RV(x) ((target_ulong)1 << (x - 'A')) 66 67 /* 68 * Consider updating register_cpu_props() when adding 69 * new MISA bits here. 70 */ 71 #define RVI RV('I') 72 #define RVE RV('E') /* E and I are mutually exclusive */ 73 #define RVM RV('M') 74 #define RVA RV('A') 75 #define RVF RV('F') 76 #define RVD RV('D') 77 #define RVV RV('V') 78 #define RVC RV('C') 79 #define RVS RV('S') 80 #define RVU RV('U') 81 #define RVH RV('H') 82 #define RVJ RV('J') 83 84 85 /* Privileged specification version */ 86 enum { 87 PRIV_VERSION_1_10_0 = 0, 88 PRIV_VERSION_1_11_0, 89 PRIV_VERSION_1_12_0, 90 }; 91 92 #define VEXT_VERSION_1_00_0 0x00010000 93 94 enum { 95 TRANSLATE_SUCCESS, 96 TRANSLATE_FAIL, 97 TRANSLATE_PMP_FAIL, 98 TRANSLATE_G_STAGE_FAIL 99 }; 100 101 #define MMU_USER_IDX 3 102 103 #define MAX_RISCV_PMPS (16) 104 105 typedef struct CPUArchState CPURISCVState; 106 107 #if !defined(CONFIG_USER_ONLY) 108 #include "pmp.h" 109 #include "debug.h" 110 #endif 111 112 #define RV_VLEN_MAX 1024 113 #define RV_MAX_MHPMEVENTS 32 114 #define RV_MAX_MHPMCOUNTERS 32 115 116 FIELD(VTYPE, VLMUL, 0, 3) 117 FIELD(VTYPE, VSEW, 3, 3) 118 FIELD(VTYPE, VTA, 6, 1) 119 FIELD(VTYPE, VMA, 7, 1) 120 FIELD(VTYPE, VEDIV, 8, 2) 121 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 122 123 typedef struct PMUCTRState { 124 /* Current value of a counter */ 125 target_ulong mhpmcounter_val; 126 /* Current value of a counter in RV32*/ 127 target_ulong mhpmcounterh_val; 128 /* Snapshot values of counter */ 129 target_ulong mhpmcounter_prev; 130 /* Snapshort value of a counter in RV32 */ 131 target_ulong mhpmcounterh_prev; 132 bool started; 133 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 134 target_ulong irq_overflow_left; 135 } PMUCTRState; 136 137 struct CPUArchState { 138 target_ulong gpr[32]; 139 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 140 141 /* vector coprocessor state. */ 142 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 143 target_ulong vxrm; 144 target_ulong vxsat; 145 target_ulong vl; 146 target_ulong vstart; 147 target_ulong vtype; 148 bool vill; 149 150 target_ulong pc; 151 target_ulong load_res; 152 target_ulong load_val; 153 154 /* Floating-Point state */ 155 uint64_t fpr[32]; /* assume both F and D extensions */ 156 target_ulong frm; 157 float_status fp_status; 158 159 target_ulong badaddr; 160 target_ulong bins; 161 162 target_ulong guest_phys_fault_addr; 163 164 target_ulong priv_ver; 165 target_ulong bext_ver; 166 target_ulong vext_ver; 167 168 /* RISCVMXL, but uint32_t for vmstate migration */ 169 uint32_t misa_mxl; /* current mxl */ 170 uint32_t misa_mxl_max; /* max mxl for this cpu */ 171 uint32_t misa_ext; /* current extensions */ 172 uint32_t misa_ext_mask; /* max ext for this cpu */ 173 uint32_t xl; /* current xlen */ 174 175 /* 128-bit helpers upper part return value */ 176 target_ulong retxh; 177 178 #ifdef CONFIG_USER_ONLY 179 uint32_t elf_flags; 180 #endif 181 182 #ifndef CONFIG_USER_ONLY 183 target_ulong priv; 184 /* This contains QEMU specific information about the virt state. */ 185 target_ulong virt; 186 target_ulong geilen; 187 uint64_t resetvec; 188 189 target_ulong mhartid; 190 /* 191 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 192 * For RV64 this is a 64-bit mstatus. 193 */ 194 uint64_t mstatus; 195 196 uint64_t mip; 197 /* 198 * MIP contains the software writable version of SEIP ORed with the 199 * external interrupt value. The MIP register is always up-to-date. 200 * To keep track of the current source, we also save booleans of the values 201 * here. 202 */ 203 bool external_seip; 204 bool software_seip; 205 206 uint64_t miclaim; 207 208 uint64_t mie; 209 uint64_t mideleg; 210 211 target_ulong satp; /* since: priv-1.10.0 */ 212 target_ulong stval; 213 target_ulong medeleg; 214 215 target_ulong stvec; 216 target_ulong sepc; 217 target_ulong scause; 218 219 target_ulong mtvec; 220 target_ulong mepc; 221 target_ulong mcause; 222 target_ulong mtval; /* since: priv-1.10.0 */ 223 224 /* Machine and Supervisor interrupt priorities */ 225 uint8_t miprio[64]; 226 uint8_t siprio[64]; 227 228 /* AIA CSRs */ 229 target_ulong miselect; 230 target_ulong siselect; 231 232 /* Hypervisor CSRs */ 233 target_ulong hstatus; 234 target_ulong hedeleg; 235 uint64_t hideleg; 236 target_ulong hcounteren; 237 target_ulong htval; 238 target_ulong htinst; 239 target_ulong hgatp; 240 target_ulong hgeie; 241 target_ulong hgeip; 242 uint64_t htimedelta; 243 244 /* Hypervisor controlled virtual interrupt priorities */ 245 target_ulong hvictl; 246 uint8_t hviprio[64]; 247 248 /* Upper 64-bits of 128-bit CSRs */ 249 uint64_t mscratchh; 250 uint64_t sscratchh; 251 252 /* Virtual CSRs */ 253 /* 254 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 255 * For RV64 this is a 64-bit vsstatus. 256 */ 257 uint64_t vsstatus; 258 target_ulong vstvec; 259 target_ulong vsscratch; 260 target_ulong vsepc; 261 target_ulong vscause; 262 target_ulong vstval; 263 target_ulong vsatp; 264 265 /* AIA VS-mode CSRs */ 266 target_ulong vsiselect; 267 268 target_ulong mtval2; 269 target_ulong mtinst; 270 271 /* HS Backup CSRs */ 272 target_ulong stvec_hs; 273 target_ulong sscratch_hs; 274 target_ulong sepc_hs; 275 target_ulong scause_hs; 276 target_ulong stval_hs; 277 target_ulong satp_hs; 278 uint64_t mstatus_hs; 279 280 /* Signals whether the current exception occurred with two-stage address 281 translation active. */ 282 bool two_stage_lookup; 283 /* 284 * Signals whether the current exception occurred while doing two-stage 285 * address translation for the VS-stage page table walk. 286 */ 287 bool two_stage_indirect_lookup; 288 289 target_ulong scounteren; 290 target_ulong mcounteren; 291 292 target_ulong mcountinhibit; 293 294 /* PMU counter state */ 295 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 296 297 /* PMU event selector configured values. First three are unused*/ 298 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 299 300 /* PMU event selector configured values for RV32*/ 301 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 302 303 target_ulong sscratch; 304 target_ulong mscratch; 305 306 /* Sstc CSRs */ 307 uint64_t stimecmp; 308 309 uint64_t vstimecmp; 310 311 /* physical memory protection */ 312 pmp_table_t pmp_state; 313 target_ulong mseccfg; 314 315 /* trigger module */ 316 target_ulong trigger_cur; 317 target_ulong tdata1[RV_MAX_TRIGGERS]; 318 target_ulong tdata2[RV_MAX_TRIGGERS]; 319 target_ulong tdata3[RV_MAX_TRIGGERS]; 320 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 321 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 322 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 323 int64_t last_icount; 324 bool itrigger_enabled; 325 326 /* machine specific rdtime callback */ 327 uint64_t (*rdtime_fn)(void *); 328 void *rdtime_fn_arg; 329 330 /* machine specific AIA ireg read-modify-write callback */ 331 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 332 ((((__xlen) & 0xff) << 24) | \ 333 (((__vgein) & 0x3f) << 20) | \ 334 (((__virt) & 0x1) << 18) | \ 335 (((__priv) & 0x3) << 16) | \ 336 (__isel & 0xffff)) 337 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 338 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 339 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 340 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 341 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 342 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 343 target_ulong *val, target_ulong new_val, target_ulong write_mask); 344 void *aia_ireg_rmw_fn_arg[4]; 345 346 /* True if in debugger mode. */ 347 bool debugger; 348 349 /* 350 * CSRs for PointerMasking extension 351 */ 352 target_ulong mmte; 353 target_ulong mpmmask; 354 target_ulong mpmbase; 355 target_ulong spmmask; 356 target_ulong spmbase; 357 target_ulong upmmask; 358 target_ulong upmbase; 359 360 /* CSRs for execution enviornment configuration */ 361 uint64_t menvcfg; 362 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 363 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 364 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 365 target_ulong senvcfg; 366 uint64_t henvcfg; 367 #endif 368 target_ulong cur_pmmask; 369 target_ulong cur_pmbase; 370 371 /* Fields from here on are preserved across CPU reset. */ 372 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 373 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 374 bool vstime_irq; 375 376 hwaddr kernel_addr; 377 hwaddr fdt_addr; 378 379 /* kvm timer */ 380 bool kvm_timer_dirty; 381 uint64_t kvm_timer_time; 382 uint64_t kvm_timer_compare; 383 uint64_t kvm_timer_state; 384 uint64_t kvm_timer_frequency; 385 }; 386 387 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 388 389 /** 390 * RISCVCPUClass: 391 * @parent_realize: The parent class' realize handler. 392 * @parent_phases: The parent class' reset phase handlers. 393 * 394 * A RISCV CPU model. 395 */ 396 struct RISCVCPUClass { 397 /*< private >*/ 398 CPUClass parent_class; 399 /*< public >*/ 400 DeviceRealize parent_realize; 401 ResettablePhases parent_phases; 402 }; 403 404 struct RISCVCPUConfig { 405 bool ext_i; 406 bool ext_e; 407 bool ext_g; 408 bool ext_m; 409 bool ext_a; 410 bool ext_f; 411 bool ext_d; 412 bool ext_c; 413 bool ext_s; 414 bool ext_u; 415 bool ext_h; 416 bool ext_j; 417 bool ext_v; 418 bool ext_zba; 419 bool ext_zbb; 420 bool ext_zbc; 421 bool ext_zbkb; 422 bool ext_zbkc; 423 bool ext_zbkx; 424 bool ext_zbs; 425 bool ext_zk; 426 bool ext_zkn; 427 bool ext_zknd; 428 bool ext_zkne; 429 bool ext_zknh; 430 bool ext_zkr; 431 bool ext_zks; 432 bool ext_zksed; 433 bool ext_zksh; 434 bool ext_zkt; 435 bool ext_ifencei; 436 bool ext_icsr; 437 bool ext_zicond; 438 bool ext_zihintpause; 439 bool ext_smstateen; 440 bool ext_sstc; 441 bool ext_svadu; 442 bool ext_svinval; 443 bool ext_svnapot; 444 bool ext_svpbmt; 445 bool ext_zdinx; 446 bool ext_zawrs; 447 bool ext_zfh; 448 bool ext_zfhmin; 449 bool ext_zfinx; 450 bool ext_zhinx; 451 bool ext_zhinxmin; 452 bool ext_zve32f; 453 bool ext_zve64f; 454 bool ext_zve64d; 455 bool ext_zmmul; 456 bool ext_zvfh; 457 bool ext_zvfhmin; 458 bool ext_smaia; 459 bool ext_ssaia; 460 bool ext_sscofpmf; 461 bool rvv_ta_all_1s; 462 bool rvv_ma_all_1s; 463 464 uint32_t mvendorid; 465 uint64_t marchid; 466 uint64_t mimpid; 467 468 /* Vendor-specific custom extensions */ 469 bool ext_xtheadba; 470 bool ext_xtheadbb; 471 bool ext_xtheadbs; 472 bool ext_xtheadcmo; 473 bool ext_xtheadcondmov; 474 bool ext_xtheadfmemidx; 475 bool ext_xtheadfmv; 476 bool ext_xtheadmac; 477 bool ext_xtheadmemidx; 478 bool ext_xtheadmempair; 479 bool ext_xtheadsync; 480 bool ext_XVentanaCondOps; 481 482 uint8_t pmu_num; 483 char *priv_spec; 484 char *user_spec; 485 char *bext_spec; 486 char *vext_spec; 487 uint16_t vlen; 488 uint16_t elen; 489 bool mmu; 490 bool pmp; 491 bool epmp; 492 bool debug; 493 bool misa_w; 494 495 bool short_isa_string; 496 }; 497 498 typedef struct RISCVCPUConfig RISCVCPUConfig; 499 500 /** 501 * RISCVCPU: 502 * @env: #CPURISCVState 503 * 504 * A RISCV CPU. 505 */ 506 struct ArchCPU { 507 /*< private >*/ 508 CPUState parent_obj; 509 /*< public >*/ 510 CPUNegativeOffsetState neg; 511 CPURISCVState env; 512 513 char *dyn_csr_xml; 514 char *dyn_vreg_xml; 515 516 /* Configuration Settings */ 517 RISCVCPUConfig cfg; 518 519 QEMUTimer *pmu_timer; 520 /* A bitmask of Available programmable counters */ 521 uint32_t pmu_avail_ctrs; 522 /* Mapping of events to counters */ 523 GHashTable *pmu_event_ctr_map; 524 }; 525 526 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 527 { 528 return (env->misa_ext & ext) != 0; 529 } 530 531 #include "cpu_user.h" 532 533 extern const char * const riscv_int_regnames[]; 534 extern const char * const riscv_int_regnamesh[]; 535 extern const char * const riscv_fpr_regnames[]; 536 537 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 538 void riscv_cpu_do_interrupt(CPUState *cpu); 539 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 540 int cpuid, DumpState *s); 541 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 542 int cpuid, DumpState *s); 543 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 544 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 545 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 546 uint8_t riscv_cpu_default_priority(int irq); 547 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 548 int riscv_cpu_mirq_pending(CPURISCVState *env); 549 int riscv_cpu_sirq_pending(CPURISCVState *env); 550 int riscv_cpu_vsirq_pending(CPURISCVState *env); 551 bool riscv_cpu_fp_enabled(CPURISCVState *env); 552 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 553 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 554 bool riscv_cpu_vector_enabled(CPURISCVState *env); 555 bool riscv_cpu_virt_enabled(CPURISCVState *env); 556 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 557 bool riscv_cpu_two_stage_lookup(int mmu_idx); 558 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 559 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 560 MMUAccessType access_type, int mmu_idx, 561 uintptr_t retaddr); 562 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 563 MMUAccessType access_type, int mmu_idx, 564 bool probe, uintptr_t retaddr); 565 char *riscv_isa_string(RISCVCPU *cpu); 566 void riscv_cpu_list(void); 567 568 #define cpu_list riscv_cpu_list 569 #define cpu_mmu_index riscv_cpu_mmu_index 570 571 #ifndef CONFIG_USER_ONLY 572 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 573 vaddr addr, unsigned size, 574 MMUAccessType access_type, 575 int mmu_idx, MemTxAttrs attrs, 576 MemTxResult response, uintptr_t retaddr); 577 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 578 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 579 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 580 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 581 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 582 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 583 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 584 void *arg); 585 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 586 int (*rmw_fn)(void *arg, 587 target_ulong reg, 588 target_ulong *val, 589 target_ulong new_val, 590 target_ulong write_mask), 591 void *rmw_fn_arg); 592 #endif 593 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 594 595 void riscv_translate_init(void); 596 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 597 uint32_t exception, uintptr_t pc); 598 599 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 600 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 601 602 #define TB_FLAGS_PRIV_MMU_MASK 3 603 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 604 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 605 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 606 607 #include "exec/cpu-all.h" 608 609 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 610 FIELD(TB_FLAGS, LMUL, 3, 3) 611 FIELD(TB_FLAGS, SEW, 6, 3) 612 /* Skip MSTATUS_VS (0x600) bits */ 613 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 614 FIELD(TB_FLAGS, VILL, 12, 1) 615 /* Skip MSTATUS_FS (0x6000) bits */ 616 /* Is a Hypervisor instruction load/store allowed? */ 617 FIELD(TB_FLAGS, HLSX, 15, 1) 618 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 619 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 620 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 621 FIELD(TB_FLAGS, XL, 20, 2) 622 /* If PointerMasking should be applied */ 623 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 624 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 625 FIELD(TB_FLAGS, VTA, 24, 1) 626 FIELD(TB_FLAGS, VMA, 25, 1) 627 /* Native debug itrigger */ 628 FIELD(TB_FLAGS, ITRIGGER, 26, 1) 629 630 #ifdef TARGET_RISCV32 631 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 632 #else 633 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 634 { 635 return env->misa_mxl; 636 } 637 #endif 638 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 639 640 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 641 { 642 return &env_archcpu(env)->cfg; 643 } 644 645 #if defined(TARGET_RISCV32) 646 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 647 #else 648 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 649 { 650 RISCVMXL xl = env->misa_mxl; 651 #if !defined(CONFIG_USER_ONLY) 652 /* 653 * When emulating a 32-bit-only cpu, use RV32. 654 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 655 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 656 * back to RV64 for lower privs. 657 */ 658 if (xl != MXL_RV32) { 659 switch (env->priv) { 660 case PRV_M: 661 break; 662 case PRV_U: 663 xl = get_field(env->mstatus, MSTATUS64_UXL); 664 break; 665 default: /* PRV_S | PRV_H */ 666 xl = get_field(env->mstatus, MSTATUS64_SXL); 667 break; 668 } 669 } 670 #endif 671 return xl; 672 } 673 #endif 674 675 static inline int riscv_cpu_xlen(CPURISCVState *env) 676 { 677 return 16 << env->xl; 678 } 679 680 #ifdef TARGET_RISCV32 681 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 682 #else 683 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 684 { 685 #ifdef CONFIG_USER_ONLY 686 return env->misa_mxl; 687 #else 688 return get_field(env->mstatus, MSTATUS64_SXL); 689 #endif 690 } 691 #endif 692 693 /* 694 * Encode LMUL to lmul as follows: 695 * LMUL vlmul lmul 696 * 1 000 0 697 * 2 001 1 698 * 4 010 2 699 * 8 011 3 700 * - 100 - 701 * 1/8 101 -3 702 * 1/4 110 -2 703 * 1/2 111 -1 704 * 705 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 706 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 707 * => VLMAX = vlen >> (1 + 3 - (-3)) 708 * = 256 >> 7 709 * = 2 710 */ 711 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 712 { 713 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 714 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 715 return cpu->cfg.vlen >> (sew + 3 - lmul); 716 } 717 718 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 719 target_ulong *cs_base, uint32_t *pflags); 720 721 void riscv_cpu_update_mask(CPURISCVState *env); 722 723 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 724 target_ulong *ret_value, 725 target_ulong new_value, target_ulong write_mask); 726 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 727 target_ulong *ret_value, 728 target_ulong new_value, 729 target_ulong write_mask); 730 731 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 732 target_ulong val) 733 { 734 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 735 } 736 737 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 738 { 739 target_ulong val = 0; 740 riscv_csrrw(env, csrno, &val, 0, 0); 741 return val; 742 } 743 744 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 745 int csrno); 746 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 747 target_ulong *ret_value); 748 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 749 target_ulong new_value); 750 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 751 target_ulong *ret_value, 752 target_ulong new_value, 753 target_ulong write_mask); 754 755 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 756 Int128 *ret_value, 757 Int128 new_value, Int128 write_mask); 758 759 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 760 Int128 *ret_value); 761 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 762 Int128 new_value); 763 764 typedef struct { 765 const char *name; 766 riscv_csr_predicate_fn predicate; 767 riscv_csr_read_fn read; 768 riscv_csr_write_fn write; 769 riscv_csr_op_fn op; 770 riscv_csr_read128_fn read128; 771 riscv_csr_write128_fn write128; 772 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 773 uint32_t min_priv_ver; 774 } riscv_csr_operations; 775 776 /* CSR function table constants */ 777 enum { 778 CSR_TABLE_SIZE = 0x1000 779 }; 780 781 /** 782 * The event id are encoded based on the encoding specified in the 783 * SBI specification v0.3 784 */ 785 786 enum riscv_pmu_event_idx { 787 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 788 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 789 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 790 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 791 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 792 }; 793 794 /* CSR function table */ 795 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 796 797 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 798 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 799 800 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 801 802 #endif /* RISCV_CPU_H */ 803