1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 #define TYPE_RISCV_CPU "riscv-cpu" 34 35 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 36 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 37 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 38 39 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 40 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 41 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 42 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 43 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 44 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 45 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 46 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 47 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 48 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 49 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 50 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 51 52 #if defined(TARGET_RISCV32) 53 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 54 #elif defined(TARGET_RISCV64) 55 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 56 #endif 57 58 #define RV(x) ((target_ulong)1 << (x - 'A')) 59 60 #define RVI RV('I') 61 #define RVE RV('E') /* E and I are mutually exclusive */ 62 #define RVM RV('M') 63 #define RVA RV('A') 64 #define RVF RV('F') 65 #define RVD RV('D') 66 #define RVV RV('V') 67 #define RVC RV('C') 68 #define RVS RV('S') 69 #define RVU RV('U') 70 #define RVH RV('H') 71 #define RVJ RV('J') 72 73 /* S extension denotes that Supervisor mode exists, however it is possible 74 to have a core that support S mode but does not have an MMU and there 75 is currently no bit in misa to indicate whether an MMU exists or not 76 so a cpu features bitfield is required, likewise for optional PMP support */ 77 enum { 78 RISCV_FEATURE_MMU, 79 RISCV_FEATURE_PMP, 80 RISCV_FEATURE_EPMP, 81 RISCV_FEATURE_MISA, 82 RISCV_FEATURE_AIA, 83 RISCV_FEATURE_DEBUG 84 }; 85 86 /* Privileged specification version */ 87 enum { 88 PRIV_VERSION_1_10_0 = 0, 89 PRIV_VERSION_1_11_0, 90 PRIV_VERSION_1_12_0, 91 }; 92 93 #define VEXT_VERSION_1_00_0 0x00010000 94 95 enum { 96 TRANSLATE_SUCCESS, 97 TRANSLATE_FAIL, 98 TRANSLATE_PMP_FAIL, 99 TRANSLATE_G_STAGE_FAIL 100 }; 101 102 #define MMU_USER_IDX 3 103 104 #define MAX_RISCV_PMPS (16) 105 106 typedef struct CPUArchState CPURISCVState; 107 108 #if !defined(CONFIG_USER_ONLY) 109 #include "pmp.h" 110 #include "debug.h" 111 #endif 112 113 #define RV_VLEN_MAX 1024 114 115 FIELD(VTYPE, VLMUL, 0, 3) 116 FIELD(VTYPE, VSEW, 3, 3) 117 FIELD(VTYPE, VTA, 6, 1) 118 FIELD(VTYPE, VMA, 7, 1) 119 FIELD(VTYPE, VEDIV, 8, 2) 120 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 121 122 struct CPUArchState { 123 target_ulong gpr[32]; 124 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 125 uint64_t fpr[32]; /* assume both F and D extensions */ 126 127 /* vector coprocessor state. */ 128 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 129 target_ulong vxrm; 130 target_ulong vxsat; 131 target_ulong vl; 132 target_ulong vstart; 133 target_ulong vtype; 134 bool vill; 135 136 target_ulong pc; 137 target_ulong load_res; 138 target_ulong load_val; 139 140 target_ulong frm; 141 142 target_ulong badaddr; 143 uint32_t bins; 144 145 target_ulong guest_phys_fault_addr; 146 147 target_ulong priv_ver; 148 target_ulong bext_ver; 149 target_ulong vext_ver; 150 151 /* RISCVMXL, but uint32_t for vmstate migration */ 152 uint32_t misa_mxl; /* current mxl */ 153 uint32_t misa_mxl_max; /* max mxl for this cpu */ 154 uint32_t misa_ext; /* current extensions */ 155 uint32_t misa_ext_mask; /* max ext for this cpu */ 156 uint32_t xl; /* current xlen */ 157 158 /* 128-bit helpers upper part return value */ 159 target_ulong retxh; 160 161 uint32_t features; 162 163 #ifdef CONFIG_USER_ONLY 164 uint32_t elf_flags; 165 #endif 166 167 #ifndef CONFIG_USER_ONLY 168 target_ulong priv; 169 /* This contains QEMU specific information about the virt state. */ 170 target_ulong virt; 171 target_ulong geilen; 172 target_ulong resetvec; 173 174 target_ulong mhartid; 175 /* 176 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 177 * For RV64 this is a 64-bit mstatus. 178 */ 179 uint64_t mstatus; 180 181 uint64_t mip; 182 /* 183 * MIP contains the software writable version of SEIP ORed with the 184 * external interrupt value. The MIP register is always up-to-date. 185 * To keep track of the current source, we also save booleans of the values 186 * here. 187 */ 188 bool external_seip; 189 bool software_seip; 190 191 uint64_t miclaim; 192 193 uint64_t mie; 194 uint64_t mideleg; 195 196 target_ulong satp; /* since: priv-1.10.0 */ 197 target_ulong stval; 198 target_ulong medeleg; 199 200 target_ulong stvec; 201 target_ulong sepc; 202 target_ulong scause; 203 204 target_ulong mtvec; 205 target_ulong mepc; 206 target_ulong mcause; 207 target_ulong mtval; /* since: priv-1.10.0 */ 208 209 /* Machine and Supervisor interrupt priorities */ 210 uint8_t miprio[64]; 211 uint8_t siprio[64]; 212 213 /* AIA CSRs */ 214 target_ulong miselect; 215 target_ulong siselect; 216 217 /* Hypervisor CSRs */ 218 target_ulong hstatus; 219 target_ulong hedeleg; 220 uint64_t hideleg; 221 target_ulong hcounteren; 222 target_ulong htval; 223 target_ulong htinst; 224 target_ulong hgatp; 225 target_ulong hgeie; 226 target_ulong hgeip; 227 uint64_t htimedelta; 228 229 /* Hypervisor controlled virtual interrupt priorities */ 230 target_ulong hvictl; 231 uint8_t hviprio[64]; 232 233 /* Upper 64-bits of 128-bit CSRs */ 234 uint64_t mscratchh; 235 uint64_t sscratchh; 236 237 /* Virtual CSRs */ 238 /* 239 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 240 * For RV64 this is a 64-bit vsstatus. 241 */ 242 uint64_t vsstatus; 243 target_ulong vstvec; 244 target_ulong vsscratch; 245 target_ulong vsepc; 246 target_ulong vscause; 247 target_ulong vstval; 248 target_ulong vsatp; 249 250 /* AIA VS-mode CSRs */ 251 target_ulong vsiselect; 252 253 target_ulong mtval2; 254 target_ulong mtinst; 255 256 /* HS Backup CSRs */ 257 target_ulong stvec_hs; 258 target_ulong sscratch_hs; 259 target_ulong sepc_hs; 260 target_ulong scause_hs; 261 target_ulong stval_hs; 262 target_ulong satp_hs; 263 uint64_t mstatus_hs; 264 265 /* Signals whether the current exception occurred with two-stage address 266 translation active. */ 267 bool two_stage_lookup; 268 269 target_ulong scounteren; 270 target_ulong mcounteren; 271 272 target_ulong sscratch; 273 target_ulong mscratch; 274 275 /* temporary htif regs */ 276 uint64_t mfromhost; 277 uint64_t mtohost; 278 uint64_t timecmp; 279 280 /* physical memory protection */ 281 pmp_table_t pmp_state; 282 target_ulong mseccfg; 283 284 /* trigger module */ 285 target_ulong trigger_cur; 286 type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; 287 288 /* machine specific rdtime callback */ 289 uint64_t (*rdtime_fn)(void *); 290 void *rdtime_fn_arg; 291 292 /* machine specific AIA ireg read-modify-write callback */ 293 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 294 ((((__xlen) & 0xff) << 24) | \ 295 (((__vgein) & 0x3f) << 20) | \ 296 (((__virt) & 0x1) << 18) | \ 297 (((__priv) & 0x3) << 16) | \ 298 (__isel & 0xffff)) 299 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 300 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 301 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 302 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 303 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 304 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 305 target_ulong *val, target_ulong new_val, target_ulong write_mask); 306 void *aia_ireg_rmw_fn_arg[4]; 307 308 /* True if in debugger mode. */ 309 bool debugger; 310 311 /* 312 * CSRs for PointerMasking extension 313 */ 314 target_ulong mmte; 315 target_ulong mpmmask; 316 target_ulong mpmbase; 317 target_ulong spmmask; 318 target_ulong spmbase; 319 target_ulong upmmask; 320 target_ulong upmbase; 321 322 /* CSRs for execution enviornment configuration */ 323 uint64_t menvcfg; 324 target_ulong senvcfg; 325 uint64_t henvcfg; 326 #endif 327 target_ulong cur_pmmask; 328 target_ulong cur_pmbase; 329 330 float_status fp_status; 331 332 /* Fields from here on are preserved across CPU reset. */ 333 QEMUTimer *timer; /* Internal timer */ 334 335 hwaddr kernel_addr; 336 hwaddr fdt_addr; 337 338 /* kvm timer */ 339 bool kvm_timer_dirty; 340 uint64_t kvm_timer_time; 341 uint64_t kvm_timer_compare; 342 uint64_t kvm_timer_state; 343 uint64_t kvm_timer_frequency; 344 }; 345 346 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 347 348 /** 349 * RISCVCPUClass: 350 * @parent_realize: The parent class' realize handler. 351 * @parent_reset: The parent class' reset handler. 352 * 353 * A RISCV CPU model. 354 */ 355 struct RISCVCPUClass { 356 /*< private >*/ 357 CPUClass parent_class; 358 /*< public >*/ 359 DeviceRealize parent_realize; 360 DeviceReset parent_reset; 361 }; 362 363 struct RISCVCPUConfig { 364 bool ext_i; 365 bool ext_e; 366 bool ext_g; 367 bool ext_m; 368 bool ext_a; 369 bool ext_f; 370 bool ext_d; 371 bool ext_c; 372 bool ext_s; 373 bool ext_u; 374 bool ext_h; 375 bool ext_j; 376 bool ext_v; 377 bool ext_zba; 378 bool ext_zbb; 379 bool ext_zbc; 380 bool ext_zbkb; 381 bool ext_zbkc; 382 bool ext_zbkx; 383 bool ext_zbs; 384 bool ext_zk; 385 bool ext_zkn; 386 bool ext_zknd; 387 bool ext_zkne; 388 bool ext_zknh; 389 bool ext_zkr; 390 bool ext_zks; 391 bool ext_zksed; 392 bool ext_zksh; 393 bool ext_zkt; 394 bool ext_counters; 395 bool ext_ifencei; 396 bool ext_icsr; 397 bool ext_svinval; 398 bool ext_svnapot; 399 bool ext_svpbmt; 400 bool ext_zdinx; 401 bool ext_zfh; 402 bool ext_zfhmin; 403 bool ext_zfinx; 404 bool ext_zhinx; 405 bool ext_zhinxmin; 406 bool ext_zve32f; 407 bool ext_zve64f; 408 409 uint32_t mvendorid; 410 uint64_t marchid; 411 uint64_t mipid; 412 413 /* Vendor-specific custom extensions */ 414 bool ext_XVentanaCondOps; 415 416 char *priv_spec; 417 char *user_spec; 418 char *bext_spec; 419 char *vext_spec; 420 uint16_t vlen; 421 uint16_t elen; 422 bool mmu; 423 bool pmp; 424 bool epmp; 425 bool aia; 426 bool debug; 427 uint64_t resetvec; 428 }; 429 430 typedef struct RISCVCPUConfig RISCVCPUConfig; 431 432 /** 433 * RISCVCPU: 434 * @env: #CPURISCVState 435 * 436 * A RISCV CPU. 437 */ 438 struct ArchCPU { 439 /*< private >*/ 440 CPUState parent_obj; 441 /*< public >*/ 442 CPUNegativeOffsetState neg; 443 CPURISCVState env; 444 445 char *dyn_csr_xml; 446 char *dyn_vreg_xml; 447 448 /* Configuration Settings */ 449 RISCVCPUConfig cfg; 450 }; 451 452 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 453 { 454 return (env->misa_ext & ext) != 0; 455 } 456 457 static inline bool riscv_feature(CPURISCVState *env, int feature) 458 { 459 return env->features & (1ULL << feature); 460 } 461 462 static inline void riscv_set_feature(CPURISCVState *env, int feature) 463 { 464 env->features |= (1ULL << feature); 465 } 466 467 #include "cpu_user.h" 468 469 extern const char * const riscv_int_regnames[]; 470 extern const char * const riscv_int_regnamesh[]; 471 extern const char * const riscv_fpr_regnames[]; 472 473 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 474 void riscv_cpu_do_interrupt(CPUState *cpu); 475 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 476 int cpuid, void *opaque); 477 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 478 int cpuid, void *opaque); 479 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 480 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 481 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 482 uint8_t riscv_cpu_default_priority(int irq); 483 int riscv_cpu_mirq_pending(CPURISCVState *env); 484 int riscv_cpu_sirq_pending(CPURISCVState *env); 485 int riscv_cpu_vsirq_pending(CPURISCVState *env); 486 bool riscv_cpu_fp_enabled(CPURISCVState *env); 487 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 488 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 489 bool riscv_cpu_vector_enabled(CPURISCVState *env); 490 bool riscv_cpu_virt_enabled(CPURISCVState *env); 491 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 492 bool riscv_cpu_two_stage_lookup(int mmu_idx); 493 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 494 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 495 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 496 MMUAccessType access_type, int mmu_idx, 497 uintptr_t retaddr); 498 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 499 MMUAccessType access_type, int mmu_idx, 500 bool probe, uintptr_t retaddr); 501 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 502 vaddr addr, unsigned size, 503 MMUAccessType access_type, 504 int mmu_idx, MemTxAttrs attrs, 505 MemTxResult response, uintptr_t retaddr); 506 char *riscv_isa_string(RISCVCPU *cpu); 507 void riscv_cpu_list(void); 508 509 #define cpu_list riscv_cpu_list 510 #define cpu_mmu_index riscv_cpu_mmu_index 511 512 #ifndef CONFIG_USER_ONLY 513 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 514 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 515 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 516 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 517 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 518 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 519 void *arg); 520 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 521 int (*rmw_fn)(void *arg, 522 target_ulong reg, 523 target_ulong *val, 524 target_ulong new_val, 525 target_ulong write_mask), 526 void *rmw_fn_arg); 527 #endif 528 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 529 530 void riscv_translate_init(void); 531 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 532 uint32_t exception, uintptr_t pc); 533 534 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 535 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 536 537 #define TB_FLAGS_PRIV_MMU_MASK 3 538 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 539 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 540 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 541 542 #include "exec/cpu-all.h" 543 544 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 545 FIELD(TB_FLAGS, LMUL, 3, 3) 546 FIELD(TB_FLAGS, SEW, 6, 3) 547 /* Skip MSTATUS_VS (0x600) bits */ 548 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 549 FIELD(TB_FLAGS, VILL, 12, 1) 550 /* Skip MSTATUS_FS (0x6000) bits */ 551 /* Is a Hypervisor instruction load/store allowed? */ 552 FIELD(TB_FLAGS, HLSX, 15, 1) 553 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 554 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 555 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 556 FIELD(TB_FLAGS, XL, 20, 2) 557 /* If PointerMasking should be applied */ 558 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 559 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 560 561 #ifdef TARGET_RISCV32 562 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 563 #else 564 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 565 { 566 return env->misa_mxl; 567 } 568 #endif 569 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 570 571 #if defined(TARGET_RISCV32) 572 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 573 #else 574 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 575 { 576 RISCVMXL xl = env->misa_mxl; 577 #if !defined(CONFIG_USER_ONLY) 578 /* 579 * When emulating a 32-bit-only cpu, use RV32. 580 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 581 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 582 * back to RV64 for lower privs. 583 */ 584 if (xl != MXL_RV32) { 585 switch (env->priv) { 586 case PRV_M: 587 break; 588 case PRV_U: 589 xl = get_field(env->mstatus, MSTATUS64_UXL); 590 break; 591 default: /* PRV_S | PRV_H */ 592 xl = get_field(env->mstatus, MSTATUS64_SXL); 593 break; 594 } 595 } 596 #endif 597 return xl; 598 } 599 #endif 600 601 static inline int riscv_cpu_xlen(CPURISCVState *env) 602 { 603 return 16 << env->xl; 604 } 605 606 #ifdef TARGET_RISCV32 607 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 608 #else 609 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 610 { 611 #ifdef CONFIG_USER_ONLY 612 return env->misa_mxl; 613 #else 614 return get_field(env->mstatus, MSTATUS64_SXL); 615 #endif 616 } 617 #endif 618 619 /* 620 * Encode LMUL to lmul as follows: 621 * LMUL vlmul lmul 622 * 1 000 0 623 * 2 001 1 624 * 4 010 2 625 * 8 011 3 626 * - 100 - 627 * 1/8 101 -3 628 * 1/4 110 -2 629 * 1/2 111 -1 630 * 631 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 632 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 633 * => VLMAX = vlen >> (1 + 3 - (-3)) 634 * = 256 >> 7 635 * = 2 636 */ 637 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 638 { 639 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 640 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 641 return cpu->cfg.vlen >> (sew + 3 - lmul); 642 } 643 644 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 645 target_ulong *cs_base, uint32_t *pflags); 646 647 void riscv_cpu_update_mask(CPURISCVState *env); 648 649 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 650 target_ulong *ret_value, 651 target_ulong new_value, target_ulong write_mask); 652 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 653 target_ulong *ret_value, 654 target_ulong new_value, 655 target_ulong write_mask); 656 657 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 658 target_ulong val) 659 { 660 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 661 } 662 663 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 664 { 665 target_ulong val = 0; 666 riscv_csrrw(env, csrno, &val, 0, 0); 667 return val; 668 } 669 670 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 671 int csrno); 672 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 673 target_ulong *ret_value); 674 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 675 target_ulong new_value); 676 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 677 target_ulong *ret_value, 678 target_ulong new_value, 679 target_ulong write_mask); 680 681 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 682 Int128 *ret_value, 683 Int128 new_value, Int128 write_mask); 684 685 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 686 Int128 *ret_value); 687 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 688 Int128 new_value); 689 690 typedef struct { 691 const char *name; 692 riscv_csr_predicate_fn predicate; 693 riscv_csr_read_fn read; 694 riscv_csr_write_fn write; 695 riscv_csr_op_fn op; 696 riscv_csr_read128_fn read128; 697 riscv_csr_write128_fn write128; 698 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 699 uint32_t min_priv_ver; 700 } riscv_csr_operations; 701 702 /* CSR function table constants */ 703 enum { 704 CSR_TABLE_SIZE = 0x1000 705 }; 706 707 /* CSR function table */ 708 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 709 710 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 711 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 712 713 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 714 715 #endif /* RISCV_CPU_H */ 716