1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 29 #define TCG_GUEST_DEFAULT_MO 0 30 31 #define TYPE_RISCV_CPU "riscv-cpu" 32 33 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 34 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 35 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 36 37 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 38 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 39 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 40 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 41 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 42 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 43 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 44 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 45 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 46 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 47 48 #if defined(TARGET_RISCV32) 49 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 50 #elif defined(TARGET_RISCV64) 51 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 52 #endif 53 54 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 55 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 56 57 #define RV(x) ((target_ulong)1 << (x - 'A')) 58 59 #define RVI RV('I') 60 #define RVE RV('E') /* E and I are mutually exclusive */ 61 #define RVM RV('M') 62 #define RVA RV('A') 63 #define RVF RV('F') 64 #define RVD RV('D') 65 #define RVV RV('V') 66 #define RVC RV('C') 67 #define RVS RV('S') 68 #define RVU RV('U') 69 #define RVH RV('H') 70 71 /* S extension denotes that Supervisor mode exists, however it is possible 72 to have a core that support S mode but does not have an MMU and there 73 is currently no bit in misa to indicate whether an MMU exists or not 74 so a cpu features bitfield is required, likewise for optional PMP support */ 75 enum { 76 RISCV_FEATURE_MMU, 77 RISCV_FEATURE_PMP, 78 RISCV_FEATURE_EPMP, 79 RISCV_FEATURE_MISA 80 }; 81 82 #define PRIV_VERSION_1_10_0 0x00011000 83 #define PRIV_VERSION_1_11_0 0x00011100 84 85 #define VEXT_VERSION_0_07_1 0x00000701 86 87 enum { 88 TRANSLATE_SUCCESS, 89 TRANSLATE_FAIL, 90 TRANSLATE_PMP_FAIL, 91 TRANSLATE_G_STAGE_FAIL 92 }; 93 94 #define MMU_USER_IDX 3 95 96 #define MAX_RISCV_PMPS (16) 97 98 typedef struct CPURISCVState CPURISCVState; 99 100 #include "pmp.h" 101 102 #define RV_VLEN_MAX 256 103 104 FIELD(VTYPE, VLMUL, 0, 2) 105 FIELD(VTYPE, VSEW, 2, 3) 106 FIELD(VTYPE, VEDIV, 5, 2) 107 FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) 108 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 109 110 struct CPURISCVState { 111 target_ulong gpr[32]; 112 uint64_t fpr[32]; /* assume both F and D extensions */ 113 114 /* vector coprocessor state. */ 115 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 116 target_ulong vxrm; 117 target_ulong vxsat; 118 target_ulong vl; 119 target_ulong vstart; 120 target_ulong vtype; 121 122 target_ulong pc; 123 target_ulong load_res; 124 target_ulong load_val; 125 126 target_ulong frm; 127 128 target_ulong badaddr; 129 target_ulong guest_phys_fault_addr; 130 131 target_ulong priv_ver; 132 target_ulong vext_ver; 133 target_ulong misa; 134 target_ulong misa_mask; 135 136 uint32_t features; 137 138 #ifdef CONFIG_USER_ONLY 139 uint32_t elf_flags; 140 #endif 141 142 #ifndef CONFIG_USER_ONLY 143 target_ulong priv; 144 /* This contains QEMU specific information about the virt state. */ 145 target_ulong virt; 146 target_ulong resetvec; 147 148 target_ulong mhartid; 149 /* 150 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 151 * For RV64 this is a 64-bit mstatus. 152 */ 153 uint64_t mstatus; 154 155 target_ulong mip; 156 157 uint32_t miclaim; 158 159 target_ulong mie; 160 target_ulong mideleg; 161 162 target_ulong satp; /* since: priv-1.10.0 */ 163 target_ulong stval; 164 target_ulong medeleg; 165 166 target_ulong stvec; 167 target_ulong sepc; 168 target_ulong scause; 169 170 target_ulong mtvec; 171 target_ulong mepc; 172 target_ulong mcause; 173 target_ulong mtval; /* since: priv-1.10.0 */ 174 175 /* Hypervisor CSRs */ 176 target_ulong hstatus; 177 target_ulong hedeleg; 178 target_ulong hideleg; 179 target_ulong hcounteren; 180 target_ulong htval; 181 target_ulong htinst; 182 target_ulong hgatp; 183 uint64_t htimedelta; 184 185 /* Virtual CSRs */ 186 /* 187 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 188 * For RV64 this is a 64-bit vsstatus. 189 */ 190 uint64_t vsstatus; 191 target_ulong vstvec; 192 target_ulong vsscratch; 193 target_ulong vsepc; 194 target_ulong vscause; 195 target_ulong vstval; 196 target_ulong vsatp; 197 198 target_ulong mtval2; 199 target_ulong mtinst; 200 201 /* HS Backup CSRs */ 202 target_ulong stvec_hs; 203 target_ulong sscratch_hs; 204 target_ulong sepc_hs; 205 target_ulong scause_hs; 206 target_ulong stval_hs; 207 target_ulong satp_hs; 208 uint64_t mstatus_hs; 209 210 /* Signals whether the current exception occurred with two-stage address 211 translation active. */ 212 bool two_stage_lookup; 213 214 target_ulong scounteren; 215 target_ulong mcounteren; 216 217 target_ulong sscratch; 218 target_ulong mscratch; 219 220 /* temporary htif regs */ 221 uint64_t mfromhost; 222 uint64_t mtohost; 223 uint64_t timecmp; 224 225 /* physical memory protection */ 226 pmp_table_t pmp_state; 227 target_ulong mseccfg; 228 229 /* machine specific rdtime callback */ 230 uint64_t (*rdtime_fn)(uint32_t); 231 uint32_t rdtime_fn_arg; 232 233 /* True if in debugger mode. */ 234 bool debugger; 235 #endif 236 237 float_status fp_status; 238 239 /* Fields from here on are preserved across CPU reset. */ 240 QEMUTimer *timer; /* Internal timer */ 241 }; 242 243 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 244 RISCV_CPU) 245 246 /** 247 * RISCVCPUClass: 248 * @parent_realize: The parent class' realize handler. 249 * @parent_reset: The parent class' reset handler. 250 * 251 * A RISCV CPU model. 252 */ 253 struct RISCVCPUClass { 254 /*< private >*/ 255 CPUClass parent_class; 256 /*< public >*/ 257 DeviceRealize parent_realize; 258 DeviceReset parent_reset; 259 }; 260 261 /** 262 * RISCVCPU: 263 * @env: #CPURISCVState 264 * 265 * A RISCV CPU. 266 */ 267 struct RISCVCPU { 268 /*< private >*/ 269 CPUState parent_obj; 270 /*< public >*/ 271 CPUNegativeOffsetState neg; 272 CPURISCVState env; 273 274 char *dyn_csr_xml; 275 276 /* Configuration Settings */ 277 struct { 278 bool ext_i; 279 bool ext_e; 280 bool ext_g; 281 bool ext_m; 282 bool ext_a; 283 bool ext_f; 284 bool ext_d; 285 bool ext_c; 286 bool ext_s; 287 bool ext_u; 288 bool ext_h; 289 bool ext_v; 290 bool ext_counters; 291 bool ext_ifencei; 292 bool ext_icsr; 293 294 char *priv_spec; 295 char *user_spec; 296 char *vext_spec; 297 uint16_t vlen; 298 uint16_t elen; 299 bool mmu; 300 bool pmp; 301 bool epmp; 302 uint64_t resetvec; 303 } cfg; 304 }; 305 306 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 307 { 308 return (env->misa & ext) != 0; 309 } 310 311 static inline bool riscv_feature(CPURISCVState *env, int feature) 312 { 313 return env->features & (1ULL << feature); 314 } 315 316 #include "cpu_user.h" 317 #include "cpu_bits.h" 318 319 extern const char * const riscv_int_regnames[]; 320 extern const char * const riscv_fpr_regnames[]; 321 extern const char * const riscv_excp_names[]; 322 extern const char * const riscv_intr_names[]; 323 324 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 325 void riscv_cpu_do_interrupt(CPUState *cpu); 326 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 327 int cpuid, void *opaque); 328 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 329 int cpuid, void *opaque); 330 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 331 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 332 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 333 bool riscv_cpu_fp_enabled(CPURISCVState *env); 334 bool riscv_cpu_virt_enabled(CPURISCVState *env); 335 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 336 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); 337 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); 338 bool riscv_cpu_two_stage_lookup(int mmu_idx); 339 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 340 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 341 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 342 MMUAccessType access_type, int mmu_idx, 343 uintptr_t retaddr); 344 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 345 MMUAccessType access_type, int mmu_idx, 346 bool probe, uintptr_t retaddr); 347 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 348 vaddr addr, unsigned size, 349 MMUAccessType access_type, 350 int mmu_idx, MemTxAttrs attrs, 351 MemTxResult response, uintptr_t retaddr); 352 char *riscv_isa_string(RISCVCPU *cpu); 353 void riscv_cpu_list(void); 354 355 #define cpu_signal_handler riscv_cpu_signal_handler 356 #define cpu_list riscv_cpu_list 357 #define cpu_mmu_index riscv_cpu_mmu_index 358 359 #ifndef CONFIG_USER_ONLY 360 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 361 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 362 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 363 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 364 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 365 uint32_t arg); 366 #endif 367 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 368 369 void riscv_translate_init(void); 370 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); 371 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 372 uint32_t exception, uintptr_t pc); 373 374 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 375 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 376 377 #define TB_FLAGS_MMU_MASK 7 378 #define TB_FLAGS_PRIV_MMU_MASK 3 379 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 380 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 381 382 typedef CPURISCVState CPUArchState; 383 typedef RISCVCPU ArchCPU; 384 #include "exec/cpu-all.h" 385 386 FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) 387 FIELD(TB_FLAGS, LMUL, 3, 2) 388 FIELD(TB_FLAGS, SEW, 5, 3) 389 FIELD(TB_FLAGS, VILL, 8, 1) 390 /* Is a Hypervisor instruction load/store allowed? */ 391 FIELD(TB_FLAGS, HLSX, 9, 1) 392 393 bool riscv_cpu_is_32bit(CPURISCVState *env); 394 395 /* 396 * A simplification for VLMAX 397 * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) 398 * = (VLEN << LMUL) / (8 << SEW) 399 * = (VLEN << LMUL) >> (SEW + 3) 400 * = VLEN >> (SEW + 3 - LMUL) 401 */ 402 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 403 { 404 uint8_t sew, lmul; 405 406 sew = FIELD_EX64(vtype, VTYPE, VSEW); 407 lmul = FIELD_EX64(vtype, VTYPE, VLMUL); 408 return cpu->cfg.vlen >> (sew + 3 - lmul); 409 } 410 411 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 412 target_ulong *cs_base, uint32_t *pflags) 413 { 414 uint32_t flags = 0; 415 416 *pc = env->pc; 417 *cs_base = 0; 418 419 if (riscv_has_ext(env, RVV)) { 420 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 421 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); 422 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 423 FIELD_EX64(env->vtype, VTYPE, VILL)); 424 flags = FIELD_DP32(flags, TB_FLAGS, SEW, 425 FIELD_EX64(env->vtype, VTYPE, VSEW)); 426 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 427 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 428 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 429 } else { 430 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 431 } 432 433 #ifdef CONFIG_USER_ONLY 434 flags |= TB_FLAGS_MSTATUS_FS; 435 #else 436 flags |= cpu_mmu_index(env, 0); 437 if (riscv_cpu_fp_enabled(env)) { 438 flags |= env->mstatus & MSTATUS_FS; 439 } 440 441 if (riscv_has_ext(env, RVH)) { 442 if (env->priv == PRV_M || 443 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 444 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 445 get_field(env->hstatus, HSTATUS_HU))) { 446 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 447 } 448 } 449 #endif 450 451 *pflags = flags; 452 } 453 454 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 455 target_ulong *ret_value, 456 target_ulong new_value, target_ulong write_mask); 457 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 458 target_ulong *ret_value, 459 target_ulong new_value, 460 target_ulong write_mask); 461 462 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 463 target_ulong val) 464 { 465 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 466 } 467 468 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 469 { 470 target_ulong val = 0; 471 riscv_csrrw(env, csrno, &val, 0, 0); 472 return val; 473 } 474 475 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 476 int csrno); 477 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 478 target_ulong *ret_value); 479 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 480 target_ulong new_value); 481 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 482 target_ulong *ret_value, 483 target_ulong new_value, 484 target_ulong write_mask); 485 486 typedef struct { 487 const char *name; 488 riscv_csr_predicate_fn predicate; 489 riscv_csr_read_fn read; 490 riscv_csr_write_fn write; 491 riscv_csr_op_fn op; 492 } riscv_csr_operations; 493 494 /* CSR function table constants */ 495 enum { 496 CSR_TABLE_SIZE = 0x1000 497 }; 498 499 /* CSR function table */ 500 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 501 502 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 503 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 504 505 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 506 507 #endif /* RISCV_CPU_H */ 508