1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "tcg-op.h" 25 #include "trace.h" 26 27 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 28 { 29 #ifdef CONFIG_USER_ONLY 30 return 0; 31 #else 32 return env->priv; 33 #endif 34 } 35 36 #ifndef CONFIG_USER_ONLY 37 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 38 { 39 target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); 40 target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); 41 target_ulong pending = atomic_read(&env->mip) & env->mie; 42 target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie); 43 target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S && mstatus_sie); 44 target_ulong irqs = (pending & ~env->mideleg & -mie) | 45 (pending & env->mideleg & -sie); 46 47 if (irqs) { 48 return ctz64(irqs); /* since non-zero */ 49 } else { 50 return EXCP_NONE; /* indicates no pending interrupt */ 51 } 52 } 53 #endif 54 55 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 56 { 57 #if !defined(CONFIG_USER_ONLY) 58 if (interrupt_request & CPU_INTERRUPT_HARD) { 59 RISCVCPU *cpu = RISCV_CPU(cs); 60 CPURISCVState *env = &cpu->env; 61 int interruptno = riscv_cpu_local_irq_pending(env); 62 if (interruptno >= 0) { 63 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 64 riscv_cpu_do_interrupt(cs); 65 return true; 66 } 67 } 68 #endif 69 return false; 70 } 71 72 #if !defined(CONFIG_USER_ONLY) 73 74 /* Return true is floating point support is currently enabled */ 75 bool riscv_cpu_fp_enabled(CPURISCVState *env) 76 { 77 if (env->mstatus & MSTATUS_FS) { 78 return true; 79 } 80 81 return false; 82 } 83 84 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) 85 { 86 CPURISCVState *env = &cpu->env; 87 if (env->miclaim & interrupts) { 88 return -1; 89 } else { 90 env->miclaim |= interrupts; 91 return 0; 92 } 93 } 94 95 struct CpuAsyncInfo { 96 uint32_t new_mip; 97 }; 98 99 static void riscv_cpu_update_mip_irqs_async(CPUState *target_cpu_state, 100 run_on_cpu_data data) 101 { 102 struct CpuAsyncInfo *info = (struct CpuAsyncInfo *) data.host_ptr; 103 104 if (info->new_mip) { 105 cpu_interrupt(target_cpu_state, CPU_INTERRUPT_HARD); 106 } else { 107 cpu_reset_interrupt(target_cpu_state, CPU_INTERRUPT_HARD); 108 } 109 110 g_free(info); 111 } 112 113 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) 114 { 115 CPURISCVState *env = &cpu->env; 116 CPUState *cs = CPU(cpu); 117 struct CpuAsyncInfo *info; 118 uint32_t old, new, cmp = atomic_read(&env->mip); 119 120 do { 121 old = cmp; 122 new = (old & ~mask) | (value & mask); 123 cmp = atomic_cmpxchg(&env->mip, old, new); 124 } while (old != cmp); 125 126 info = g_new(struct CpuAsyncInfo, 1); 127 info->new_mip = new; 128 129 async_run_on_cpu(cs, riscv_cpu_update_mip_irqs_async, 130 RUN_ON_CPU_HOST_PTR(info)); 131 132 return old; 133 } 134 135 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 136 { 137 if (newpriv > PRV_M) { 138 g_assert_not_reached(); 139 } 140 if (newpriv == PRV_H) { 141 newpriv = PRV_U; 142 } 143 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 144 env->priv = newpriv; 145 146 /* 147 * Clear the load reservation - otherwise a reservation placed in one 148 * context/process can be used by another, resulting in an SC succeeding 149 * incorrectly. Version 2.2 of the ISA specification explicitly requires 150 * this behaviour, while later revisions say that the kernel "should" use 151 * an SC instruction to force the yielding of a load reservation on a 152 * preemptive context switch. As a result, do both. 153 */ 154 env->load_res = -1; 155 } 156 157 /* get_physical_address - get the physical address for this virtual address 158 * 159 * Do a page table walk to obtain the physical address corresponding to a 160 * virtual address. Returns 0 if the translation was successful 161 * 162 * Adapted from Spike's mmu_t::translate and mmu_t::walk 163 * 164 */ 165 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 166 int *prot, target_ulong addr, 167 int access_type, int mmu_idx) 168 { 169 /* NOTE: the env->pc value visible here will not be 170 * correct, but the value visible to the exception handler 171 * (riscv_cpu_do_interrupt) is correct */ 172 MemTxResult res; 173 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 174 int mode = mmu_idx; 175 176 if (mode == PRV_M && access_type != MMU_INST_FETCH) { 177 if (get_field(env->mstatus, MSTATUS_MPRV)) { 178 mode = get_field(env->mstatus, MSTATUS_MPP); 179 } 180 } 181 182 if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { 183 *physical = addr; 184 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 185 return TRANSLATE_SUCCESS; 186 } 187 188 *prot = 0; 189 190 hwaddr base; 191 int levels, ptidxbits, ptesize, vm, sum; 192 int mxr = get_field(env->mstatus, MSTATUS_MXR); 193 194 if (env->priv_ver >= PRIV_VERSION_1_10_0) { 195 base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; 196 sum = get_field(env->mstatus, MSTATUS_SUM); 197 vm = get_field(env->satp, SATP_MODE); 198 switch (vm) { 199 case VM_1_10_SV32: 200 levels = 2; ptidxbits = 10; ptesize = 4; break; 201 case VM_1_10_SV39: 202 levels = 3; ptidxbits = 9; ptesize = 8; break; 203 case VM_1_10_SV48: 204 levels = 4; ptidxbits = 9; ptesize = 8; break; 205 case VM_1_10_SV57: 206 levels = 5; ptidxbits = 9; ptesize = 8; break; 207 case VM_1_10_MBARE: 208 *physical = addr; 209 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 210 return TRANSLATE_SUCCESS; 211 default: 212 g_assert_not_reached(); 213 } 214 } else { 215 base = (hwaddr)(env->sptbr) << PGSHIFT; 216 sum = !get_field(env->mstatus, MSTATUS_PUM); 217 vm = get_field(env->mstatus, MSTATUS_VM); 218 switch (vm) { 219 case VM_1_09_SV32: 220 levels = 2; ptidxbits = 10; ptesize = 4; break; 221 case VM_1_09_SV39: 222 levels = 3; ptidxbits = 9; ptesize = 8; break; 223 case VM_1_09_SV48: 224 levels = 4; ptidxbits = 9; ptesize = 8; break; 225 case VM_1_09_MBARE: 226 *physical = addr; 227 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 228 return TRANSLATE_SUCCESS; 229 default: 230 g_assert_not_reached(); 231 } 232 } 233 234 CPUState *cs = env_cpu(env); 235 int va_bits = PGSHIFT + levels * ptidxbits; 236 target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 237 target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask; 238 if (masked_msbs != 0 && masked_msbs != mask) { 239 return TRANSLATE_FAIL; 240 } 241 242 int ptshift = (levels - 1) * ptidxbits; 243 int i; 244 245 #if !TCG_OVERSIZED_GUEST 246 restart: 247 #endif 248 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 249 target_ulong idx = (addr >> (PGSHIFT + ptshift)) & 250 ((1 << ptidxbits) - 1); 251 252 /* check that physical address of PTE is legal */ 253 hwaddr pte_addr = base + idx * ptesize; 254 255 if (riscv_feature(env, RISCV_FEATURE_PMP) && 256 !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), 257 1 << MMU_DATA_LOAD, PRV_S)) { 258 return TRANSLATE_PMP_FAIL; 259 } 260 261 #if defined(TARGET_RISCV32) 262 target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 263 #elif defined(TARGET_RISCV64) 264 target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 265 #endif 266 if (res != MEMTX_OK) { 267 return TRANSLATE_FAIL; 268 } 269 270 hwaddr ppn = pte >> PTE_PPN_SHIFT; 271 272 if (!(pte & PTE_V)) { 273 /* Invalid PTE */ 274 return TRANSLATE_FAIL; 275 } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { 276 /* Inner PTE, continue walking */ 277 base = ppn << PGSHIFT; 278 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { 279 /* Reserved leaf PTE flags: PTE_W */ 280 return TRANSLATE_FAIL; 281 } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { 282 /* Reserved leaf PTE flags: PTE_W + PTE_X */ 283 return TRANSLATE_FAIL; 284 } else if ((pte & PTE_U) && ((mode != PRV_U) && 285 (!sum || access_type == MMU_INST_FETCH))) { 286 /* User PTE flags when not U mode and mstatus.SUM is not set, 287 or the access type is an instruction fetch */ 288 return TRANSLATE_FAIL; 289 } else if (!(pte & PTE_U) && (mode != PRV_S)) { 290 /* Supervisor PTE flags when not S mode */ 291 return TRANSLATE_FAIL; 292 } else if (ppn & ((1ULL << ptshift) - 1)) { 293 /* Misaligned PPN */ 294 return TRANSLATE_FAIL; 295 } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || 296 ((pte & PTE_X) && mxr))) { 297 /* Read access check failed */ 298 return TRANSLATE_FAIL; 299 } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { 300 /* Write access check failed */ 301 return TRANSLATE_FAIL; 302 } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { 303 /* Fetch access check failed */ 304 return TRANSLATE_FAIL; 305 } else { 306 /* if necessary, set accessed and dirty bits. */ 307 target_ulong updated_pte = pte | PTE_A | 308 (access_type == MMU_DATA_STORE ? PTE_D : 0); 309 310 /* Page table updates need to be atomic with MTTCG enabled */ 311 if (updated_pte != pte) { 312 /* 313 * - if accessed or dirty bits need updating, and the PTE is 314 * in RAM, then we do so atomically with a compare and swap. 315 * - if the PTE is in IO space or ROM, then it can't be updated 316 * and we return TRANSLATE_FAIL. 317 * - if the PTE changed by the time we went to update it, then 318 * it is no longer valid and we must re-walk the page table. 319 */ 320 MemoryRegion *mr; 321 hwaddr l = sizeof(target_ulong), addr1; 322 mr = address_space_translate(cs->as, pte_addr, 323 &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); 324 if (memory_region_is_ram(mr)) { 325 target_ulong *pte_pa = 326 qemu_map_ram_ptr(mr->ram_block, addr1); 327 #if TCG_OVERSIZED_GUEST 328 /* MTTCG is not enabled on oversized TCG guests so 329 * page table updates do not need to be atomic */ 330 *pte_pa = pte = updated_pte; 331 #else 332 target_ulong old_pte = 333 atomic_cmpxchg(pte_pa, pte, updated_pte); 334 if (old_pte != pte) { 335 goto restart; 336 } else { 337 pte = updated_pte; 338 } 339 #endif 340 } else { 341 /* misconfigured PTE in ROM (AD bits are not preset) or 342 * PTE is in IO space and can't be updated atomically */ 343 return TRANSLATE_FAIL; 344 } 345 } 346 347 /* for superpage mappings, make a fake leaf PTE for the TLB's 348 benefit. */ 349 target_ulong vpn = addr >> PGSHIFT; 350 *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; 351 352 /* set permissions on the TLB entry */ 353 if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { 354 *prot |= PAGE_READ; 355 } 356 if ((pte & PTE_X)) { 357 *prot |= PAGE_EXEC; 358 } 359 /* add write permission on stores or if the page is already dirty, 360 so that we TLB miss on later writes to update the dirty bit */ 361 if ((pte & PTE_W) && 362 (access_type == MMU_DATA_STORE || (pte & PTE_D))) { 363 *prot |= PAGE_WRITE; 364 } 365 return TRANSLATE_SUCCESS; 366 } 367 } 368 return TRANSLATE_FAIL; 369 } 370 371 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 372 MMUAccessType access_type, bool pmp_violation) 373 { 374 CPUState *cs = env_cpu(env); 375 int page_fault_exceptions = 376 (env->priv_ver >= PRIV_VERSION_1_10_0) && 377 get_field(env->satp, SATP_MODE) != VM_1_10_MBARE && 378 !pmp_violation; 379 switch (access_type) { 380 case MMU_INST_FETCH: 381 cs->exception_index = page_fault_exceptions ? 382 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 383 break; 384 case MMU_DATA_LOAD: 385 cs->exception_index = page_fault_exceptions ? 386 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 387 break; 388 case MMU_DATA_STORE: 389 cs->exception_index = page_fault_exceptions ? 390 RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 391 break; 392 default: 393 g_assert_not_reached(); 394 } 395 env->badaddr = address; 396 } 397 398 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 399 { 400 RISCVCPU *cpu = RISCV_CPU(cs); 401 hwaddr phys_addr; 402 int prot; 403 int mmu_idx = cpu_mmu_index(&cpu->env, false); 404 405 if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) { 406 return -1; 407 } 408 return phys_addr; 409 } 410 411 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 412 vaddr addr, unsigned size, 413 MMUAccessType access_type, 414 int mmu_idx, MemTxAttrs attrs, 415 MemTxResult response, uintptr_t retaddr) 416 { 417 RISCVCPU *cpu = RISCV_CPU(cs); 418 CPURISCVState *env = &cpu->env; 419 420 if (access_type == MMU_DATA_STORE) { 421 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 422 } else { 423 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 424 } 425 426 env->badaddr = addr; 427 riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); 428 } 429 430 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 431 MMUAccessType access_type, int mmu_idx, 432 uintptr_t retaddr) 433 { 434 RISCVCPU *cpu = RISCV_CPU(cs); 435 CPURISCVState *env = &cpu->env; 436 switch (access_type) { 437 case MMU_INST_FETCH: 438 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 439 break; 440 case MMU_DATA_LOAD: 441 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 442 break; 443 case MMU_DATA_STORE: 444 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 445 break; 446 default: 447 g_assert_not_reached(); 448 } 449 env->badaddr = addr; 450 riscv_raise_exception(env, cs->exception_index, retaddr); 451 } 452 #endif 453 454 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 455 MMUAccessType access_type, int mmu_idx, 456 bool probe, uintptr_t retaddr) 457 { 458 RISCVCPU *cpu = RISCV_CPU(cs); 459 CPURISCVState *env = &cpu->env; 460 #ifndef CONFIG_USER_ONLY 461 hwaddr pa = 0; 462 int prot; 463 bool pmp_violation = false; 464 int ret = TRANSLATE_FAIL; 465 int mode = mmu_idx; 466 467 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 468 __func__, address, access_type, mmu_idx); 469 470 ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx); 471 472 if (mode == PRV_M && access_type != MMU_INST_FETCH) { 473 if (get_field(env->mstatus, MSTATUS_MPRV)) { 474 mode = get_field(env->mstatus, MSTATUS_MPP); 475 } 476 } 477 478 qemu_log_mask(CPU_LOG_MMU, 479 "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx 480 " prot %d\n", __func__, address, ret, pa, prot); 481 482 if (riscv_feature(env, RISCV_FEATURE_PMP) && 483 (ret == TRANSLATE_SUCCESS) && 484 !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { 485 ret = TRANSLATE_PMP_FAIL; 486 } 487 if (ret == TRANSLATE_PMP_FAIL) { 488 pmp_violation = true; 489 } 490 if (ret == TRANSLATE_SUCCESS) { 491 tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, 492 prot, mmu_idx, TARGET_PAGE_SIZE); 493 return true; 494 } else if (probe) { 495 return false; 496 } else { 497 raise_mmu_exception(env, address, access_type, pmp_violation); 498 riscv_raise_exception(env, cs->exception_index, retaddr); 499 } 500 #else 501 switch (access_type) { 502 case MMU_INST_FETCH: 503 cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; 504 break; 505 case MMU_DATA_LOAD: 506 cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; 507 break; 508 case MMU_DATA_STORE: 509 cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; 510 break; 511 default: 512 g_assert_not_reached(); 513 } 514 env->badaddr = address; 515 cpu_loop_exit_restore(cs, retaddr); 516 #endif 517 } 518 519 /* 520 * Handle Traps 521 * 522 * Adapted from Spike's processor_t::take_trap. 523 * 524 */ 525 void riscv_cpu_do_interrupt(CPUState *cs) 526 { 527 #if !defined(CONFIG_USER_ONLY) 528 529 RISCVCPU *cpu = RISCV_CPU(cs); 530 CPURISCVState *env = &cpu->env; 531 532 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 533 * so we mask off the MSB and separate into trap type and cause. 534 */ 535 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 536 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 537 target_ulong deleg = async ? env->mideleg : env->medeleg; 538 target_ulong tval = 0; 539 540 static const int ecall_cause_map[] = { 541 [PRV_U] = RISCV_EXCP_U_ECALL, 542 [PRV_S] = RISCV_EXCP_S_ECALL, 543 [PRV_H] = RISCV_EXCP_H_ECALL, 544 [PRV_M] = RISCV_EXCP_M_ECALL 545 }; 546 547 if (!async) { 548 /* set tval to badaddr for traps with address information */ 549 switch (cause) { 550 case RISCV_EXCP_INST_ADDR_MIS: 551 case RISCV_EXCP_INST_ACCESS_FAULT: 552 case RISCV_EXCP_LOAD_ADDR_MIS: 553 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 554 case RISCV_EXCP_LOAD_ACCESS_FAULT: 555 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 556 case RISCV_EXCP_INST_PAGE_FAULT: 557 case RISCV_EXCP_LOAD_PAGE_FAULT: 558 case RISCV_EXCP_STORE_PAGE_FAULT: 559 tval = env->badaddr; 560 break; 561 default: 562 break; 563 } 564 /* ecall is dispatched as one cause so translate based on mode */ 565 if (cause == RISCV_EXCP_U_ECALL) { 566 assert(env->priv <= 3); 567 cause = ecall_cause_map[env->priv]; 568 } 569 } 570 571 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 16 ? 572 (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); 573 574 if (env->priv <= PRV_S && 575 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 576 /* handle the trap in S-mode */ 577 target_ulong s = env->mstatus; 578 s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? 579 get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv)); 580 s = set_field(s, MSTATUS_SPP, env->priv); 581 s = set_field(s, MSTATUS_SIE, 0); 582 env->mstatus = s; 583 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 584 env->sepc = env->pc; 585 env->sbadaddr = tval; 586 env->pc = (env->stvec >> 2 << 2) + 587 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 588 riscv_cpu_set_mode(env, PRV_S); 589 } else { 590 /* handle the trap in M-mode */ 591 target_ulong s = env->mstatus; 592 s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? 593 get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv)); 594 s = set_field(s, MSTATUS_MPP, env->priv); 595 s = set_field(s, MSTATUS_MIE, 0); 596 env->mstatus = s; 597 env->mcause = cause | ~(((target_ulong)-1) >> async); 598 env->mepc = env->pc; 599 env->mbadaddr = tval; 600 env->pc = (env->mtvec >> 2 << 2) + 601 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 602 riscv_cpu_set_mode(env, PRV_M); 603 } 604 605 /* NOTE: it is not necessary to yield load reservations here. It is only 606 * necessary for an SC from "another hart" to cause a load reservation 607 * to be yielded. Refer to the memory consistency model section of the 608 * RISC-V ISA Specification. 609 */ 610 611 #endif 612 cs->exception_index = EXCP_NONE; /* mark handled to qemu */ 613 } 614