1 /* 2 * RISC-V CPU helpers for qemu. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/main-loop.h" 23 #include "cpu.h" 24 #include "internals.h" 25 #include "pmu.h" 26 #include "exec/exec-all.h" 27 #include "instmap.h" 28 #include "tcg/tcg-op.h" 29 #include "trace.h" 30 #include "semihosting/common-semi.h" 31 #include "sysemu/cpu-timers.h" 32 #include "cpu_bits.h" 33 #include "debug.h" 34 #include "tcg/oversized-guest.h" 35 36 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) 37 { 38 #ifdef CONFIG_USER_ONLY 39 return 0; 40 #else 41 bool virt = env->virt_enabled; 42 int mode = env->priv; 43 44 /* All priv -> mmu_idx mapping are here */ 45 if (!ifetch) { 46 uint64_t status = env->mstatus; 47 48 if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) { 49 mode = get_field(env->mstatus, MSTATUS_MPP); 50 virt = get_field(env->mstatus, MSTATUS_MPV); 51 if (virt) { 52 status = env->vsstatus; 53 } 54 } 55 if (mode == PRV_S && get_field(status, MSTATUS_SUM)) { 56 mode = MMUIdx_S_SUM; 57 } 58 } 59 60 return mode | (virt ? MMU_2STAGE_BIT : 0); 61 #endif 62 } 63 64 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 65 target_ulong *cs_base, uint32_t *pflags) 66 { 67 CPUState *cs = env_cpu(env); 68 RISCVCPU *cpu = RISCV_CPU(cs); 69 RISCVExtStatus fs, vs; 70 uint32_t flags = 0; 71 72 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; 73 *cs_base = 0; 74 75 if (cpu->cfg.ext_zve32f) { 76 /* 77 * If env->vl equals to VLMAX, we can use generic vector operation 78 * expanders (GVEC) to accerlate the vector operations. 79 * However, as LMUL could be a fractional number. The maximum 80 * vector size can be operated might be less than 8 bytes, 81 * which is not supported by GVEC. So we set vl_eq_vlmax flag to true 82 * only when maxsz >= 8 bytes. 83 */ 84 uint32_t vlmax = vext_get_vlmax(cpu, env->vtype); 85 uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); 86 uint32_t maxsz = vlmax << sew; 87 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && 88 (maxsz >= 8); 89 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); 90 flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); 91 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 92 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 93 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 94 flags = FIELD_DP32(flags, TB_FLAGS, VTA, 95 FIELD_EX64(env->vtype, VTYPE, VTA)); 96 flags = FIELD_DP32(flags, TB_FLAGS, VMA, 97 FIELD_EX64(env->vtype, VTYPE, VMA)); 98 flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0); 99 } else { 100 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 101 } 102 103 #ifdef CONFIG_USER_ONLY 104 fs = EXT_STATUS_DIRTY; 105 vs = EXT_STATUS_DIRTY; 106 #else 107 flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); 108 109 flags |= cpu_mmu_index(env, 0); 110 fs = get_field(env->mstatus, MSTATUS_FS); 111 vs = get_field(env->mstatus, MSTATUS_VS); 112 113 if (env->virt_enabled) { 114 flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); 115 /* 116 * Merge DISABLED and !DIRTY states using MIN. 117 * We will set both fields when dirtying. 118 */ 119 fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); 120 vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); 121 } 122 123 /* With Zfinx, floating point is enabled/disabled by Smstateen. */ 124 if (!riscv_has_ext(env, RVF)) { 125 fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) 126 ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; 127 } 128 129 if (cpu->cfg.debug && !icount_enabled()) { 130 flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); 131 } 132 #endif 133 134 flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); 135 flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); 136 flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); 137 if (env->cur_pmmask != 0) { 138 flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); 139 } 140 if (env->cur_pmbase != 0) { 141 flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); 142 } 143 144 *pflags = flags; 145 } 146 147 void riscv_cpu_update_mask(CPURISCVState *env) 148 { 149 target_ulong mask = 0, base = 0; 150 /* 151 * TODO: Current RVJ spec does not specify 152 * how the extension interacts with XLEN. 153 */ 154 #ifndef CONFIG_USER_ONLY 155 if (riscv_has_ext(env, RVJ)) { 156 switch (env->priv) { 157 case PRV_M: 158 if (env->mmte & M_PM_ENABLE) { 159 mask = env->mpmmask; 160 base = env->mpmbase; 161 } 162 break; 163 case PRV_S: 164 if (env->mmte & S_PM_ENABLE) { 165 mask = env->spmmask; 166 base = env->spmbase; 167 } 168 break; 169 case PRV_U: 170 if (env->mmte & U_PM_ENABLE) { 171 mask = env->upmmask; 172 base = env->upmbase; 173 } 174 break; 175 default: 176 g_assert_not_reached(); 177 } 178 } 179 #endif 180 if (env->xl == MXL_RV32) { 181 env->cur_pmmask = mask & UINT32_MAX; 182 env->cur_pmbase = base & UINT32_MAX; 183 } else { 184 env->cur_pmmask = mask; 185 env->cur_pmbase = base; 186 } 187 } 188 189 #ifndef CONFIG_USER_ONLY 190 191 /* 192 * The HS-mode is allowed to configure priority only for the 193 * following VS-mode local interrupts: 194 * 195 * 0 (Reserved interrupt, reads as zero) 196 * 1 Supervisor software interrupt 197 * 4 (Reserved interrupt, reads as zero) 198 * 5 Supervisor timer interrupt 199 * 8 (Reserved interrupt, reads as zero) 200 * 13 (Reserved interrupt) 201 * 14 " 202 * 15 " 203 * 16 " 204 * 17 " 205 * 18 " 206 * 19 " 207 * 20 " 208 * 21 " 209 * 22 " 210 * 23 " 211 */ 212 213 static const int hviprio_index2irq[] = { 214 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; 215 static const int hviprio_index2rdzero[] = { 216 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; 217 218 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) 219 { 220 if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <= index) { 221 return -EINVAL; 222 } 223 224 if (out_irq) { 225 *out_irq = hviprio_index2irq[index]; 226 } 227 228 if (out_rdzero) { 229 *out_rdzero = hviprio_index2rdzero[index]; 230 } 231 232 return 0; 233 } 234 235 /* 236 * Default priorities of local interrupts are defined in the 237 * RISC-V Advanced Interrupt Architecture specification. 238 * 239 * ---------------------------------------------------------------- 240 * Default | 241 * Priority | Major Interrupt Numbers 242 * ---------------------------------------------------------------- 243 * Highest | 47, 23, 46, 45, 22, 44, 244 * | 43, 21, 42, 41, 20, 40 245 * | 246 * | 11 (0b), 3 (03), 7 (07) 247 * | 9 (09), 1 (01), 5 (05) 248 * | 12 (0c) 249 * | 10 (0a), 2 (02), 6 (06) 250 * | 251 * | 39, 19, 38, 37, 18, 36, 252 * Lowest | 35, 17, 34, 33, 16, 32 253 * ---------------------------------------------------------------- 254 */ 255 static const uint8_t default_iprio[64] = { 256 /* Custom interrupts 48 to 63 */ 257 [63] = IPRIO_MMAXIPRIO, 258 [62] = IPRIO_MMAXIPRIO, 259 [61] = IPRIO_MMAXIPRIO, 260 [60] = IPRIO_MMAXIPRIO, 261 [59] = IPRIO_MMAXIPRIO, 262 [58] = IPRIO_MMAXIPRIO, 263 [57] = IPRIO_MMAXIPRIO, 264 [56] = IPRIO_MMAXIPRIO, 265 [55] = IPRIO_MMAXIPRIO, 266 [54] = IPRIO_MMAXIPRIO, 267 [53] = IPRIO_MMAXIPRIO, 268 [52] = IPRIO_MMAXIPRIO, 269 [51] = IPRIO_MMAXIPRIO, 270 [50] = IPRIO_MMAXIPRIO, 271 [49] = IPRIO_MMAXIPRIO, 272 [48] = IPRIO_MMAXIPRIO, 273 274 /* Custom interrupts 24 to 31 */ 275 [31] = IPRIO_MMAXIPRIO, 276 [30] = IPRIO_MMAXIPRIO, 277 [29] = IPRIO_MMAXIPRIO, 278 [28] = IPRIO_MMAXIPRIO, 279 [27] = IPRIO_MMAXIPRIO, 280 [26] = IPRIO_MMAXIPRIO, 281 [25] = IPRIO_MMAXIPRIO, 282 [24] = IPRIO_MMAXIPRIO, 283 284 [47] = IPRIO_DEFAULT_UPPER, 285 [23] = IPRIO_DEFAULT_UPPER + 1, 286 [46] = IPRIO_DEFAULT_UPPER + 2, 287 [45] = IPRIO_DEFAULT_UPPER + 3, 288 [22] = IPRIO_DEFAULT_UPPER + 4, 289 [44] = IPRIO_DEFAULT_UPPER + 5, 290 291 [43] = IPRIO_DEFAULT_UPPER + 6, 292 [21] = IPRIO_DEFAULT_UPPER + 7, 293 [42] = IPRIO_DEFAULT_UPPER + 8, 294 [41] = IPRIO_DEFAULT_UPPER + 9, 295 [20] = IPRIO_DEFAULT_UPPER + 10, 296 [40] = IPRIO_DEFAULT_UPPER + 11, 297 298 [11] = IPRIO_DEFAULT_M, 299 [3] = IPRIO_DEFAULT_M + 1, 300 [7] = IPRIO_DEFAULT_M + 2, 301 302 [9] = IPRIO_DEFAULT_S, 303 [1] = IPRIO_DEFAULT_S + 1, 304 [5] = IPRIO_DEFAULT_S + 2, 305 306 [12] = IPRIO_DEFAULT_SGEXT, 307 308 [10] = IPRIO_DEFAULT_VS, 309 [2] = IPRIO_DEFAULT_VS + 1, 310 [6] = IPRIO_DEFAULT_VS + 2, 311 312 [39] = IPRIO_DEFAULT_LOWER, 313 [19] = IPRIO_DEFAULT_LOWER + 1, 314 [38] = IPRIO_DEFAULT_LOWER + 2, 315 [37] = IPRIO_DEFAULT_LOWER + 3, 316 [18] = IPRIO_DEFAULT_LOWER + 4, 317 [36] = IPRIO_DEFAULT_LOWER + 5, 318 319 [35] = IPRIO_DEFAULT_LOWER + 6, 320 [17] = IPRIO_DEFAULT_LOWER + 7, 321 [34] = IPRIO_DEFAULT_LOWER + 8, 322 [33] = IPRIO_DEFAULT_LOWER + 9, 323 [16] = IPRIO_DEFAULT_LOWER + 10, 324 [32] = IPRIO_DEFAULT_LOWER + 11, 325 }; 326 327 uint8_t riscv_cpu_default_priority(int irq) 328 { 329 if (irq < 0 || irq > 63) { 330 return IPRIO_MMAXIPRIO; 331 } 332 333 return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; 334 }; 335 336 static int riscv_cpu_pending_to_irq(CPURISCVState *env, 337 int extirq, unsigned int extirq_def_prio, 338 uint64_t pending, uint8_t *iprio) 339 { 340 int irq, best_irq = RISCV_EXCP_NONE; 341 unsigned int prio, best_prio = UINT_MAX; 342 343 if (!pending) { 344 return RISCV_EXCP_NONE; 345 } 346 347 irq = ctz64(pending); 348 if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : 349 riscv_cpu_cfg(env)->ext_ssaia)) { 350 return irq; 351 } 352 353 pending = pending >> irq; 354 while (pending) { 355 prio = iprio[irq]; 356 if (!prio) { 357 if (irq == extirq) { 358 prio = extirq_def_prio; 359 } else { 360 prio = (riscv_cpu_default_priority(irq) < extirq_def_prio) ? 361 1 : IPRIO_MMAXIPRIO; 362 } 363 } 364 if ((pending & 0x1) && (prio <= best_prio)) { 365 best_irq = irq; 366 best_prio = prio; 367 } 368 irq++; 369 pending = pending >> 1; 370 } 371 372 return best_irq; 373 } 374 375 uint64_t riscv_cpu_all_pending(CPURISCVState *env) 376 { 377 uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); 378 uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 379 uint64_t vstip = (env->vstime_irq) ? MIP_VSTIP : 0; 380 381 return (env->mip | vsgein | vstip) & env->mie; 382 } 383 384 int riscv_cpu_mirq_pending(CPURISCVState *env) 385 { 386 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & 387 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 388 389 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 390 irqs, env->miprio); 391 } 392 393 int riscv_cpu_sirq_pending(CPURISCVState *env) 394 { 395 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 396 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 397 398 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 399 irqs, env->siprio); 400 } 401 402 int riscv_cpu_vsirq_pending(CPURISCVState *env) 403 { 404 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & 405 (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); 406 407 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 408 irqs >> 1, env->hviprio); 409 } 410 411 static int riscv_cpu_local_irq_pending(CPURISCVState *env) 412 { 413 int virq; 414 uint64_t irqs, pending, mie, hsie, vsie; 415 416 /* Determine interrupt enable state of all privilege modes */ 417 if (env->virt_enabled) { 418 mie = 1; 419 hsie = 1; 420 vsie = (env->priv < PRV_S) || 421 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 422 } else { 423 mie = (env->priv < PRV_M) || 424 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); 425 hsie = (env->priv < PRV_S) || 426 (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_SIE)); 427 vsie = 0; 428 } 429 430 /* Determine all pending interrupts */ 431 pending = riscv_cpu_all_pending(env); 432 433 /* Check M-mode interrupts */ 434 irqs = pending & ~env->mideleg & -mie; 435 if (irqs) { 436 return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, 437 irqs, env->miprio); 438 } 439 440 /* Check HS-mode interrupts */ 441 irqs = pending & env->mideleg & ~env->hideleg & -hsie; 442 if (irqs) { 443 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 444 irqs, env->siprio); 445 } 446 447 /* Check VS-mode interrupts */ 448 irqs = pending & env->mideleg & env->hideleg & -vsie; 449 if (irqs) { 450 virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, 451 irqs >> 1, env->hviprio); 452 return (virq <= 0) ? virq : virq + 1; 453 } 454 455 /* Indicate no pending interrupt */ 456 return RISCV_EXCP_NONE; 457 } 458 459 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 460 { 461 if (interrupt_request & CPU_INTERRUPT_HARD) { 462 RISCVCPU *cpu = RISCV_CPU(cs); 463 CPURISCVState *env = &cpu->env; 464 int interruptno = riscv_cpu_local_irq_pending(env); 465 if (interruptno >= 0) { 466 cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; 467 riscv_cpu_do_interrupt(cs); 468 return true; 469 } 470 } 471 return false; 472 } 473 474 /* Return true is floating point support is currently enabled */ 475 bool riscv_cpu_fp_enabled(CPURISCVState *env) 476 { 477 if (env->mstatus & MSTATUS_FS) { 478 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { 479 return false; 480 } 481 return true; 482 } 483 484 return false; 485 } 486 487 /* Return true is vector support is currently enabled */ 488 bool riscv_cpu_vector_enabled(CPURISCVState *env) 489 { 490 if (env->mstatus & MSTATUS_VS) { 491 if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { 492 return false; 493 } 494 return true; 495 } 496 497 return false; 498 } 499 500 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 501 { 502 uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | 503 MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | 504 MSTATUS64_UXL | MSTATUS_VS; 505 506 if (riscv_has_ext(env, RVF)) { 507 mstatus_mask |= MSTATUS_FS; 508 } 509 bool current_virt = env->virt_enabled; 510 511 g_assert(riscv_has_ext(env, RVH)); 512 513 if (current_virt) { 514 /* Current V=1 and we are about to change to V=0 */ 515 env->vsstatus = env->mstatus & mstatus_mask; 516 env->mstatus &= ~mstatus_mask; 517 env->mstatus |= env->mstatus_hs; 518 519 env->vstvec = env->stvec; 520 env->stvec = env->stvec_hs; 521 522 env->vsscratch = env->sscratch; 523 env->sscratch = env->sscratch_hs; 524 525 env->vsepc = env->sepc; 526 env->sepc = env->sepc_hs; 527 528 env->vscause = env->scause; 529 env->scause = env->scause_hs; 530 531 env->vstval = env->stval; 532 env->stval = env->stval_hs; 533 534 env->vsatp = env->satp; 535 env->satp = env->satp_hs; 536 } else { 537 /* Current V=0 and we are about to change to V=1 */ 538 env->mstatus_hs = env->mstatus & mstatus_mask; 539 env->mstatus &= ~mstatus_mask; 540 env->mstatus |= env->vsstatus; 541 542 env->stvec_hs = env->stvec; 543 env->stvec = env->vstvec; 544 545 env->sscratch_hs = env->sscratch; 546 env->sscratch = env->vsscratch; 547 548 env->sepc_hs = env->sepc; 549 env->sepc = env->vsepc; 550 551 env->scause_hs = env->scause; 552 env->scause = env->vscause; 553 554 env->stval_hs = env->stval; 555 env->stval = env->vstval; 556 557 env->satp_hs = env->satp; 558 env->satp = env->vsatp; 559 } 560 } 561 562 target_ulong riscv_cpu_get_geilen(CPURISCVState *env) 563 { 564 if (!riscv_has_ext(env, RVH)) { 565 return 0; 566 } 567 568 return env->geilen; 569 } 570 571 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) 572 { 573 if (!riscv_has_ext(env, RVH)) { 574 return; 575 } 576 577 if (geilen > (TARGET_LONG_BITS - 1)) { 578 return; 579 } 580 581 env->geilen = geilen; 582 } 583 584 /* This function can only be called to set virt when RVH is enabled */ 585 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) 586 { 587 /* Flush the TLB on all virt mode changes. */ 588 if (env->virt_enabled != enable) { 589 tlb_flush(env_cpu(env)); 590 } 591 592 env->virt_enabled = enable; 593 594 if (enable) { 595 /* 596 * The guest external interrupts from an interrupt controller are 597 * delivered only when the Guest/VM is running (i.e. V=1). This means 598 * any guest external interrupt which is triggered while the Guest/VM 599 * is not running (i.e. V=0) will be missed on QEMU resulting in guest 600 * with sluggish response to serial console input and other I/O events. 601 * 602 * To solve this, we check and inject interrupt after setting V=1. 603 */ 604 riscv_cpu_update_mip(env, 0, 0); 605 } 606 } 607 608 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) 609 { 610 CPURISCVState *env = &cpu->env; 611 if (env->miclaim & interrupts) { 612 return -1; 613 } else { 614 env->miclaim |= interrupts; 615 return 0; 616 } 617 } 618 619 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 620 uint64_t value) 621 { 622 CPUState *cs = env_cpu(env); 623 uint64_t gein, vsgein = 0, vstip = 0, old = env->mip; 624 625 if (env->virt_enabled) { 626 gein = get_field(env->hstatus, HSTATUS_VGEIN); 627 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 628 } 629 630 vstip = env->vstime_irq ? MIP_VSTIP : 0; 631 632 QEMU_IOTHREAD_LOCK_GUARD(); 633 634 env->mip = (env->mip & ~mask) | (value & mask); 635 636 if (env->mip | vsgein | vstip) { 637 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 638 } else { 639 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 640 } 641 642 return old; 643 } 644 645 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 646 void *arg) 647 { 648 env->rdtime_fn = fn; 649 env->rdtime_fn_arg = arg; 650 } 651 652 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 653 int (*rmw_fn)(void *arg, 654 target_ulong reg, 655 target_ulong *val, 656 target_ulong new_val, 657 target_ulong write_mask), 658 void *rmw_fn_arg) 659 { 660 if (priv <= PRV_M) { 661 env->aia_ireg_rmw_fn[priv] = rmw_fn; 662 env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; 663 } 664 } 665 666 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) 667 { 668 g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED); 669 670 if (icount_enabled() && newpriv != env->priv) { 671 riscv_itrigger_update_priv(env); 672 } 673 /* tlb_flush is unnecessary as mode is contained in mmu_idx */ 674 env->priv = newpriv; 675 env->xl = cpu_recompute_xl(env); 676 riscv_cpu_update_mask(env); 677 678 /* 679 * Clear the load reservation - otherwise a reservation placed in one 680 * context/process can be used by another, resulting in an SC succeeding 681 * incorrectly. Version 2.2 of the ISA specification explicitly requires 682 * this behaviour, while later revisions say that the kernel "should" use 683 * an SC instruction to force the yielding of a load reservation on a 684 * preemptive context switch. As a result, do both. 685 */ 686 env->load_res = -1; 687 } 688 689 /* 690 * get_physical_address_pmp - check PMP permission for this physical address 691 * 692 * Match the PMP region and check permission for this physical address and it's 693 * TLB page. Returns 0 if the permission checking was successful 694 * 695 * @env: CPURISCVState 696 * @prot: The returned protection attributes 697 * @addr: The physical address to be checked permission 698 * @access_type: The type of MMU access 699 * @mode: Indicates current privilege level. 700 */ 701 static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr, 702 int size, MMUAccessType access_type, 703 int mode) 704 { 705 pmp_priv_t pmp_priv; 706 bool pmp_has_privs; 707 708 if (!riscv_cpu_cfg(env)->pmp) { 709 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 710 return TRANSLATE_SUCCESS; 711 } 712 713 pmp_has_privs = pmp_hart_has_privs(env, addr, size, 1 << access_type, 714 &pmp_priv, mode); 715 if (!pmp_has_privs) { 716 *prot = 0; 717 return TRANSLATE_PMP_FAIL; 718 } 719 720 *prot = pmp_priv_to_page_prot(pmp_priv); 721 722 return TRANSLATE_SUCCESS; 723 } 724 725 /* 726 * get_physical_address - get the physical address for this virtual address 727 * 728 * Do a page table walk to obtain the physical address corresponding to a 729 * virtual address. Returns 0 if the translation was successful 730 * 731 * Adapted from Spike's mmu_t::translate and mmu_t::walk 732 * 733 * @env: CPURISCVState 734 * @physical: This will be set to the calculated physical address 735 * @prot: The returned protection attributes 736 * @addr: The virtual address or guest physical address to be translated 737 * @fault_pte_addr: If not NULL, this will be set to fault pte address 738 * when a error occurs on pte address translation. 739 * This will already be shifted to match htval. 740 * @access_type: The type of MMU access 741 * @mmu_idx: Indicates current privilege level 742 * @first_stage: Are we in first stage translation? 743 * Second stage is used for hypervisor guest translation 744 * @two_stage: Are we going to perform two stage translation 745 * @is_debug: Is this access from a debugger or the monitor? 746 */ 747 static int get_physical_address(CPURISCVState *env, hwaddr *physical, 748 int *ret_prot, vaddr addr, 749 target_ulong *fault_pte_addr, 750 int access_type, int mmu_idx, 751 bool first_stage, bool two_stage, 752 bool is_debug) 753 { 754 /* 755 * NOTE: the env->pc value visible here will not be 756 * correct, but the value visible to the exception handler 757 * (riscv_cpu_do_interrupt) is correct 758 */ 759 MemTxResult res; 760 MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 761 int mode = mmuidx_priv(mmu_idx); 762 bool use_background = false; 763 hwaddr ppn; 764 int napot_bits = 0; 765 target_ulong napot_mask; 766 767 /* 768 * Check if we should use the background registers for the two 769 * stage translation. We don't need to check if we actually need 770 * two stage translation as that happened before this function 771 * was called. Background registers will be used if the guest has 772 * forced a two stage translation to be on (in HS or M mode). 773 */ 774 if (!env->virt_enabled && two_stage) { 775 use_background = true; 776 } 777 778 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { 779 *physical = addr; 780 *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 781 return TRANSLATE_SUCCESS; 782 } 783 784 *ret_prot = 0; 785 786 hwaddr base; 787 int levels, ptidxbits, ptesize, vm, widened; 788 789 if (first_stage == true) { 790 if (use_background) { 791 if (riscv_cpu_mxl(env) == MXL_RV32) { 792 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT; 793 vm = get_field(env->vsatp, SATP32_MODE); 794 } else { 795 base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT; 796 vm = get_field(env->vsatp, SATP64_MODE); 797 } 798 } else { 799 if (riscv_cpu_mxl(env) == MXL_RV32) { 800 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; 801 vm = get_field(env->satp, SATP32_MODE); 802 } else { 803 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; 804 vm = get_field(env->satp, SATP64_MODE); 805 } 806 } 807 widened = 0; 808 } else { 809 if (riscv_cpu_mxl(env) == MXL_RV32) { 810 base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; 811 vm = get_field(env->hgatp, SATP32_MODE); 812 } else { 813 base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; 814 vm = get_field(env->hgatp, SATP64_MODE); 815 } 816 widened = 2; 817 } 818 819 switch (vm) { 820 case VM_1_10_SV32: 821 levels = 2; ptidxbits = 10; ptesize = 4; break; 822 case VM_1_10_SV39: 823 levels = 3; ptidxbits = 9; ptesize = 8; break; 824 case VM_1_10_SV48: 825 levels = 4; ptidxbits = 9; ptesize = 8; break; 826 case VM_1_10_SV57: 827 levels = 5; ptidxbits = 9; ptesize = 8; break; 828 case VM_1_10_MBARE: 829 *physical = addr; 830 *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 831 return TRANSLATE_SUCCESS; 832 default: 833 g_assert_not_reached(); 834 } 835 836 CPUState *cs = env_cpu(env); 837 int va_bits = PGSHIFT + levels * ptidxbits + widened; 838 839 if (first_stage == true) { 840 target_ulong mask, masked_msbs; 841 842 if (TARGET_LONG_BITS > (va_bits - 1)) { 843 mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; 844 } else { 845 mask = 0; 846 } 847 masked_msbs = (addr >> (va_bits - 1)) & mask; 848 849 if (masked_msbs != 0 && masked_msbs != mask) { 850 return TRANSLATE_FAIL; 851 } 852 } else { 853 if (vm != VM_1_10_SV32 && addr >> va_bits != 0) { 854 return TRANSLATE_FAIL; 855 } 856 } 857 858 bool pbmte = env->menvcfg & MENVCFG_PBMTE; 859 bool hade = env->menvcfg & MENVCFG_HADE; 860 861 if (first_stage && two_stage && env->virt_enabled) { 862 pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); 863 hade = hade && (env->henvcfg & HENVCFG_HADE); 864 } 865 866 int ptshift = (levels - 1) * ptidxbits; 867 target_ulong pte; 868 hwaddr pte_addr; 869 int i; 870 871 #if !TCG_OVERSIZED_GUEST 872 restart: 873 #endif 874 for (i = 0; i < levels; i++, ptshift -= ptidxbits) { 875 target_ulong idx; 876 if (i == 0) { 877 idx = (addr >> (PGSHIFT + ptshift)) & 878 ((1 << (ptidxbits + widened)) - 1); 879 } else { 880 idx = (addr >> (PGSHIFT + ptshift)) & 881 ((1 << ptidxbits) - 1); 882 } 883 884 /* check that physical address of PTE is legal */ 885 886 if (two_stage && first_stage) { 887 int vbase_prot; 888 hwaddr vbase; 889 890 /* Do the second stage translation on the base PTE address. */ 891 int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, 892 base, NULL, MMU_DATA_LOAD, 893 MMUIdx_U, false, true, 894 is_debug); 895 896 if (vbase_ret != TRANSLATE_SUCCESS) { 897 if (fault_pte_addr) { 898 *fault_pte_addr = (base + idx * ptesize) >> 2; 899 } 900 return TRANSLATE_G_STAGE_FAIL; 901 } 902 903 pte_addr = vbase + idx * ptesize; 904 } else { 905 pte_addr = base + idx * ptesize; 906 } 907 908 int pmp_prot; 909 int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr, 910 sizeof(target_ulong), 911 MMU_DATA_LOAD, PRV_S); 912 if (pmp_ret != TRANSLATE_SUCCESS) { 913 return TRANSLATE_PMP_FAIL; 914 } 915 916 if (riscv_cpu_mxl(env) == MXL_RV32) { 917 pte = address_space_ldl(cs->as, pte_addr, attrs, &res); 918 } else { 919 pte = address_space_ldq(cs->as, pte_addr, attrs, &res); 920 } 921 922 if (res != MEMTX_OK) { 923 return TRANSLATE_FAIL; 924 } 925 926 if (riscv_cpu_sxl(env) == MXL_RV32) { 927 ppn = pte >> PTE_PPN_SHIFT; 928 } else { 929 if (pte & PTE_RESERVED) { 930 return TRANSLATE_FAIL; 931 } 932 933 if (!pbmte && (pte & PTE_PBMT)) { 934 return TRANSLATE_FAIL; 935 } 936 937 if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { 938 return TRANSLATE_FAIL; 939 } 940 941 ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; 942 } 943 944 if (!(pte & PTE_V)) { 945 /* Invalid PTE */ 946 return TRANSLATE_FAIL; 947 } 948 if (pte & (PTE_R | PTE_W | PTE_X)) { 949 goto leaf; 950 } 951 952 /* Inner PTE, continue walking */ 953 if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { 954 return TRANSLATE_FAIL; 955 } 956 base = ppn << PGSHIFT; 957 } 958 959 /* No leaf pte at any translation level. */ 960 return TRANSLATE_FAIL; 961 962 leaf: 963 if (ppn & ((1ULL << ptshift) - 1)) { 964 /* Misaligned PPN */ 965 return TRANSLATE_FAIL; 966 } 967 if (!pbmte && (pte & PTE_PBMT)) { 968 /* Reserved without Svpbmt. */ 969 return TRANSLATE_FAIL; 970 } 971 972 /* Check for reserved combinations of RWX flags. */ 973 switch (pte & (PTE_R | PTE_W | PTE_X)) { 974 case PTE_W: 975 case PTE_W | PTE_X: 976 return TRANSLATE_FAIL; 977 } 978 979 int prot = 0; 980 if (pte & PTE_R) { 981 prot |= PAGE_READ; 982 } 983 if (pte & PTE_W) { 984 prot |= PAGE_WRITE; 985 } 986 if (pte & PTE_X) { 987 bool mxr; 988 989 if (first_stage == true) { 990 mxr = get_field(env->mstatus, MSTATUS_MXR); 991 } else { 992 mxr = get_field(env->vsstatus, MSTATUS_MXR); 993 } 994 if (mxr) { 995 prot |= PAGE_READ; 996 } 997 prot |= PAGE_EXEC; 998 } 999 1000 if (pte & PTE_U) { 1001 if (mode != PRV_U) { 1002 if (!mmuidx_sum(mmu_idx)) { 1003 return TRANSLATE_FAIL; 1004 } 1005 /* SUM allows only read+write, not execute. */ 1006 prot &= PAGE_READ | PAGE_WRITE; 1007 } 1008 } else if (mode != PRV_S) { 1009 /* Supervisor PTE flags when not S mode */ 1010 return TRANSLATE_FAIL; 1011 } 1012 1013 if (!((prot >> access_type) & 1)) { 1014 /* Access check failed */ 1015 return TRANSLATE_FAIL; 1016 } 1017 1018 /* If necessary, set accessed and dirty bits. */ 1019 target_ulong updated_pte = pte | PTE_A | 1020 (access_type == MMU_DATA_STORE ? PTE_D : 0); 1021 1022 /* Page table updates need to be atomic with MTTCG enabled */ 1023 if (updated_pte != pte && !is_debug) { 1024 if (!hade) { 1025 return TRANSLATE_FAIL; 1026 } 1027 1028 /* 1029 * - if accessed or dirty bits need updating, and the PTE is 1030 * in RAM, then we do so atomically with a compare and swap. 1031 * - if the PTE is in IO space or ROM, then it can't be updated 1032 * and we return TRANSLATE_FAIL. 1033 * - if the PTE changed by the time we went to update it, then 1034 * it is no longer valid and we must re-walk the page table. 1035 */ 1036 MemoryRegion *mr; 1037 hwaddr l = sizeof(target_ulong), addr1; 1038 mr = address_space_translate(cs->as, pte_addr, &addr1, &l, 1039 false, MEMTXATTRS_UNSPECIFIED); 1040 if (memory_region_is_ram(mr)) { 1041 target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1); 1042 #if TCG_OVERSIZED_GUEST 1043 /* 1044 * MTTCG is not enabled on oversized TCG guests so 1045 * page table updates do not need to be atomic 1046 */ 1047 *pte_pa = pte = updated_pte; 1048 #else 1049 target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte); 1050 if (old_pte != pte) { 1051 goto restart; 1052 } 1053 pte = updated_pte; 1054 #endif 1055 } else { 1056 /* 1057 * Misconfigured PTE in ROM (AD bits are not preset) or 1058 * PTE is in IO space and can't be updated atomically. 1059 */ 1060 return TRANSLATE_FAIL; 1061 } 1062 } 1063 1064 /* For superpage mappings, make a fake leaf PTE for the TLB's benefit. */ 1065 target_ulong vpn = addr >> PGSHIFT; 1066 1067 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { 1068 napot_bits = ctzl(ppn) + 1; 1069 if ((i != (levels - 1)) || (napot_bits != 4)) { 1070 return TRANSLATE_FAIL; 1071 } 1072 } 1073 1074 napot_mask = (1 << napot_bits) - 1; 1075 *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | 1076 (vpn & (((target_ulong)1 << ptshift) - 1)) 1077 ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); 1078 1079 /* 1080 * Remove write permission unless this is a store, or the page is 1081 * already dirty, so that we TLB miss on later writes to update 1082 * the dirty bit. 1083 */ 1084 if (access_type != MMU_DATA_STORE && !(pte & PTE_D)) { 1085 prot &= ~PAGE_WRITE; 1086 } 1087 *ret_prot = prot; 1088 1089 return TRANSLATE_SUCCESS; 1090 } 1091 1092 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, 1093 MMUAccessType access_type, bool pmp_violation, 1094 bool first_stage, bool two_stage, 1095 bool two_stage_indirect) 1096 { 1097 CPUState *cs = env_cpu(env); 1098 int page_fault_exceptions, vm; 1099 uint64_t stap_mode; 1100 1101 if (riscv_cpu_mxl(env) == MXL_RV32) { 1102 stap_mode = SATP32_MODE; 1103 } else { 1104 stap_mode = SATP64_MODE; 1105 } 1106 1107 if (first_stage) { 1108 vm = get_field(env->satp, stap_mode); 1109 } else { 1110 vm = get_field(env->hgatp, stap_mode); 1111 } 1112 1113 page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; 1114 1115 switch (access_type) { 1116 case MMU_INST_FETCH: 1117 if (env->virt_enabled && !first_stage) { 1118 cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; 1119 } else { 1120 cs->exception_index = page_fault_exceptions ? 1121 RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; 1122 } 1123 break; 1124 case MMU_DATA_LOAD: 1125 if (two_stage && !first_stage) { 1126 cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; 1127 } else { 1128 cs->exception_index = page_fault_exceptions ? 1129 RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; 1130 } 1131 break; 1132 case MMU_DATA_STORE: 1133 if (two_stage && !first_stage) { 1134 cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; 1135 } else { 1136 cs->exception_index = page_fault_exceptions ? 1137 RISCV_EXCP_STORE_PAGE_FAULT : 1138 RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1139 } 1140 break; 1141 default: 1142 g_assert_not_reached(); 1143 } 1144 env->badaddr = address; 1145 env->two_stage_lookup = two_stage; 1146 env->two_stage_indirect_lookup = two_stage_indirect; 1147 } 1148 1149 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 1150 { 1151 RISCVCPU *cpu = RISCV_CPU(cs); 1152 CPURISCVState *env = &cpu->env; 1153 hwaddr phys_addr; 1154 int prot; 1155 int mmu_idx = cpu_mmu_index(&cpu->env, false); 1156 1157 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, 1158 true, env->virt_enabled, true)) { 1159 return -1; 1160 } 1161 1162 if (env->virt_enabled) { 1163 if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 1164 0, mmu_idx, false, true, true)) { 1165 return -1; 1166 } 1167 } 1168 1169 return phys_addr & TARGET_PAGE_MASK; 1170 } 1171 1172 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 1173 vaddr addr, unsigned size, 1174 MMUAccessType access_type, 1175 int mmu_idx, MemTxAttrs attrs, 1176 MemTxResult response, uintptr_t retaddr) 1177 { 1178 RISCVCPU *cpu = RISCV_CPU(cs); 1179 CPURISCVState *env = &cpu->env; 1180 1181 if (access_type == MMU_DATA_STORE) { 1182 cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; 1183 } else if (access_type == MMU_DATA_LOAD) { 1184 cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; 1185 } else { 1186 cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; 1187 } 1188 1189 env->badaddr = addr; 1190 env->two_stage_lookup = mmuidx_2stage(mmu_idx); 1191 env->two_stage_indirect_lookup = false; 1192 cpu_loop_exit_restore(cs, retaddr); 1193 } 1194 1195 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 1196 MMUAccessType access_type, int mmu_idx, 1197 uintptr_t retaddr) 1198 { 1199 RISCVCPU *cpu = RISCV_CPU(cs); 1200 CPURISCVState *env = &cpu->env; 1201 switch (access_type) { 1202 case MMU_INST_FETCH: 1203 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; 1204 break; 1205 case MMU_DATA_LOAD: 1206 cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; 1207 break; 1208 case MMU_DATA_STORE: 1209 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; 1210 break; 1211 default: 1212 g_assert_not_reached(); 1213 } 1214 env->badaddr = addr; 1215 env->two_stage_lookup = mmuidx_2stage(mmu_idx); 1216 env->two_stage_indirect_lookup = false; 1217 cpu_loop_exit_restore(cs, retaddr); 1218 } 1219 1220 1221 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) 1222 { 1223 enum riscv_pmu_event_idx pmu_event_type; 1224 1225 switch (access_type) { 1226 case MMU_INST_FETCH: 1227 pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; 1228 break; 1229 case MMU_DATA_LOAD: 1230 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; 1231 break; 1232 case MMU_DATA_STORE: 1233 pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; 1234 break; 1235 default: 1236 return; 1237 } 1238 1239 riscv_pmu_incr_ctr(cpu, pmu_event_type); 1240 } 1241 1242 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 1243 MMUAccessType access_type, int mmu_idx, 1244 bool probe, uintptr_t retaddr) 1245 { 1246 RISCVCPU *cpu = RISCV_CPU(cs); 1247 CPURISCVState *env = &cpu->env; 1248 vaddr im_address; 1249 hwaddr pa = 0; 1250 int prot, prot2, prot_pmp; 1251 bool pmp_violation = false; 1252 bool first_stage_error = true; 1253 bool two_stage_lookup = mmuidx_2stage(mmu_idx); 1254 bool two_stage_indirect_error = false; 1255 int ret = TRANSLATE_FAIL; 1256 int mode = mmu_idx; 1257 /* default TLB page size */ 1258 target_ulong tlb_size = TARGET_PAGE_SIZE; 1259 1260 env->guest_phys_fault_addr = 0; 1261 1262 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", 1263 __func__, address, access_type, mmu_idx); 1264 1265 pmu_tlb_fill_incr_ctr(cpu, access_type); 1266 if (two_stage_lookup) { 1267 /* Two stage lookup */ 1268 ret = get_physical_address(env, &pa, &prot, address, 1269 &env->guest_phys_fault_addr, access_type, 1270 mmu_idx, true, true, false); 1271 1272 /* 1273 * A G-stage exception may be triggered during two state lookup. 1274 * And the env->guest_phys_fault_addr has already been set in 1275 * get_physical_address(). 1276 */ 1277 if (ret == TRANSLATE_G_STAGE_FAIL) { 1278 first_stage_error = false; 1279 two_stage_indirect_error = true; 1280 access_type = MMU_DATA_LOAD; 1281 } 1282 1283 qemu_log_mask(CPU_LOG_MMU, 1284 "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " 1285 HWADDR_FMT_plx " prot %d\n", 1286 __func__, address, ret, pa, prot); 1287 1288 if (ret == TRANSLATE_SUCCESS) { 1289 /* Second stage lookup */ 1290 im_address = pa; 1291 1292 ret = get_physical_address(env, &pa, &prot2, im_address, NULL, 1293 access_type, MMUIdx_U, false, true, 1294 false); 1295 1296 qemu_log_mask(CPU_LOG_MMU, 1297 "%s 2nd-stage address=%" VADDR_PRIx 1298 " ret %d physical " 1299 HWADDR_FMT_plx " prot %d\n", 1300 __func__, im_address, ret, pa, prot2); 1301 1302 prot &= prot2; 1303 1304 if (ret == TRANSLATE_SUCCESS) { 1305 ret = get_physical_address_pmp(env, &prot_pmp, pa, 1306 size, access_type, mode); 1307 tlb_size = pmp_get_tlb_size(env, pa); 1308 1309 qemu_log_mask(CPU_LOG_MMU, 1310 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1311 " %d tlb_size " TARGET_FMT_lu "\n", 1312 __func__, pa, ret, prot_pmp, tlb_size); 1313 1314 prot &= prot_pmp; 1315 } 1316 1317 if (ret != TRANSLATE_SUCCESS) { 1318 /* 1319 * Guest physical address translation failed, this is a HS 1320 * level exception 1321 */ 1322 first_stage_error = false; 1323 env->guest_phys_fault_addr = (im_address | 1324 (address & 1325 (TARGET_PAGE_SIZE - 1))) >> 2; 1326 } 1327 } 1328 } else { 1329 /* Single stage lookup */ 1330 ret = get_physical_address(env, &pa, &prot, address, NULL, 1331 access_type, mmu_idx, true, false, false); 1332 1333 qemu_log_mask(CPU_LOG_MMU, 1334 "%s address=%" VADDR_PRIx " ret %d physical " 1335 HWADDR_FMT_plx " prot %d\n", 1336 __func__, address, ret, pa, prot); 1337 1338 if (ret == TRANSLATE_SUCCESS) { 1339 ret = get_physical_address_pmp(env, &prot_pmp, pa, 1340 size, access_type, mode); 1341 tlb_size = pmp_get_tlb_size(env, pa); 1342 1343 qemu_log_mask(CPU_LOG_MMU, 1344 "%s PMP address=" HWADDR_FMT_plx " ret %d prot" 1345 " %d tlb_size " TARGET_FMT_lu "\n", 1346 __func__, pa, ret, prot_pmp, tlb_size); 1347 1348 prot &= prot_pmp; 1349 } 1350 } 1351 1352 if (ret == TRANSLATE_PMP_FAIL) { 1353 pmp_violation = true; 1354 } 1355 1356 if (ret == TRANSLATE_SUCCESS) { 1357 tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), 1358 prot, mmu_idx, tlb_size); 1359 return true; 1360 } else if (probe) { 1361 return false; 1362 } else { 1363 raise_mmu_exception(env, address, access_type, pmp_violation, 1364 first_stage_error, two_stage_lookup, 1365 two_stage_indirect_error); 1366 cpu_loop_exit_restore(cs, retaddr); 1367 } 1368 1369 return true; 1370 } 1371 1372 static target_ulong riscv_transformed_insn(CPURISCVState *env, 1373 target_ulong insn, 1374 target_ulong taddr) 1375 { 1376 target_ulong xinsn = 0; 1377 target_ulong access_rs1 = 0, access_imm = 0, access_size = 0; 1378 1379 /* 1380 * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to 1381 * be uncompressed. The Quadrant 1 of RVC instruction space need 1382 * not be transformed because these instructions won't generate 1383 * any load/store trap. 1384 */ 1385 1386 if ((insn & 0x3) != 0x3) { 1387 /* Transform 16bit instruction into 32bit instruction */ 1388 switch (GET_C_OP(insn)) { 1389 case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ 1390 switch (GET_C_FUNC(insn)) { 1391 case OPC_RISC_C_FUNC_FLD_LQ: 1392 if (riscv_cpu_xlen(env) != 128) { /* C.FLD (RV32/64) */ 1393 xinsn = OPC_RISC_FLD; 1394 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1395 access_rs1 = GET_C_RS1S(insn); 1396 access_imm = GET_C_LD_IMM(insn); 1397 access_size = 8; 1398 } 1399 break; 1400 case OPC_RISC_C_FUNC_LW: /* C.LW */ 1401 xinsn = OPC_RISC_LW; 1402 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1403 access_rs1 = GET_C_RS1S(insn); 1404 access_imm = GET_C_LW_IMM(insn); 1405 access_size = 4; 1406 break; 1407 case OPC_RISC_C_FUNC_FLW_LD: 1408 if (riscv_cpu_xlen(env) == 32) { /* C.FLW (RV32) */ 1409 xinsn = OPC_RISC_FLW; 1410 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1411 access_rs1 = GET_C_RS1S(insn); 1412 access_imm = GET_C_LW_IMM(insn); 1413 access_size = 4; 1414 } else { /* C.LD (RV64/RV128) */ 1415 xinsn = OPC_RISC_LD; 1416 xinsn = SET_RD(xinsn, GET_C_RS2S(insn)); 1417 access_rs1 = GET_C_RS1S(insn); 1418 access_imm = GET_C_LD_IMM(insn); 1419 access_size = 8; 1420 } 1421 break; 1422 case OPC_RISC_C_FUNC_FSD_SQ: 1423 if (riscv_cpu_xlen(env) != 128) { /* C.FSD (RV32/64) */ 1424 xinsn = OPC_RISC_FSD; 1425 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1426 access_rs1 = GET_C_RS1S(insn); 1427 access_imm = GET_C_SD_IMM(insn); 1428 access_size = 8; 1429 } 1430 break; 1431 case OPC_RISC_C_FUNC_SW: /* C.SW */ 1432 xinsn = OPC_RISC_SW; 1433 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1434 access_rs1 = GET_C_RS1S(insn); 1435 access_imm = GET_C_SW_IMM(insn); 1436 access_size = 4; 1437 break; 1438 case OPC_RISC_C_FUNC_FSW_SD: 1439 if (riscv_cpu_xlen(env) == 32) { /* C.FSW (RV32) */ 1440 xinsn = OPC_RISC_FSW; 1441 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1442 access_rs1 = GET_C_RS1S(insn); 1443 access_imm = GET_C_SW_IMM(insn); 1444 access_size = 4; 1445 } else { /* C.SD (RV64/RV128) */ 1446 xinsn = OPC_RISC_SD; 1447 xinsn = SET_RS2(xinsn, GET_C_RS2S(insn)); 1448 access_rs1 = GET_C_RS1S(insn); 1449 access_imm = GET_C_SD_IMM(insn); 1450 access_size = 8; 1451 } 1452 break; 1453 default: 1454 break; 1455 } 1456 break; 1457 case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ 1458 switch (GET_C_FUNC(insn)) { 1459 case OPC_RISC_C_FUNC_FLDSP_LQSP: 1460 if (riscv_cpu_xlen(env) != 128) { /* C.FLDSP (RV32/64) */ 1461 xinsn = OPC_RISC_FLD; 1462 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1463 access_rs1 = 2; 1464 access_imm = GET_C_LDSP_IMM(insn); 1465 access_size = 8; 1466 } 1467 break; 1468 case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ 1469 xinsn = OPC_RISC_LW; 1470 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1471 access_rs1 = 2; 1472 access_imm = GET_C_LWSP_IMM(insn); 1473 access_size = 4; 1474 break; 1475 case OPC_RISC_C_FUNC_FLWSP_LDSP: 1476 if (riscv_cpu_xlen(env) == 32) { /* C.FLWSP (RV32) */ 1477 xinsn = OPC_RISC_FLW; 1478 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1479 access_rs1 = 2; 1480 access_imm = GET_C_LWSP_IMM(insn); 1481 access_size = 4; 1482 } else { /* C.LDSP (RV64/RV128) */ 1483 xinsn = OPC_RISC_LD; 1484 xinsn = SET_RD(xinsn, GET_C_RD(insn)); 1485 access_rs1 = 2; 1486 access_imm = GET_C_LDSP_IMM(insn); 1487 access_size = 8; 1488 } 1489 break; 1490 case OPC_RISC_C_FUNC_FSDSP_SQSP: 1491 if (riscv_cpu_xlen(env) != 128) { /* C.FSDSP (RV32/64) */ 1492 xinsn = OPC_RISC_FSD; 1493 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1494 access_rs1 = 2; 1495 access_imm = GET_C_SDSP_IMM(insn); 1496 access_size = 8; 1497 } 1498 break; 1499 case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ 1500 xinsn = OPC_RISC_SW; 1501 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1502 access_rs1 = 2; 1503 access_imm = GET_C_SWSP_IMM(insn); 1504 access_size = 4; 1505 break; 1506 case 7: 1507 if (riscv_cpu_xlen(env) == 32) { /* C.FSWSP (RV32) */ 1508 xinsn = OPC_RISC_FSW; 1509 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1510 access_rs1 = 2; 1511 access_imm = GET_C_SWSP_IMM(insn); 1512 access_size = 4; 1513 } else { /* C.SDSP (RV64/RV128) */ 1514 xinsn = OPC_RISC_SD; 1515 xinsn = SET_RS2(xinsn, GET_C_RS2(insn)); 1516 access_rs1 = 2; 1517 access_imm = GET_C_SDSP_IMM(insn); 1518 access_size = 8; 1519 } 1520 break; 1521 default: 1522 break; 1523 } 1524 break; 1525 default: 1526 break; 1527 } 1528 1529 /* 1530 * Clear Bit1 of transformed instruction to indicate that 1531 * original insruction was a 16bit instruction 1532 */ 1533 xinsn &= ~((target_ulong)0x2); 1534 } else { 1535 /* Transform 32bit (or wider) instructions */ 1536 switch (MASK_OP_MAJOR(insn)) { 1537 case OPC_RISC_ATOMIC: 1538 xinsn = insn; 1539 access_rs1 = GET_RS1(insn); 1540 access_size = 1 << GET_FUNCT3(insn); 1541 break; 1542 case OPC_RISC_LOAD: 1543 case OPC_RISC_FP_LOAD: 1544 xinsn = SET_I_IMM(insn, 0); 1545 access_rs1 = GET_RS1(insn); 1546 access_imm = GET_IMM(insn); 1547 access_size = 1 << GET_FUNCT3(insn); 1548 break; 1549 case OPC_RISC_STORE: 1550 case OPC_RISC_FP_STORE: 1551 xinsn = SET_S_IMM(insn, 0); 1552 access_rs1 = GET_RS1(insn); 1553 access_imm = GET_STORE_IMM(insn); 1554 access_size = 1 << GET_FUNCT3(insn); 1555 break; 1556 case OPC_RISC_SYSTEM: 1557 if (MASK_OP_SYSTEM(insn) == OPC_RISC_HLVHSV) { 1558 xinsn = insn; 1559 access_rs1 = GET_RS1(insn); 1560 access_size = 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); 1561 access_size = 1 << access_size; 1562 } 1563 break; 1564 default: 1565 break; 1566 } 1567 } 1568 1569 if (access_size) { 1570 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & 1571 (access_size - 1)); 1572 } 1573 1574 return xinsn; 1575 } 1576 #endif /* !CONFIG_USER_ONLY */ 1577 1578 /* 1579 * Handle Traps 1580 * 1581 * Adapted from Spike's processor_t::take_trap. 1582 * 1583 */ 1584 void riscv_cpu_do_interrupt(CPUState *cs) 1585 { 1586 #if !defined(CONFIG_USER_ONLY) 1587 1588 RISCVCPU *cpu = RISCV_CPU(cs); 1589 CPURISCVState *env = &cpu->env; 1590 bool write_gva = false; 1591 uint64_t s; 1592 1593 /* 1594 * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide 1595 * so we mask off the MSB and separate into trap type and cause. 1596 */ 1597 bool async = !!(cs->exception_index & RISCV_EXCP_INT_FLAG); 1598 target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK; 1599 uint64_t deleg = async ? env->mideleg : env->medeleg; 1600 target_ulong tval = 0; 1601 target_ulong tinst = 0; 1602 target_ulong htval = 0; 1603 target_ulong mtval2 = 0; 1604 1605 if (cause == RISCV_EXCP_SEMIHOST) { 1606 do_common_semihosting(cs); 1607 env->pc += 4; 1608 return; 1609 } 1610 1611 if (!async) { 1612 /* set tval to badaddr for traps with address information */ 1613 switch (cause) { 1614 case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: 1615 case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: 1616 case RISCV_EXCP_LOAD_ADDR_MIS: 1617 case RISCV_EXCP_STORE_AMO_ADDR_MIS: 1618 case RISCV_EXCP_LOAD_ACCESS_FAULT: 1619 case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: 1620 case RISCV_EXCP_LOAD_PAGE_FAULT: 1621 case RISCV_EXCP_STORE_PAGE_FAULT: 1622 write_gva = env->two_stage_lookup; 1623 tval = env->badaddr; 1624 if (env->two_stage_indirect_lookup) { 1625 /* 1626 * special pseudoinstruction for G-stage fault taken while 1627 * doing VS-stage page table walk. 1628 */ 1629 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1630 } else { 1631 /* 1632 * The "Addr. Offset" field in transformed instruction is 1633 * non-zero only for misaligned access. 1634 */ 1635 tinst = riscv_transformed_insn(env, env->bins, tval); 1636 } 1637 break; 1638 case RISCV_EXCP_INST_GUEST_PAGE_FAULT: 1639 case RISCV_EXCP_INST_ADDR_MIS: 1640 case RISCV_EXCP_INST_ACCESS_FAULT: 1641 case RISCV_EXCP_INST_PAGE_FAULT: 1642 write_gva = env->two_stage_lookup; 1643 tval = env->badaddr; 1644 if (env->two_stage_indirect_lookup) { 1645 /* 1646 * special pseudoinstruction for G-stage fault taken while 1647 * doing VS-stage page table walk. 1648 */ 1649 tinst = (riscv_cpu_xlen(env) == 32) ? 0x00002000 : 0x00003000; 1650 } 1651 break; 1652 case RISCV_EXCP_ILLEGAL_INST: 1653 case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: 1654 tval = env->bins; 1655 break; 1656 case RISCV_EXCP_BREAKPOINT: 1657 if (cs->watchpoint_hit) { 1658 tval = cs->watchpoint_hit->hitaddr; 1659 cs->watchpoint_hit = NULL; 1660 } 1661 break; 1662 default: 1663 break; 1664 } 1665 /* ecall is dispatched as one cause so translate based on mode */ 1666 if (cause == RISCV_EXCP_U_ECALL) { 1667 assert(env->priv <= 3); 1668 1669 if (env->priv == PRV_M) { 1670 cause = RISCV_EXCP_M_ECALL; 1671 } else if (env->priv == PRV_S && env->virt_enabled) { 1672 cause = RISCV_EXCP_VS_ECALL; 1673 } else if (env->priv == PRV_S && !env->virt_enabled) { 1674 cause = RISCV_EXCP_S_ECALL; 1675 } else if (env->priv == PRV_U) { 1676 cause = RISCV_EXCP_U_ECALL; 1677 } 1678 } 1679 } 1680 1681 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, 1682 riscv_cpu_get_trap_name(cause, async)); 1683 1684 qemu_log_mask(CPU_LOG_INT, 1685 "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " 1686 "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", 1687 __func__, env->mhartid, async, cause, env->pc, tval, 1688 riscv_cpu_get_trap_name(cause, async)); 1689 1690 if (env->priv <= PRV_S && 1691 cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { 1692 /* handle the trap in S-mode */ 1693 if (riscv_has_ext(env, RVH)) { 1694 uint64_t hdeleg = async ? env->hideleg : env->hedeleg; 1695 1696 if (env->virt_enabled && ((hdeleg >> cause) & 1)) { 1697 /* Trap to VS mode */ 1698 /* 1699 * See if we need to adjust cause. Yes if its VS mode interrupt 1700 * no if hypervisor has delegated one of hs mode's interrupt 1701 */ 1702 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT || 1703 cause == IRQ_VS_EXT) { 1704 cause = cause - 1; 1705 } 1706 write_gva = false; 1707 } else if (env->virt_enabled) { 1708 /* Trap into HS mode, from virt */ 1709 riscv_cpu_swap_hypervisor_regs(env); 1710 env->hstatus = set_field(env->hstatus, HSTATUS_SPVP, 1711 env->priv); 1712 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, true); 1713 1714 htval = env->guest_phys_fault_addr; 1715 1716 riscv_cpu_set_virt_enabled(env, 0); 1717 } else { 1718 /* Trap into HS mode */ 1719 env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); 1720 htval = env->guest_phys_fault_addr; 1721 } 1722 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); 1723 } 1724 1725 s = env->mstatus; 1726 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); 1727 s = set_field(s, MSTATUS_SPP, env->priv); 1728 s = set_field(s, MSTATUS_SIE, 0); 1729 env->mstatus = s; 1730 env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); 1731 env->sepc = env->pc; 1732 env->stval = tval; 1733 env->htval = htval; 1734 env->htinst = tinst; 1735 env->pc = (env->stvec >> 2 << 2) + 1736 ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); 1737 riscv_cpu_set_mode(env, PRV_S); 1738 } else { 1739 /* handle the trap in M-mode */ 1740 if (riscv_has_ext(env, RVH)) { 1741 if (env->virt_enabled) { 1742 riscv_cpu_swap_hypervisor_regs(env); 1743 } 1744 env->mstatus = set_field(env->mstatus, MSTATUS_MPV, 1745 env->virt_enabled); 1746 if (env->virt_enabled && tval) { 1747 env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); 1748 } 1749 1750 mtval2 = env->guest_phys_fault_addr; 1751 1752 /* Trapping to M mode, virt is disabled */ 1753 riscv_cpu_set_virt_enabled(env, 0); 1754 } 1755 1756 s = env->mstatus; 1757 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); 1758 s = set_field(s, MSTATUS_MPP, env->priv); 1759 s = set_field(s, MSTATUS_MIE, 0); 1760 env->mstatus = s; 1761 env->mcause = cause | ~(((target_ulong)-1) >> async); 1762 env->mepc = env->pc; 1763 env->mtval = tval; 1764 env->mtval2 = mtval2; 1765 env->mtinst = tinst; 1766 env->pc = (env->mtvec >> 2 << 2) + 1767 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); 1768 riscv_cpu_set_mode(env, PRV_M); 1769 } 1770 1771 /* 1772 * NOTE: it is not necessary to yield load reservations here. It is only 1773 * necessary for an SC from "another hart" to cause a load reservation 1774 * to be yielded. Refer to the memory consistency model section of the 1775 * RISC-V ISA Specification. 1776 */ 1777 1778 env->two_stage_lookup = false; 1779 env->two_stage_indirect_lookup = false; 1780 #endif 1781 cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */ 1782 } 1783