1/*
2 * RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
3 *
4 * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
5 * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
6 * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_ZBA(ctx) do {                    \
22    if (!ctx->cfg_ptr->ext_zba) {                \
23        return false;                            \
24    }                                            \
25} while (0)
26
27#define REQUIRE_ZBB(ctx) do {                    \
28    if (!ctx->cfg_ptr->ext_zbb) {                \
29        return false;                            \
30    }                                            \
31} while (0)
32
33#define REQUIRE_ZBC(ctx) do {                    \
34    if (!ctx->cfg_ptr->ext_zbc) {                \
35        return false;                            \
36    }                                            \
37} while (0)
38
39#define REQUIRE_ZBS(ctx) do {                    \
40    if (!ctx->cfg_ptr->ext_zbs) {                \
41        return false;                            \
42    }                                            \
43} while (0)
44
45#define REQUIRE_ZBKB(ctx) do {                   \
46    if (!ctx->cfg_ptr->ext_zbkb) {               \
47        return false;                            \
48    }                                            \
49} while (0)
50
51#define REQUIRE_ZBKX(ctx) do {                   \
52    if (!ctx->cfg_ptr->ext_zbkx) {               \
53        return false;                            \
54    }                                            \
55} while (0)
56
57static void gen_clz(TCGv ret, TCGv arg1)
58{
59    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
60}
61
62static void gen_clzw(TCGv ret, TCGv arg1)
63{
64    TCGv t = tcg_temp_new();
65    tcg_gen_shli_tl(t, arg1, 32);
66    tcg_gen_clzi_tl(ret, t, 32);
67}
68
69static bool trans_clz(DisasContext *ctx, arg_clz *a)
70{
71    REQUIRE_ZBB(ctx);
72    return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
73}
74
75static void gen_ctz(TCGv ret, TCGv arg1)
76{
77    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
78}
79
80static void gen_ctzw(TCGv ret, TCGv arg1)
81{
82    tcg_gen_ctzi_tl(ret, arg1, 32);
83}
84
85static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
86{
87    REQUIRE_ZBB(ctx);
88    return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw);
89}
90
91static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
92{
93    REQUIRE_ZBB(ctx);
94    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
95}
96
97static bool trans_andn(DisasContext *ctx, arg_andn *a)
98{
99    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
100    return gen_logic(ctx, a, tcg_gen_andc_tl);
101}
102
103static bool trans_orn(DisasContext *ctx, arg_orn *a)
104{
105    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
106    return gen_logic(ctx, a, tcg_gen_orc_tl);
107}
108
109static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
110{
111    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
112    return gen_logic(ctx, a, tcg_gen_eqv_tl);
113}
114
115static bool trans_min(DisasContext *ctx, arg_min *a)
116{
117    REQUIRE_ZBB(ctx);
118    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl, NULL);
119}
120
121static bool trans_max(DisasContext *ctx, arg_max *a)
122{
123    REQUIRE_ZBB(ctx);
124    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl, NULL);
125}
126
127static bool trans_minu(DisasContext *ctx, arg_minu *a)
128{
129    REQUIRE_ZBB(ctx);
130    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl, NULL);
131}
132
133static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
134{
135    REQUIRE_ZBB(ctx);
136    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl, NULL);
137}
138
139static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
140{
141    REQUIRE_ZBB(ctx);
142    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
143}
144
145static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
146{
147    REQUIRE_ZBB(ctx);
148    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
149}
150
151static void gen_sbop_mask(TCGv ret, TCGv shamt)
152{
153    tcg_gen_movi_tl(ret, 1);
154    tcg_gen_shl_tl(ret, ret, shamt);
155}
156
157static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
158{
159    TCGv t = tcg_temp_new();
160
161    gen_sbop_mask(t, shamt);
162    tcg_gen_or_tl(ret, arg1, t);
163}
164
165static bool trans_bset(DisasContext *ctx, arg_bset *a)
166{
167    REQUIRE_ZBS(ctx);
168    return gen_shift(ctx, a, EXT_NONE, gen_bset, NULL);
169}
170
171static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
172{
173    REQUIRE_ZBS(ctx);
174    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
175}
176
177static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
178{
179    TCGv t = tcg_temp_new();
180
181    gen_sbop_mask(t, shamt);
182    tcg_gen_andc_tl(ret, arg1, t);
183}
184
185static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
186{
187    REQUIRE_ZBS(ctx);
188    return gen_shift(ctx, a, EXT_NONE, gen_bclr, NULL);
189}
190
191static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
192{
193    REQUIRE_ZBS(ctx);
194    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
195}
196
197static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
198{
199    TCGv t = tcg_temp_new();
200
201    gen_sbop_mask(t, shamt);
202    tcg_gen_xor_tl(ret, arg1, t);
203}
204
205static bool trans_binv(DisasContext *ctx, arg_binv *a)
206{
207    REQUIRE_ZBS(ctx);
208    return gen_shift(ctx, a, EXT_NONE, gen_binv, NULL);
209}
210
211static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
212{
213    REQUIRE_ZBS(ctx);
214    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
215}
216
217static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
218{
219    tcg_gen_shr_tl(ret, arg1, shamt);
220    tcg_gen_andi_tl(ret, ret, 1);
221}
222
223static bool trans_bext(DisasContext *ctx, arg_bext *a)
224{
225    REQUIRE_ZBS(ctx);
226    return gen_shift(ctx, a, EXT_NONE, gen_bext, NULL);
227}
228
229static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
230{
231    REQUIRE_ZBS(ctx);
232    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
233}
234
235static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
236{
237    TCGv_i32 t1 = tcg_temp_new_i32();
238    TCGv_i32 t2 = tcg_temp_new_i32();
239
240    /* truncate to 32-bits */
241    tcg_gen_trunc_tl_i32(t1, arg1);
242    tcg_gen_trunc_tl_i32(t2, arg2);
243
244    tcg_gen_rotr_i32(t1, t1, t2);
245
246    /* sign-extend 64-bits */
247    tcg_gen_ext_i32_tl(ret, t1);
248}
249
250static bool trans_ror(DisasContext *ctx, arg_ror *a)
251{
252    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
253    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
254}
255
256static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
257{
258    TCGv_i32 t1 = tcg_temp_new_i32();
259
260    tcg_gen_trunc_tl_i32(t1, arg1);
261    tcg_gen_rotri_i32(t1, t1, shamt);
262    tcg_gen_ext_i32_tl(ret, t1);
263}
264
265static bool trans_rori(DisasContext *ctx, arg_rori *a)
266{
267    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
268    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
269                                   tcg_gen_rotri_tl, gen_roriw, NULL);
270}
271
272static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
273{
274    TCGv_i32 t1 = tcg_temp_new_i32();
275    TCGv_i32 t2 = tcg_temp_new_i32();
276
277    /* truncate to 32-bits */
278    tcg_gen_trunc_tl_i32(t1, arg1);
279    tcg_gen_trunc_tl_i32(t2, arg2);
280
281    tcg_gen_rotl_i32(t1, t1, t2);
282
283    /* sign-extend 64-bits */
284    tcg_gen_ext_i32_tl(ret, t1);
285}
286
287static bool trans_rol(DisasContext *ctx, arg_rol *a)
288{
289    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
290    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
291}
292
293static void gen_rev8_32(TCGv ret, TCGv src1)
294{
295    tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
296}
297
298static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
299{
300    REQUIRE_32BIT(ctx);
301    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
302    return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
303}
304
305static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
306{
307    REQUIRE_64BIT(ctx);
308    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
309    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
310}
311
312static void gen_orc_b(TCGv ret, TCGv source1)
313{
314    TCGv  tmp = tcg_temp_new();
315    TCGv  low7 = tcg_constant_tl(dup_const_tl(MO_8, 0x7f));
316
317    /* Set msb in each byte if the byte was non-zero. */
318    tcg_gen_and_tl(tmp, source1, low7);
319    tcg_gen_add_tl(tmp, tmp, low7);
320    tcg_gen_or_tl(tmp, tmp, source1);
321
322    /* Extract the msb to the lsb in each byte */
323    tcg_gen_andc_tl(tmp, tmp, low7);
324    tcg_gen_shri_tl(tmp, tmp, 7);
325
326    /* Replicate the lsb of each byte across the byte. */
327    tcg_gen_muli_tl(ret, tmp, 0xff);
328}
329
330static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
331{
332    REQUIRE_ZBB(ctx);
333    return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
334}
335
336#define GEN_SHADD(SHAMT)                                       \
337static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
338{                                                              \
339    TCGv t = tcg_temp_new();                                   \
340                                                               \
341    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
342    tcg_gen_add_tl(ret, t, arg2);                              \
343}
344
345GEN_SHADD(1)
346GEN_SHADD(2)
347GEN_SHADD(3)
348
349#define GEN_TRANS_SHADD(SHAMT)                                             \
350static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
351{                                                                          \
352    REQUIRE_ZBA(ctx);                                                      \
353    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add, NULL);          \
354}
355
356GEN_TRANS_SHADD(1)
357GEN_TRANS_SHADD(2)
358GEN_TRANS_SHADD(3)
359
360static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a)
361{
362    REQUIRE_32BIT(ctx);
363    REQUIRE_ZBB(ctx);
364    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
365}
366
367static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
368{
369    REQUIRE_64BIT(ctx);
370    REQUIRE_ZBB(ctx);
371    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
372}
373
374static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
375{
376    REQUIRE_64BIT(ctx);
377    REQUIRE_ZBB(ctx);
378    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
379}
380
381static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
382{
383    REQUIRE_64BIT(ctx);
384    REQUIRE_ZBB(ctx);
385    ctx->ol = MXL_RV32;
386    return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
387}
388
389static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
390{
391    REQUIRE_64BIT(ctx);
392    REQUIRE_ZBB(ctx);
393    ctx->ol = MXL_RV32;
394    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
395}
396
397static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
398{
399    REQUIRE_64BIT(ctx);
400    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
401    ctx->ol = MXL_RV32;
402    return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
403}
404
405static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
406{
407    REQUIRE_64BIT(ctx);
408    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
409    ctx->ol = MXL_RV32;
410    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
411}
412
413static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
414{
415    REQUIRE_64BIT(ctx);
416    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
417    ctx->ol = MXL_RV32;
418    return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
419}
420
421#define GEN_SHADD_UW(SHAMT)                                       \
422static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
423{                                                                 \
424    TCGv t = tcg_temp_new();                                      \
425                                                                  \
426    tcg_gen_ext32u_tl(t, arg1);                                   \
427                                                                  \
428    tcg_gen_shli_tl(t, t, SHAMT);                                 \
429    tcg_gen_add_tl(ret, t, arg2);                                 \
430}
431
432GEN_SHADD_UW(1)
433GEN_SHADD_UW(2)
434GEN_SHADD_UW(3)
435
436#define GEN_TRANS_SHADD_UW(SHAMT)                             \
437static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
438                                    arg_sh##SHAMT##add_uw *a) \
439{                                                             \
440    REQUIRE_64BIT(ctx);                                       \
441    REQUIRE_ZBA(ctx);                                         \
442    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw, NULL); \
443}
444
445GEN_TRANS_SHADD_UW(1)
446GEN_TRANS_SHADD_UW(2)
447GEN_TRANS_SHADD_UW(3)
448
449static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
450{
451    TCGv t = tcg_temp_new();
452    tcg_gen_ext32u_tl(t, arg1);
453    tcg_gen_add_tl(ret, t, arg2);
454}
455
456static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
457{
458    REQUIRE_64BIT(ctx);
459    REQUIRE_ZBA(ctx);
460    return gen_arith(ctx, a, EXT_NONE, gen_add_uw, NULL);
461}
462
463static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
464{
465    tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
466}
467
468static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
469{
470    REQUIRE_64BIT(ctx);
471    REQUIRE_ZBA(ctx);
472    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw, NULL);
473}
474
475static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
476{
477    REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
478    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
479}
480
481static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
482{
483     gen_helper_clmulr(dst, src1, src2);
484     tcg_gen_shri_tl(dst, dst, 1);
485}
486
487static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
488{
489    REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
490    return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
491}
492
493static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
494{
495    REQUIRE_ZBC(ctx);
496    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
497}
498
499static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
500{
501    tcg_gen_deposit_tl(ret, src1, src2,
502                       TARGET_LONG_BITS / 2,
503                       TARGET_LONG_BITS / 2);
504}
505
506static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
507{
508    TCGv t = tcg_temp_new();
509
510    tcg_gen_ext8u_tl(t, src2);
511    tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
512}
513
514static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
515{
516    TCGv t = tcg_temp_new();
517
518    tcg_gen_ext16s_tl(t, src2);
519    tcg_gen_deposit_tl(ret, src1, t, 16, TARGET_LONG_BITS - 16);
520}
521
522static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
523{
524    REQUIRE_ZBKB(ctx);
525    return gen_unary(ctx, a, EXT_NONE, gen_helper_brev8);
526}
527
528static bool trans_pack(DisasContext *ctx, arg_pack *a)
529{
530    REQUIRE_ZBKB(ctx);
531    return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
532}
533
534static bool trans_packh(DisasContext *ctx, arg_packh *a)
535{
536    REQUIRE_ZBKB(ctx);
537    return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
538}
539
540static bool trans_packw(DisasContext *ctx, arg_packw *a)
541{
542    REQUIRE_64BIT(ctx);
543    REQUIRE_ZBKB(ctx);
544    return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
545}
546
547static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
548{
549    REQUIRE_32BIT(ctx);
550    REQUIRE_ZBKB(ctx);
551    return gen_unary(ctx, a, EXT_NONE, gen_helper_unzip);
552}
553
554static bool trans_zip(DisasContext *ctx, arg_zip *a)
555{
556    REQUIRE_32BIT(ctx);
557    REQUIRE_ZBKB(ctx);
558    return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
559}
560
561static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a)
562{
563    REQUIRE_ZBKX(ctx);
564    return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL);
565}
566
567static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
568{
569    REQUIRE_ZBKX(ctx);
570    return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
571}
572