1/*
2 * RISC-V translation routines for the RV64F Standard Extension.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_FPU do {\
22    if (ctx->mstatus_fs == 0) \
23        if (!ctx->cfg_ptr->ext_zfinx) \
24            return false; \
25} while (0)
26
27#define REQUIRE_ZFINX_OR_F(ctx) do {\
28    if (!ctx->cfg_ptr->ext_zfinx) { \
29        REQUIRE_EXT(ctx, RVF); \
30    } \
31} while (0)
32
33static bool trans_flw(DisasContext *ctx, arg_flw *a)
34{
35    TCGv_i64 dest;
36    TCGv addr;
37
38    REQUIRE_FPU;
39    REQUIRE_EXT(ctx, RVF);
40
41    decode_save_opc(ctx);
42    addr = get_address(ctx, a->rs1, a->imm);
43    dest = cpu_fpr[a->rd];
44    tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
45    gen_nanbox_s(dest, dest);
46
47    mark_fs_dirty(ctx);
48    return true;
49}
50
51static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
52{
53    TCGv addr;
54
55    REQUIRE_FPU;
56    REQUIRE_EXT(ctx, RVF);
57
58    decode_save_opc(ctx);
59    addr = get_address(ctx, a->rs1, a->imm);
60    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
61    return true;
62}
63
64static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
65{
66    REQUIRE_FPU;
67    REQUIRE_ZFINX_OR_F(ctx);
68
69    TCGv_i64 dest = dest_fpr(ctx, a->rd);
70    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
71    TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
72    TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
73
74    gen_set_rm(ctx, a->rm);
75    gen_helper_fmadd_s(dest, cpu_env, src1, src2, src3);
76    gen_set_fpr_hs(ctx, a->rd, dest);
77    mark_fs_dirty(ctx);
78    return true;
79}
80
81static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
82{
83    REQUIRE_FPU;
84    REQUIRE_ZFINX_OR_F(ctx);
85
86    TCGv_i64 dest = dest_fpr(ctx, a->rd);
87    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
88    TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
89    TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
90
91    gen_set_rm(ctx, a->rm);
92    gen_helper_fmsub_s(dest, cpu_env, src1, src2, src3);
93    gen_set_fpr_hs(ctx, a->rd, dest);
94    mark_fs_dirty(ctx);
95    return true;
96}
97
98static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
99{
100    REQUIRE_FPU;
101    REQUIRE_ZFINX_OR_F(ctx);
102
103    TCGv_i64 dest = dest_fpr(ctx, a->rd);
104    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
105    TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
106    TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
107
108    gen_set_rm(ctx, a->rm);
109    gen_helper_fnmsub_s(dest, cpu_env, src1, src2, src3);
110    gen_set_fpr_hs(ctx, a->rd, dest);
111    mark_fs_dirty(ctx);
112    return true;
113}
114
115static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
116{
117    REQUIRE_FPU;
118    REQUIRE_ZFINX_OR_F(ctx);
119
120    TCGv_i64 dest = dest_fpr(ctx, a->rd);
121    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
122    TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
123    TCGv_i64 src3 = get_fpr_hs(ctx, a->rs3);
124
125    gen_set_rm(ctx, a->rm);
126    gen_helper_fnmadd_s(dest, cpu_env, src1, src2, src3);
127    gen_set_fpr_hs(ctx, a->rd, dest);
128    mark_fs_dirty(ctx);
129    return true;
130}
131
132static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
133{
134    REQUIRE_FPU;
135    REQUIRE_ZFINX_OR_F(ctx);
136
137    TCGv_i64 dest = dest_fpr(ctx, a->rd);
138    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
139    TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
140
141    gen_set_rm(ctx, a->rm);
142    gen_helper_fadd_s(dest, cpu_env, src1, src2);
143    gen_set_fpr_hs(ctx, a->rd, dest);
144    mark_fs_dirty(ctx);
145    return true;
146}
147
148static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
149{
150    REQUIRE_FPU;
151    REQUIRE_ZFINX_OR_F(ctx);
152
153    TCGv_i64 dest = dest_fpr(ctx, a->rd);
154    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
155    TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
156
157    gen_set_rm(ctx, a->rm);
158    gen_helper_fsub_s(dest, cpu_env, src1, src2);
159    gen_set_fpr_hs(ctx, a->rd, dest);
160    mark_fs_dirty(ctx);
161    return true;
162}
163
164static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
165{
166    REQUIRE_FPU;
167    REQUIRE_ZFINX_OR_F(ctx);
168
169    TCGv_i64 dest = dest_fpr(ctx, a->rd);
170    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
171    TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
172
173    gen_set_rm(ctx, a->rm);
174    gen_helper_fmul_s(dest, cpu_env, src1, src2);
175    gen_set_fpr_hs(ctx, a->rd, dest);
176    mark_fs_dirty(ctx);
177    return true;
178}
179
180static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
181{
182    REQUIRE_FPU;
183    REQUIRE_ZFINX_OR_F(ctx);
184
185    TCGv_i64 dest = dest_fpr(ctx, a->rd);
186    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
187    TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
188
189    gen_set_rm(ctx, a->rm);
190    gen_helper_fdiv_s(dest, cpu_env, src1, src2);
191    gen_set_fpr_hs(ctx, a->rd, dest);
192    mark_fs_dirty(ctx);
193    return true;
194}
195
196static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
197{
198    REQUIRE_FPU;
199    REQUIRE_ZFINX_OR_F(ctx);
200
201    TCGv_i64 dest = dest_fpr(ctx, a->rd);
202    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
203
204    gen_set_rm(ctx, a->rm);
205    gen_helper_fsqrt_s(dest, cpu_env, src1);
206    gen_set_fpr_hs(ctx, a->rd, dest);
207    mark_fs_dirty(ctx);
208    return true;
209}
210
211static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
212{
213    REQUIRE_FPU;
214    REQUIRE_ZFINX_OR_F(ctx);
215
216    TCGv_i64 dest = dest_fpr(ctx, a->rd);
217    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
218
219    if (a->rs1 == a->rs2) { /* FMOV */
220        if (!ctx->cfg_ptr->ext_zfinx) {
221            gen_check_nanbox_s(dest, src1);
222        } else {
223            tcg_gen_ext32s_i64(dest, src1);
224        }
225    } else { /* FSGNJ */
226        TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
227
228        if (!ctx->cfg_ptr->ext_zfinx) {
229            TCGv_i64 rs1 = tcg_temp_new_i64();
230            TCGv_i64 rs2 = tcg_temp_new_i64();
231            gen_check_nanbox_s(rs1, src1);
232            gen_check_nanbox_s(rs2, src2);
233
234            /* This formulation retains the nanboxing of rs2 in normal 'F'. */
235            tcg_gen_deposit_i64(dest, rs2, rs1, 0, 31);
236        } else {
237            tcg_gen_deposit_i64(dest, src2, src1, 0, 31);
238            tcg_gen_ext32s_i64(dest, dest);
239        }
240    }
241    gen_set_fpr_hs(ctx, a->rd, dest);
242    mark_fs_dirty(ctx);
243    return true;
244}
245
246static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
247{
248    TCGv_i64 rs1, rs2, mask;
249
250    REQUIRE_FPU;
251    REQUIRE_ZFINX_OR_F(ctx);
252
253    TCGv_i64 dest = dest_fpr(ctx, a->rd);
254    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
255
256    rs1 = tcg_temp_new_i64();
257    if (!ctx->cfg_ptr->ext_zfinx) {
258        gen_check_nanbox_s(rs1, src1);
259    } else {
260        tcg_gen_mov_i64(rs1, src1);
261    }
262    if (a->rs1 == a->rs2) { /* FNEG */
263        tcg_gen_xori_i64(dest, rs1, MAKE_64BIT_MASK(31, 1));
264    } else {
265        TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
266        rs2 = tcg_temp_new_i64();
267        if (!ctx->cfg_ptr->ext_zfinx) {
268            gen_check_nanbox_s(rs2, src2);
269        } else {
270            tcg_gen_mov_i64(rs2, src2);
271        }
272
273        /*
274         * Replace bit 31 in rs1 with inverse in rs2.
275         * This formulation retains the nanboxing of rs1.
276         */
277        mask = tcg_constant_i64(~MAKE_64BIT_MASK(31, 1));
278        tcg_gen_nor_i64(rs2, rs2, mask);
279        tcg_gen_and_i64(dest, mask, rs1);
280        tcg_gen_or_i64(dest, dest, rs2);
281    }
282    /* signed-extended intead of nanboxing for result if enable zfinx */
283    if (ctx->cfg_ptr->ext_zfinx) {
284        tcg_gen_ext32s_i64(dest, dest);
285    }
286    gen_set_fpr_hs(ctx, a->rd, dest);
287    mark_fs_dirty(ctx);
288    return true;
289}
290
291static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
292{
293    TCGv_i64 rs1, rs2;
294
295    REQUIRE_FPU;
296    REQUIRE_ZFINX_OR_F(ctx);
297
298    TCGv_i64 dest = dest_fpr(ctx, a->rd);
299    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
300    rs1 = tcg_temp_new_i64();
301
302    if (!ctx->cfg_ptr->ext_zfinx) {
303        gen_check_nanbox_s(rs1, src1);
304    } else {
305        tcg_gen_mov_i64(rs1, src1);
306    }
307
308    if (a->rs1 == a->rs2) { /* FABS */
309        tcg_gen_andi_i64(dest, rs1, ~MAKE_64BIT_MASK(31, 1));
310    } else {
311        TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
312        rs2 = tcg_temp_new_i64();
313
314        if (!ctx->cfg_ptr->ext_zfinx) {
315            gen_check_nanbox_s(rs2, src2);
316        } else {
317            tcg_gen_mov_i64(rs2, src2);
318        }
319
320        /*
321         * Xor bit 31 in rs1 with that in rs2.
322         * This formulation retains the nanboxing of rs1.
323         */
324        tcg_gen_andi_i64(dest, rs2, MAKE_64BIT_MASK(31, 1));
325        tcg_gen_xor_i64(dest, rs1, dest);
326    }
327    /* signed-extended intead of nanboxing for result if enable zfinx */
328    if (ctx->cfg_ptr->ext_zfinx) {
329        tcg_gen_ext32s_i64(dest, dest);
330    }
331    gen_set_fpr_hs(ctx, a->rd, dest);
332    mark_fs_dirty(ctx);
333    return true;
334}
335
336static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
337{
338    REQUIRE_FPU;
339    REQUIRE_ZFINX_OR_F(ctx);
340
341    TCGv_i64 dest = dest_fpr(ctx, a->rd);
342    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
343    TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
344
345    gen_helper_fmin_s(dest, cpu_env, src1, src2);
346    gen_set_fpr_hs(ctx, a->rd, dest);
347    mark_fs_dirty(ctx);
348    return true;
349}
350
351static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
352{
353    REQUIRE_FPU;
354    REQUIRE_ZFINX_OR_F(ctx);
355
356    TCGv_i64 dest = dest_fpr(ctx, a->rd);
357    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
358    TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
359
360    gen_helper_fmax_s(dest, cpu_env, src1, src2);
361    gen_set_fpr_hs(ctx, a->rd, dest);
362    mark_fs_dirty(ctx);
363    return true;
364}
365
366static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
367{
368    REQUIRE_FPU;
369    REQUIRE_ZFINX_OR_F(ctx);
370
371    TCGv dest = dest_gpr(ctx, a->rd);
372    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
373
374    gen_set_rm(ctx, a->rm);
375    gen_helper_fcvt_w_s(dest, cpu_env, src1);
376    gen_set_gpr(ctx, a->rd, dest);
377    return true;
378}
379
380static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
381{
382    REQUIRE_FPU;
383    REQUIRE_ZFINX_OR_F(ctx);
384
385    TCGv dest = dest_gpr(ctx, a->rd);
386    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
387
388    gen_set_rm(ctx, a->rm);
389    gen_helper_fcvt_wu_s(dest, cpu_env, src1);
390    gen_set_gpr(ctx, a->rd, dest);
391    return true;
392}
393
394static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
395{
396    /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
397    REQUIRE_FPU;
398    REQUIRE_ZFINX_OR_F(ctx);
399
400    TCGv dest = dest_gpr(ctx, a->rd);
401    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
402#if defined(TARGET_RISCV64)
403    tcg_gen_ext32s_tl(dest, src1);
404#else
405    tcg_gen_extrl_i64_i32(dest, src1);
406#endif
407
408    gen_set_gpr(ctx, a->rd, dest);
409    return true;
410}
411
412static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
413{
414    REQUIRE_FPU;
415    REQUIRE_ZFINX_OR_F(ctx);
416
417    TCGv dest = dest_gpr(ctx, a->rd);
418    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
419    TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
420
421    gen_helper_feq_s(dest, cpu_env, src1, src2);
422    gen_set_gpr(ctx, a->rd, dest);
423    return true;
424}
425
426static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
427{
428    REQUIRE_FPU;
429    REQUIRE_ZFINX_OR_F(ctx);
430
431    TCGv dest = dest_gpr(ctx, a->rd);
432    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
433    TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
434
435    gen_helper_flt_s(dest, cpu_env, src1, src2);
436    gen_set_gpr(ctx, a->rd, dest);
437    return true;
438}
439
440static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
441{
442    REQUIRE_FPU;
443    REQUIRE_ZFINX_OR_F(ctx);
444
445    TCGv dest = dest_gpr(ctx, a->rd);
446    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
447    TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
448
449    gen_helper_fle_s(dest, cpu_env, src1, src2);
450    gen_set_gpr(ctx, a->rd, dest);
451    return true;
452}
453
454static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
455{
456    REQUIRE_FPU;
457    REQUIRE_ZFINX_OR_F(ctx);
458
459    TCGv dest = dest_gpr(ctx, a->rd);
460    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
461
462    gen_helper_fclass_s(dest, cpu_env, src1);
463    gen_set_gpr(ctx, a->rd, dest);
464    return true;
465}
466
467static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
468{
469    REQUIRE_FPU;
470    REQUIRE_ZFINX_OR_F(ctx);
471
472    TCGv_i64 dest = dest_fpr(ctx, a->rd);
473    TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
474
475    gen_set_rm(ctx, a->rm);
476    gen_helper_fcvt_s_w(dest, cpu_env, src);
477    gen_set_fpr_hs(ctx, a->rd, dest);
478    mark_fs_dirty(ctx);
479    return true;
480}
481
482static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
483{
484    REQUIRE_FPU;
485    REQUIRE_ZFINX_OR_F(ctx);
486
487    TCGv_i64 dest = dest_fpr(ctx, a->rd);
488    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
489
490    gen_set_rm(ctx, a->rm);
491    gen_helper_fcvt_s_wu(dest, cpu_env, src);
492    gen_set_fpr_hs(ctx, a->rd, dest);
493    mark_fs_dirty(ctx);
494    return true;
495}
496
497static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
498{
499    /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
500    REQUIRE_FPU;
501    REQUIRE_ZFINX_OR_F(ctx);
502
503    TCGv_i64 dest = dest_fpr(ctx, a->rd);
504    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
505
506    tcg_gen_extu_tl_i64(dest, src);
507    gen_nanbox_s(dest, dest);
508    gen_set_fpr_hs(ctx, a->rd, dest);
509    mark_fs_dirty(ctx);
510    return true;
511}
512
513static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
514{
515    REQUIRE_64BIT(ctx);
516    REQUIRE_FPU;
517    REQUIRE_ZFINX_OR_F(ctx);
518
519    TCGv dest = dest_gpr(ctx, a->rd);
520    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
521
522    gen_set_rm(ctx, a->rm);
523    gen_helper_fcvt_l_s(dest, cpu_env, src1);
524    gen_set_gpr(ctx, a->rd, dest);
525    return true;
526}
527
528static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
529{
530    REQUIRE_64BIT(ctx);
531    REQUIRE_FPU;
532    REQUIRE_ZFINX_OR_F(ctx);
533
534    TCGv dest = dest_gpr(ctx, a->rd);
535    TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
536
537    gen_set_rm(ctx, a->rm);
538    gen_helper_fcvt_lu_s(dest, cpu_env, src1);
539    gen_set_gpr(ctx, a->rd, dest);
540    return true;
541}
542
543static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
544{
545    REQUIRE_64BIT(ctx);
546    REQUIRE_FPU;
547    REQUIRE_ZFINX_OR_F(ctx);
548
549    TCGv_i64 dest = dest_fpr(ctx, a->rd);
550    TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
551
552    gen_set_rm(ctx, a->rm);
553    gen_helper_fcvt_s_l(dest, cpu_env, src);
554    gen_set_fpr_hs(ctx, a->rd, dest);
555    mark_fs_dirty(ctx);
556    return true;
557}
558
559static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
560{
561    REQUIRE_64BIT(ctx);
562    REQUIRE_FPU;
563    REQUIRE_ZFINX_OR_F(ctx);
564
565    TCGv_i64 dest = dest_fpr(ctx, a->rd);
566    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
567
568    gen_set_rm(ctx, a->rm);
569    gen_helper_fcvt_s_lu(dest, cpu_env, src);
570    gen_set_fpr_hs(ctx, a->rd, dest);
571    mark_fs_dirty(ctx);
572    return true;
573}
574