1/*
2 * RISC-V translation routines for the RVXI Base Integer Instruction Set.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21static bool trans_illegal(DisasContext *ctx, arg_empty *a)
22{
23    gen_exception_illegal(ctx);
24    return true;
25}
26
27static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
28{
29    REQUIRE_64_OR_128BIT(ctx);
30    return trans_illegal(ctx, a);
31}
32
33static bool trans_lui(DisasContext *ctx, arg_lui *a)
34{
35    gen_set_gpri(ctx, a->rd, a->imm);
36    return true;
37}
38
39static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
40{
41    TCGv target_pc = dest_gpr(ctx, a->rd);
42    gen_pc_plus_diff(target_pc, ctx, a->imm);
43    gen_set_gpr(ctx, a->rd, target_pc);
44    return true;
45}
46
47static bool trans_jal(DisasContext *ctx, arg_jal *a)
48{
49    gen_jal(ctx, a->rd, a->imm);
50    return true;
51}
52
53static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
54{
55    TCGLabel *misaligned = NULL;
56    TCGv target_pc = tcg_temp_new();
57    TCGv succ_pc = dest_gpr(ctx, a->rd);
58
59    tcg_gen_addi_tl(target_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
60    tcg_gen_andi_tl(target_pc, target_pc, (target_ulong)-2);
61
62    if (get_xl(ctx) == MXL_RV32) {
63        tcg_gen_ext32s_tl(target_pc, target_pc);
64    }
65
66    if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
67        TCGv t0 = tcg_temp_new();
68
69        misaligned = gen_new_label();
70        tcg_gen_andi_tl(t0, target_pc, 0x2);
71        tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
72    }
73
74    gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
75    gen_set_gpr(ctx, a->rd, succ_pc);
76
77    tcg_gen_mov_tl(cpu_pc, target_pc);
78    lookup_and_goto_ptr(ctx);
79
80    if (misaligned) {
81        gen_set_label(misaligned);
82        gen_exception_inst_addr_mis(ctx, target_pc);
83    }
84    ctx->base.is_jmp = DISAS_NORETURN;
85
86    return true;
87}
88
89static TCGCond gen_compare_i128(bool bz, TCGv rl,
90                                TCGv al, TCGv ah, TCGv bl, TCGv bh,
91                                TCGCond cond)
92{
93    TCGv rh = tcg_temp_new();
94    bool invert = false;
95
96    switch (cond) {
97    case TCG_COND_EQ:
98    case TCG_COND_NE:
99        if (bz) {
100            tcg_gen_or_tl(rl, al, ah);
101        } else {
102            tcg_gen_xor_tl(rl, al, bl);
103            tcg_gen_xor_tl(rh, ah, bh);
104            tcg_gen_or_tl(rl, rl, rh);
105        }
106        break;
107
108    case TCG_COND_GE:
109    case TCG_COND_LT:
110        if (bz) {
111            tcg_gen_mov_tl(rl, ah);
112        } else {
113            TCGv tmp = tcg_temp_new();
114
115            tcg_gen_sub2_tl(rl, rh, al, ah, bl, bh);
116            tcg_gen_xor_tl(rl, rh, ah);
117            tcg_gen_xor_tl(tmp, ah, bh);
118            tcg_gen_and_tl(rl, rl, tmp);
119            tcg_gen_xor_tl(rl, rh, rl);
120        }
121        break;
122
123    case TCG_COND_LTU:
124        invert = true;
125        /* fallthrough */
126    case TCG_COND_GEU:
127        {
128            TCGv tmp = tcg_temp_new();
129            TCGv zero = tcg_constant_tl(0);
130            TCGv one = tcg_constant_tl(1);
131
132            cond = TCG_COND_NE;
133            /* borrow in to second word */
134            tcg_gen_setcond_tl(TCG_COND_LTU, tmp, al, bl);
135            /* seed third word with 1, which will be result */
136            tcg_gen_sub2_tl(tmp, rh, ah, one, tmp, zero);
137            tcg_gen_sub2_tl(tmp, rl, tmp, rh, bh, zero);
138        }
139        break;
140
141    default:
142        g_assert_not_reached();
143    }
144
145    if (invert) {
146        cond = tcg_invert_cond(cond);
147    }
148    return cond;
149}
150
151static void gen_setcond_i128(TCGv rl, TCGv rh,
152                             TCGv src1l, TCGv src1h,
153                             TCGv src2l, TCGv src2h,
154                             TCGCond cond)
155{
156    cond = gen_compare_i128(false, rl, src1l, src1h, src2l, src2h, cond);
157    tcg_gen_setcondi_tl(cond, rl, rl, 0);
158    tcg_gen_movi_tl(rh, 0);
159}
160
161static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
162{
163    TCGLabel *l = gen_new_label();
164    TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
165    TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
166    target_ulong orig_pc_save = ctx->pc_save;
167
168    if (get_xl(ctx) == MXL_RV128) {
169        TCGv src1h = get_gprh(ctx, a->rs1);
170        TCGv src2h = get_gprh(ctx, a->rs2);
171        TCGv tmp = tcg_temp_new();
172
173        cond = gen_compare_i128(a->rs2 == 0,
174                                tmp, src1, src1h, src2, src2h, cond);
175        tcg_gen_brcondi_tl(cond, tmp, 0, l);
176    } else {
177        tcg_gen_brcond_tl(cond, src1, src2, l);
178    }
179    gen_goto_tb(ctx, 1, ctx->cur_insn_len);
180    ctx->pc_save = orig_pc_save;
181
182    gen_set_label(l); /* branch taken */
183
184    if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca &&
185        (a->imm & 0x3)) {
186        /* misaligned */
187        TCGv target_pc = tcg_temp_new();
188        gen_pc_plus_diff(target_pc, ctx, a->imm);
189        gen_exception_inst_addr_mis(ctx, target_pc);
190    } else {
191        gen_goto_tb(ctx, 0, a->imm);
192    }
193    ctx->pc_save = -1;
194    ctx->base.is_jmp = DISAS_NORETURN;
195
196    return true;
197}
198
199static bool trans_beq(DisasContext *ctx, arg_beq *a)
200{
201    return gen_branch(ctx, a, TCG_COND_EQ);
202}
203
204static bool trans_bne(DisasContext *ctx, arg_bne *a)
205{
206    return gen_branch(ctx, a, TCG_COND_NE);
207}
208
209static bool trans_blt(DisasContext *ctx, arg_blt *a)
210{
211    return gen_branch(ctx, a, TCG_COND_LT);
212}
213
214static bool trans_bge(DisasContext *ctx, arg_bge *a)
215{
216    return gen_branch(ctx, a, TCG_COND_GE);
217}
218
219static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
220{
221    return gen_branch(ctx, a, TCG_COND_LTU);
222}
223
224static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
225{
226    return gen_branch(ctx, a, TCG_COND_GEU);
227}
228
229static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
230{
231    TCGv dest = dest_gpr(ctx, a->rd);
232    TCGv addr = get_address(ctx, a->rs1, a->imm);
233
234    tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
235    gen_set_gpr(ctx, a->rd, dest);
236    return true;
237}
238
239/* Compute only 64-bit addresses to use the address translation mechanism */
240static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
241{
242    TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
243    TCGv destl = dest_gpr(ctx, a->rd);
244    TCGv desth = dest_gprh(ctx, a->rd);
245    TCGv addrl = tcg_temp_new();
246
247    tcg_gen_addi_tl(addrl, src1l, a->imm);
248
249    if ((memop & MO_SIZE) <= MO_64) {
250        tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, memop);
251        if (memop & MO_SIGN) {
252            tcg_gen_sari_tl(desth, destl, 63);
253        } else {
254            tcg_gen_movi_tl(desth, 0);
255        }
256    } else {
257        /* assume little-endian memory access for now */
258        tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, MO_TEUQ);
259        tcg_gen_addi_tl(addrl, addrl, 8);
260        tcg_gen_qemu_ld_tl(desth, addrl, ctx->mem_idx, MO_TEUQ);
261    }
262
263    gen_set_gpr128(ctx, a->rd, destl, desth);
264    return true;
265}
266
267static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
268{
269    decode_save_opc(ctx);
270    if (get_xl(ctx) == MXL_RV128) {
271        return gen_load_i128(ctx, a, memop);
272    } else {
273        return gen_load_tl(ctx, a, memop);
274    }
275}
276
277static bool trans_lb(DisasContext *ctx, arg_lb *a)
278{
279    return gen_load(ctx, a, MO_SB);
280}
281
282static bool trans_lh(DisasContext *ctx, arg_lh *a)
283{
284    return gen_load(ctx, a, MO_TESW);
285}
286
287static bool trans_lw(DisasContext *ctx, arg_lw *a)
288{
289    return gen_load(ctx, a, MO_TESL);
290}
291
292static bool trans_ld(DisasContext *ctx, arg_ld *a)
293{
294    REQUIRE_64_OR_128BIT(ctx);
295    return gen_load(ctx, a, MO_TESQ);
296}
297
298static bool trans_lq(DisasContext *ctx, arg_lq *a)
299{
300    REQUIRE_128BIT(ctx);
301    return gen_load(ctx, a, MO_TEUO);
302}
303
304static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
305{
306    return gen_load(ctx, a, MO_UB);
307}
308
309static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
310{
311    return gen_load(ctx, a, MO_TEUW);
312}
313
314static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
315{
316    REQUIRE_64_OR_128BIT(ctx);
317    return gen_load(ctx, a, MO_TEUL);
318}
319
320static bool trans_ldu(DisasContext *ctx, arg_ldu *a)
321{
322    REQUIRE_128BIT(ctx);
323    return gen_load(ctx, a, MO_TEUQ);
324}
325
326static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
327{
328    TCGv addr = get_address(ctx, a->rs1, a->imm);
329    TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
330
331    tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
332    return true;
333}
334
335static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
336{
337    TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
338    TCGv src2l = get_gpr(ctx, a->rs2, EXT_NONE);
339    TCGv src2h = get_gprh(ctx, a->rs2);
340    TCGv addrl = tcg_temp_new();
341
342    tcg_gen_addi_tl(addrl, src1l, a->imm);
343
344    if ((memop & MO_SIZE) <= MO_64) {
345        tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop);
346    } else {
347        /* little-endian memory access assumed for now */
348        tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, MO_TEUQ);
349        tcg_gen_addi_tl(addrl, addrl, 8);
350        tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, MO_TEUQ);
351    }
352    return true;
353}
354
355static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
356{
357    decode_save_opc(ctx);
358    if (get_xl(ctx) == MXL_RV128) {
359        return gen_store_i128(ctx, a, memop);
360    } else {
361        return gen_store_tl(ctx, a, memop);
362    }
363}
364
365static bool trans_sb(DisasContext *ctx, arg_sb *a)
366{
367    return gen_store(ctx, a, MO_SB);
368}
369
370static bool trans_sh(DisasContext *ctx, arg_sh *a)
371{
372    return gen_store(ctx, a, MO_TESW);
373}
374
375static bool trans_sw(DisasContext *ctx, arg_sw *a)
376{
377    return gen_store(ctx, a, MO_TESL);
378}
379
380static bool trans_sd(DisasContext *ctx, arg_sd *a)
381{
382    REQUIRE_64_OR_128BIT(ctx);
383    return gen_store(ctx, a, MO_TEUQ);
384}
385
386static bool trans_sq(DisasContext *ctx, arg_sq *a)
387{
388    REQUIRE_128BIT(ctx);
389    return gen_store(ctx, a, MO_TEUO);
390}
391
392static bool trans_addd(DisasContext *ctx, arg_addd *a)
393{
394    REQUIRE_128BIT(ctx);
395    ctx->ol = MXL_RV64;
396    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, NULL);
397}
398
399static bool trans_addid(DisasContext *ctx, arg_addid *a)
400{
401    REQUIRE_128BIT(ctx);
402    ctx->ol = MXL_RV64;
403    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, NULL);
404}
405
406static bool trans_subd(DisasContext *ctx, arg_subd *a)
407{
408    REQUIRE_128BIT(ctx);
409    ctx->ol = MXL_RV64;
410    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, NULL);
411}
412
413static void gen_addi2_i128(TCGv retl, TCGv reth,
414                           TCGv srcl, TCGv srch, target_long imm)
415{
416    TCGv imml  = tcg_constant_tl(imm);
417    TCGv immh  = tcg_constant_tl(-(imm < 0));
418    tcg_gen_add2_tl(retl, reth, srcl, srch, imml, immh);
419}
420
421static bool trans_addi(DisasContext *ctx, arg_addi *a)
422{
423    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, gen_addi2_i128);
424}
425
426static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
427{
428    tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
429}
430
431static void gen_slt_i128(TCGv retl, TCGv reth,
432                         TCGv s1l, TCGv s1h, TCGv s2l, TCGv s2h)
433{
434    gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LT);
435}
436
437static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
438{
439    tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
440}
441
442static void gen_sltu_i128(TCGv retl, TCGv reth,
443                          TCGv s1l, TCGv s1h, TCGv s2l, TCGv s2h)
444{
445    gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LTU);
446}
447
448static bool trans_slti(DisasContext *ctx, arg_slti *a)
449{
450    return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt, gen_slt_i128);
451}
452
453static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
454{
455    return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu, gen_sltu_i128);
456}
457
458static bool trans_xori(DisasContext *ctx, arg_xori *a)
459{
460    return gen_logic_imm_fn(ctx, a, tcg_gen_xori_tl);
461}
462
463static bool trans_ori(DisasContext *ctx, arg_ori *a)
464{
465    return gen_logic_imm_fn(ctx, a, tcg_gen_ori_tl);
466}
467
468static bool trans_andi(DisasContext *ctx, arg_andi *a)
469{
470    return gen_logic_imm_fn(ctx, a, tcg_gen_andi_tl);
471}
472
473static void gen_slli_i128(TCGv retl, TCGv reth,
474                          TCGv src1l, TCGv src1h,
475                          target_long shamt)
476{
477    if (shamt >= 64) {
478        tcg_gen_shli_tl(reth, src1l, shamt - 64);
479        tcg_gen_movi_tl(retl, 0);
480    } else {
481        tcg_gen_extract2_tl(reth, src1l, src1h, 64 - shamt);
482        tcg_gen_shli_tl(retl, src1l, shamt);
483    }
484}
485
486static bool trans_slli(DisasContext *ctx, arg_slli *a)
487{
488    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, gen_slli_i128);
489}
490
491static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
492{
493    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
494}
495
496static void gen_srli_i128(TCGv retl, TCGv reth,
497                          TCGv src1l, TCGv src1h,
498                          target_long shamt)
499{
500    if (shamt >= 64) {
501        tcg_gen_shri_tl(retl, src1h, shamt - 64);
502        tcg_gen_movi_tl(reth, 0);
503    } else {
504        tcg_gen_extract2_tl(retl, src1l, src1h, shamt);
505        tcg_gen_shri_tl(reth, src1h, shamt);
506    }
507}
508
509static bool trans_srli(DisasContext *ctx, arg_srli *a)
510{
511    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
512                                   tcg_gen_shri_tl, gen_srliw, gen_srli_i128);
513}
514
515static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
516{
517    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
518}
519
520static void gen_srai_i128(TCGv retl, TCGv reth,
521                          TCGv src1l, TCGv src1h,
522                          target_long shamt)
523{
524    if (shamt >= 64) {
525        tcg_gen_sari_tl(retl, src1h, shamt - 64);
526        tcg_gen_sari_tl(reth, src1h, 63);
527    } else {
528        tcg_gen_extract2_tl(retl, src1l, src1h, shamt);
529        tcg_gen_sari_tl(reth, src1h, shamt);
530    }
531}
532
533static bool trans_srai(DisasContext *ctx, arg_srai *a)
534{
535    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
536                                   tcg_gen_sari_tl, gen_sraiw, gen_srai_i128);
537}
538
539static bool trans_add(DisasContext *ctx, arg_add *a)
540{
541    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, tcg_gen_add2_tl);
542}
543
544static bool trans_sub(DisasContext *ctx, arg_sub *a)
545{
546    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, tcg_gen_sub2_tl);
547}
548
549static void gen_sll_i128(TCGv destl, TCGv desth,
550                         TCGv src1l, TCGv src1h, TCGv shamt)
551{
552    TCGv ls = tcg_temp_new();
553    TCGv rs = tcg_temp_new();
554    TCGv hs = tcg_temp_new();
555    TCGv ll = tcg_temp_new();
556    TCGv lr = tcg_temp_new();
557    TCGv h0 = tcg_temp_new();
558    TCGv h1 = tcg_temp_new();
559    TCGv zero = tcg_constant_tl(0);
560
561    tcg_gen_andi_tl(hs, shamt, 64);
562    tcg_gen_andi_tl(ls, shamt, 63);
563    tcg_gen_neg_tl(shamt, shamt);
564    tcg_gen_andi_tl(rs, shamt, 63);
565
566    tcg_gen_shl_tl(ll, src1l, ls);
567    tcg_gen_shl_tl(h0, src1h, ls);
568    tcg_gen_shr_tl(lr, src1l, rs);
569    tcg_gen_movcond_tl(TCG_COND_NE, lr, shamt, zero, lr, zero);
570    tcg_gen_or_tl(h1, h0, lr);
571
572    tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, zero, ll);
573    tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, ll, h1);
574}
575
576static bool trans_sll(DisasContext *ctx, arg_sll *a)
577{
578    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, gen_sll_i128);
579}
580
581static bool trans_slt(DisasContext *ctx, arg_slt *a)
582{
583    return gen_arith(ctx, a, EXT_SIGN, gen_slt, gen_slt_i128);
584}
585
586static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
587{
588    return gen_arith(ctx, a, EXT_SIGN, gen_sltu, gen_sltu_i128);
589}
590
591static void gen_srl_i128(TCGv destl, TCGv desth,
592                         TCGv src1l, TCGv src1h, TCGv shamt)
593{
594    TCGv ls = tcg_temp_new();
595    TCGv rs = tcg_temp_new();
596    TCGv hs = tcg_temp_new();
597    TCGv ll = tcg_temp_new();
598    TCGv lr = tcg_temp_new();
599    TCGv h0 = tcg_temp_new();
600    TCGv h1 = tcg_temp_new();
601    TCGv zero = tcg_constant_tl(0);
602
603    tcg_gen_andi_tl(hs, shamt, 64);
604    tcg_gen_andi_tl(rs, shamt, 63);
605    tcg_gen_neg_tl(shamt, shamt);
606    tcg_gen_andi_tl(ls, shamt, 63);
607
608    tcg_gen_shr_tl(lr, src1l, rs);
609    tcg_gen_shr_tl(h1, src1h, rs);
610    tcg_gen_shl_tl(ll, src1h, ls);
611    tcg_gen_movcond_tl(TCG_COND_NE, ll, shamt, zero, ll, zero);
612    tcg_gen_or_tl(h0, ll, lr);
613
614    tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, h1, h0);
615    tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, zero, h1);
616}
617
618static bool trans_srl(DisasContext *ctx, arg_srl *a)
619{
620    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, gen_srl_i128);
621}
622
623static void gen_sra_i128(TCGv destl, TCGv desth,
624                         TCGv src1l, TCGv src1h, TCGv shamt)
625{
626    TCGv ls = tcg_temp_new();
627    TCGv rs = tcg_temp_new();
628    TCGv hs = tcg_temp_new();
629    TCGv ll = tcg_temp_new();
630    TCGv lr = tcg_temp_new();
631    TCGv h0 = tcg_temp_new();
632    TCGv h1 = tcg_temp_new();
633    TCGv zero = tcg_constant_tl(0);
634
635    tcg_gen_andi_tl(hs, shamt, 64);
636    tcg_gen_andi_tl(rs, shamt, 63);
637    tcg_gen_neg_tl(shamt, shamt);
638    tcg_gen_andi_tl(ls, shamt, 63);
639
640    tcg_gen_shr_tl(lr, src1l, rs);
641    tcg_gen_sar_tl(h1, src1h, rs);
642    tcg_gen_shl_tl(ll, src1h, ls);
643    tcg_gen_movcond_tl(TCG_COND_NE, ll, shamt, zero, ll, zero);
644    tcg_gen_or_tl(h0, ll, lr);
645    tcg_gen_sari_tl(lr, src1h, 63);
646
647    tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, h1, h0);
648    tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, lr, h1);
649}
650
651static bool trans_sra(DisasContext *ctx, arg_sra *a)
652{
653    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, gen_sra_i128);
654}
655
656static bool trans_xor(DisasContext *ctx, arg_xor *a)
657{
658    return gen_logic(ctx, a, tcg_gen_xor_tl);
659}
660
661static bool trans_or(DisasContext *ctx, arg_or *a)
662{
663    return gen_logic(ctx, a, tcg_gen_or_tl);
664}
665
666static bool trans_and(DisasContext *ctx, arg_and *a)
667{
668    return gen_logic(ctx, a, tcg_gen_and_tl);
669}
670
671static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
672{
673    REQUIRE_64_OR_128BIT(ctx);
674    ctx->ol = MXL_RV32;
675    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, NULL);
676}
677
678static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
679{
680    REQUIRE_64_OR_128BIT(ctx);
681    ctx->ol = MXL_RV32;
682    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, NULL);
683}
684
685static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
686{
687    REQUIRE_64_OR_128BIT(ctx);
688    ctx->ol = MXL_RV32;
689    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw, NULL);
690}
691
692static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
693{
694    REQUIRE_64_OR_128BIT(ctx);
695    ctx->ol = MXL_RV32;
696    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw, NULL);
697}
698
699static bool trans_sllid(DisasContext *ctx, arg_sllid *a)
700{
701    REQUIRE_128BIT(ctx);
702    ctx->ol = MXL_RV64;
703    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, NULL);
704}
705
706static bool trans_srlid(DisasContext *ctx, arg_srlid *a)
707{
708    REQUIRE_128BIT(ctx);
709    ctx->ol = MXL_RV64;
710    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shri_tl, NULL);
711}
712
713static bool trans_sraid(DisasContext *ctx, arg_sraid *a)
714{
715    REQUIRE_128BIT(ctx);
716    ctx->ol = MXL_RV64;
717    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_sari_tl,  NULL);
718}
719
720static bool trans_addw(DisasContext *ctx, arg_addw *a)
721{
722    REQUIRE_64_OR_128BIT(ctx);
723    ctx->ol = MXL_RV32;
724    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, NULL);
725}
726
727static bool trans_subw(DisasContext *ctx, arg_subw *a)
728{
729    REQUIRE_64_OR_128BIT(ctx);
730    ctx->ol = MXL_RV32;
731    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, NULL);
732}
733
734static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
735{
736    REQUIRE_64_OR_128BIT(ctx);
737    ctx->ol = MXL_RV32;
738    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, NULL);
739}
740
741static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
742{
743    REQUIRE_64_OR_128BIT(ctx);
744    ctx->ol = MXL_RV32;
745    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, NULL);
746}
747
748static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
749{
750    REQUIRE_64_OR_128BIT(ctx);
751    ctx->ol = MXL_RV32;
752    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
753}
754
755static bool trans_slld(DisasContext *ctx, arg_slld *a)
756{
757    REQUIRE_128BIT(ctx);
758    ctx->ol = MXL_RV64;
759    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, NULL);
760}
761
762static bool trans_srld(DisasContext *ctx, arg_srld *a)
763{
764    REQUIRE_128BIT(ctx);
765    ctx->ol = MXL_RV64;
766    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, NULL);
767}
768
769static bool trans_srad(DisasContext *ctx, arg_srad *a)
770{
771    REQUIRE_128BIT(ctx);
772    ctx->ol = MXL_RV64;
773    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
774}
775
776static bool trans_pause(DisasContext *ctx, arg_pause *a)
777{
778    if (!ctx->cfg_ptr->ext_zihintpause) {
779        return false;
780    }
781
782    /*
783     * PAUSE is a no-op in QEMU,
784     * end the TB and return to main loop
785     */
786    gen_update_pc(ctx, ctx->cur_insn_len);
787    exit_tb(ctx);
788    ctx->base.is_jmp = DISAS_NORETURN;
789
790    return true;
791}
792
793static bool trans_fence(DisasContext *ctx, arg_fence *a)
794{
795    /* FENCE is a full memory barrier. */
796    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
797    return true;
798}
799
800static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
801{
802    if (!ctx->cfg_ptr->ext_ifencei) {
803        return false;
804    }
805
806    /*
807     * FENCE_I is a no-op in QEMU,
808     * however we need to end the translation block
809     */
810    gen_update_pc(ctx, ctx->cur_insn_len);
811    exit_tb(ctx);
812    ctx->base.is_jmp = DISAS_NORETURN;
813    return true;
814}
815
816static bool do_csr_post(DisasContext *ctx)
817{
818    /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
819    decode_save_opc(ctx);
820    /* We may have changed important cpu state -- exit to main loop. */
821    gen_update_pc(ctx, ctx->cur_insn_len);
822    exit_tb(ctx);
823    ctx->base.is_jmp = DISAS_NORETURN;
824    return true;
825}
826
827static bool do_csrr(DisasContext *ctx, int rd, int rc)
828{
829    TCGv dest = dest_gpr(ctx, rd);
830    TCGv_i32 csr = tcg_constant_i32(rc);
831
832    translator_io_start(&ctx->base);
833    gen_helper_csrr(dest, cpu_env, csr);
834    gen_set_gpr(ctx, rd, dest);
835    return do_csr_post(ctx);
836}
837
838static bool do_csrw(DisasContext *ctx, int rc, TCGv src)
839{
840    TCGv_i32 csr = tcg_constant_i32(rc);
841
842    translator_io_start(&ctx->base);
843    gen_helper_csrw(cpu_env, csr, src);
844    return do_csr_post(ctx);
845}
846
847static bool do_csrrw(DisasContext *ctx, int rd, int rc, TCGv src, TCGv mask)
848{
849    TCGv dest = dest_gpr(ctx, rd);
850    TCGv_i32 csr = tcg_constant_i32(rc);
851
852    translator_io_start(&ctx->base);
853    gen_helper_csrrw(dest, cpu_env, csr, src, mask);
854    gen_set_gpr(ctx, rd, dest);
855    return do_csr_post(ctx);
856}
857
858static bool do_csrr_i128(DisasContext *ctx, int rd, int rc)
859{
860    TCGv destl = dest_gpr(ctx, rd);
861    TCGv desth = dest_gprh(ctx, rd);
862    TCGv_i32 csr = tcg_constant_i32(rc);
863
864    translator_io_start(&ctx->base);
865    gen_helper_csrr_i128(destl, cpu_env, csr);
866    tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh));
867    gen_set_gpr128(ctx, rd, destl, desth);
868    return do_csr_post(ctx);
869}
870
871static bool do_csrw_i128(DisasContext *ctx, int rc, TCGv srcl, TCGv srch)
872{
873    TCGv_i32 csr = tcg_constant_i32(rc);
874
875    translator_io_start(&ctx->base);
876    gen_helper_csrw_i128(cpu_env, csr, srcl, srch);
877    return do_csr_post(ctx);
878}
879
880static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc,
881                          TCGv srcl, TCGv srch, TCGv maskl, TCGv maskh)
882{
883    TCGv destl = dest_gpr(ctx, rd);
884    TCGv desth = dest_gprh(ctx, rd);
885    TCGv_i32 csr = tcg_constant_i32(rc);
886
887    translator_io_start(&ctx->base);
888    gen_helper_csrrw_i128(destl, cpu_env, csr, srcl, srch, maskl, maskh);
889    tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh));
890    gen_set_gpr128(ctx, rd, destl, desth);
891    return do_csr_post(ctx);
892}
893
894static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
895{
896    RISCVMXL xl = get_xl(ctx);
897    if (xl < MXL_RV128) {
898        TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
899
900        /*
901         * If rd == 0, the insn shall not read the csr, nor cause any of the
902         * side effects that might occur on a csr read.
903         */
904        if (a->rd == 0) {
905            return do_csrw(ctx, a->csr, src);
906        }
907
908        TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
909                                                     (target_ulong)-1);
910        return do_csrrw(ctx, a->rd, a->csr, src, mask);
911    } else {
912        TCGv srcl = get_gpr(ctx, a->rs1, EXT_NONE);
913        TCGv srch = get_gprh(ctx, a->rs1);
914
915        /*
916         * If rd == 0, the insn shall not read the csr, nor cause any of the
917         * side effects that might occur on a csr read.
918         */
919        if (a->rd == 0) {
920            return do_csrw_i128(ctx, a->csr, srcl, srch);
921        }
922
923        TCGv mask = tcg_constant_tl(-1);
924        return do_csrrw_i128(ctx, a->rd, a->csr, srcl, srch, mask, mask);
925    }
926}
927
928static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
929{
930    /*
931     * If rs1 == 0, the insn shall not write to the csr at all, nor
932     * cause any of the side effects that might occur on a csr write.
933     * Note that if rs1 specifies a register other than x0, holding
934     * a zero value, the instruction will still attempt to write the
935     * unmodified value back to the csr and will cause side effects.
936     */
937    if (get_xl(ctx) < MXL_RV128) {
938        if (a->rs1 == 0) {
939            return do_csrr(ctx, a->rd, a->csr);
940        }
941
942        TCGv ones = tcg_constant_tl(-1);
943        TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
944        return do_csrrw(ctx, a->rd, a->csr, ones, mask);
945    } else {
946        if (a->rs1 == 0) {
947            return do_csrr_i128(ctx, a->rd, a->csr);
948        }
949
950        TCGv ones = tcg_constant_tl(-1);
951        TCGv maskl = get_gpr(ctx, a->rs1, EXT_ZERO);
952        TCGv maskh = get_gprh(ctx, a->rs1);
953        return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, maskl, maskh);
954    }
955}
956
957static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
958{
959    /*
960     * If rs1 == 0, the insn shall not write to the csr at all, nor
961     * cause any of the side effects that might occur on a csr write.
962     * Note that if rs1 specifies a register other than x0, holding
963     * a zero value, the instruction will still attempt to write the
964     * unmodified value back to the csr and will cause side effects.
965     */
966    if (get_xl(ctx) < MXL_RV128) {
967        if (a->rs1 == 0) {
968            return do_csrr(ctx, a->rd, a->csr);
969        }
970
971        TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
972        return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
973    } else {
974        if (a->rs1 == 0) {
975            return do_csrr_i128(ctx, a->rd, a->csr);
976        }
977
978        TCGv maskl = get_gpr(ctx, a->rs1, EXT_ZERO);
979        TCGv maskh = get_gprh(ctx, a->rs1);
980        return do_csrrw_i128(ctx, a->rd, a->csr,
981                             ctx->zero, ctx->zero, maskl, maskh);
982    }
983}
984
985static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
986{
987    RISCVMXL xl = get_xl(ctx);
988    if (xl < MXL_RV128) {
989        TCGv src = tcg_constant_tl(a->rs1);
990
991        /*
992         * If rd == 0, the insn shall not read the csr, nor cause any of the
993         * side effects that might occur on a csr read.
994         */
995        if (a->rd == 0) {
996            return do_csrw(ctx, a->csr, src);
997        }
998
999        TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
1000                                                     (target_ulong)-1);
1001        return do_csrrw(ctx, a->rd, a->csr, src, mask);
1002    } else {
1003        TCGv src = tcg_constant_tl(a->rs1);
1004
1005        /*
1006         * If rd == 0, the insn shall not read the csr, nor cause any of the
1007         * side effects that might occur on a csr read.
1008         */
1009        if (a->rd == 0) {
1010            return do_csrw_i128(ctx, a->csr, src, ctx->zero);
1011        }
1012
1013        TCGv mask = tcg_constant_tl(-1);
1014        return do_csrrw_i128(ctx, a->rd, a->csr, src, ctx->zero, mask, mask);
1015    }
1016}
1017
1018static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
1019{
1020    /*
1021     * If rs1 == 0, the insn shall not write to the csr at all, nor
1022     * cause any of the side effects that might occur on a csr write.
1023     * Note that if rs1 specifies a register other than x0, holding
1024     * a zero value, the instruction will still attempt to write the
1025     * unmodified value back to the csr and will cause side effects.
1026     */
1027    if (get_xl(ctx) < MXL_RV128) {
1028        if (a->rs1 == 0) {
1029            return do_csrr(ctx, a->rd, a->csr);
1030        }
1031
1032        TCGv ones = tcg_constant_tl(-1);
1033        TCGv mask = tcg_constant_tl(a->rs1);
1034        return do_csrrw(ctx, a->rd, a->csr, ones, mask);
1035    } else {
1036        if (a->rs1 == 0) {
1037            return do_csrr_i128(ctx, a->rd, a->csr);
1038        }
1039
1040        TCGv ones = tcg_constant_tl(-1);
1041        TCGv mask = tcg_constant_tl(a->rs1);
1042        return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, mask, ctx->zero);
1043    }
1044}
1045
1046static bool trans_csrrci(DisasContext *ctx, arg_csrrci * a)
1047{
1048    /*
1049     * If rs1 == 0, the insn shall not write to the csr at all, nor
1050     * cause any of the side effects that might occur on a csr write.
1051     * Note that if rs1 specifies a register other than x0, holding
1052     * a zero value, the instruction will still attempt to write the
1053     * unmodified value back to the csr and will cause side effects.
1054     */
1055    if (get_xl(ctx) < MXL_RV128) {
1056        if (a->rs1 == 0) {
1057            return do_csrr(ctx, a->rd, a->csr);
1058        }
1059
1060        TCGv mask = tcg_constant_tl(a->rs1);
1061        return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
1062    } else {
1063        if (a->rs1 == 0) {
1064            return do_csrr_i128(ctx, a->rd, a->csr);
1065        }
1066
1067        TCGv mask = tcg_constant_tl(a->rs1);
1068        return do_csrrw_i128(ctx, a->rd, a->csr,
1069                             ctx->zero, ctx->zero, mask, ctx->zero);
1070    }
1071}
1072