1/*
2 * RISC-V translation routines for the RVXI Base Integer Instruction Set.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21static bool trans_illegal(DisasContext *ctx, arg_empty *a)
22{
23    gen_exception_illegal(ctx);
24    return true;
25}
26
27static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
28{
29    REQUIRE_64_OR_128BIT(ctx);
30    return trans_illegal(ctx, a);
31}
32
33static bool trans_lui(DisasContext *ctx, arg_lui *a)
34{
35    gen_set_gpri(ctx, a->rd, a->imm);
36    return true;
37}
38
39static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
40{
41    gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
42    return true;
43}
44
45static bool trans_jal(DisasContext *ctx, arg_jal *a)
46{
47    gen_jal(ctx, a->rd, a->imm);
48    return true;
49}
50
51static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
52{
53    TCGLabel *misaligned = NULL;
54
55    tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
56    tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
57
58    gen_set_pc(ctx, cpu_pc);
59    if (!has_ext(ctx, RVC)) {
60        TCGv t0 = tcg_temp_new();
61
62        misaligned = gen_new_label();
63        tcg_gen_andi_tl(t0, cpu_pc, 0x2);
64        tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
65        tcg_temp_free(t0);
66    }
67
68    gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
69    lookup_and_goto_ptr(ctx);
70
71    if (misaligned) {
72        gen_set_label(misaligned);
73        gen_exception_inst_addr_mis(ctx);
74    }
75    ctx->base.is_jmp = DISAS_NORETURN;
76
77    return true;
78}
79
80static TCGCond gen_compare_i128(bool bz, TCGv rl,
81                                TCGv al, TCGv ah, TCGv bl, TCGv bh,
82                                TCGCond cond)
83{
84    TCGv rh = tcg_temp_new();
85    bool invert = false;
86
87    switch (cond) {
88    case TCG_COND_EQ:
89    case TCG_COND_NE:
90        if (bz) {
91            tcg_gen_or_tl(rl, al, ah);
92        } else {
93            tcg_gen_xor_tl(rl, al, bl);
94            tcg_gen_xor_tl(rh, ah, bh);
95            tcg_gen_or_tl(rl, rl, rh);
96        }
97        break;
98
99    case TCG_COND_GE:
100    case TCG_COND_LT:
101        if (bz) {
102            tcg_gen_mov_tl(rl, ah);
103        } else {
104            TCGv tmp = tcg_temp_new();
105
106            tcg_gen_sub2_tl(rl, rh, al, ah, bl, bh);
107            tcg_gen_xor_tl(rl, rh, ah);
108            tcg_gen_xor_tl(tmp, ah, bh);
109            tcg_gen_and_tl(rl, rl, tmp);
110            tcg_gen_xor_tl(rl, rh, rl);
111
112            tcg_temp_free(tmp);
113        }
114        break;
115
116    case TCG_COND_LTU:
117        invert = true;
118        /* fallthrough */
119    case TCG_COND_GEU:
120        {
121            TCGv tmp = tcg_temp_new();
122            TCGv zero = tcg_constant_tl(0);
123            TCGv one = tcg_constant_tl(1);
124
125            cond = TCG_COND_NE;
126            /* borrow in to second word */
127            tcg_gen_setcond_tl(TCG_COND_LTU, tmp, al, bl);
128            /* seed third word with 1, which will be result */
129            tcg_gen_sub2_tl(tmp, rh, ah, one, tmp, zero);
130            tcg_gen_sub2_tl(tmp, rl, tmp, rh, bh, zero);
131
132            tcg_temp_free(tmp);
133        }
134        break;
135
136    default:
137        g_assert_not_reached();
138    }
139
140    if (invert) {
141        cond = tcg_invert_cond(cond);
142    }
143
144    tcg_temp_free(rh);
145    return cond;
146}
147
148static void gen_setcond_i128(TCGv rl, TCGv rh,
149                             TCGv src1l, TCGv src1h,
150                             TCGv src2l, TCGv src2h,
151                             TCGCond cond)
152{
153    cond = gen_compare_i128(false, rl, src1l, src1h, src2l, src2h, cond);
154    tcg_gen_setcondi_tl(cond, rl, rl, 0);
155    tcg_gen_movi_tl(rh, 0);
156}
157
158static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
159{
160    TCGLabel *l = gen_new_label();
161    TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
162    TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
163
164    if (get_xl(ctx) == MXL_RV128) {
165        TCGv src1h = get_gprh(ctx, a->rs1);
166        TCGv src2h = get_gprh(ctx, a->rs2);
167        TCGv tmp = tcg_temp_new();
168
169        cond = gen_compare_i128(a->rs2 == 0,
170                                tmp, src1, src1h, src2, src2h, cond);
171        tcg_gen_brcondi_tl(cond, tmp, 0, l);
172
173        tcg_temp_free(tmp);
174    } else {
175        tcg_gen_brcond_tl(cond, src1, src2, l);
176    }
177    gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
178
179    gen_set_label(l); /* branch taken */
180
181    if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
182        /* misaligned */
183        gen_exception_inst_addr_mis(ctx);
184    } else {
185        gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
186    }
187    ctx->base.is_jmp = DISAS_NORETURN;
188
189    return true;
190}
191
192static bool trans_beq(DisasContext *ctx, arg_beq *a)
193{
194    return gen_branch(ctx, a, TCG_COND_EQ);
195}
196
197static bool trans_bne(DisasContext *ctx, arg_bne *a)
198{
199    return gen_branch(ctx, a, TCG_COND_NE);
200}
201
202static bool trans_blt(DisasContext *ctx, arg_blt *a)
203{
204    return gen_branch(ctx, a, TCG_COND_LT);
205}
206
207static bool trans_bge(DisasContext *ctx, arg_bge *a)
208{
209    return gen_branch(ctx, a, TCG_COND_GE);
210}
211
212static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
213{
214    return gen_branch(ctx, a, TCG_COND_LTU);
215}
216
217static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
218{
219    return gen_branch(ctx, a, TCG_COND_GEU);
220}
221
222static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
223{
224    TCGv dest = dest_gpr(ctx, a->rd);
225    TCGv addr = get_address(ctx, a->rs1, a->imm);
226
227    tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
228    gen_set_gpr(ctx, a->rd, dest);
229    return true;
230}
231
232/* Compute only 64-bit addresses to use the address translation mechanism */
233static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
234{
235    TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
236    TCGv destl = dest_gpr(ctx, a->rd);
237    TCGv desth = dest_gprh(ctx, a->rd);
238    TCGv addrl = tcg_temp_new();
239
240    tcg_gen_addi_tl(addrl, src1l, a->imm);
241
242    if ((memop & MO_SIZE) <= MO_64) {
243        tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, memop);
244        if (memop & MO_SIGN) {
245            tcg_gen_sari_tl(desth, destl, 63);
246        } else {
247            tcg_gen_movi_tl(desth, 0);
248        }
249    } else {
250        /* assume little-endian memory access for now */
251        tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, MO_TEUQ);
252        tcg_gen_addi_tl(addrl, addrl, 8);
253        tcg_gen_qemu_ld_tl(desth, addrl, ctx->mem_idx, MO_TEUQ);
254    }
255
256    gen_set_gpr128(ctx, a->rd, destl, desth);
257
258    tcg_temp_free(addrl);
259    return true;
260}
261
262static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
263{
264    decode_save_opc(ctx);
265    if (get_xl(ctx) == MXL_RV128) {
266        return gen_load_i128(ctx, a, memop);
267    } else {
268        return gen_load_tl(ctx, a, memop);
269    }
270}
271
272static bool trans_lb(DisasContext *ctx, arg_lb *a)
273{
274    return gen_load(ctx, a, MO_SB);
275}
276
277static bool trans_lh(DisasContext *ctx, arg_lh *a)
278{
279    return gen_load(ctx, a, MO_TESW);
280}
281
282static bool trans_lw(DisasContext *ctx, arg_lw *a)
283{
284    return gen_load(ctx, a, MO_TESL);
285}
286
287static bool trans_ld(DisasContext *ctx, arg_ld *a)
288{
289    REQUIRE_64_OR_128BIT(ctx);
290    return gen_load(ctx, a, MO_TESQ);
291}
292
293static bool trans_lq(DisasContext *ctx, arg_lq *a)
294{
295    REQUIRE_128BIT(ctx);
296    return gen_load(ctx, a, MO_TEUO);
297}
298
299static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
300{
301    return gen_load(ctx, a, MO_UB);
302}
303
304static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
305{
306    return gen_load(ctx, a, MO_TEUW);
307}
308
309static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
310{
311    REQUIRE_64_OR_128BIT(ctx);
312    return gen_load(ctx, a, MO_TEUL);
313}
314
315static bool trans_ldu(DisasContext *ctx, arg_ldu *a)
316{
317    REQUIRE_128BIT(ctx);
318    return gen_load(ctx, a, MO_TEUQ);
319}
320
321static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
322{
323    TCGv addr = get_address(ctx, a->rs1, a->imm);
324    TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
325
326    tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
327    return true;
328}
329
330static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
331{
332    TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
333    TCGv src2l = get_gpr(ctx, a->rs2, EXT_NONE);
334    TCGv src2h = get_gprh(ctx, a->rs2);
335    TCGv addrl = tcg_temp_new();
336
337    tcg_gen_addi_tl(addrl, src1l, a->imm);
338
339    if ((memop & MO_SIZE) <= MO_64) {
340        tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop);
341    } else {
342        /* little-endian memory access assumed for now */
343        tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, MO_TEUQ);
344        tcg_gen_addi_tl(addrl, addrl, 8);
345        tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, MO_TEUQ);
346    }
347
348    tcg_temp_free(addrl);
349    return true;
350}
351
352static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
353{
354    decode_save_opc(ctx);
355    if (get_xl(ctx) == MXL_RV128) {
356        return gen_store_i128(ctx, a, memop);
357    } else {
358        return gen_store_tl(ctx, a, memop);
359    }
360}
361
362static bool trans_sb(DisasContext *ctx, arg_sb *a)
363{
364    return gen_store(ctx, a, MO_SB);
365}
366
367static bool trans_sh(DisasContext *ctx, arg_sh *a)
368{
369    return gen_store(ctx, a, MO_TESW);
370}
371
372static bool trans_sw(DisasContext *ctx, arg_sw *a)
373{
374    return gen_store(ctx, a, MO_TESL);
375}
376
377static bool trans_sd(DisasContext *ctx, arg_sd *a)
378{
379    REQUIRE_64_OR_128BIT(ctx);
380    return gen_store(ctx, a, MO_TEUQ);
381}
382
383static bool trans_sq(DisasContext *ctx, arg_sq *a)
384{
385    REQUIRE_128BIT(ctx);
386    return gen_store(ctx, a, MO_TEUO);
387}
388
389static bool trans_addd(DisasContext *ctx, arg_addd *a)
390{
391    REQUIRE_128BIT(ctx);
392    ctx->ol = MXL_RV64;
393    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, NULL);
394}
395
396static bool trans_addid(DisasContext *ctx, arg_addid *a)
397{
398    REQUIRE_128BIT(ctx);
399    ctx->ol = MXL_RV64;
400    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, NULL);
401}
402
403static bool trans_subd(DisasContext *ctx, arg_subd *a)
404{
405    REQUIRE_128BIT(ctx);
406    ctx->ol = MXL_RV64;
407    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, NULL);
408}
409
410static void gen_addi2_i128(TCGv retl, TCGv reth,
411                           TCGv srcl, TCGv srch, target_long imm)
412{
413    TCGv imml  = tcg_constant_tl(imm);
414    TCGv immh  = tcg_constant_tl(-(imm < 0));
415    tcg_gen_add2_tl(retl, reth, srcl, srch, imml, immh);
416}
417
418static bool trans_addi(DisasContext *ctx, arg_addi *a)
419{
420    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, gen_addi2_i128);
421}
422
423static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
424{
425    tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
426}
427
428static void gen_slt_i128(TCGv retl, TCGv reth,
429                         TCGv s1l, TCGv s1h, TCGv s2l, TCGv s2h)
430{
431    gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LT);
432}
433
434static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
435{
436    tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
437}
438
439static void gen_sltu_i128(TCGv retl, TCGv reth,
440                          TCGv s1l, TCGv s1h, TCGv s2l, TCGv s2h)
441{
442    gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LTU);
443}
444
445static bool trans_slti(DisasContext *ctx, arg_slti *a)
446{
447    return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt, gen_slt_i128);
448}
449
450static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
451{
452    return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu, gen_sltu_i128);
453}
454
455static bool trans_xori(DisasContext *ctx, arg_xori *a)
456{
457    return gen_logic_imm_fn(ctx, a, tcg_gen_xori_tl);
458}
459
460static bool trans_ori(DisasContext *ctx, arg_ori *a)
461{
462    return gen_logic_imm_fn(ctx, a, tcg_gen_ori_tl);
463}
464
465static bool trans_andi(DisasContext *ctx, arg_andi *a)
466{
467    return gen_logic_imm_fn(ctx, a, tcg_gen_andi_tl);
468}
469
470static void gen_slli_i128(TCGv retl, TCGv reth,
471                          TCGv src1l, TCGv src1h,
472                          target_long shamt)
473{
474    if (shamt >= 64) {
475        tcg_gen_shli_tl(reth, src1l, shamt - 64);
476        tcg_gen_movi_tl(retl, 0);
477    } else {
478        tcg_gen_extract2_tl(reth, src1l, src1h, 64 - shamt);
479        tcg_gen_shli_tl(retl, src1l, shamt);
480    }
481}
482
483static bool trans_slli(DisasContext *ctx, arg_slli *a)
484{
485    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, gen_slli_i128);
486}
487
488static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
489{
490    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
491}
492
493static void gen_srli_i128(TCGv retl, TCGv reth,
494                          TCGv src1l, TCGv src1h,
495                          target_long shamt)
496{
497    if (shamt >= 64) {
498        tcg_gen_shri_tl(retl, src1h, shamt - 64);
499        tcg_gen_movi_tl(reth, 0);
500    } else {
501        tcg_gen_extract2_tl(retl, src1l, src1h, shamt);
502        tcg_gen_shri_tl(reth, src1h, shamt);
503    }
504}
505
506static bool trans_srli(DisasContext *ctx, arg_srli *a)
507{
508    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
509                                   tcg_gen_shri_tl, gen_srliw, gen_srli_i128);
510}
511
512static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
513{
514    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
515}
516
517static void gen_srai_i128(TCGv retl, TCGv reth,
518                          TCGv src1l, TCGv src1h,
519                          target_long shamt)
520{
521    if (shamt >= 64) {
522        tcg_gen_sari_tl(retl, src1h, shamt - 64);
523        tcg_gen_sari_tl(reth, src1h, 63);
524    } else {
525        tcg_gen_extract2_tl(retl, src1l, src1h, shamt);
526        tcg_gen_sari_tl(reth, src1h, shamt);
527    }
528}
529
530static bool trans_srai(DisasContext *ctx, arg_srai *a)
531{
532    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
533                                   tcg_gen_sari_tl, gen_sraiw, gen_srai_i128);
534}
535
536static bool trans_add(DisasContext *ctx, arg_add *a)
537{
538    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, tcg_gen_add2_tl);
539}
540
541static bool trans_sub(DisasContext *ctx, arg_sub *a)
542{
543    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, tcg_gen_sub2_tl);
544}
545
546static void gen_sll_i128(TCGv destl, TCGv desth,
547                         TCGv src1l, TCGv src1h, TCGv shamt)
548{
549    TCGv ls = tcg_temp_new();
550    TCGv rs = tcg_temp_new();
551    TCGv hs = tcg_temp_new();
552    TCGv ll = tcg_temp_new();
553    TCGv lr = tcg_temp_new();
554    TCGv h0 = tcg_temp_new();
555    TCGv h1 = tcg_temp_new();
556    TCGv zero = tcg_constant_tl(0);
557
558    tcg_gen_andi_tl(hs, shamt, 64);
559    tcg_gen_andi_tl(ls, shamt, 63);
560    tcg_gen_neg_tl(shamt, shamt);
561    tcg_gen_andi_tl(rs, shamt, 63);
562
563    tcg_gen_shl_tl(ll, src1l, ls);
564    tcg_gen_shl_tl(h0, src1h, ls);
565    tcg_gen_shr_tl(lr, src1l, rs);
566    tcg_gen_movcond_tl(TCG_COND_NE, lr, shamt, zero, lr, zero);
567    tcg_gen_or_tl(h1, h0, lr);
568
569    tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, zero, ll);
570    tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, ll, h1);
571
572    tcg_temp_free(ls);
573    tcg_temp_free(rs);
574    tcg_temp_free(hs);
575    tcg_temp_free(ll);
576    tcg_temp_free(lr);
577    tcg_temp_free(h0);
578    tcg_temp_free(h1);
579}
580
581static bool trans_sll(DisasContext *ctx, arg_sll *a)
582{
583    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, gen_sll_i128);
584}
585
586static bool trans_slt(DisasContext *ctx, arg_slt *a)
587{
588    return gen_arith(ctx, a, EXT_SIGN, gen_slt, gen_slt_i128);
589}
590
591static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
592{
593    return gen_arith(ctx, a, EXT_SIGN, gen_sltu, gen_sltu_i128);
594}
595
596static void gen_srl_i128(TCGv destl, TCGv desth,
597                         TCGv src1l, TCGv src1h, TCGv shamt)
598{
599    TCGv ls = tcg_temp_new();
600    TCGv rs = tcg_temp_new();
601    TCGv hs = tcg_temp_new();
602    TCGv ll = tcg_temp_new();
603    TCGv lr = tcg_temp_new();
604    TCGv h0 = tcg_temp_new();
605    TCGv h1 = tcg_temp_new();
606    TCGv zero = tcg_constant_tl(0);
607
608    tcg_gen_andi_tl(hs, shamt, 64);
609    tcg_gen_andi_tl(rs, shamt, 63);
610    tcg_gen_neg_tl(shamt, shamt);
611    tcg_gen_andi_tl(ls, shamt, 63);
612
613    tcg_gen_shr_tl(lr, src1l, rs);
614    tcg_gen_shr_tl(h1, src1h, rs);
615    tcg_gen_shl_tl(ll, src1h, ls);
616    tcg_gen_movcond_tl(TCG_COND_NE, ll, shamt, zero, ll, zero);
617    tcg_gen_or_tl(h0, ll, lr);
618
619    tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, h1, h0);
620    tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, zero, h1);
621
622    tcg_temp_free(ls);
623    tcg_temp_free(rs);
624    tcg_temp_free(hs);
625    tcg_temp_free(ll);
626    tcg_temp_free(lr);
627    tcg_temp_free(h0);
628    tcg_temp_free(h1);
629}
630
631static bool trans_srl(DisasContext *ctx, arg_srl *a)
632{
633    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, gen_srl_i128);
634}
635
636static void gen_sra_i128(TCGv destl, TCGv desth,
637                         TCGv src1l, TCGv src1h, TCGv shamt)
638{
639    TCGv ls = tcg_temp_new();
640    TCGv rs = tcg_temp_new();
641    TCGv hs = tcg_temp_new();
642    TCGv ll = tcg_temp_new();
643    TCGv lr = tcg_temp_new();
644    TCGv h0 = tcg_temp_new();
645    TCGv h1 = tcg_temp_new();
646    TCGv zero = tcg_constant_tl(0);
647
648    tcg_gen_andi_tl(hs, shamt, 64);
649    tcg_gen_andi_tl(rs, shamt, 63);
650    tcg_gen_neg_tl(shamt, shamt);
651    tcg_gen_andi_tl(ls, shamt, 63);
652
653    tcg_gen_shr_tl(lr, src1l, rs);
654    tcg_gen_sar_tl(h1, src1h, rs);
655    tcg_gen_shl_tl(ll, src1h, ls);
656    tcg_gen_movcond_tl(TCG_COND_NE, ll, shamt, zero, ll, zero);
657    tcg_gen_or_tl(h0, ll, lr);
658    tcg_gen_sari_tl(lr, src1h, 63);
659
660    tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, h1, h0);
661    tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, lr, h1);
662
663    tcg_temp_free(ls);
664    tcg_temp_free(rs);
665    tcg_temp_free(hs);
666    tcg_temp_free(ll);
667    tcg_temp_free(lr);
668    tcg_temp_free(h0);
669    tcg_temp_free(h1);
670}
671
672static bool trans_sra(DisasContext *ctx, arg_sra *a)
673{
674    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, gen_sra_i128);
675}
676
677static bool trans_xor(DisasContext *ctx, arg_xor *a)
678{
679    return gen_logic(ctx, a, tcg_gen_xor_tl);
680}
681
682static bool trans_or(DisasContext *ctx, arg_or *a)
683{
684    return gen_logic(ctx, a, tcg_gen_or_tl);
685}
686
687static bool trans_and(DisasContext *ctx, arg_and *a)
688{
689    return gen_logic(ctx, a, tcg_gen_and_tl);
690}
691
692static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
693{
694    REQUIRE_64_OR_128BIT(ctx);
695    ctx->ol = MXL_RV32;
696    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl, NULL);
697}
698
699static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
700{
701    REQUIRE_64_OR_128BIT(ctx);
702    ctx->ol = MXL_RV32;
703    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, NULL);
704}
705
706static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
707{
708    REQUIRE_64_OR_128BIT(ctx);
709    ctx->ol = MXL_RV32;
710    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw, NULL);
711}
712
713static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
714{
715    REQUIRE_64_OR_128BIT(ctx);
716    ctx->ol = MXL_RV32;
717    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw, NULL);
718}
719
720static bool trans_sllid(DisasContext *ctx, arg_sllid *a)
721{
722    REQUIRE_128BIT(ctx);
723    ctx->ol = MXL_RV64;
724    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl, NULL);
725}
726
727static bool trans_srlid(DisasContext *ctx, arg_srlid *a)
728{
729    REQUIRE_128BIT(ctx);
730    ctx->ol = MXL_RV64;
731    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shri_tl, NULL);
732}
733
734static bool trans_sraid(DisasContext *ctx, arg_sraid *a)
735{
736    REQUIRE_128BIT(ctx);
737    ctx->ol = MXL_RV64;
738    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_sari_tl,  NULL);
739}
740
741static bool trans_addw(DisasContext *ctx, arg_addw *a)
742{
743    REQUIRE_64_OR_128BIT(ctx);
744    ctx->ol = MXL_RV32;
745    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl, NULL);
746}
747
748static bool trans_subw(DisasContext *ctx, arg_subw *a)
749{
750    REQUIRE_64_OR_128BIT(ctx);
751    ctx->ol = MXL_RV32;
752    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl, NULL);
753}
754
755static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
756{
757    REQUIRE_64_OR_128BIT(ctx);
758    ctx->ol = MXL_RV32;
759    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, NULL);
760}
761
762static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
763{
764    REQUIRE_64_OR_128BIT(ctx);
765    ctx->ol = MXL_RV32;
766    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, NULL);
767}
768
769static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
770{
771    REQUIRE_64_OR_128BIT(ctx);
772    ctx->ol = MXL_RV32;
773    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
774}
775
776static bool trans_slld(DisasContext *ctx, arg_slld *a)
777{
778    REQUIRE_128BIT(ctx);
779    ctx->ol = MXL_RV64;
780    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl, NULL);
781}
782
783static bool trans_srld(DisasContext *ctx, arg_srld *a)
784{
785    REQUIRE_128BIT(ctx);
786    ctx->ol = MXL_RV64;
787    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, NULL);
788}
789
790static bool trans_srad(DisasContext *ctx, arg_srad *a)
791{
792    REQUIRE_128BIT(ctx);
793    ctx->ol = MXL_RV64;
794    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
795}
796
797static bool trans_pause(DisasContext *ctx, arg_pause *a)
798{
799    if (!ctx->cfg_ptr->ext_zihintpause) {
800        return false;
801    }
802
803    /*
804     * PAUSE is a no-op in QEMU,
805     * end the TB and return to main loop
806     */
807    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
808    exit_tb(ctx);
809    ctx->base.is_jmp = DISAS_NORETURN;
810
811    return true;
812}
813
814static bool trans_fence(DisasContext *ctx, arg_fence *a)
815{
816    /* FENCE is a full memory barrier. */
817    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
818    return true;
819}
820
821static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
822{
823    if (!ctx->cfg_ptr->ext_ifencei) {
824        return false;
825    }
826
827    /*
828     * FENCE_I is a no-op in QEMU,
829     * however we need to end the translation block
830     */
831    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
832    exit_tb(ctx);
833    ctx->base.is_jmp = DISAS_NORETURN;
834    return true;
835}
836
837static bool do_csr_post(DisasContext *ctx)
838{
839    /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
840    decode_save_opc(ctx);
841    /* We may have changed important cpu state -- exit to main loop. */
842    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
843    exit_tb(ctx);
844    ctx->base.is_jmp = DISAS_NORETURN;
845    return true;
846}
847
848static bool do_csrr(DisasContext *ctx, int rd, int rc)
849{
850    TCGv dest = dest_gpr(ctx, rd);
851    TCGv_i32 csr = tcg_constant_i32(rc);
852
853    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
854        gen_io_start();
855    }
856    gen_helper_csrr(dest, cpu_env, csr);
857    gen_set_gpr(ctx, rd, dest);
858    return do_csr_post(ctx);
859}
860
861static bool do_csrw(DisasContext *ctx, int rc, TCGv src)
862{
863    TCGv_i32 csr = tcg_constant_i32(rc);
864
865    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
866        gen_io_start();
867    }
868    gen_helper_csrw(cpu_env, csr, src);
869    return do_csr_post(ctx);
870}
871
872static bool do_csrrw(DisasContext *ctx, int rd, int rc, TCGv src, TCGv mask)
873{
874    TCGv dest = dest_gpr(ctx, rd);
875    TCGv_i32 csr = tcg_constant_i32(rc);
876
877    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
878        gen_io_start();
879    }
880    gen_helper_csrrw(dest, cpu_env, csr, src, mask);
881    gen_set_gpr(ctx, rd, dest);
882    return do_csr_post(ctx);
883}
884
885static bool do_csrr_i128(DisasContext *ctx, int rd, int rc)
886{
887    TCGv destl = dest_gpr(ctx, rd);
888    TCGv desth = dest_gprh(ctx, rd);
889    TCGv_i32 csr = tcg_constant_i32(rc);
890
891    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
892        gen_io_start();
893    }
894    gen_helper_csrr_i128(destl, cpu_env, csr);
895    tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh));
896    gen_set_gpr128(ctx, rd, destl, desth);
897    return do_csr_post(ctx);
898}
899
900static bool do_csrw_i128(DisasContext *ctx, int rc, TCGv srcl, TCGv srch)
901{
902    TCGv_i32 csr = tcg_constant_i32(rc);
903
904    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
905        gen_io_start();
906    }
907    gen_helper_csrw_i128(cpu_env, csr, srcl, srch);
908    return do_csr_post(ctx);
909}
910
911static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc,
912                          TCGv srcl, TCGv srch, TCGv maskl, TCGv maskh)
913{
914    TCGv destl = dest_gpr(ctx, rd);
915    TCGv desth = dest_gprh(ctx, rd);
916    TCGv_i32 csr = tcg_constant_i32(rc);
917
918    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
919        gen_io_start();
920    }
921    gen_helper_csrrw_i128(destl, cpu_env, csr, srcl, srch, maskl, maskh);
922    tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh));
923    gen_set_gpr128(ctx, rd, destl, desth);
924    return do_csr_post(ctx);
925}
926
927static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
928{
929    RISCVMXL xl = get_xl(ctx);
930    if (xl < MXL_RV128) {
931        TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
932
933        /*
934         * If rd == 0, the insn shall not read the csr, nor cause any of the
935         * side effects that might occur on a csr read.
936         */
937        if (a->rd == 0) {
938            return do_csrw(ctx, a->csr, src);
939        }
940
941        TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
942                                                     (target_ulong)-1);
943        return do_csrrw(ctx, a->rd, a->csr, src, mask);
944    } else {
945        TCGv srcl = get_gpr(ctx, a->rs1, EXT_NONE);
946        TCGv srch = get_gprh(ctx, a->rs1);
947
948        /*
949         * If rd == 0, the insn shall not read the csr, nor cause any of the
950         * side effects that might occur on a csr read.
951         */
952        if (a->rd == 0) {
953            return do_csrw_i128(ctx, a->csr, srcl, srch);
954        }
955
956        TCGv mask = tcg_constant_tl(-1);
957        return do_csrrw_i128(ctx, a->rd, a->csr, srcl, srch, mask, mask);
958    }
959}
960
961static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
962{
963    /*
964     * If rs1 == 0, the insn shall not write to the csr at all, nor
965     * cause any of the side effects that might occur on a csr write.
966     * Note that if rs1 specifies a register other than x0, holding
967     * a zero value, the instruction will still attempt to write the
968     * unmodified value back to the csr and will cause side effects.
969     */
970    if (get_xl(ctx) < MXL_RV128) {
971        if (a->rs1 == 0) {
972            return do_csrr(ctx, a->rd, a->csr);
973        }
974
975        TCGv ones = tcg_constant_tl(-1);
976        TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
977        return do_csrrw(ctx, a->rd, a->csr, ones, mask);
978    } else {
979        if (a->rs1 == 0) {
980            return do_csrr_i128(ctx, a->rd, a->csr);
981        }
982
983        TCGv ones = tcg_constant_tl(-1);
984        TCGv maskl = get_gpr(ctx, a->rs1, EXT_ZERO);
985        TCGv maskh = get_gprh(ctx, a->rs1);
986        return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, maskl, maskh);
987    }
988}
989
990static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
991{
992    /*
993     * If rs1 == 0, the insn shall not write to the csr at all, nor
994     * cause any of the side effects that might occur on a csr write.
995     * Note that if rs1 specifies a register other than x0, holding
996     * a zero value, the instruction will still attempt to write the
997     * unmodified value back to the csr and will cause side effects.
998     */
999    if (get_xl(ctx) < MXL_RV128) {
1000        if (a->rs1 == 0) {
1001            return do_csrr(ctx, a->rd, a->csr);
1002        }
1003
1004        TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
1005        return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
1006    } else {
1007        if (a->rs1 == 0) {
1008            return do_csrr_i128(ctx, a->rd, a->csr);
1009        }
1010
1011        TCGv maskl = get_gpr(ctx, a->rs1, EXT_ZERO);
1012        TCGv maskh = get_gprh(ctx, a->rs1);
1013        return do_csrrw_i128(ctx, a->rd, a->csr,
1014                             ctx->zero, ctx->zero, maskl, maskh);
1015    }
1016}
1017
1018static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
1019{
1020    RISCVMXL xl = get_xl(ctx);
1021    if (xl < MXL_RV128) {
1022        TCGv src = tcg_constant_tl(a->rs1);
1023
1024        /*
1025         * If rd == 0, the insn shall not read the csr, nor cause any of the
1026         * side effects that might occur on a csr read.
1027         */
1028        if (a->rd == 0) {
1029            return do_csrw(ctx, a->csr, src);
1030        }
1031
1032        TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
1033                                                     (target_ulong)-1);
1034        return do_csrrw(ctx, a->rd, a->csr, src, mask);
1035    } else {
1036        TCGv src = tcg_constant_tl(a->rs1);
1037
1038        /*
1039         * If rd == 0, the insn shall not read the csr, nor cause any of the
1040         * side effects that might occur on a csr read.
1041         */
1042        if (a->rd == 0) {
1043            return do_csrw_i128(ctx, a->csr, src, ctx->zero);
1044        }
1045
1046        TCGv mask = tcg_constant_tl(-1);
1047        return do_csrrw_i128(ctx, a->rd, a->csr, src, ctx->zero, mask, mask);
1048    }
1049}
1050
1051static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
1052{
1053    /*
1054     * If rs1 == 0, the insn shall not write to the csr at all, nor
1055     * cause any of the side effects that might occur on a csr write.
1056     * Note that if rs1 specifies a register other than x0, holding
1057     * a zero value, the instruction will still attempt to write the
1058     * unmodified value back to the csr and will cause side effects.
1059     */
1060    if (get_xl(ctx) < MXL_RV128) {
1061        if (a->rs1 == 0) {
1062            return do_csrr(ctx, a->rd, a->csr);
1063        }
1064
1065        TCGv ones = tcg_constant_tl(-1);
1066        TCGv mask = tcg_constant_tl(a->rs1);
1067        return do_csrrw(ctx, a->rd, a->csr, ones, mask);
1068    } else {
1069        if (a->rs1 == 0) {
1070            return do_csrr_i128(ctx, a->rd, a->csr);
1071        }
1072
1073        TCGv ones = tcg_constant_tl(-1);
1074        TCGv mask = tcg_constant_tl(a->rs1);
1075        return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, mask, ctx->zero);
1076    }
1077}
1078
1079static bool trans_csrrci(DisasContext *ctx, arg_csrrci * a)
1080{
1081    /*
1082     * If rs1 == 0, the insn shall not write to the csr at all, nor
1083     * cause any of the side effects that might occur on a csr write.
1084     * Note that if rs1 specifies a register other than x0, holding
1085     * a zero value, the instruction will still attempt to write the
1086     * unmodified value back to the csr and will cause side effects.
1087     */
1088    if (get_xl(ctx) < MXL_RV128) {
1089        if (a->rs1 == 0) {
1090            return do_csrr(ctx, a->rd, a->csr);
1091        }
1092
1093        TCGv mask = tcg_constant_tl(a->rs1);
1094        return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
1095    } else {
1096        if (a->rs1 == 0) {
1097            return do_csrr_i128(ctx, a->rd, a->csr);
1098        }
1099
1100        TCGv mask = tcg_constant_tl(a->rs1);
1101        return do_csrrw_i128(ctx, a->rd, a->csr,
1102                             ctx->zero, ctx->zero, mask, ctx->zero);
1103    }
1104}
1105