1/*
2 * RISC-V translation routines for the RISC-V Zawrs Extension.
3 *
4 * Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.io
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program.  If not, see <http://www.gnu.org/licenses/>.
17 */
18
19static bool trans_wrs(DisasContext *ctx)
20{
21    if (!ctx->cfg_ptr->ext_zawrs) {
22        return false;
23    }
24
25    /*
26     * The specification says:
27     * While stalled, an implementation is permitted to occasionally
28     * terminate the stall and complete execution for any reason.
29     *
30     * So let's just exit TB and return to the main loop.
31     */
32
33    /* Clear the load reservation  (if any).  */
34    tcg_gen_movi_tl(load_res, -1);
35
36    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
37    tcg_gen_exit_tb(NULL, 0);
38    ctx->base.is_jmp = DISAS_NORETURN;
39
40    return true;
41}
42
43#define GEN_TRANS_WRS(insn)                                     \
44static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
45{                                                               \
46    (void)a;                                                    \
47    return trans_wrs(ctx);                                      \
48}
49
50GEN_TRANS_WRS(wrs_nto)
51GEN_TRANS_WRS(wrs_sto)
52