1 /* 2 * RISC-V implementation of KVM hooks 3 * 4 * Copyright (c) 2020 Huawei Technologies Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include <sys/ioctl.h> 21 22 #include <linux/kvm.h> 23 24 #include "qemu/timer.h" 25 #include "qapi/error.h" 26 #include "qemu/error-report.h" 27 #include "qemu/main-loop.h" 28 #include "qapi/visitor.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/kvm_int.h" 32 #include "cpu.h" 33 #include "trace.h" 34 #include "hw/core/accel-cpu.h" 35 #include "hw/pci/pci.h" 36 #include "exec/memattrs.h" 37 #include "exec/address-spaces.h" 38 #include "hw/boards.h" 39 #include "hw/irq.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "qemu/log.h" 42 #include "hw/loader.h" 43 #include "kvm_riscv.h" 44 #include "sbi_ecall_interface.h" 45 #include "chardev/char-fe.h" 46 #include "migration/migration.h" 47 #include "sysemu/runstate.h" 48 #include "hw/riscv/numa.h" 49 50 void riscv_kvm_aplic_request(void *opaque, int irq, int level) 51 { 52 kvm_set_irq(kvm_state, irq, !!level); 53 } 54 55 static bool cap_has_mp_state; 56 57 static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, 58 uint64_t idx) 59 { 60 uint64_t id = KVM_REG_RISCV | type | idx; 61 62 switch (riscv_cpu_mxl(env)) { 63 case MXL_RV32: 64 id |= KVM_REG_SIZE_U32; 65 break; 66 case MXL_RV64: 67 id |= KVM_REG_SIZE_U64; 68 break; 69 default: 70 g_assert_not_reached(); 71 } 72 return id; 73 } 74 75 static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) 76 { 77 return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; 78 } 79 80 static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) 81 { 82 return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; 83 } 84 85 #define RISCV_CORE_REG(env, name) \ 86 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ 87 KVM_REG_RISCV_CORE_REG(name)) 88 89 #define RISCV_CSR_REG(env, name) \ 90 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ 91 KVM_REG_RISCV_CSR_REG(name)) 92 93 #define RISCV_CONFIG_REG(env, name) \ 94 kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ 95 KVM_REG_RISCV_CONFIG_REG(name)) 96 97 #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ 98 KVM_REG_RISCV_TIMER_REG(name)) 99 100 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) 101 102 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) 103 104 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ 105 do { \ 106 int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 107 if (_ret) { \ 108 return _ret; \ 109 } \ 110 } while (0) 111 112 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ 113 do { \ 114 int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ 115 if (_ret) { \ 116 return _ret; \ 117 } \ 118 } while (0) 119 120 #define KVM_RISCV_GET_TIMER(cs, name, reg) \ 121 do { \ 122 int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 123 if (ret) { \ 124 abort(); \ 125 } \ 126 } while (0) 127 128 #define KVM_RISCV_SET_TIMER(cs, name, reg) \ 129 do { \ 130 int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ 131 if (ret) { \ 132 abort(); \ 133 } \ 134 } while (0) 135 136 typedef struct KVMCPUConfig { 137 const char *name; 138 const char *description; 139 target_ulong offset; 140 int kvm_reg_id; 141 bool user_set; 142 bool supported; 143 } KVMCPUConfig; 144 145 #define KVM_MISA_CFG(_bit, _reg_id) \ 146 {.offset = _bit, .kvm_reg_id = _reg_id} 147 148 /* KVM ISA extensions */ 149 static KVMCPUConfig kvm_misa_ext_cfgs[] = { 150 KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), 151 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), 152 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), 153 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), 154 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), 155 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), 156 KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), 157 }; 158 159 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, 160 const char *name, 161 void *opaque, Error **errp) 162 { 163 KVMCPUConfig *misa_ext_cfg = opaque; 164 target_ulong misa_bit = misa_ext_cfg->offset; 165 RISCVCPU *cpu = RISCV_CPU(obj); 166 CPURISCVState *env = &cpu->env; 167 bool value = env->misa_ext_mask & misa_bit; 168 169 visit_type_bool(v, name, &value, errp); 170 } 171 172 static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 173 const char *name, 174 void *opaque, Error **errp) 175 { 176 KVMCPUConfig *misa_ext_cfg = opaque; 177 target_ulong misa_bit = misa_ext_cfg->offset; 178 RISCVCPU *cpu = RISCV_CPU(obj); 179 CPURISCVState *env = &cpu->env; 180 bool value, host_bit; 181 182 if (!visit_type_bool(v, name, &value, errp)) { 183 return; 184 } 185 186 host_bit = env->misa_ext_mask & misa_bit; 187 188 if (value == host_bit) { 189 return; 190 } 191 192 if (!value) { 193 misa_ext_cfg->user_set = true; 194 return; 195 } 196 197 /* 198 * Forbid users to enable extensions that aren't 199 * available in the hart. 200 */ 201 error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " 202 "enabled in the host", misa_ext_cfg->name); 203 } 204 205 static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) 206 { 207 CPURISCVState *env = &cpu->env; 208 uint64_t id, reg; 209 int i, ret; 210 211 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 212 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 213 target_ulong misa_bit = misa_cfg->offset; 214 215 if (!misa_cfg->user_set) { 216 continue; 217 } 218 219 /* If we're here we're going to disable the MISA bit */ 220 reg = 0; 221 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 222 misa_cfg->kvm_reg_id); 223 ret = kvm_set_one_reg(cs, id, ®); 224 if (ret != 0) { 225 /* 226 * We're not checking for -EINVAL because if the bit is about 227 * to be disabled, it means that it was already enabled by 228 * KVM. We determined that by fetching the 'isa' register 229 * during init() time. Any error at this point is worth 230 * aborting. 231 */ 232 error_report("Unable to set KVM reg %s, error %d", 233 misa_cfg->name, ret); 234 exit(EXIT_FAILURE); 235 } 236 env->misa_ext &= ~misa_bit; 237 } 238 } 239 240 #define KVM_EXT_CFG(_name, _prop, _reg_id) \ 241 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 242 .kvm_reg_id = _reg_id} 243 244 static KVMCPUConfig kvm_multi_ext_cfgs[] = { 245 KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), 246 KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), 247 KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), 248 KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), 249 KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), 250 KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), 251 KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), 252 KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), 253 KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), 254 KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), 255 KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), 256 KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), 257 KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), 258 KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), 259 KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), 260 }; 261 262 static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) 263 { 264 return (void *)&cpu->cfg + kvmcfg->offset; 265 } 266 267 static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, 268 uint32_t val) 269 { 270 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 271 272 *ext_enabled = val; 273 } 274 275 static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, 276 KVMCPUConfig *multi_ext) 277 { 278 bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); 279 280 return *ext_enabled; 281 } 282 283 static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, 284 const char *name, 285 void *opaque, Error **errp) 286 { 287 KVMCPUConfig *multi_ext_cfg = opaque; 288 RISCVCPU *cpu = RISCV_CPU(obj); 289 bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 290 291 visit_type_bool(v, name, &value, errp); 292 } 293 294 static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, 295 const char *name, 296 void *opaque, Error **errp) 297 { 298 KVMCPUConfig *multi_ext_cfg = opaque; 299 RISCVCPU *cpu = RISCV_CPU(obj); 300 bool value, host_val; 301 302 if (!visit_type_bool(v, name, &value, errp)) { 303 return; 304 } 305 306 host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 307 308 /* 309 * Ignore if the user is setting the same value 310 * as the host. 311 */ 312 if (value == host_val) { 313 return; 314 } 315 316 if (!multi_ext_cfg->supported) { 317 /* 318 * Error out if the user is trying to enable an 319 * extension that KVM doesn't support. Ignore 320 * option otherwise. 321 */ 322 if (value) { 323 error_setg(errp, "KVM does not support disabling extension %s", 324 multi_ext_cfg->name); 325 } 326 327 return; 328 } 329 330 multi_ext_cfg->user_set = true; 331 kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); 332 } 333 334 static KVMCPUConfig kvm_cbom_blocksize = { 335 .name = "cbom_blocksize", 336 .offset = CPU_CFG_OFFSET(cbom_blocksize), 337 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) 338 }; 339 340 static KVMCPUConfig kvm_cboz_blocksize = { 341 .name = "cboz_blocksize", 342 .offset = CPU_CFG_OFFSET(cboz_blocksize), 343 .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) 344 }; 345 346 static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, 347 const char *name, 348 void *opaque, Error **errp) 349 { 350 KVMCPUConfig *cbomz_cfg = opaque; 351 RISCVCPU *cpu = RISCV_CPU(obj); 352 uint16_t value, *host_val; 353 354 if (!visit_type_uint16(v, name, &value, errp)) { 355 return; 356 } 357 358 host_val = kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 359 360 if (value != *host_val) { 361 error_report("Unable to set %s to a different value than " 362 "the host (%u)", 363 cbomz_cfg->name, *host_val); 364 exit(EXIT_FAILURE); 365 } 366 367 cbomz_cfg->user_set = true; 368 } 369 370 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) 371 { 372 CPURISCVState *env = &cpu->env; 373 uint64_t id, reg; 374 int i, ret; 375 376 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 377 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 378 379 if (!multi_ext_cfg->user_set) { 380 continue; 381 } 382 383 id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 384 multi_ext_cfg->kvm_reg_id); 385 reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); 386 ret = kvm_set_one_reg(cs, id, ®); 387 if (ret != 0) { 388 error_report("Unable to %s extension %s in KVM, error %d", 389 reg ? "enable" : "disable", 390 multi_ext_cfg->name, ret); 391 exit(EXIT_FAILURE); 392 } 393 } 394 } 395 396 static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, 397 const char *name, 398 void *opaque, Error **errp) 399 { 400 bool value = false; 401 402 visit_type_bool(v, name, &value, errp); 403 } 404 405 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 406 const char *name, 407 void *opaque, Error **errp) 408 { 409 const char *propname = opaque; 410 bool value; 411 412 if (!visit_type_bool(v, name, &value, errp)) { 413 return; 414 } 415 416 if (value) { 417 error_setg(errp, "extension %s is not available with KVM", 418 propname); 419 } 420 } 421 422 static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) 423 { 424 /* Check if KVM created the property already */ 425 if (object_property_find(obj, prop_name)) { 426 return; 427 } 428 429 /* 430 * Set the default to disabled for every extension 431 * unknown to KVM and error out if the user attempts 432 * to enable any of them. 433 */ 434 object_property_add(obj, prop_name, "bool", 435 cpu_get_cfg_unavailable, 436 cpu_set_cfg_unavailable, 437 NULL, (void *)prop_name); 438 } 439 440 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, 441 const RISCVCPUMultiExtConfig *array) 442 { 443 const RISCVCPUMultiExtConfig *prop; 444 445 g_assert(array); 446 447 for (prop = array; prop && prop->name; prop++) { 448 riscv_cpu_add_kvm_unavail_prop(obj, prop->name); 449 } 450 } 451 452 static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) 453 { 454 int i; 455 456 riscv_add_satp_mode_properties(cpu_obj); 457 458 for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { 459 KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; 460 int bit = misa_cfg->offset; 461 462 misa_cfg->name = riscv_get_misa_ext_name(bit); 463 misa_cfg->description = riscv_get_misa_ext_description(bit); 464 465 object_property_add(cpu_obj, misa_cfg->name, "bool", 466 kvm_cpu_get_misa_ext_cfg, 467 kvm_cpu_set_misa_ext_cfg, 468 NULL, misa_cfg); 469 object_property_set_description(cpu_obj, misa_cfg->name, 470 misa_cfg->description); 471 } 472 473 for (i = 0; misa_bits[i] != 0; i++) { 474 const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); 475 riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); 476 } 477 478 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 479 KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; 480 481 object_property_add(cpu_obj, multi_cfg->name, "bool", 482 kvm_cpu_get_multi_ext_cfg, 483 kvm_cpu_set_multi_ext_cfg, 484 NULL, multi_cfg); 485 } 486 487 object_property_add(cpu_obj, "cbom_blocksize", "uint16", 488 NULL, kvm_cpu_set_cbomz_blksize, 489 NULL, &kvm_cbom_blocksize); 490 491 object_property_add(cpu_obj, "cboz_blocksize", "uint16", 492 NULL, kvm_cpu_set_cbomz_blksize, 493 NULL, &kvm_cboz_blocksize); 494 495 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); 496 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 497 riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_exts); 498 } 499 500 static int kvm_riscv_get_regs_core(CPUState *cs) 501 { 502 int ret = 0; 503 int i; 504 target_ulong reg; 505 CPURISCVState *env = &RISCV_CPU(cs)->env; 506 507 ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 508 if (ret) { 509 return ret; 510 } 511 env->pc = reg; 512 513 for (i = 1; i < 32; i++) { 514 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 515 ret = kvm_get_one_reg(cs, id, ®); 516 if (ret) { 517 return ret; 518 } 519 env->gpr[i] = reg; 520 } 521 522 return ret; 523 } 524 525 static int kvm_riscv_put_regs_core(CPUState *cs) 526 { 527 int ret = 0; 528 int i; 529 target_ulong reg; 530 CPURISCVState *env = &RISCV_CPU(cs)->env; 531 532 reg = env->pc; 533 ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); 534 if (ret) { 535 return ret; 536 } 537 538 for (i = 1; i < 32; i++) { 539 uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); 540 reg = env->gpr[i]; 541 ret = kvm_set_one_reg(cs, id, ®); 542 if (ret) { 543 return ret; 544 } 545 } 546 547 return ret; 548 } 549 550 static int kvm_riscv_get_regs_csr(CPUState *cs) 551 { 552 CPURISCVState *env = &RISCV_CPU(cs)->env; 553 554 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); 555 KVM_RISCV_GET_CSR(cs, env, sie, env->mie); 556 KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); 557 KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); 558 KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); 559 KVM_RISCV_GET_CSR(cs, env, scause, env->scause); 560 KVM_RISCV_GET_CSR(cs, env, stval, env->stval); 561 KVM_RISCV_GET_CSR(cs, env, sip, env->mip); 562 KVM_RISCV_GET_CSR(cs, env, satp, env->satp); 563 564 return 0; 565 } 566 567 static int kvm_riscv_put_regs_csr(CPUState *cs) 568 { 569 CPURISCVState *env = &RISCV_CPU(cs)->env; 570 571 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); 572 KVM_RISCV_SET_CSR(cs, env, sie, env->mie); 573 KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); 574 KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); 575 KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); 576 KVM_RISCV_SET_CSR(cs, env, scause, env->scause); 577 KVM_RISCV_SET_CSR(cs, env, stval, env->stval); 578 KVM_RISCV_SET_CSR(cs, env, sip, env->mip); 579 KVM_RISCV_SET_CSR(cs, env, satp, env->satp); 580 581 return 0; 582 } 583 584 static int kvm_riscv_get_regs_fp(CPUState *cs) 585 { 586 int ret = 0; 587 int i; 588 CPURISCVState *env = &RISCV_CPU(cs)->env; 589 590 if (riscv_has_ext(env, RVD)) { 591 uint64_t reg; 592 for (i = 0; i < 32; i++) { 593 ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); 594 if (ret) { 595 return ret; 596 } 597 env->fpr[i] = reg; 598 } 599 return ret; 600 } 601 602 if (riscv_has_ext(env, RVF)) { 603 uint32_t reg; 604 for (i = 0; i < 32; i++) { 605 ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); 606 if (ret) { 607 return ret; 608 } 609 env->fpr[i] = reg; 610 } 611 return ret; 612 } 613 614 return ret; 615 } 616 617 static int kvm_riscv_put_regs_fp(CPUState *cs) 618 { 619 int ret = 0; 620 int i; 621 CPURISCVState *env = &RISCV_CPU(cs)->env; 622 623 if (riscv_has_ext(env, RVD)) { 624 uint64_t reg; 625 for (i = 0; i < 32; i++) { 626 reg = env->fpr[i]; 627 ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); 628 if (ret) { 629 return ret; 630 } 631 } 632 return ret; 633 } 634 635 if (riscv_has_ext(env, RVF)) { 636 uint32_t reg; 637 for (i = 0; i < 32; i++) { 638 reg = env->fpr[i]; 639 ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); 640 if (ret) { 641 return ret; 642 } 643 } 644 return ret; 645 } 646 647 return ret; 648 } 649 650 static void kvm_riscv_get_regs_timer(CPUState *cs) 651 { 652 CPURISCVState *env = &RISCV_CPU(cs)->env; 653 654 if (env->kvm_timer_dirty) { 655 return; 656 } 657 658 KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); 659 KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); 660 KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); 661 KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); 662 663 env->kvm_timer_dirty = true; 664 } 665 666 static void kvm_riscv_put_regs_timer(CPUState *cs) 667 { 668 uint64_t reg; 669 CPURISCVState *env = &RISCV_CPU(cs)->env; 670 671 if (!env->kvm_timer_dirty) { 672 return; 673 } 674 675 KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); 676 KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); 677 678 /* 679 * To set register of RISCV_TIMER_REG(state) will occur a error from KVM 680 * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it 681 * doesn't matter that adaping in QEMU now. 682 * TODO If KVM changes, adapt here. 683 */ 684 if (env->kvm_timer_state) { 685 KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); 686 } 687 688 /* 689 * For now, migration will not work between Hosts with different timer 690 * frequency. Therefore, we should check whether they are the same here 691 * during the migration. 692 */ 693 if (migration_is_running(migrate_get_current()->state)) { 694 KVM_RISCV_GET_TIMER(cs, frequency, reg); 695 if (reg != env->kvm_timer_frequency) { 696 error_report("Dst Hosts timer frequency != Src Hosts"); 697 } 698 } 699 700 env->kvm_timer_dirty = false; 701 } 702 703 typedef struct KVMScratchCPU { 704 int kvmfd; 705 int vmfd; 706 int cpufd; 707 } KVMScratchCPU; 708 709 /* 710 * Heavily inspired by kvm_arm_create_scratch_host_vcpu() 711 * from target/arm/kvm.c. 712 */ 713 static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) 714 { 715 int kvmfd = -1, vmfd = -1, cpufd = -1; 716 717 kvmfd = qemu_open_old("/dev/kvm", O_RDWR); 718 if (kvmfd < 0) { 719 goto err; 720 } 721 do { 722 vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); 723 } while (vmfd == -1 && errno == EINTR); 724 if (vmfd < 0) { 725 goto err; 726 } 727 cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); 728 if (cpufd < 0) { 729 goto err; 730 } 731 732 scratch->kvmfd = kvmfd; 733 scratch->vmfd = vmfd; 734 scratch->cpufd = cpufd; 735 736 return true; 737 738 err: 739 if (cpufd >= 0) { 740 close(cpufd); 741 } 742 if (vmfd >= 0) { 743 close(vmfd); 744 } 745 if (kvmfd >= 0) { 746 close(kvmfd); 747 } 748 749 return false; 750 } 751 752 static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) 753 { 754 close(scratch->cpufd); 755 close(scratch->vmfd); 756 close(scratch->kvmfd); 757 } 758 759 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 760 { 761 CPURISCVState *env = &cpu->env; 762 struct kvm_one_reg reg; 763 int ret; 764 765 reg.id = RISCV_CONFIG_REG(env, mvendorid); 766 reg.addr = (uint64_t)&cpu->cfg.mvendorid; 767 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 768 if (ret != 0) { 769 error_report("Unable to retrieve mvendorid from host, error %d", ret); 770 } 771 772 reg.id = RISCV_CONFIG_REG(env, marchid); 773 reg.addr = (uint64_t)&cpu->cfg.marchid; 774 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 775 if (ret != 0) { 776 error_report("Unable to retrieve marchid from host, error %d", ret); 777 } 778 779 reg.id = RISCV_CONFIG_REG(env, mimpid); 780 reg.addr = (uint64_t)&cpu->cfg.mimpid; 781 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 782 if (ret != 0) { 783 error_report("Unable to retrieve mimpid from host, error %d", ret); 784 } 785 } 786 787 static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, 788 KVMScratchCPU *kvmcpu) 789 { 790 CPURISCVState *env = &cpu->env; 791 struct kvm_one_reg reg; 792 int ret; 793 794 reg.id = RISCV_CONFIG_REG(env, isa); 795 reg.addr = (uint64_t)&env->misa_ext_mask; 796 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 797 798 if (ret) { 799 error_report("Unable to fetch ISA register from KVM, " 800 "error %d", ret); 801 kvm_riscv_destroy_scratch_vcpu(kvmcpu); 802 exit(EXIT_FAILURE); 803 } 804 805 env->misa_ext = env->misa_ext_mask; 806 } 807 808 static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, 809 KVMCPUConfig *cbomz_cfg) 810 { 811 CPURISCVState *env = &cpu->env; 812 struct kvm_one_reg reg; 813 int ret; 814 815 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, 816 cbomz_cfg->kvm_reg_id); 817 reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); 818 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 819 if (ret != 0) { 820 error_report("Unable to read KVM reg %s, error %d", 821 cbomz_cfg->name, ret); 822 exit(EXIT_FAILURE); 823 } 824 } 825 826 static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, 827 KVMScratchCPU *kvmcpu) 828 { 829 CPURISCVState *env = &cpu->env; 830 uint64_t val; 831 int i, ret; 832 833 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 834 KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 835 struct kvm_one_reg reg; 836 837 reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, 838 multi_ext_cfg->kvm_reg_id); 839 reg.addr = (uint64_t)&val; 840 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 841 if (ret != 0) { 842 if (errno == EINVAL) { 843 /* Silently default to 'false' if KVM does not support it. */ 844 multi_ext_cfg->supported = false; 845 val = false; 846 } else { 847 error_report("Unable to read ISA_EXT KVM register %s: %s", 848 multi_ext_cfg->name, strerror(errno)); 849 exit(EXIT_FAILURE); 850 } 851 } else { 852 multi_ext_cfg->supported = true; 853 } 854 855 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 856 } 857 858 if (cpu->cfg.ext_zicbom) { 859 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 860 } 861 862 if (cpu->cfg.ext_zicboz) { 863 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 864 } 865 } 866 867 static int uint64_cmp(const void *a, const void *b) 868 { 869 uint64_t val1 = *(const uint64_t *)a; 870 uint64_t val2 = *(const uint64_t *)b; 871 872 if (val1 < val2) { 873 return -1; 874 } 875 876 if (val1 > val2) { 877 return 1; 878 } 879 880 return 0; 881 } 882 883 static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) 884 { 885 KVMCPUConfig *multi_ext_cfg; 886 struct kvm_one_reg reg; 887 struct kvm_reg_list rl_struct; 888 struct kvm_reg_list *reglist; 889 uint64_t val, reg_id, *reg_search; 890 int i, ret; 891 892 rl_struct.n = 0; 893 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); 894 895 /* 896 * If KVM_GET_REG_LIST isn't supported we'll get errno 22 897 * (EINVAL). Use read_legacy() in this case. 898 */ 899 if (errno == EINVAL) { 900 return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); 901 } else if (errno != E2BIG) { 902 /* 903 * E2BIG is an expected error message for the API since we 904 * don't know the number of registers. The right amount will 905 * be written in rl_struct.n. 906 * 907 * Error out if we get any other errno. 908 */ 909 error_report("Error when accessing get-reg-list: %s", 910 strerror(errno)); 911 exit(EXIT_FAILURE); 912 } 913 914 reglist = g_malloc(sizeof(struct kvm_reg_list) + 915 rl_struct.n * sizeof(uint64_t)); 916 reglist->n = rl_struct.n; 917 ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); 918 if (ret) { 919 error_report("Error when reading KVM_GET_REG_LIST: %s", 920 strerror(errno)); 921 exit(EXIT_FAILURE); 922 } 923 924 /* sort reglist to use bsearch() */ 925 qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); 926 927 for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { 928 multi_ext_cfg = &kvm_multi_ext_cfgs[i]; 929 reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, 930 multi_ext_cfg->kvm_reg_id); 931 reg_search = bsearch(®_id, reglist->reg, reglist->n, 932 sizeof(uint64_t), uint64_cmp); 933 if (!reg_search) { 934 continue; 935 } 936 937 reg.id = reg_id; 938 reg.addr = (uint64_t)&val; 939 ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); 940 if (ret != 0) { 941 error_report("Unable to read ISA_EXT KVM register %s: %s", 942 multi_ext_cfg->name, strerror(errno)); 943 exit(EXIT_FAILURE); 944 } 945 946 multi_ext_cfg->supported = true; 947 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); 948 } 949 950 if (cpu->cfg.ext_zicbom) { 951 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); 952 } 953 954 if (cpu->cfg.ext_zicboz) { 955 kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); 956 } 957 } 958 959 static void riscv_init_kvm_registers(Object *cpu_obj) 960 { 961 RISCVCPU *cpu = RISCV_CPU(cpu_obj); 962 KVMScratchCPU kvmcpu; 963 964 if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { 965 return; 966 } 967 968 kvm_riscv_init_machine_ids(cpu, &kvmcpu); 969 kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); 970 kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); 971 972 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); 973 } 974 975 const KVMCapabilityInfo kvm_arch_required_capabilities[] = { 976 KVM_CAP_LAST_INFO 977 }; 978 979 int kvm_arch_get_registers(CPUState *cs) 980 { 981 int ret = 0; 982 983 ret = kvm_riscv_get_regs_core(cs); 984 if (ret) { 985 return ret; 986 } 987 988 ret = kvm_riscv_get_regs_csr(cs); 989 if (ret) { 990 return ret; 991 } 992 993 ret = kvm_riscv_get_regs_fp(cs); 994 if (ret) { 995 return ret; 996 } 997 998 return ret; 999 } 1000 1001 int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state) 1002 { 1003 if (cap_has_mp_state) { 1004 struct kvm_mp_state mp_state = { 1005 .mp_state = state 1006 }; 1007 1008 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); 1009 if (ret) { 1010 fprintf(stderr, "%s: failed to sync MP_STATE %d/%s\n", 1011 __func__, ret, strerror(-ret)); 1012 return -1; 1013 } 1014 } 1015 1016 return 0; 1017 } 1018 1019 int kvm_arch_put_registers(CPUState *cs, int level) 1020 { 1021 int ret = 0; 1022 1023 ret = kvm_riscv_put_regs_core(cs); 1024 if (ret) { 1025 return ret; 1026 } 1027 1028 ret = kvm_riscv_put_regs_csr(cs); 1029 if (ret) { 1030 return ret; 1031 } 1032 1033 ret = kvm_riscv_put_regs_fp(cs); 1034 if (ret) { 1035 return ret; 1036 } 1037 1038 if (KVM_PUT_RESET_STATE == level) { 1039 RISCVCPU *cpu = RISCV_CPU(cs); 1040 if (cs->cpu_index == 0) { 1041 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_RUNNABLE); 1042 } else { 1043 ret = kvm_riscv_sync_mpstate_to_kvm(cpu, KVM_MP_STATE_STOPPED); 1044 } 1045 if (ret) { 1046 return ret; 1047 } 1048 } 1049 1050 return ret; 1051 } 1052 1053 int kvm_arch_release_virq_post(int virq) 1054 { 1055 return 0; 1056 } 1057 1058 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, 1059 uint64_t address, uint32_t data, PCIDevice *dev) 1060 { 1061 return 0; 1062 } 1063 1064 int kvm_arch_destroy_vcpu(CPUState *cs) 1065 { 1066 return 0; 1067 } 1068 1069 unsigned long kvm_arch_vcpu_id(CPUState *cpu) 1070 { 1071 return cpu->cpu_index; 1072 } 1073 1074 static void kvm_riscv_vm_state_change(void *opaque, bool running, 1075 RunState state) 1076 { 1077 CPUState *cs = opaque; 1078 1079 if (running) { 1080 kvm_riscv_put_regs_timer(cs); 1081 } else { 1082 kvm_riscv_get_regs_timer(cs); 1083 } 1084 } 1085 1086 void kvm_arch_init_irq_routing(KVMState *s) 1087 { 1088 } 1089 1090 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) 1091 { 1092 CPURISCVState *env = &cpu->env; 1093 target_ulong reg; 1094 uint64_t id; 1095 int ret; 1096 1097 id = RISCV_CONFIG_REG(env, mvendorid); 1098 /* 1099 * cfg.mvendorid is an uint32 but a target_ulong will 1100 * be written. Assign it to a target_ulong var to avoid 1101 * writing pieces of other cpu->cfg fields in the reg. 1102 */ 1103 reg = cpu->cfg.mvendorid; 1104 ret = kvm_set_one_reg(cs, id, ®); 1105 if (ret != 0) { 1106 return ret; 1107 } 1108 1109 id = RISCV_CONFIG_REG(env, marchid); 1110 ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); 1111 if (ret != 0) { 1112 return ret; 1113 } 1114 1115 id = RISCV_CONFIG_REG(env, mimpid); 1116 ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); 1117 1118 return ret; 1119 } 1120 1121 int kvm_arch_init_vcpu(CPUState *cs) 1122 { 1123 int ret = 0; 1124 RISCVCPU *cpu = RISCV_CPU(cs); 1125 1126 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); 1127 1128 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { 1129 ret = kvm_vcpu_set_machine_ids(cpu, cs); 1130 if (ret != 0) { 1131 return ret; 1132 } 1133 } 1134 1135 kvm_riscv_update_cpu_misa_ext(cpu, cs); 1136 kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); 1137 1138 return ret; 1139 } 1140 1141 int kvm_arch_msi_data_to_gsi(uint32_t data) 1142 { 1143 abort(); 1144 } 1145 1146 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, 1147 int vector, PCIDevice *dev) 1148 { 1149 return 0; 1150 } 1151 1152 int kvm_arch_get_default_type(MachineState *ms) 1153 { 1154 return 0; 1155 } 1156 1157 int kvm_arch_init(MachineState *ms, KVMState *s) 1158 { 1159 cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); 1160 return 0; 1161 } 1162 1163 int kvm_arch_irqchip_create(KVMState *s) 1164 { 1165 if (kvm_kernel_irqchip_split()) { 1166 error_report("-machine kernel_irqchip=split is not supported on RISC-V."); 1167 exit(1); 1168 } 1169 1170 /* 1171 * We can create the VAIA using the newer device control API. 1172 */ 1173 return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); 1174 } 1175 1176 int kvm_arch_process_async_events(CPUState *cs) 1177 { 1178 return 0; 1179 } 1180 1181 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) 1182 { 1183 } 1184 1185 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) 1186 { 1187 return MEMTXATTRS_UNSPECIFIED; 1188 } 1189 1190 bool kvm_arch_stop_on_emulation_error(CPUState *cs) 1191 { 1192 return true; 1193 } 1194 1195 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) 1196 { 1197 int ret = 0; 1198 unsigned char ch; 1199 switch (run->riscv_sbi.extension_id) { 1200 case SBI_EXT_0_1_CONSOLE_PUTCHAR: 1201 ch = run->riscv_sbi.args[0]; 1202 qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); 1203 break; 1204 case SBI_EXT_0_1_CONSOLE_GETCHAR: 1205 ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); 1206 if (ret == sizeof(ch)) { 1207 run->riscv_sbi.ret[0] = ch; 1208 } else { 1209 run->riscv_sbi.ret[0] = -1; 1210 } 1211 ret = 0; 1212 break; 1213 default: 1214 qemu_log_mask(LOG_UNIMP, 1215 "%s: un-handled SBI EXIT, specific reasons is %lu\n", 1216 __func__, run->riscv_sbi.extension_id); 1217 ret = -1; 1218 break; 1219 } 1220 return ret; 1221 } 1222 1223 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) 1224 { 1225 int ret = 0; 1226 switch (run->exit_reason) { 1227 case KVM_EXIT_RISCV_SBI: 1228 ret = kvm_riscv_handle_sbi(cs, run); 1229 break; 1230 default: 1231 qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", 1232 __func__, run->exit_reason); 1233 ret = -1; 1234 break; 1235 } 1236 return ret; 1237 } 1238 1239 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) 1240 { 1241 CPURISCVState *env = &cpu->env; 1242 int i; 1243 1244 if (!kvm_enabled()) { 1245 return; 1246 } 1247 for (i = 0; i < 32; i++) { 1248 env->gpr[i] = 0; 1249 } 1250 env->pc = cpu->env.kernel_addr; 1251 env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ 1252 env->gpr[11] = cpu->env.fdt_addr; /* a1 */ 1253 env->satp = 0; 1254 env->mie = 0; 1255 env->stvec = 0; 1256 env->sscratch = 0; 1257 env->sepc = 0; 1258 env->scause = 0; 1259 env->stval = 0; 1260 env->mip = 0; 1261 } 1262 1263 void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) 1264 { 1265 int ret; 1266 unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; 1267 1268 if (irq != IRQ_S_EXT) { 1269 perror("kvm riscv set irq != IRQ_S_EXT\n"); 1270 abort(); 1271 } 1272 1273 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); 1274 if (ret < 0) { 1275 perror("Set irq failed"); 1276 abort(); 1277 } 1278 } 1279 1280 bool kvm_arch_cpu_check_are_resettable(void) 1281 { 1282 return true; 1283 } 1284 1285 static int aia_mode; 1286 1287 static const char *kvm_aia_mode_str(uint64_t mode) 1288 { 1289 switch (mode) { 1290 case KVM_DEV_RISCV_AIA_MODE_EMUL: 1291 return "emul"; 1292 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 1293 return "hwaccel"; 1294 case KVM_DEV_RISCV_AIA_MODE_AUTO: 1295 default: 1296 return "auto"; 1297 }; 1298 } 1299 1300 static char *riscv_get_kvm_aia(Object *obj, Error **errp) 1301 { 1302 return g_strdup(kvm_aia_mode_str(aia_mode)); 1303 } 1304 1305 static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) 1306 { 1307 if (!strcmp(val, "emul")) { 1308 aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; 1309 } else if (!strcmp(val, "hwaccel")) { 1310 aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; 1311 } else if (!strcmp(val, "auto")) { 1312 aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; 1313 } else { 1314 error_setg(errp, "Invalid KVM AIA mode"); 1315 error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); 1316 } 1317 } 1318 1319 void kvm_arch_accel_class_init(ObjectClass *oc) 1320 { 1321 object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, 1322 riscv_set_kvm_aia); 1323 object_class_property_set_description(oc, "riscv-aia", 1324 "Set KVM AIA mode. Valid values are " 1325 "emul, hwaccel, and auto. Default " 1326 "is auto."); 1327 object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), 1328 "auto"); 1329 } 1330 1331 void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, 1332 uint64_t aia_irq_num, uint64_t aia_msi_num, 1333 uint64_t aplic_base, uint64_t imsic_base, 1334 uint64_t guest_num) 1335 { 1336 int ret, i; 1337 int aia_fd = -1; 1338 uint64_t default_aia_mode; 1339 uint64_t socket_count = riscv_socket_count(machine); 1340 uint64_t max_hart_per_socket = 0; 1341 uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; 1342 uint64_t socket_bits, hart_bits, guest_bits; 1343 1344 aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); 1345 1346 if (aia_fd < 0) { 1347 error_report("Unable to create in-kernel irqchip"); 1348 exit(1); 1349 } 1350 1351 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1352 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1353 &default_aia_mode, false, NULL); 1354 if (ret < 0) { 1355 error_report("KVM AIA: failed to get current KVM AIA mode"); 1356 exit(1); 1357 } 1358 qemu_log("KVM AIA: default mode is %s\n", 1359 kvm_aia_mode_str(default_aia_mode)); 1360 1361 if (default_aia_mode != aia_mode) { 1362 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1363 KVM_DEV_RISCV_AIA_CONFIG_MODE, 1364 &aia_mode, true, NULL); 1365 if (ret < 0) 1366 warn_report("KVM AIA: failed to set KVM AIA mode"); 1367 else 1368 qemu_log("KVM AIA: set current mode to %s\n", 1369 kvm_aia_mode_str(aia_mode)); 1370 } 1371 1372 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1373 KVM_DEV_RISCV_AIA_CONFIG_SRCS, 1374 &aia_irq_num, true, NULL); 1375 if (ret < 0) { 1376 error_report("KVM AIA: failed to set number of input irq lines"); 1377 exit(1); 1378 } 1379 1380 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1381 KVM_DEV_RISCV_AIA_CONFIG_IDS, 1382 &aia_msi_num, true, NULL); 1383 if (ret < 0) { 1384 error_report("KVM AIA: failed to set number of msi"); 1385 exit(1); 1386 } 1387 1388 socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; 1389 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1390 KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, 1391 &socket_bits, true, NULL); 1392 if (ret < 0) { 1393 error_report("KVM AIA: failed to set group_bits"); 1394 exit(1); 1395 } 1396 1397 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1398 KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, 1399 &group_shift, true, NULL); 1400 if (ret < 0) { 1401 error_report("KVM AIA: failed to set group_shift"); 1402 exit(1); 1403 } 1404 1405 guest_bits = guest_num == 0 ? 0 : 1406 find_last_bit(&guest_num, BITS_PER_LONG) + 1; 1407 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1408 KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, 1409 &guest_bits, true, NULL); 1410 if (ret < 0) { 1411 error_report("KVM AIA: failed to set guest_bits"); 1412 exit(1); 1413 } 1414 1415 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1416 KVM_DEV_RISCV_AIA_ADDR_APLIC, 1417 &aplic_base, true, NULL); 1418 if (ret < 0) { 1419 error_report("KVM AIA: failed to set the base address of APLIC"); 1420 exit(1); 1421 } 1422 1423 for (socket = 0; socket < socket_count; socket++) { 1424 socket_imsic_base = imsic_base + socket * (1U << group_shift); 1425 hart_count = riscv_socket_hart_count(machine, socket); 1426 base_hart = riscv_socket_first_hartid(machine, socket); 1427 1428 if (max_hart_per_socket < hart_count) { 1429 max_hart_per_socket = hart_count; 1430 } 1431 1432 for (i = 0; i < hart_count; i++) { 1433 imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); 1434 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, 1435 KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), 1436 &imsic_addr, true, NULL); 1437 if (ret < 0) { 1438 error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); 1439 exit(1); 1440 } 1441 } 1442 } 1443 1444 hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; 1445 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, 1446 KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, 1447 &hart_bits, true, NULL); 1448 if (ret < 0) { 1449 error_report("KVM AIA: failed to set hart_bits"); 1450 exit(1); 1451 } 1452 1453 if (kvm_has_gsi_routing()) { 1454 for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { 1455 /* KVM AIA only has one APLIC instance */ 1456 kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); 1457 } 1458 kvm_gsi_routing_allowed = true; 1459 kvm_irqchip_commit_routes(kvm_state); 1460 } 1461 1462 ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, 1463 KVM_DEV_RISCV_AIA_CTRL_INIT, 1464 NULL, true, NULL); 1465 if (ret < 0) { 1466 error_report("KVM AIA: initialized fail"); 1467 exit(1); 1468 } 1469 1470 kvm_msi_via_irqfd_allowed = true; 1471 } 1472 1473 static void kvm_cpu_instance_init(CPUState *cs) 1474 { 1475 Object *obj = OBJECT(RISCV_CPU(cs)); 1476 DeviceState *dev = DEVICE(obj); 1477 1478 riscv_init_kvm_registers(obj); 1479 1480 kvm_riscv_add_cpu_user_properties(obj); 1481 1482 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1483 /* Check if we have a specific KVM handler for the option */ 1484 if (object_property_find(obj, prop->name)) { 1485 continue; 1486 } 1487 qdev_property_add_static(dev, prop); 1488 } 1489 } 1490 1491 static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) 1492 { 1493 AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); 1494 1495 acc->cpu_instance_init = kvm_cpu_instance_init; 1496 } 1497 1498 static const TypeInfo kvm_cpu_accel_type_info = { 1499 .name = ACCEL_CPU_NAME("kvm"), 1500 1501 .parent = TYPE_ACCEL_CPU, 1502 .class_init = kvm_cpu_accel_class_init, 1503 .abstract = true, 1504 }; 1505 static void kvm_cpu_accel_register_types(void) 1506 { 1507 type_register_static(&kvm_cpu_accel_type_info); 1508 } 1509 type_init(kvm_cpu_accel_register_types); 1510 1511 static void riscv_host_cpu_init(Object *obj) 1512 { 1513 CPURISCVState *env = &RISCV_CPU(obj)->env; 1514 1515 #if defined(TARGET_RISCV32) 1516 env->misa_mxl_max = env->misa_mxl = MXL_RV32; 1517 #elif defined(TARGET_RISCV64) 1518 env->misa_mxl_max = env->misa_mxl = MXL_RV64; 1519 #endif 1520 } 1521 1522 static const TypeInfo riscv_kvm_cpu_type_infos[] = { 1523 { 1524 .name = TYPE_RISCV_CPU_HOST, 1525 .parent = TYPE_RISCV_CPU, 1526 .instance_init = riscv_host_cpu_init, 1527 } 1528 }; 1529 1530 DEFINE_TYPES(riscv_kvm_cpu_type_infos) 1531