xref: /qemu/target/riscv/trace-events (revision 2582a95c)
1b15e402fSMarkus Armbruster# cpu_helper.c
2929f0a7fSMichael Clarkriscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s"
36591efb5SPhilippe Mathieu-Daudé
46591efb5SPhilippe Mathieu-Daudé# pmp.c
56591efb5SPhilippe Mathieu-Daudépmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": read reg%" PRIu32", val: 0x%" PRIx64
66591efb5SPhilippe Mathieu-Daudépmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64
76591efb5SPhilippe Mathieu-Daudépmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64
86591efb5SPhilippe Mathieu-Daudépmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64
9*2582a95cSHou Weiying
10*2582a95cSHou Weiyingmseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64
11*2582a95cSHou Weiyingmseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64
12