1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 #define HELPER_H "helper.h" 37 #include "exec/helper-info.c.inc" 38 #undef HELPER_H 39 40 /* global register indices */ 41 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 42 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 43 static TCGv load_res; 44 static TCGv load_val; 45 /* globals for PM CSRs */ 46 static TCGv pm_mask; 47 static TCGv pm_base; 48 49 /* 50 * If an operation is being performed on less than TARGET_LONG_BITS, 51 * it may require the inputs to be sign- or zero-extended; which will 52 * depend on the exact operation being performed. 53 */ 54 typedef enum { 55 EXT_NONE, 56 EXT_SIGN, 57 EXT_ZERO, 58 } DisasExtend; 59 60 typedef struct DisasContext { 61 DisasContextBase base; 62 /* pc_succ_insn points to the instruction following base.pc_next */ 63 target_ulong pc_succ_insn; 64 target_ulong priv_ver; 65 RISCVMXL misa_mxl_max; 66 RISCVMXL xl; 67 uint32_t misa_ext; 68 uint32_t opcode; 69 RISCVExtStatus mstatus_fs; 70 RISCVExtStatus mstatus_vs; 71 uint32_t mem_idx; 72 uint32_t priv; 73 /* 74 * Remember the rounding mode encoded in the previous fp instruction, 75 * which we have already installed into env->fp_status. Or -1 for 76 * no previous fp instruction. Note that we exit the TB when writing 77 * to any system register, which includes CSR_FRM, so we do not have 78 * to reset this known value. 79 */ 80 int frm; 81 RISCVMXL ol; 82 bool virt_inst_excp; 83 bool virt_enabled; 84 const RISCVCPUConfig *cfg_ptr; 85 /* vector extension */ 86 bool vill; 87 /* 88 * Encode LMUL to lmul as follows: 89 * LMUL vlmul lmul 90 * 1 000 0 91 * 2 001 1 92 * 4 010 2 93 * 8 011 3 94 * - 100 - 95 * 1/8 101 -3 96 * 1/4 110 -2 97 * 1/2 111 -1 98 */ 99 int8_t lmul; 100 uint8_t sew; 101 uint8_t vta; 102 uint8_t vma; 103 bool cfg_vta_all_1s; 104 bool vstart_eq_zero; 105 bool vl_eq_vlmax; 106 CPUState *cs; 107 TCGv zero; 108 /* PointerMasking extension */ 109 bool pm_mask_enabled; 110 bool pm_base_enabled; 111 /* Use icount trigger for native debug */ 112 bool itrigger; 113 /* FRM is known to contain a valid value. */ 114 bool frm_valid; 115 /* TCG of the current insn_start */ 116 TCGOp *insn_start; 117 } DisasContext; 118 119 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 120 { 121 return ctx->misa_ext & ext; 122 } 123 124 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 125 { 126 return true; 127 } 128 129 static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) 130 { 131 return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || 132 ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || 133 ctx->cfg_ptr->ext_xtheadcondmov || 134 ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || 135 ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || 136 ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; 137 } 138 139 #define MATERIALISE_EXT_PREDICATE(ext) \ 140 static bool has_ ## ext ## _p(DisasContext *ctx) \ 141 { \ 142 return ctx->cfg_ptr->ext_ ## ext ; \ 143 } 144 145 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 146 147 #ifdef TARGET_RISCV32 148 #define get_xl(ctx) MXL_RV32 149 #elif defined(CONFIG_USER_ONLY) 150 #define get_xl(ctx) MXL_RV64 151 #else 152 #define get_xl(ctx) ((ctx)->xl) 153 #endif 154 155 /* The word size for this machine mode. */ 156 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 157 { 158 return 16 << get_xl(ctx); 159 } 160 161 /* The operation length, as opposed to the xlen. */ 162 #ifdef TARGET_RISCV32 163 #define get_ol(ctx) MXL_RV32 164 #else 165 #define get_ol(ctx) ((ctx)->ol) 166 #endif 167 168 static inline int get_olen(DisasContext *ctx) 169 { 170 return 16 << get_ol(ctx); 171 } 172 173 /* The maximum register length */ 174 #ifdef TARGET_RISCV32 175 #define get_xl_max(ctx) MXL_RV32 176 #else 177 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 178 #endif 179 180 /* 181 * RISC-V requires NaN-boxing of narrower width floating point values. 182 * This applies when a 32-bit value is assigned to a 64-bit FP register. 183 * For consistency and simplicity, we nanbox results even when the RVD 184 * extension is not present. 185 */ 186 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 187 { 188 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 189 } 190 191 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 192 { 193 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 194 } 195 196 /* 197 * A narrow n-bit operation, where n < FLEN, checks that input operands 198 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 199 * If so, the least-significant bits of the input are used, otherwise the 200 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 201 * 202 * Here, the result is always nan-boxed, even the canonical nan. 203 */ 204 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 205 { 206 TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull); 207 TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull); 208 209 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 210 } 211 212 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 213 { 214 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 215 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 216 217 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 218 } 219 220 static void decode_save_opc(DisasContext *ctx) 221 { 222 assert(ctx->insn_start != NULL); 223 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 224 ctx->insn_start = NULL; 225 } 226 227 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 228 { 229 if (get_xl(ctx) == MXL_RV32) { 230 dest = (int32_t)dest; 231 } 232 tcg_gen_movi_tl(cpu_pc, dest); 233 } 234 235 static void gen_set_pc(DisasContext *ctx, TCGv dest) 236 { 237 if (get_xl(ctx) == MXL_RV32) { 238 tcg_gen_ext32s_tl(cpu_pc, dest); 239 } else { 240 tcg_gen_mov_tl(cpu_pc, dest); 241 } 242 } 243 244 static void generate_exception(DisasContext *ctx, int excp) 245 { 246 gen_set_pc_imm(ctx, ctx->base.pc_next); 247 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 248 ctx->base.is_jmp = DISAS_NORETURN; 249 } 250 251 static void gen_exception_illegal(DisasContext *ctx) 252 { 253 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 254 offsetof(CPURISCVState, bins)); 255 if (ctx->virt_inst_excp) { 256 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 257 } else { 258 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 259 } 260 } 261 262 static void gen_exception_inst_addr_mis(DisasContext *ctx) 263 { 264 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 265 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 266 } 267 268 static void lookup_and_goto_ptr(DisasContext *ctx) 269 { 270 #ifndef CONFIG_USER_ONLY 271 if (ctx->itrigger) { 272 gen_helper_itrigger_match(cpu_env); 273 } 274 #endif 275 tcg_gen_lookup_and_goto_ptr(); 276 } 277 278 static void exit_tb(DisasContext *ctx) 279 { 280 #ifndef CONFIG_USER_ONLY 281 if (ctx->itrigger) { 282 gen_helper_itrigger_match(cpu_env); 283 } 284 #endif 285 tcg_gen_exit_tb(NULL, 0); 286 } 287 288 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 289 { 290 /* 291 * Under itrigger, instruction executes one by one like singlestep, 292 * direct block chain benefits will be small. 293 */ 294 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 295 tcg_gen_goto_tb(n); 296 gen_set_pc_imm(ctx, dest); 297 tcg_gen_exit_tb(ctx->base.tb, n); 298 } else { 299 gen_set_pc_imm(ctx, dest); 300 lookup_and_goto_ptr(ctx); 301 } 302 } 303 304 /* 305 * Wrappers for getting reg values. 306 * 307 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 308 * constant zero as a source, and an uninitialized sink as destination. 309 * 310 * Further, we may provide an extension for word operations. 311 */ 312 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 313 { 314 TCGv t; 315 316 if (reg_num == 0) { 317 return ctx->zero; 318 } 319 320 switch (get_ol(ctx)) { 321 case MXL_RV32: 322 switch (ext) { 323 case EXT_NONE: 324 break; 325 case EXT_SIGN: 326 t = tcg_temp_new(); 327 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 328 return t; 329 case EXT_ZERO: 330 t = tcg_temp_new(); 331 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 332 return t; 333 default: 334 g_assert_not_reached(); 335 } 336 break; 337 case MXL_RV64: 338 case MXL_RV128: 339 break; 340 default: 341 g_assert_not_reached(); 342 } 343 return cpu_gpr[reg_num]; 344 } 345 346 static TCGv get_gprh(DisasContext *ctx, int reg_num) 347 { 348 assert(get_xl(ctx) == MXL_RV128); 349 if (reg_num == 0) { 350 return ctx->zero; 351 } 352 return cpu_gprh[reg_num]; 353 } 354 355 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 356 { 357 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 358 return tcg_temp_new(); 359 } 360 return cpu_gpr[reg_num]; 361 } 362 363 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 364 { 365 if (reg_num == 0) { 366 return tcg_temp_new(); 367 } 368 return cpu_gprh[reg_num]; 369 } 370 371 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 372 { 373 if (reg_num != 0) { 374 switch (get_ol(ctx)) { 375 case MXL_RV32: 376 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 377 break; 378 case MXL_RV64: 379 case MXL_RV128: 380 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 381 break; 382 default: 383 g_assert_not_reached(); 384 } 385 386 if (get_xl_max(ctx) == MXL_RV128) { 387 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 388 } 389 } 390 } 391 392 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 393 { 394 if (reg_num != 0) { 395 switch (get_ol(ctx)) { 396 case MXL_RV32: 397 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 398 break; 399 case MXL_RV64: 400 case MXL_RV128: 401 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 402 break; 403 default: 404 g_assert_not_reached(); 405 } 406 407 if (get_xl_max(ctx) == MXL_RV128) { 408 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 409 } 410 } 411 } 412 413 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 414 { 415 assert(get_ol(ctx) == MXL_RV128); 416 if (reg_num != 0) { 417 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 418 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 419 } 420 } 421 422 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 423 { 424 if (!ctx->cfg_ptr->ext_zfinx) { 425 return cpu_fpr[reg_num]; 426 } 427 428 if (reg_num == 0) { 429 return tcg_constant_i64(0); 430 } 431 switch (get_xl(ctx)) { 432 case MXL_RV32: 433 #ifdef TARGET_RISCV32 434 { 435 TCGv_i64 t = tcg_temp_new_i64(); 436 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 437 return t; 438 } 439 #else 440 /* fall through */ 441 case MXL_RV64: 442 return cpu_gpr[reg_num]; 443 #endif 444 default: 445 g_assert_not_reached(); 446 } 447 } 448 449 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 450 { 451 if (!ctx->cfg_ptr->ext_zfinx) { 452 return cpu_fpr[reg_num]; 453 } 454 455 if (reg_num == 0) { 456 return tcg_constant_i64(0); 457 } 458 switch (get_xl(ctx)) { 459 case MXL_RV32: 460 { 461 TCGv_i64 t = tcg_temp_new_i64(); 462 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 463 return t; 464 } 465 #ifdef TARGET_RISCV64 466 case MXL_RV64: 467 return cpu_gpr[reg_num]; 468 #endif 469 default: 470 g_assert_not_reached(); 471 } 472 } 473 474 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 475 { 476 if (!ctx->cfg_ptr->ext_zfinx) { 477 return cpu_fpr[reg_num]; 478 } 479 480 if (reg_num == 0) { 481 return tcg_temp_new_i64(); 482 } 483 484 switch (get_xl(ctx)) { 485 case MXL_RV32: 486 return tcg_temp_new_i64(); 487 #ifdef TARGET_RISCV64 488 case MXL_RV64: 489 return cpu_gpr[reg_num]; 490 #endif 491 default: 492 g_assert_not_reached(); 493 } 494 } 495 496 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ 497 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 498 { 499 if (!ctx->cfg_ptr->ext_zfinx) { 500 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 501 return; 502 } 503 if (reg_num != 0) { 504 switch (get_xl(ctx)) { 505 case MXL_RV32: 506 #ifdef TARGET_RISCV32 507 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 508 break; 509 #else 510 /* fall through */ 511 case MXL_RV64: 512 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 513 break; 514 #endif 515 default: 516 g_assert_not_reached(); 517 } 518 } 519 } 520 521 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 522 { 523 if (!ctx->cfg_ptr->ext_zfinx) { 524 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 525 return; 526 } 527 528 if (reg_num != 0) { 529 switch (get_xl(ctx)) { 530 case MXL_RV32: 531 #ifdef TARGET_RISCV32 532 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 533 break; 534 #else 535 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 536 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 537 break; 538 case MXL_RV64: 539 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 540 break; 541 #endif 542 default: 543 g_assert_not_reached(); 544 } 545 } 546 } 547 548 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 549 { 550 target_ulong next_pc; 551 552 /* check misaligned: */ 553 next_pc = ctx->base.pc_next + imm; 554 if (!ctx->cfg_ptr->ext_zca) { 555 if ((next_pc & 0x3) != 0) { 556 gen_exception_inst_addr_mis(ctx); 557 return; 558 } 559 } 560 561 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 562 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 563 ctx->base.is_jmp = DISAS_NORETURN; 564 } 565 566 /* Compute a canonical address from a register plus offset. */ 567 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 568 { 569 TCGv addr = tcg_temp_new(); 570 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 571 572 tcg_gen_addi_tl(addr, src1, imm); 573 if (ctx->pm_mask_enabled) { 574 tcg_gen_andc_tl(addr, addr, pm_mask); 575 } else if (get_xl(ctx) == MXL_RV32) { 576 tcg_gen_ext32u_tl(addr, addr); 577 } 578 if (ctx->pm_base_enabled) { 579 tcg_gen_or_tl(addr, addr, pm_base); 580 } 581 return addr; 582 } 583 584 /* Compute a canonical address from a register plus reg offset. */ 585 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 586 { 587 TCGv addr = tcg_temp_new(); 588 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 589 590 tcg_gen_add_tl(addr, src1, offs); 591 if (ctx->pm_mask_enabled) { 592 tcg_gen_andc_tl(addr, addr, pm_mask); 593 } else if (get_xl(ctx) == MXL_RV32) { 594 tcg_gen_ext32u_tl(addr, addr); 595 } 596 if (ctx->pm_base_enabled) { 597 tcg_gen_or_tl(addr, addr, pm_base); 598 } 599 return addr; 600 } 601 602 #ifndef CONFIG_USER_ONLY 603 /* 604 * We will have already diagnosed disabled state, 605 * and need to turn initial/clean into dirty. 606 */ 607 static void mark_fs_dirty(DisasContext *ctx) 608 { 609 TCGv tmp; 610 611 if (!has_ext(ctx, RVF)) { 612 return; 613 } 614 615 if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { 616 /* Remember the state change for the rest of the TB. */ 617 ctx->mstatus_fs = EXT_STATUS_DIRTY; 618 619 tmp = tcg_temp_new(); 620 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 621 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 622 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 623 624 if (ctx->virt_enabled) { 625 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 626 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 627 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 628 } 629 } 630 } 631 #else 632 static inline void mark_fs_dirty(DisasContext *ctx) { } 633 #endif 634 635 #ifndef CONFIG_USER_ONLY 636 /* 637 * We will have already diagnosed disabled state, 638 * and need to turn initial/clean into dirty. 639 */ 640 static void mark_vs_dirty(DisasContext *ctx) 641 { 642 TCGv tmp; 643 644 if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { 645 /* Remember the state change for the rest of the TB. */ 646 ctx->mstatus_vs = EXT_STATUS_DIRTY; 647 648 tmp = tcg_temp_new(); 649 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 650 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 651 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 652 653 if (ctx->virt_enabled) { 654 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 655 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 656 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 657 } 658 } 659 } 660 #else 661 static inline void mark_vs_dirty(DisasContext *ctx) { } 662 #endif 663 664 static void gen_set_rm(DisasContext *ctx, int rm) 665 { 666 if (ctx->frm == rm) { 667 return; 668 } 669 ctx->frm = rm; 670 671 if (rm == RISCV_FRM_DYN) { 672 /* The helper will return only if frm valid. */ 673 ctx->frm_valid = true; 674 } 675 676 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 677 decode_save_opc(ctx); 678 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 679 } 680 681 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 682 { 683 if (ctx->frm == rm && ctx->frm_valid) { 684 return; 685 } 686 ctx->frm = rm; 687 ctx->frm_valid = true; 688 689 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 690 decode_save_opc(ctx); 691 gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); 692 } 693 694 static int ex_plus_1(DisasContext *ctx, int nf) 695 { 696 return nf + 1; 697 } 698 699 #define EX_SH(amount) \ 700 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 701 { \ 702 return imm << amount; \ 703 } 704 EX_SH(1) 705 EX_SH(2) 706 EX_SH(3) 707 EX_SH(4) 708 EX_SH(12) 709 710 #define REQUIRE_EXT(ctx, ext) do { \ 711 if (!has_ext(ctx, ext)) { \ 712 return false; \ 713 } \ 714 } while (0) 715 716 #define REQUIRE_32BIT(ctx) do { \ 717 if (get_xl(ctx) != MXL_RV32) { \ 718 return false; \ 719 } \ 720 } while (0) 721 722 #define REQUIRE_64BIT(ctx) do { \ 723 if (get_xl(ctx) != MXL_RV64) { \ 724 return false; \ 725 } \ 726 } while (0) 727 728 #define REQUIRE_128BIT(ctx) do { \ 729 if (get_xl(ctx) != MXL_RV128) { \ 730 return false; \ 731 } \ 732 } while (0) 733 734 #define REQUIRE_64_OR_128BIT(ctx) do { \ 735 if (get_xl(ctx) == MXL_RV32) { \ 736 return false; \ 737 } \ 738 } while (0) 739 740 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 741 if (!ctx->cfg_ptr->ext_##A && \ 742 !ctx->cfg_ptr->ext_##B) { \ 743 return false; \ 744 } \ 745 } while (0) 746 747 static int ex_rvc_register(DisasContext *ctx, int reg) 748 { 749 return 8 + reg; 750 } 751 752 static int ex_sreg_register(DisasContext *ctx, int reg) 753 { 754 return reg < 2 ? reg + 8 : reg + 16; 755 } 756 757 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 758 { 759 /* For RV128 a shamt of 0 means a shift by 64. */ 760 if (get_ol(ctx) == MXL_RV128) { 761 imm = imm ? imm : 64; 762 } 763 return imm; 764 } 765 766 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 767 { 768 /* 769 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 770 * shifts, the shamt is sign-extended. 771 */ 772 if (get_ol(ctx) == MXL_RV128) { 773 imm = imm | (imm & 32) << 1; 774 imm = imm ? imm : 64; 775 } 776 return imm; 777 } 778 779 /* Include the auto-generated decoder for 32 bit insn */ 780 #include "decode-insn32.c.inc" 781 782 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 783 void (*func)(TCGv, TCGv, target_long)) 784 { 785 TCGv dest = dest_gpr(ctx, a->rd); 786 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 787 788 func(dest, src1, a->imm); 789 790 if (get_xl(ctx) == MXL_RV128) { 791 TCGv src1h = get_gprh(ctx, a->rs1); 792 TCGv desth = dest_gprh(ctx, a->rd); 793 794 func(desth, src1h, -(a->imm < 0)); 795 gen_set_gpr128(ctx, a->rd, dest, desth); 796 } else { 797 gen_set_gpr(ctx, a->rd, dest); 798 } 799 800 return true; 801 } 802 803 static bool gen_logic(DisasContext *ctx, arg_r *a, 804 void (*func)(TCGv, TCGv, TCGv)) 805 { 806 TCGv dest = dest_gpr(ctx, a->rd); 807 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 808 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 809 810 func(dest, src1, src2); 811 812 if (get_xl(ctx) == MXL_RV128) { 813 TCGv src1h = get_gprh(ctx, a->rs1); 814 TCGv src2h = get_gprh(ctx, a->rs2); 815 TCGv desth = dest_gprh(ctx, a->rd); 816 817 func(desth, src1h, src2h); 818 gen_set_gpr128(ctx, a->rd, dest, desth); 819 } else { 820 gen_set_gpr(ctx, a->rd, dest); 821 } 822 823 return true; 824 } 825 826 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 827 void (*func)(TCGv, TCGv, target_long), 828 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 829 { 830 TCGv dest = dest_gpr(ctx, a->rd); 831 TCGv src1 = get_gpr(ctx, a->rs1, ext); 832 833 if (get_ol(ctx) < MXL_RV128) { 834 func(dest, src1, a->imm); 835 gen_set_gpr(ctx, a->rd, dest); 836 } else { 837 if (f128 == NULL) { 838 return false; 839 } 840 841 TCGv src1h = get_gprh(ctx, a->rs1); 842 TCGv desth = dest_gprh(ctx, a->rd); 843 844 f128(dest, desth, src1, src1h, a->imm); 845 gen_set_gpr128(ctx, a->rd, dest, desth); 846 } 847 return true; 848 } 849 850 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 851 void (*func)(TCGv, TCGv, TCGv), 852 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 853 { 854 TCGv dest = dest_gpr(ctx, a->rd); 855 TCGv src1 = get_gpr(ctx, a->rs1, ext); 856 TCGv src2 = tcg_constant_tl(a->imm); 857 858 if (get_ol(ctx) < MXL_RV128) { 859 func(dest, src1, src2); 860 gen_set_gpr(ctx, a->rd, dest); 861 } else { 862 if (f128 == NULL) { 863 return false; 864 } 865 866 TCGv src1h = get_gprh(ctx, a->rs1); 867 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 868 TCGv desth = dest_gprh(ctx, a->rd); 869 870 f128(dest, desth, src1, src1h, src2, src2h); 871 gen_set_gpr128(ctx, a->rd, dest, desth); 872 } 873 return true; 874 } 875 876 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 877 void (*func)(TCGv, TCGv, TCGv), 878 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 879 { 880 TCGv dest = dest_gpr(ctx, a->rd); 881 TCGv src1 = get_gpr(ctx, a->rs1, ext); 882 TCGv src2 = get_gpr(ctx, a->rs2, ext); 883 884 if (get_ol(ctx) < MXL_RV128) { 885 func(dest, src1, src2); 886 gen_set_gpr(ctx, a->rd, dest); 887 } else { 888 if (f128 == NULL) { 889 return false; 890 } 891 892 TCGv src1h = get_gprh(ctx, a->rs1); 893 TCGv src2h = get_gprh(ctx, a->rs2); 894 TCGv desth = dest_gprh(ctx, a->rd); 895 896 f128(dest, desth, src1, src1h, src2, src2h); 897 gen_set_gpr128(ctx, a->rd, dest, desth); 898 } 899 return true; 900 } 901 902 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 903 void (*f_tl)(TCGv, TCGv, TCGv), 904 void (*f_32)(TCGv, TCGv, TCGv), 905 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 906 { 907 int olen = get_olen(ctx); 908 909 if (olen != TARGET_LONG_BITS) { 910 if (olen == 32) { 911 f_tl = f_32; 912 } else if (olen != 128) { 913 g_assert_not_reached(); 914 } 915 } 916 return gen_arith(ctx, a, ext, f_tl, f_128); 917 } 918 919 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 920 void (*func)(TCGv, TCGv, target_long), 921 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 922 { 923 TCGv dest, src1; 924 int max_len = get_olen(ctx); 925 926 if (a->shamt >= max_len) { 927 return false; 928 } 929 930 dest = dest_gpr(ctx, a->rd); 931 src1 = get_gpr(ctx, a->rs1, ext); 932 933 if (max_len < 128) { 934 func(dest, src1, a->shamt); 935 gen_set_gpr(ctx, a->rd, dest); 936 } else { 937 TCGv src1h = get_gprh(ctx, a->rs1); 938 TCGv desth = dest_gprh(ctx, a->rd); 939 940 if (f128 == NULL) { 941 return false; 942 } 943 f128(dest, desth, src1, src1h, a->shamt); 944 gen_set_gpr128(ctx, a->rd, dest, desth); 945 } 946 return true; 947 } 948 949 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 950 DisasExtend ext, 951 void (*f_tl)(TCGv, TCGv, target_long), 952 void (*f_32)(TCGv, TCGv, target_long), 953 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 954 target_long)) 955 { 956 int olen = get_olen(ctx); 957 if (olen != TARGET_LONG_BITS) { 958 if (olen == 32) { 959 f_tl = f_32; 960 } else if (olen != 128) { 961 g_assert_not_reached(); 962 } 963 } 964 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 965 } 966 967 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 968 void (*func)(TCGv, TCGv, TCGv)) 969 { 970 TCGv dest, src1, src2; 971 int max_len = get_olen(ctx); 972 973 if (a->shamt >= max_len) { 974 return false; 975 } 976 977 dest = dest_gpr(ctx, a->rd); 978 src1 = get_gpr(ctx, a->rs1, ext); 979 src2 = tcg_constant_tl(a->shamt); 980 981 func(dest, src1, src2); 982 983 gen_set_gpr(ctx, a->rd, dest); 984 return true; 985 } 986 987 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 988 void (*func)(TCGv, TCGv, TCGv), 989 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 990 { 991 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 992 TCGv ext2 = tcg_temp_new(); 993 int max_len = get_olen(ctx); 994 995 tcg_gen_andi_tl(ext2, src2, max_len - 1); 996 997 TCGv dest = dest_gpr(ctx, a->rd); 998 TCGv src1 = get_gpr(ctx, a->rs1, ext); 999 1000 if (max_len < 128) { 1001 func(dest, src1, ext2); 1002 gen_set_gpr(ctx, a->rd, dest); 1003 } else { 1004 TCGv src1h = get_gprh(ctx, a->rs1); 1005 TCGv desth = dest_gprh(ctx, a->rd); 1006 1007 if (f128 == NULL) { 1008 return false; 1009 } 1010 f128(dest, desth, src1, src1h, ext2); 1011 gen_set_gpr128(ctx, a->rd, dest, desth); 1012 } 1013 return true; 1014 } 1015 1016 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1017 void (*f_tl)(TCGv, TCGv, TCGv), 1018 void (*f_32)(TCGv, TCGv, TCGv), 1019 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1020 { 1021 int olen = get_olen(ctx); 1022 if (olen != TARGET_LONG_BITS) { 1023 if (olen == 32) { 1024 f_tl = f_32; 1025 } else if (olen != 128) { 1026 g_assert_not_reached(); 1027 } 1028 } 1029 return gen_shift(ctx, a, ext, f_tl, f_128); 1030 } 1031 1032 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1033 void (*func)(TCGv, TCGv)) 1034 { 1035 TCGv dest = dest_gpr(ctx, a->rd); 1036 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1037 1038 func(dest, src1); 1039 1040 gen_set_gpr(ctx, a->rd, dest); 1041 return true; 1042 } 1043 1044 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1045 void (*f_tl)(TCGv, TCGv), 1046 void (*f_32)(TCGv, TCGv)) 1047 { 1048 int olen = get_olen(ctx); 1049 1050 if (olen != TARGET_LONG_BITS) { 1051 if (olen == 32) { 1052 f_tl = f_32; 1053 } else { 1054 g_assert_not_reached(); 1055 } 1056 } 1057 return gen_unary(ctx, a, ext, f_tl); 1058 } 1059 1060 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1061 { 1062 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1063 CPUState *cpu = ctx->cs; 1064 CPURISCVState *env = cpu->env_ptr; 1065 1066 return cpu_ldl_code(env, pc); 1067 } 1068 1069 /* Include insn module translation function */ 1070 #include "insn_trans/trans_rvi.c.inc" 1071 #include "insn_trans/trans_rvm.c.inc" 1072 #include "insn_trans/trans_rva.c.inc" 1073 #include "insn_trans/trans_rvf.c.inc" 1074 #include "insn_trans/trans_rvd.c.inc" 1075 #include "insn_trans/trans_rvh.c.inc" 1076 #include "insn_trans/trans_rvv.c.inc" 1077 #include "insn_trans/trans_rvb.c.inc" 1078 #include "insn_trans/trans_rvzicond.c.inc" 1079 #include "insn_trans/trans_rvzawrs.c.inc" 1080 #include "insn_trans/trans_rvzicbo.c.inc" 1081 #include "insn_trans/trans_rvzfh.c.inc" 1082 #include "insn_trans/trans_rvk.c.inc" 1083 #include "insn_trans/trans_privileged.c.inc" 1084 #include "insn_trans/trans_svinval.c.inc" 1085 #include "decode-xthead.c.inc" 1086 #include "insn_trans/trans_xthead.c.inc" 1087 #include "insn_trans/trans_xventanacondops.c.inc" 1088 1089 /* Include the auto-generated decoder for 16 bit insn */ 1090 #include "decode-insn16.c.inc" 1091 #include "insn_trans/trans_rvzce.c.inc" 1092 1093 /* Include decoders for factored-out extensions */ 1094 #include "decode-XVentanaCondOps.c.inc" 1095 1096 /* The specification allows for longer insns, but not supported by qemu. */ 1097 #define MAX_INSN_LEN 4 1098 1099 static inline int insn_len(uint16_t first_word) 1100 { 1101 return (first_word & 3) == 3 ? 4 : 2; 1102 } 1103 1104 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1105 { 1106 /* 1107 * A table with predicate (i.e., guard) functions and decoder functions 1108 * that are tested in-order until a decoder matches onto the opcode. 1109 */ 1110 static const struct { 1111 bool (*guard_func)(DisasContext *); 1112 bool (*decode_func)(DisasContext *, uint32_t); 1113 } decoders[] = { 1114 { always_true_p, decode_insn32 }, 1115 { has_xthead_p, decode_xthead }, 1116 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1117 }; 1118 1119 ctx->virt_inst_excp = false; 1120 /* Check for compressed insn */ 1121 if (insn_len(opcode) == 2) { 1122 ctx->opcode = opcode; 1123 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1124 /* 1125 * The Zca extension is added as way to refer to instructions in the C 1126 * extension that do not include the floating-point loads and stores 1127 */ 1128 if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) { 1129 return; 1130 } 1131 } else { 1132 uint32_t opcode32 = opcode; 1133 opcode32 = deposit32(opcode32, 16, 16, 1134 translator_lduw(env, &ctx->base, 1135 ctx->base.pc_next + 2)); 1136 ctx->opcode = opcode32; 1137 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1138 1139 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1140 if (decoders[i].guard_func(ctx) && 1141 decoders[i].decode_func(ctx, opcode32)) { 1142 return; 1143 } 1144 } 1145 } 1146 1147 gen_exception_illegal(ctx); 1148 } 1149 1150 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1151 { 1152 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1153 CPURISCVState *env = cs->env_ptr; 1154 RISCVCPU *cpu = RISCV_CPU(cs); 1155 uint32_t tb_flags = ctx->base.tb->flags; 1156 1157 ctx->pc_succ_insn = ctx->base.pc_first; 1158 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 1159 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1160 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); 1161 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); 1162 ctx->priv_ver = env->priv_ver; 1163 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); 1164 ctx->misa_ext = env->misa_ext; 1165 ctx->frm = -1; /* unknown rounding mode */ 1166 ctx->cfg_ptr = &(cpu->cfg); 1167 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1168 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1169 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1170 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1171 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1172 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1173 ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); 1174 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1175 ctx->misa_mxl_max = env->misa_mxl_max; 1176 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1177 ctx->cs = cs; 1178 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1179 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1180 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1181 ctx->zero = tcg_constant_tl(0); 1182 ctx->virt_inst_excp = false; 1183 } 1184 1185 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1186 { 1187 } 1188 1189 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1190 { 1191 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1192 1193 tcg_gen_insn_start(ctx->base.pc_next, 0); 1194 ctx->insn_start = tcg_last_op(); 1195 } 1196 1197 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1198 { 1199 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1200 CPURISCVState *env = cpu->env_ptr; 1201 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1202 1203 ctx->ol = ctx->xl; 1204 decode_opc(env, ctx, opcode16); 1205 ctx->base.pc_next = ctx->pc_succ_insn; 1206 1207 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1208 if (ctx->base.is_jmp == DISAS_NEXT) { 1209 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1210 ctx->base.is_jmp = DISAS_TOO_MANY; 1211 } else { 1212 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1213 1214 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1215 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1216 int len = insn_len(next_insn); 1217 1218 if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { 1219 ctx->base.is_jmp = DISAS_TOO_MANY; 1220 } 1221 } 1222 } 1223 } 1224 } 1225 1226 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1227 { 1228 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1229 1230 switch (ctx->base.is_jmp) { 1231 case DISAS_TOO_MANY: 1232 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1233 break; 1234 case DISAS_NORETURN: 1235 break; 1236 default: 1237 g_assert_not_reached(); 1238 } 1239 } 1240 1241 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1242 CPUState *cpu, FILE *logfile) 1243 { 1244 #ifndef CONFIG_USER_ONLY 1245 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1246 CPURISCVState *env = &rvcpu->env; 1247 #endif 1248 1249 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1250 #ifndef CONFIG_USER_ONLY 1251 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n", 1252 env->priv, env->virt_enabled); 1253 #endif 1254 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1255 } 1256 1257 static const TranslatorOps riscv_tr_ops = { 1258 .init_disas_context = riscv_tr_init_disas_context, 1259 .tb_start = riscv_tr_tb_start, 1260 .insn_start = riscv_tr_insn_start, 1261 .translate_insn = riscv_tr_translate_insn, 1262 .tb_stop = riscv_tr_tb_stop, 1263 .disas_log = riscv_tr_disas_log, 1264 }; 1265 1266 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1267 target_ulong pc, void *host_pc) 1268 { 1269 DisasContext ctx; 1270 1271 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1272 } 1273 1274 void riscv_translate_init(void) 1275 { 1276 int i; 1277 1278 /* 1279 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1280 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1281 * unless you specifically block reads/writes to reg 0. 1282 */ 1283 cpu_gpr[0] = NULL; 1284 cpu_gprh[0] = NULL; 1285 1286 for (i = 1; i < 32; i++) { 1287 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1288 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1289 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1290 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1291 } 1292 1293 for (i = 0; i < 32; i++) { 1294 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1295 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1296 } 1297 1298 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1299 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1300 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1301 "vstart"); 1302 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1303 "load_res"); 1304 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1305 "load_val"); 1306 /* Assign PM CSRs to tcg globals */ 1307 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1308 "pmmask"); 1309 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1310 "pmbase"); 1311 } 1312