1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask; 42 static TCGv pm_base; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 const RISCVCPUConfig *cfg_ptr; 80 bool hlsx; 81 /* vector extension */ 82 bool vill; 83 /* 84 * Encode LMUL to lmul as follows: 85 * LMUL vlmul lmul 86 * 1 000 0 87 * 2 001 1 88 * 4 010 2 89 * 8 011 3 90 * - 100 - 91 * 1/8 101 -3 92 * 1/4 110 -2 93 * 1/2 111 -1 94 */ 95 int8_t lmul; 96 uint8_t sew; 97 target_ulong vstart; 98 bool vl_eq_vlmax; 99 uint8_t ntemp; 100 CPUState *cs; 101 TCGv zero; 102 /* Space for 3 operands plus 1 extra for address computation. */ 103 TCGv temp[4]; 104 /* PointerMasking extension */ 105 bool pm_mask_enabled; 106 bool pm_base_enabled; 107 } DisasContext; 108 109 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 110 { 111 return ctx->misa_ext & ext; 112 } 113 114 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 115 { 116 return true; 117 } 118 119 #define MATERIALISE_EXT_PREDICATE(ext) \ 120 static bool has_ ## ext ## _p(DisasContext *ctx) \ 121 { \ 122 return ctx->cfg_ptr->ext_ ## ext ; \ 123 } 124 125 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 126 127 #ifdef TARGET_RISCV32 128 #define get_xl(ctx) MXL_RV32 129 #elif defined(CONFIG_USER_ONLY) 130 #define get_xl(ctx) MXL_RV64 131 #else 132 #define get_xl(ctx) ((ctx)->xl) 133 #endif 134 135 /* The word size for this machine mode. */ 136 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 137 { 138 return 16 << get_xl(ctx); 139 } 140 141 /* The operation length, as opposed to the xlen. */ 142 #ifdef TARGET_RISCV32 143 #define get_ol(ctx) MXL_RV32 144 #else 145 #define get_ol(ctx) ((ctx)->ol) 146 #endif 147 148 static inline int get_olen(DisasContext *ctx) 149 { 150 return 16 << get_ol(ctx); 151 } 152 153 /* The maximum register length */ 154 #ifdef TARGET_RISCV32 155 #define get_xl_max(ctx) MXL_RV32 156 #else 157 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 158 #endif 159 160 /* 161 * RISC-V requires NaN-boxing of narrower width floating point values. 162 * This applies when a 32-bit value is assigned to a 64-bit FP register. 163 * For consistency and simplicity, we nanbox results even when the RVD 164 * extension is not present. 165 */ 166 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 167 { 168 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 169 } 170 171 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 172 { 173 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 174 } 175 176 /* 177 * A narrow n-bit operation, where n < FLEN, checks that input operands 178 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 179 * If so, the least-significant bits of the input are used, otherwise the 180 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 181 * 182 * Here, the result is always nan-boxed, even the canonical nan. 183 */ 184 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 185 { 186 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 187 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 188 189 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 190 tcg_temp_free_i64(t_max); 191 tcg_temp_free_i64(t_nan); 192 } 193 194 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 195 { 196 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 197 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 198 199 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 200 } 201 202 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 203 { 204 if (get_xl(ctx) == MXL_RV32) { 205 dest = (int32_t)dest; 206 } 207 tcg_gen_movi_tl(cpu_pc, dest); 208 } 209 210 static void gen_set_pc(DisasContext *ctx, TCGv dest) 211 { 212 if (get_xl(ctx) == MXL_RV32) { 213 tcg_gen_ext32s_tl(cpu_pc, dest); 214 } else { 215 tcg_gen_mov_tl(cpu_pc, dest); 216 } 217 } 218 219 static void generate_exception(DisasContext *ctx, int excp) 220 { 221 gen_set_pc_imm(ctx, ctx->base.pc_next); 222 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 223 ctx->base.is_jmp = DISAS_NORETURN; 224 } 225 226 static void generate_exception_mtval(DisasContext *ctx, int excp) 227 { 228 gen_set_pc_imm(ctx, ctx->base.pc_next); 229 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 230 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 231 ctx->base.is_jmp = DISAS_NORETURN; 232 } 233 234 static void gen_exception_illegal(DisasContext *ctx) 235 { 236 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 237 offsetof(CPURISCVState, bins)); 238 239 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 240 } 241 242 static void gen_exception_inst_addr_mis(DisasContext *ctx) 243 { 244 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 245 } 246 247 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 248 { 249 if (translator_use_goto_tb(&ctx->base, dest)) { 250 tcg_gen_goto_tb(n); 251 gen_set_pc_imm(ctx, dest); 252 tcg_gen_exit_tb(ctx->base.tb, n); 253 } else { 254 gen_set_pc_imm(ctx, dest); 255 tcg_gen_lookup_and_goto_ptr(); 256 } 257 } 258 259 /* 260 * Wrappers for getting reg values. 261 * 262 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 263 * constant zero as a source, and an uninitialized sink as destination. 264 * 265 * Further, we may provide an extension for word operations. 266 */ 267 static TCGv temp_new(DisasContext *ctx) 268 { 269 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 270 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 271 } 272 273 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 274 { 275 TCGv t; 276 277 if (reg_num == 0) { 278 return ctx->zero; 279 } 280 281 switch (get_ol(ctx)) { 282 case MXL_RV32: 283 switch (ext) { 284 case EXT_NONE: 285 break; 286 case EXT_SIGN: 287 t = temp_new(ctx); 288 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 289 return t; 290 case EXT_ZERO: 291 t = temp_new(ctx); 292 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 293 return t; 294 default: 295 g_assert_not_reached(); 296 } 297 break; 298 case MXL_RV64: 299 case MXL_RV128: 300 break; 301 default: 302 g_assert_not_reached(); 303 } 304 return cpu_gpr[reg_num]; 305 } 306 307 static TCGv get_gprh(DisasContext *ctx, int reg_num) 308 { 309 assert(get_xl(ctx) == MXL_RV128); 310 if (reg_num == 0) { 311 return ctx->zero; 312 } 313 return cpu_gprh[reg_num]; 314 } 315 316 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 317 { 318 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 319 return temp_new(ctx); 320 } 321 return cpu_gpr[reg_num]; 322 } 323 324 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 325 { 326 if (reg_num == 0) { 327 return temp_new(ctx); 328 } 329 return cpu_gprh[reg_num]; 330 } 331 332 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 333 { 334 if (reg_num != 0) { 335 switch (get_ol(ctx)) { 336 case MXL_RV32: 337 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 338 break; 339 case MXL_RV64: 340 case MXL_RV128: 341 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 342 break; 343 default: 344 g_assert_not_reached(); 345 } 346 347 if (get_xl_max(ctx) == MXL_RV128) { 348 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 349 } 350 } 351 } 352 353 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 354 { 355 if (reg_num != 0) { 356 switch (get_ol(ctx)) { 357 case MXL_RV32: 358 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 359 break; 360 case MXL_RV64: 361 case MXL_RV128: 362 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 363 break; 364 default: 365 g_assert_not_reached(); 366 } 367 368 if (get_xl_max(ctx) == MXL_RV128) { 369 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 370 } 371 } 372 } 373 374 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 375 { 376 assert(get_ol(ctx) == MXL_RV128); 377 if (reg_num != 0) { 378 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 379 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 380 } 381 } 382 383 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 384 { 385 target_ulong next_pc; 386 387 /* check misaligned: */ 388 next_pc = ctx->base.pc_next + imm; 389 if (!has_ext(ctx, RVC)) { 390 if ((next_pc & 0x3) != 0) { 391 gen_exception_inst_addr_mis(ctx); 392 return; 393 } 394 } 395 396 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 397 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 398 ctx->base.is_jmp = DISAS_NORETURN; 399 } 400 401 /* Compute a canonical address from a register plus offset. */ 402 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 403 { 404 TCGv addr = temp_new(ctx); 405 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 406 407 tcg_gen_addi_tl(addr, src1, imm); 408 if (ctx->pm_mask_enabled) { 409 tcg_gen_and_tl(addr, addr, pm_mask); 410 } else if (get_xl(ctx) == MXL_RV32) { 411 tcg_gen_ext32u_tl(addr, addr); 412 } 413 if (ctx->pm_base_enabled) { 414 tcg_gen_or_tl(addr, addr, pm_base); 415 } 416 return addr; 417 } 418 419 #ifndef CONFIG_USER_ONLY 420 /* The states of mstatus_fs are: 421 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 422 * We will have already diagnosed disabled state, 423 * and need to turn initial/clean into dirty. 424 */ 425 static void mark_fs_dirty(DisasContext *ctx) 426 { 427 TCGv tmp; 428 429 if (ctx->mstatus_fs != MSTATUS_FS) { 430 /* Remember the state change for the rest of the TB. */ 431 ctx->mstatus_fs = MSTATUS_FS; 432 433 tmp = tcg_temp_new(); 434 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 435 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 436 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 437 tcg_temp_free(tmp); 438 } 439 440 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 441 /* Remember the stage change for the rest of the TB. */ 442 ctx->mstatus_hs_fs = MSTATUS_FS; 443 444 tmp = tcg_temp_new(); 445 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 446 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 447 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 448 tcg_temp_free(tmp); 449 } 450 } 451 #else 452 static inline void mark_fs_dirty(DisasContext *ctx) { } 453 #endif 454 455 #ifndef CONFIG_USER_ONLY 456 /* The states of mstatus_vs are: 457 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 458 * We will have already diagnosed disabled state, 459 * and need to turn initial/clean into dirty. 460 */ 461 static void mark_vs_dirty(DisasContext *ctx) 462 { 463 TCGv tmp; 464 465 if (ctx->mstatus_vs != MSTATUS_VS) { 466 /* Remember the state change for the rest of the TB. */ 467 ctx->mstatus_vs = MSTATUS_VS; 468 469 tmp = tcg_temp_new(); 470 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 471 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 472 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 473 tcg_temp_free(tmp); 474 } 475 476 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 477 /* Remember the stage change for the rest of the TB. */ 478 ctx->mstatus_hs_vs = MSTATUS_VS; 479 480 tmp = tcg_temp_new(); 481 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 482 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 483 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 484 tcg_temp_free(tmp); 485 } 486 } 487 #else 488 static inline void mark_vs_dirty(DisasContext *ctx) { } 489 #endif 490 491 static void gen_set_rm(DisasContext *ctx, int rm) 492 { 493 if (ctx->frm == rm) { 494 return; 495 } 496 ctx->frm = rm; 497 498 if (rm == RISCV_FRM_ROD) { 499 gen_helper_set_rod_rounding_mode(cpu_env); 500 return; 501 } 502 503 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 504 } 505 506 static int ex_plus_1(DisasContext *ctx, int nf) 507 { 508 return nf + 1; 509 } 510 511 #define EX_SH(amount) \ 512 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 513 { \ 514 return imm << amount; \ 515 } 516 EX_SH(1) 517 EX_SH(2) 518 EX_SH(3) 519 EX_SH(4) 520 EX_SH(12) 521 522 #define REQUIRE_EXT(ctx, ext) do { \ 523 if (!has_ext(ctx, ext)) { \ 524 return false; \ 525 } \ 526 } while (0) 527 528 #define REQUIRE_32BIT(ctx) do { \ 529 if (get_xl(ctx) != MXL_RV32) { \ 530 return false; \ 531 } \ 532 } while (0) 533 534 #define REQUIRE_64BIT(ctx) do { \ 535 if (get_xl(ctx) != MXL_RV64) { \ 536 return false; \ 537 } \ 538 } while (0) 539 540 #define REQUIRE_128BIT(ctx) do { \ 541 if (get_xl(ctx) != MXL_RV128) { \ 542 return false; \ 543 } \ 544 } while (0) 545 546 #define REQUIRE_64_OR_128BIT(ctx) do { \ 547 if (get_xl(ctx) == MXL_RV32) { \ 548 return false; \ 549 } \ 550 } while (0) 551 552 static int ex_rvc_register(DisasContext *ctx, int reg) 553 { 554 return 8 + reg; 555 } 556 557 static int ex_rvc_shifti(DisasContext *ctx, int imm) 558 { 559 /* For RV128 a shamt of 0 means a shift by 64. */ 560 return imm ? imm : 64; 561 } 562 563 /* Include the auto-generated decoder for 32 bit insn */ 564 #include "decode-insn32.c.inc" 565 566 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 567 void (*func)(TCGv, TCGv, target_long)) 568 { 569 TCGv dest = dest_gpr(ctx, a->rd); 570 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 571 572 func(dest, src1, a->imm); 573 574 if (get_xl(ctx) == MXL_RV128) { 575 TCGv src1h = get_gprh(ctx, a->rs1); 576 TCGv desth = dest_gprh(ctx, a->rd); 577 578 func(desth, src1h, -(a->imm < 0)); 579 gen_set_gpr128(ctx, a->rd, dest, desth); 580 } else { 581 gen_set_gpr(ctx, a->rd, dest); 582 } 583 584 return true; 585 } 586 587 static bool gen_logic(DisasContext *ctx, arg_r *a, 588 void (*func)(TCGv, TCGv, TCGv)) 589 { 590 TCGv dest = dest_gpr(ctx, a->rd); 591 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 592 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 593 594 func(dest, src1, src2); 595 596 if (get_xl(ctx) == MXL_RV128) { 597 TCGv src1h = get_gprh(ctx, a->rs1); 598 TCGv src2h = get_gprh(ctx, a->rs2); 599 TCGv desth = dest_gprh(ctx, a->rd); 600 601 func(desth, src1h, src2h); 602 gen_set_gpr128(ctx, a->rd, dest, desth); 603 } else { 604 gen_set_gpr(ctx, a->rd, dest); 605 } 606 607 return true; 608 } 609 610 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 611 void (*func)(TCGv, TCGv, target_long), 612 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 613 { 614 TCGv dest = dest_gpr(ctx, a->rd); 615 TCGv src1 = get_gpr(ctx, a->rs1, ext); 616 617 if (get_ol(ctx) < MXL_RV128) { 618 func(dest, src1, a->imm); 619 gen_set_gpr(ctx, a->rd, dest); 620 } else { 621 if (f128 == NULL) { 622 return false; 623 } 624 625 TCGv src1h = get_gprh(ctx, a->rs1); 626 TCGv desth = dest_gprh(ctx, a->rd); 627 628 f128(dest, desth, src1, src1h, a->imm); 629 gen_set_gpr128(ctx, a->rd, dest, desth); 630 } 631 return true; 632 } 633 634 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 635 void (*func)(TCGv, TCGv, TCGv), 636 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 637 { 638 TCGv dest = dest_gpr(ctx, a->rd); 639 TCGv src1 = get_gpr(ctx, a->rs1, ext); 640 TCGv src2 = tcg_constant_tl(a->imm); 641 642 if (get_ol(ctx) < MXL_RV128) { 643 func(dest, src1, src2); 644 gen_set_gpr(ctx, a->rd, dest); 645 } else { 646 if (f128 == NULL) { 647 return false; 648 } 649 650 TCGv src1h = get_gprh(ctx, a->rs1); 651 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 652 TCGv desth = dest_gprh(ctx, a->rd); 653 654 f128(dest, desth, src1, src1h, src2, src2h); 655 gen_set_gpr128(ctx, a->rd, dest, desth); 656 } 657 return true; 658 } 659 660 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 661 void (*func)(TCGv, TCGv, TCGv), 662 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 663 { 664 TCGv dest = dest_gpr(ctx, a->rd); 665 TCGv src1 = get_gpr(ctx, a->rs1, ext); 666 TCGv src2 = get_gpr(ctx, a->rs2, ext); 667 668 if (get_ol(ctx) < MXL_RV128) { 669 func(dest, src1, src2); 670 gen_set_gpr(ctx, a->rd, dest); 671 } else { 672 if (f128 == NULL) { 673 return false; 674 } 675 676 TCGv src1h = get_gprh(ctx, a->rs1); 677 TCGv src2h = get_gprh(ctx, a->rs2); 678 TCGv desth = dest_gprh(ctx, a->rd); 679 680 f128(dest, desth, src1, src1h, src2, src2h); 681 gen_set_gpr128(ctx, a->rd, dest, desth); 682 } 683 return true; 684 } 685 686 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 687 void (*f_tl)(TCGv, TCGv, TCGv), 688 void (*f_32)(TCGv, TCGv, TCGv), 689 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 690 { 691 int olen = get_olen(ctx); 692 693 if (olen != TARGET_LONG_BITS) { 694 if (olen == 32) { 695 f_tl = f_32; 696 } else if (olen != 128) { 697 g_assert_not_reached(); 698 } 699 } 700 return gen_arith(ctx, a, ext, f_tl, f_128); 701 } 702 703 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 704 void (*func)(TCGv, TCGv, target_long), 705 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 706 { 707 TCGv dest, src1; 708 int max_len = get_olen(ctx); 709 710 if (a->shamt >= max_len) { 711 return false; 712 } 713 714 dest = dest_gpr(ctx, a->rd); 715 src1 = get_gpr(ctx, a->rs1, ext); 716 717 if (max_len < 128) { 718 func(dest, src1, a->shamt); 719 gen_set_gpr(ctx, a->rd, dest); 720 } else { 721 TCGv src1h = get_gprh(ctx, a->rs1); 722 TCGv desth = dest_gprh(ctx, a->rd); 723 724 if (f128 == NULL) { 725 return false; 726 } 727 f128(dest, desth, src1, src1h, a->shamt); 728 gen_set_gpr128(ctx, a->rd, dest, desth); 729 } 730 return true; 731 } 732 733 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 734 DisasExtend ext, 735 void (*f_tl)(TCGv, TCGv, target_long), 736 void (*f_32)(TCGv, TCGv, target_long), 737 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 738 target_long)) 739 { 740 int olen = get_olen(ctx); 741 if (olen != TARGET_LONG_BITS) { 742 if (olen == 32) { 743 f_tl = f_32; 744 } else if (olen != 128) { 745 g_assert_not_reached(); 746 } 747 } 748 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 749 } 750 751 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 752 void (*func)(TCGv, TCGv, TCGv)) 753 { 754 TCGv dest, src1, src2; 755 int max_len = get_olen(ctx); 756 757 if (a->shamt >= max_len) { 758 return false; 759 } 760 761 dest = dest_gpr(ctx, a->rd); 762 src1 = get_gpr(ctx, a->rs1, ext); 763 src2 = tcg_constant_tl(a->shamt); 764 765 func(dest, src1, src2); 766 767 gen_set_gpr(ctx, a->rd, dest); 768 return true; 769 } 770 771 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 772 void (*func)(TCGv, TCGv, TCGv), 773 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 774 { 775 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 776 TCGv ext2 = tcg_temp_new(); 777 int max_len = get_olen(ctx); 778 779 tcg_gen_andi_tl(ext2, src2, max_len - 1); 780 781 TCGv dest = dest_gpr(ctx, a->rd); 782 TCGv src1 = get_gpr(ctx, a->rs1, ext); 783 784 if (max_len < 128) { 785 func(dest, src1, ext2); 786 gen_set_gpr(ctx, a->rd, dest); 787 } else { 788 TCGv src1h = get_gprh(ctx, a->rs1); 789 TCGv desth = dest_gprh(ctx, a->rd); 790 791 if (f128 == NULL) { 792 return false; 793 } 794 f128(dest, desth, src1, src1h, ext2); 795 gen_set_gpr128(ctx, a->rd, dest, desth); 796 } 797 tcg_temp_free(ext2); 798 return true; 799 } 800 801 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 802 void (*f_tl)(TCGv, TCGv, TCGv), 803 void (*f_32)(TCGv, TCGv, TCGv), 804 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 805 { 806 int olen = get_olen(ctx); 807 if (olen != TARGET_LONG_BITS) { 808 if (olen == 32) { 809 f_tl = f_32; 810 } else if (olen != 128) { 811 g_assert_not_reached(); 812 } 813 } 814 return gen_shift(ctx, a, ext, f_tl, f_128); 815 } 816 817 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 818 void (*func)(TCGv, TCGv)) 819 { 820 TCGv dest = dest_gpr(ctx, a->rd); 821 TCGv src1 = get_gpr(ctx, a->rs1, ext); 822 823 func(dest, src1); 824 825 gen_set_gpr(ctx, a->rd, dest); 826 return true; 827 } 828 829 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 830 void (*f_tl)(TCGv, TCGv), 831 void (*f_32)(TCGv, TCGv)) 832 { 833 int olen = get_olen(ctx); 834 835 if (olen != TARGET_LONG_BITS) { 836 if (olen == 32) { 837 f_tl = f_32; 838 } else { 839 g_assert_not_reached(); 840 } 841 } 842 return gen_unary(ctx, a, ext, f_tl); 843 } 844 845 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 846 { 847 DisasContext *ctx = container_of(dcbase, DisasContext, base); 848 CPUState *cpu = ctx->cs; 849 CPURISCVState *env = cpu->env_ptr; 850 851 return cpu_ldl_code(env, pc); 852 } 853 854 /* Include insn module translation function */ 855 #include "insn_trans/trans_rvi.c.inc" 856 #include "insn_trans/trans_rvm.c.inc" 857 #include "insn_trans/trans_rva.c.inc" 858 #include "insn_trans/trans_rvf.c.inc" 859 #include "insn_trans/trans_rvd.c.inc" 860 #include "insn_trans/trans_rvh.c.inc" 861 #include "insn_trans/trans_rvv.c.inc" 862 #include "insn_trans/trans_rvb.c.inc" 863 #include "insn_trans/trans_rvzfh.c.inc" 864 #include "insn_trans/trans_privileged.c.inc" 865 #include "insn_trans/trans_svinval.c.inc" 866 #include "insn_trans/trans_xventanacondops.c.inc" 867 868 /* Include the auto-generated decoder for 16 bit insn */ 869 #include "decode-insn16.c.inc" 870 /* Include decoders for factored-out extensions */ 871 #include "decode-XVentanaCondOps.c.inc" 872 873 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 874 { 875 /* 876 * A table with predicate (i.e., guard) functions and decoder functions 877 * that are tested in-order until a decoder matches onto the opcode. 878 */ 879 static const struct { 880 bool (*guard_func)(DisasContext *); 881 bool (*decode_func)(DisasContext *, uint32_t); 882 } decoders[] = { 883 { always_true_p, decode_insn32 }, 884 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 885 }; 886 887 /* Check for compressed insn */ 888 if (extract16(opcode, 0, 2) != 3) { 889 if (!has_ext(ctx, RVC)) { 890 gen_exception_illegal(ctx); 891 } else { 892 ctx->opcode = opcode; 893 ctx->pc_succ_insn = ctx->base.pc_next + 2; 894 if (decode_insn16(ctx, opcode)) { 895 return; 896 } 897 } 898 } else { 899 uint32_t opcode32 = opcode; 900 opcode32 = deposit32(opcode32, 16, 16, 901 translator_lduw(env, &ctx->base, 902 ctx->base.pc_next + 2)); 903 ctx->opcode = opcode32; 904 ctx->pc_succ_insn = ctx->base.pc_next + 4; 905 906 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 907 if (decoders[i].guard_func(ctx) && 908 decoders[i].decode_func(ctx, opcode32)) { 909 return; 910 } 911 } 912 } 913 914 gen_exception_illegal(ctx); 915 } 916 917 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 918 { 919 DisasContext *ctx = container_of(dcbase, DisasContext, base); 920 CPURISCVState *env = cs->env_ptr; 921 RISCVCPU *cpu = RISCV_CPU(cs); 922 uint32_t tb_flags = ctx->base.tb->flags; 923 924 ctx->pc_succ_insn = ctx->base.pc_first; 925 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 926 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 927 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 928 ctx->priv_ver = env->priv_ver; 929 #if !defined(CONFIG_USER_ONLY) 930 if (riscv_has_ext(env, RVH)) { 931 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 932 } else { 933 ctx->virt_enabled = false; 934 } 935 #else 936 ctx->virt_enabled = false; 937 #endif 938 ctx->misa_ext = env->misa_ext; 939 ctx->frm = -1; /* unknown rounding mode */ 940 ctx->cfg_ptr = &(cpu->cfg); 941 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 942 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 943 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 944 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 945 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 946 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 947 ctx->vstart = env->vstart; 948 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 949 ctx->misa_mxl_max = env->misa_mxl_max; 950 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 951 ctx->cs = cs; 952 ctx->ntemp = 0; 953 memset(ctx->temp, 0, sizeof(ctx->temp)); 954 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 955 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 956 ctx->zero = tcg_constant_tl(0); 957 } 958 959 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 960 { 961 } 962 963 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 964 { 965 DisasContext *ctx = container_of(dcbase, DisasContext, base); 966 967 tcg_gen_insn_start(ctx->base.pc_next); 968 } 969 970 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 971 { 972 DisasContext *ctx = container_of(dcbase, DisasContext, base); 973 CPURISCVState *env = cpu->env_ptr; 974 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 975 976 ctx->ol = ctx->xl; 977 decode_opc(env, ctx, opcode16); 978 ctx->base.pc_next = ctx->pc_succ_insn; 979 980 for (int i = ctx->ntemp - 1; i >= 0; --i) { 981 tcg_temp_free(ctx->temp[i]); 982 ctx->temp[i] = NULL; 983 } 984 ctx->ntemp = 0; 985 986 if (ctx->base.is_jmp == DISAS_NEXT) { 987 target_ulong page_start; 988 989 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 990 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 991 ctx->base.is_jmp = DISAS_TOO_MANY; 992 } 993 } 994 } 995 996 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 997 { 998 DisasContext *ctx = container_of(dcbase, DisasContext, base); 999 1000 switch (ctx->base.is_jmp) { 1001 case DISAS_TOO_MANY: 1002 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1003 break; 1004 case DISAS_NORETURN: 1005 break; 1006 default: 1007 g_assert_not_reached(); 1008 } 1009 } 1010 1011 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 1012 { 1013 #ifndef CONFIG_USER_ONLY 1014 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1015 CPURISCVState *env = &rvcpu->env; 1016 #endif 1017 1018 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 1019 #ifndef CONFIG_USER_ONLY 1020 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 1021 #endif 1022 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 1023 } 1024 1025 static const TranslatorOps riscv_tr_ops = { 1026 .init_disas_context = riscv_tr_init_disas_context, 1027 .tb_start = riscv_tr_tb_start, 1028 .insn_start = riscv_tr_insn_start, 1029 .translate_insn = riscv_tr_translate_insn, 1030 .tb_stop = riscv_tr_tb_stop, 1031 .disas_log = riscv_tr_disas_log, 1032 }; 1033 1034 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 1035 { 1036 DisasContext ctx; 1037 1038 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 1039 } 1040 1041 void riscv_translate_init(void) 1042 { 1043 int i; 1044 1045 /* 1046 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1047 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1048 * unless you specifically block reads/writes to reg 0. 1049 */ 1050 cpu_gpr[0] = NULL; 1051 cpu_gprh[0] = NULL; 1052 1053 for (i = 1; i < 32; i++) { 1054 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1055 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1056 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1057 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1058 } 1059 1060 for (i = 0; i < 32; i++) { 1061 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1062 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1063 } 1064 1065 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1066 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1067 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1068 "vstart"); 1069 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1070 "load_res"); 1071 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1072 "load_val"); 1073 /* Assign PM CSRs to tcg globals */ 1074 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1075 "pmmask"); 1076 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1077 "pmbase"); 1078 } 1079