1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 #define HELPER_H "helper.h" 37 #include "exec/helper-info.c.inc" 38 #undef HELPER_H 39 40 /* global register indices */ 41 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 42 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 43 static TCGv load_res; 44 static TCGv load_val; 45 /* globals for PM CSRs */ 46 static TCGv pm_mask; 47 static TCGv pm_base; 48 49 #include "exec/gen-icount.h" 50 51 /* 52 * If an operation is being performed on less than TARGET_LONG_BITS, 53 * it may require the inputs to be sign- or zero-extended; which will 54 * depend on the exact operation being performed. 55 */ 56 typedef enum { 57 EXT_NONE, 58 EXT_SIGN, 59 EXT_ZERO, 60 } DisasExtend; 61 62 typedef struct DisasContext { 63 DisasContextBase base; 64 /* pc_succ_insn points to the instruction following base.pc_next */ 65 target_ulong pc_succ_insn; 66 target_ulong priv_ver; 67 RISCVMXL misa_mxl_max; 68 RISCVMXL xl; 69 uint32_t misa_ext; 70 uint32_t opcode; 71 RISCVExtStatus mstatus_fs; 72 RISCVExtStatus mstatus_vs; 73 uint32_t mem_idx; 74 uint32_t priv; 75 /* 76 * Remember the rounding mode encoded in the previous fp instruction, 77 * which we have already installed into env->fp_status. Or -1 for 78 * no previous fp instruction. Note that we exit the TB when writing 79 * to any system register, which includes CSR_FRM, so we do not have 80 * to reset this known value. 81 */ 82 int frm; 83 RISCVMXL ol; 84 bool virt_inst_excp; 85 bool virt_enabled; 86 const RISCVCPUConfig *cfg_ptr; 87 /* vector extension */ 88 bool vill; 89 /* 90 * Encode LMUL to lmul as follows: 91 * LMUL vlmul lmul 92 * 1 000 0 93 * 2 001 1 94 * 4 010 2 95 * 8 011 3 96 * - 100 - 97 * 1/8 101 -3 98 * 1/4 110 -2 99 * 1/2 111 -1 100 */ 101 int8_t lmul; 102 uint8_t sew; 103 uint8_t vta; 104 uint8_t vma; 105 bool cfg_vta_all_1s; 106 bool vstart_eq_zero; 107 bool vl_eq_vlmax; 108 CPUState *cs; 109 TCGv zero; 110 /* PointerMasking extension */ 111 bool pm_mask_enabled; 112 bool pm_base_enabled; 113 /* Use icount trigger for native debug */ 114 bool itrigger; 115 /* FRM is known to contain a valid value. */ 116 bool frm_valid; 117 /* TCG of the current insn_start */ 118 TCGOp *insn_start; 119 } DisasContext; 120 121 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 122 { 123 return ctx->misa_ext & ext; 124 } 125 126 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 127 { 128 return true; 129 } 130 131 static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) 132 { 133 return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || 134 ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || 135 ctx->cfg_ptr->ext_xtheadcondmov || 136 ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || 137 ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || 138 ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; 139 } 140 141 #define MATERIALISE_EXT_PREDICATE(ext) \ 142 static bool has_ ## ext ## _p(DisasContext *ctx) \ 143 { \ 144 return ctx->cfg_ptr->ext_ ## ext ; \ 145 } 146 147 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 148 149 #ifdef TARGET_RISCV32 150 #define get_xl(ctx) MXL_RV32 151 #elif defined(CONFIG_USER_ONLY) 152 #define get_xl(ctx) MXL_RV64 153 #else 154 #define get_xl(ctx) ((ctx)->xl) 155 #endif 156 157 /* The word size for this machine mode. */ 158 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 159 { 160 return 16 << get_xl(ctx); 161 } 162 163 /* The operation length, as opposed to the xlen. */ 164 #ifdef TARGET_RISCV32 165 #define get_ol(ctx) MXL_RV32 166 #else 167 #define get_ol(ctx) ((ctx)->ol) 168 #endif 169 170 static inline int get_olen(DisasContext *ctx) 171 { 172 return 16 << get_ol(ctx); 173 } 174 175 /* The maximum register length */ 176 #ifdef TARGET_RISCV32 177 #define get_xl_max(ctx) MXL_RV32 178 #else 179 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 180 #endif 181 182 /* 183 * RISC-V requires NaN-boxing of narrower width floating point values. 184 * This applies when a 32-bit value is assigned to a 64-bit FP register. 185 * For consistency and simplicity, we nanbox results even when the RVD 186 * extension is not present. 187 */ 188 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 189 { 190 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 191 } 192 193 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 194 { 195 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 196 } 197 198 /* 199 * A narrow n-bit operation, where n < FLEN, checks that input operands 200 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 201 * If so, the least-significant bits of the input are used, otherwise the 202 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 203 * 204 * Here, the result is always nan-boxed, even the canonical nan. 205 */ 206 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 207 { 208 TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull); 209 TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull); 210 211 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 212 } 213 214 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 215 { 216 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 217 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 218 219 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 220 } 221 222 static void decode_save_opc(DisasContext *ctx) 223 { 224 assert(ctx->insn_start != NULL); 225 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 226 ctx->insn_start = NULL; 227 } 228 229 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 230 { 231 if (get_xl(ctx) == MXL_RV32) { 232 dest = (int32_t)dest; 233 } 234 tcg_gen_movi_tl(cpu_pc, dest); 235 } 236 237 static void gen_set_pc(DisasContext *ctx, TCGv dest) 238 { 239 if (get_xl(ctx) == MXL_RV32) { 240 tcg_gen_ext32s_tl(cpu_pc, dest); 241 } else { 242 tcg_gen_mov_tl(cpu_pc, dest); 243 } 244 } 245 246 static void generate_exception(DisasContext *ctx, int excp) 247 { 248 gen_set_pc_imm(ctx, ctx->base.pc_next); 249 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 250 ctx->base.is_jmp = DISAS_NORETURN; 251 } 252 253 static void gen_exception_illegal(DisasContext *ctx) 254 { 255 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 256 offsetof(CPURISCVState, bins)); 257 if (ctx->virt_inst_excp) { 258 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 259 } else { 260 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 261 } 262 } 263 264 static void gen_exception_inst_addr_mis(DisasContext *ctx) 265 { 266 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 267 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 268 } 269 270 static void lookup_and_goto_ptr(DisasContext *ctx) 271 { 272 #ifndef CONFIG_USER_ONLY 273 if (ctx->itrigger) { 274 gen_helper_itrigger_match(cpu_env); 275 } 276 #endif 277 tcg_gen_lookup_and_goto_ptr(); 278 } 279 280 static void exit_tb(DisasContext *ctx) 281 { 282 #ifndef CONFIG_USER_ONLY 283 if (ctx->itrigger) { 284 gen_helper_itrigger_match(cpu_env); 285 } 286 #endif 287 tcg_gen_exit_tb(NULL, 0); 288 } 289 290 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 291 { 292 /* 293 * Under itrigger, instruction executes one by one like singlestep, 294 * direct block chain benefits will be small. 295 */ 296 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 297 tcg_gen_goto_tb(n); 298 gen_set_pc_imm(ctx, dest); 299 tcg_gen_exit_tb(ctx->base.tb, n); 300 } else { 301 gen_set_pc_imm(ctx, dest); 302 lookup_and_goto_ptr(ctx); 303 } 304 } 305 306 /* 307 * Wrappers for getting reg values. 308 * 309 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 310 * constant zero as a source, and an uninitialized sink as destination. 311 * 312 * Further, we may provide an extension for word operations. 313 */ 314 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 315 { 316 TCGv t; 317 318 if (reg_num == 0) { 319 return ctx->zero; 320 } 321 322 switch (get_ol(ctx)) { 323 case MXL_RV32: 324 switch (ext) { 325 case EXT_NONE: 326 break; 327 case EXT_SIGN: 328 t = tcg_temp_new(); 329 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 330 return t; 331 case EXT_ZERO: 332 t = tcg_temp_new(); 333 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 334 return t; 335 default: 336 g_assert_not_reached(); 337 } 338 break; 339 case MXL_RV64: 340 case MXL_RV128: 341 break; 342 default: 343 g_assert_not_reached(); 344 } 345 return cpu_gpr[reg_num]; 346 } 347 348 static TCGv get_gprh(DisasContext *ctx, int reg_num) 349 { 350 assert(get_xl(ctx) == MXL_RV128); 351 if (reg_num == 0) { 352 return ctx->zero; 353 } 354 return cpu_gprh[reg_num]; 355 } 356 357 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 358 { 359 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 360 return tcg_temp_new(); 361 } 362 return cpu_gpr[reg_num]; 363 } 364 365 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 366 { 367 if (reg_num == 0) { 368 return tcg_temp_new(); 369 } 370 return cpu_gprh[reg_num]; 371 } 372 373 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 374 { 375 if (reg_num != 0) { 376 switch (get_ol(ctx)) { 377 case MXL_RV32: 378 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 379 break; 380 case MXL_RV64: 381 case MXL_RV128: 382 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 383 break; 384 default: 385 g_assert_not_reached(); 386 } 387 388 if (get_xl_max(ctx) == MXL_RV128) { 389 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 390 } 391 } 392 } 393 394 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 395 { 396 if (reg_num != 0) { 397 switch (get_ol(ctx)) { 398 case MXL_RV32: 399 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 400 break; 401 case MXL_RV64: 402 case MXL_RV128: 403 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 404 break; 405 default: 406 g_assert_not_reached(); 407 } 408 409 if (get_xl_max(ctx) == MXL_RV128) { 410 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 411 } 412 } 413 } 414 415 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 416 { 417 assert(get_ol(ctx) == MXL_RV128); 418 if (reg_num != 0) { 419 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 420 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 421 } 422 } 423 424 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 425 { 426 if (!ctx->cfg_ptr->ext_zfinx) { 427 return cpu_fpr[reg_num]; 428 } 429 430 if (reg_num == 0) { 431 return tcg_constant_i64(0); 432 } 433 switch (get_xl(ctx)) { 434 case MXL_RV32: 435 #ifdef TARGET_RISCV32 436 { 437 TCGv_i64 t = tcg_temp_new_i64(); 438 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 439 return t; 440 } 441 #else 442 /* fall through */ 443 case MXL_RV64: 444 return cpu_gpr[reg_num]; 445 #endif 446 default: 447 g_assert_not_reached(); 448 } 449 } 450 451 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 452 { 453 if (!ctx->cfg_ptr->ext_zfinx) { 454 return cpu_fpr[reg_num]; 455 } 456 457 if (reg_num == 0) { 458 return tcg_constant_i64(0); 459 } 460 switch (get_xl(ctx)) { 461 case MXL_RV32: 462 { 463 TCGv_i64 t = tcg_temp_new_i64(); 464 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 465 return t; 466 } 467 #ifdef TARGET_RISCV64 468 case MXL_RV64: 469 return cpu_gpr[reg_num]; 470 #endif 471 default: 472 g_assert_not_reached(); 473 } 474 } 475 476 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 477 { 478 if (!ctx->cfg_ptr->ext_zfinx) { 479 return cpu_fpr[reg_num]; 480 } 481 482 if (reg_num == 0) { 483 return tcg_temp_new_i64(); 484 } 485 486 switch (get_xl(ctx)) { 487 case MXL_RV32: 488 return tcg_temp_new_i64(); 489 #ifdef TARGET_RISCV64 490 case MXL_RV64: 491 return cpu_gpr[reg_num]; 492 #endif 493 default: 494 g_assert_not_reached(); 495 } 496 } 497 498 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ 499 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 500 { 501 if (!ctx->cfg_ptr->ext_zfinx) { 502 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 503 return; 504 } 505 if (reg_num != 0) { 506 switch (get_xl(ctx)) { 507 case MXL_RV32: 508 #ifdef TARGET_RISCV32 509 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 510 break; 511 #else 512 /* fall through */ 513 case MXL_RV64: 514 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 515 break; 516 #endif 517 default: 518 g_assert_not_reached(); 519 } 520 } 521 } 522 523 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 524 { 525 if (!ctx->cfg_ptr->ext_zfinx) { 526 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 527 return; 528 } 529 530 if (reg_num != 0) { 531 switch (get_xl(ctx)) { 532 case MXL_RV32: 533 #ifdef TARGET_RISCV32 534 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 535 break; 536 #else 537 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 538 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 539 break; 540 case MXL_RV64: 541 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 542 break; 543 #endif 544 default: 545 g_assert_not_reached(); 546 } 547 } 548 } 549 550 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 551 { 552 target_ulong next_pc; 553 554 /* check misaligned: */ 555 next_pc = ctx->base.pc_next + imm; 556 if (!ctx->cfg_ptr->ext_zca) { 557 if ((next_pc & 0x3) != 0) { 558 gen_exception_inst_addr_mis(ctx); 559 return; 560 } 561 } 562 563 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 564 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 565 ctx->base.is_jmp = DISAS_NORETURN; 566 } 567 568 /* Compute a canonical address from a register plus offset. */ 569 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 570 { 571 TCGv addr = tcg_temp_new(); 572 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 573 574 tcg_gen_addi_tl(addr, src1, imm); 575 if (ctx->pm_mask_enabled) { 576 tcg_gen_andc_tl(addr, addr, pm_mask); 577 } else if (get_xl(ctx) == MXL_RV32) { 578 tcg_gen_ext32u_tl(addr, addr); 579 } 580 if (ctx->pm_base_enabled) { 581 tcg_gen_or_tl(addr, addr, pm_base); 582 } 583 return addr; 584 } 585 586 /* Compute a canonical address from a register plus reg offset. */ 587 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 588 { 589 TCGv addr = tcg_temp_new(); 590 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 591 592 tcg_gen_add_tl(addr, src1, offs); 593 if (ctx->pm_mask_enabled) { 594 tcg_gen_andc_tl(addr, addr, pm_mask); 595 } else if (get_xl(ctx) == MXL_RV32) { 596 tcg_gen_ext32u_tl(addr, addr); 597 } 598 if (ctx->pm_base_enabled) { 599 tcg_gen_or_tl(addr, addr, pm_base); 600 } 601 return addr; 602 } 603 604 #ifndef CONFIG_USER_ONLY 605 /* 606 * We will have already diagnosed disabled state, 607 * and need to turn initial/clean into dirty. 608 */ 609 static void mark_fs_dirty(DisasContext *ctx) 610 { 611 TCGv tmp; 612 613 if (!has_ext(ctx, RVF)) { 614 return; 615 } 616 617 if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { 618 /* Remember the state change for the rest of the TB. */ 619 ctx->mstatus_fs = EXT_STATUS_DIRTY; 620 621 tmp = tcg_temp_new(); 622 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 623 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 624 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 625 626 if (ctx->virt_enabled) { 627 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 628 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 629 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 630 } 631 } 632 } 633 #else 634 static inline void mark_fs_dirty(DisasContext *ctx) { } 635 #endif 636 637 #ifndef CONFIG_USER_ONLY 638 /* 639 * We will have already diagnosed disabled state, 640 * and need to turn initial/clean into dirty. 641 */ 642 static void mark_vs_dirty(DisasContext *ctx) 643 { 644 TCGv tmp; 645 646 if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { 647 /* Remember the state change for the rest of the TB. */ 648 ctx->mstatus_vs = EXT_STATUS_DIRTY; 649 650 tmp = tcg_temp_new(); 651 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 652 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 653 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 654 655 if (ctx->virt_enabled) { 656 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 657 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 658 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 659 } 660 } 661 } 662 #else 663 static inline void mark_vs_dirty(DisasContext *ctx) { } 664 #endif 665 666 static void gen_set_rm(DisasContext *ctx, int rm) 667 { 668 if (ctx->frm == rm) { 669 return; 670 } 671 ctx->frm = rm; 672 673 if (rm == RISCV_FRM_DYN) { 674 /* The helper will return only if frm valid. */ 675 ctx->frm_valid = true; 676 } 677 678 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 679 decode_save_opc(ctx); 680 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 681 } 682 683 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 684 { 685 if (ctx->frm == rm && ctx->frm_valid) { 686 return; 687 } 688 ctx->frm = rm; 689 ctx->frm_valid = true; 690 691 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 692 decode_save_opc(ctx); 693 gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); 694 } 695 696 static int ex_plus_1(DisasContext *ctx, int nf) 697 { 698 return nf + 1; 699 } 700 701 #define EX_SH(amount) \ 702 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 703 { \ 704 return imm << amount; \ 705 } 706 EX_SH(1) 707 EX_SH(2) 708 EX_SH(3) 709 EX_SH(4) 710 EX_SH(12) 711 712 #define REQUIRE_EXT(ctx, ext) do { \ 713 if (!has_ext(ctx, ext)) { \ 714 return false; \ 715 } \ 716 } while (0) 717 718 #define REQUIRE_32BIT(ctx) do { \ 719 if (get_xl(ctx) != MXL_RV32) { \ 720 return false; \ 721 } \ 722 } while (0) 723 724 #define REQUIRE_64BIT(ctx) do { \ 725 if (get_xl(ctx) != MXL_RV64) { \ 726 return false; \ 727 } \ 728 } while (0) 729 730 #define REQUIRE_128BIT(ctx) do { \ 731 if (get_xl(ctx) != MXL_RV128) { \ 732 return false; \ 733 } \ 734 } while (0) 735 736 #define REQUIRE_64_OR_128BIT(ctx) do { \ 737 if (get_xl(ctx) == MXL_RV32) { \ 738 return false; \ 739 } \ 740 } while (0) 741 742 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 743 if (!ctx->cfg_ptr->ext_##A && \ 744 !ctx->cfg_ptr->ext_##B) { \ 745 return false; \ 746 } \ 747 } while (0) 748 749 static int ex_rvc_register(DisasContext *ctx, int reg) 750 { 751 return 8 + reg; 752 } 753 754 static int ex_sreg_register(DisasContext *ctx, int reg) 755 { 756 return reg < 2 ? reg + 8 : reg + 16; 757 } 758 759 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 760 { 761 /* For RV128 a shamt of 0 means a shift by 64. */ 762 if (get_ol(ctx) == MXL_RV128) { 763 imm = imm ? imm : 64; 764 } 765 return imm; 766 } 767 768 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 769 { 770 /* 771 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 772 * shifts, the shamt is sign-extended. 773 */ 774 if (get_ol(ctx) == MXL_RV128) { 775 imm = imm | (imm & 32) << 1; 776 imm = imm ? imm : 64; 777 } 778 return imm; 779 } 780 781 /* Include the auto-generated decoder for 32 bit insn */ 782 #include "decode-insn32.c.inc" 783 784 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 785 void (*func)(TCGv, TCGv, target_long)) 786 { 787 TCGv dest = dest_gpr(ctx, a->rd); 788 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 789 790 func(dest, src1, a->imm); 791 792 if (get_xl(ctx) == MXL_RV128) { 793 TCGv src1h = get_gprh(ctx, a->rs1); 794 TCGv desth = dest_gprh(ctx, a->rd); 795 796 func(desth, src1h, -(a->imm < 0)); 797 gen_set_gpr128(ctx, a->rd, dest, desth); 798 } else { 799 gen_set_gpr(ctx, a->rd, dest); 800 } 801 802 return true; 803 } 804 805 static bool gen_logic(DisasContext *ctx, arg_r *a, 806 void (*func)(TCGv, TCGv, TCGv)) 807 { 808 TCGv dest = dest_gpr(ctx, a->rd); 809 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 810 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 811 812 func(dest, src1, src2); 813 814 if (get_xl(ctx) == MXL_RV128) { 815 TCGv src1h = get_gprh(ctx, a->rs1); 816 TCGv src2h = get_gprh(ctx, a->rs2); 817 TCGv desth = dest_gprh(ctx, a->rd); 818 819 func(desth, src1h, src2h); 820 gen_set_gpr128(ctx, a->rd, dest, desth); 821 } else { 822 gen_set_gpr(ctx, a->rd, dest); 823 } 824 825 return true; 826 } 827 828 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 829 void (*func)(TCGv, TCGv, target_long), 830 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 831 { 832 TCGv dest = dest_gpr(ctx, a->rd); 833 TCGv src1 = get_gpr(ctx, a->rs1, ext); 834 835 if (get_ol(ctx) < MXL_RV128) { 836 func(dest, src1, a->imm); 837 gen_set_gpr(ctx, a->rd, dest); 838 } else { 839 if (f128 == NULL) { 840 return false; 841 } 842 843 TCGv src1h = get_gprh(ctx, a->rs1); 844 TCGv desth = dest_gprh(ctx, a->rd); 845 846 f128(dest, desth, src1, src1h, a->imm); 847 gen_set_gpr128(ctx, a->rd, dest, desth); 848 } 849 return true; 850 } 851 852 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 853 void (*func)(TCGv, TCGv, TCGv), 854 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 855 { 856 TCGv dest = dest_gpr(ctx, a->rd); 857 TCGv src1 = get_gpr(ctx, a->rs1, ext); 858 TCGv src2 = tcg_constant_tl(a->imm); 859 860 if (get_ol(ctx) < MXL_RV128) { 861 func(dest, src1, src2); 862 gen_set_gpr(ctx, a->rd, dest); 863 } else { 864 if (f128 == NULL) { 865 return false; 866 } 867 868 TCGv src1h = get_gprh(ctx, a->rs1); 869 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 870 TCGv desth = dest_gprh(ctx, a->rd); 871 872 f128(dest, desth, src1, src1h, src2, src2h); 873 gen_set_gpr128(ctx, a->rd, dest, desth); 874 } 875 return true; 876 } 877 878 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 879 void (*func)(TCGv, TCGv, TCGv), 880 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 881 { 882 TCGv dest = dest_gpr(ctx, a->rd); 883 TCGv src1 = get_gpr(ctx, a->rs1, ext); 884 TCGv src2 = get_gpr(ctx, a->rs2, ext); 885 886 if (get_ol(ctx) < MXL_RV128) { 887 func(dest, src1, src2); 888 gen_set_gpr(ctx, a->rd, dest); 889 } else { 890 if (f128 == NULL) { 891 return false; 892 } 893 894 TCGv src1h = get_gprh(ctx, a->rs1); 895 TCGv src2h = get_gprh(ctx, a->rs2); 896 TCGv desth = dest_gprh(ctx, a->rd); 897 898 f128(dest, desth, src1, src1h, src2, src2h); 899 gen_set_gpr128(ctx, a->rd, dest, desth); 900 } 901 return true; 902 } 903 904 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 905 void (*f_tl)(TCGv, TCGv, TCGv), 906 void (*f_32)(TCGv, TCGv, TCGv), 907 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 908 { 909 int olen = get_olen(ctx); 910 911 if (olen != TARGET_LONG_BITS) { 912 if (olen == 32) { 913 f_tl = f_32; 914 } else if (olen != 128) { 915 g_assert_not_reached(); 916 } 917 } 918 return gen_arith(ctx, a, ext, f_tl, f_128); 919 } 920 921 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 922 void (*func)(TCGv, TCGv, target_long), 923 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 924 { 925 TCGv dest, src1; 926 int max_len = get_olen(ctx); 927 928 if (a->shamt >= max_len) { 929 return false; 930 } 931 932 dest = dest_gpr(ctx, a->rd); 933 src1 = get_gpr(ctx, a->rs1, ext); 934 935 if (max_len < 128) { 936 func(dest, src1, a->shamt); 937 gen_set_gpr(ctx, a->rd, dest); 938 } else { 939 TCGv src1h = get_gprh(ctx, a->rs1); 940 TCGv desth = dest_gprh(ctx, a->rd); 941 942 if (f128 == NULL) { 943 return false; 944 } 945 f128(dest, desth, src1, src1h, a->shamt); 946 gen_set_gpr128(ctx, a->rd, dest, desth); 947 } 948 return true; 949 } 950 951 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 952 DisasExtend ext, 953 void (*f_tl)(TCGv, TCGv, target_long), 954 void (*f_32)(TCGv, TCGv, target_long), 955 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 956 target_long)) 957 { 958 int olen = get_olen(ctx); 959 if (olen != TARGET_LONG_BITS) { 960 if (olen == 32) { 961 f_tl = f_32; 962 } else if (olen != 128) { 963 g_assert_not_reached(); 964 } 965 } 966 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 967 } 968 969 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 970 void (*func)(TCGv, TCGv, TCGv)) 971 { 972 TCGv dest, src1, src2; 973 int max_len = get_olen(ctx); 974 975 if (a->shamt >= max_len) { 976 return false; 977 } 978 979 dest = dest_gpr(ctx, a->rd); 980 src1 = get_gpr(ctx, a->rs1, ext); 981 src2 = tcg_constant_tl(a->shamt); 982 983 func(dest, src1, src2); 984 985 gen_set_gpr(ctx, a->rd, dest); 986 return true; 987 } 988 989 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 990 void (*func)(TCGv, TCGv, TCGv), 991 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 992 { 993 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 994 TCGv ext2 = tcg_temp_new(); 995 int max_len = get_olen(ctx); 996 997 tcg_gen_andi_tl(ext2, src2, max_len - 1); 998 999 TCGv dest = dest_gpr(ctx, a->rd); 1000 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1001 1002 if (max_len < 128) { 1003 func(dest, src1, ext2); 1004 gen_set_gpr(ctx, a->rd, dest); 1005 } else { 1006 TCGv src1h = get_gprh(ctx, a->rs1); 1007 TCGv desth = dest_gprh(ctx, a->rd); 1008 1009 if (f128 == NULL) { 1010 return false; 1011 } 1012 f128(dest, desth, src1, src1h, ext2); 1013 gen_set_gpr128(ctx, a->rd, dest, desth); 1014 } 1015 return true; 1016 } 1017 1018 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1019 void (*f_tl)(TCGv, TCGv, TCGv), 1020 void (*f_32)(TCGv, TCGv, TCGv), 1021 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1022 { 1023 int olen = get_olen(ctx); 1024 if (olen != TARGET_LONG_BITS) { 1025 if (olen == 32) { 1026 f_tl = f_32; 1027 } else if (olen != 128) { 1028 g_assert_not_reached(); 1029 } 1030 } 1031 return gen_shift(ctx, a, ext, f_tl, f_128); 1032 } 1033 1034 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1035 void (*func)(TCGv, TCGv)) 1036 { 1037 TCGv dest = dest_gpr(ctx, a->rd); 1038 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1039 1040 func(dest, src1); 1041 1042 gen_set_gpr(ctx, a->rd, dest); 1043 return true; 1044 } 1045 1046 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1047 void (*f_tl)(TCGv, TCGv), 1048 void (*f_32)(TCGv, TCGv)) 1049 { 1050 int olen = get_olen(ctx); 1051 1052 if (olen != TARGET_LONG_BITS) { 1053 if (olen == 32) { 1054 f_tl = f_32; 1055 } else { 1056 g_assert_not_reached(); 1057 } 1058 } 1059 return gen_unary(ctx, a, ext, f_tl); 1060 } 1061 1062 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1063 { 1064 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1065 CPUState *cpu = ctx->cs; 1066 CPURISCVState *env = cpu->env_ptr; 1067 1068 return cpu_ldl_code(env, pc); 1069 } 1070 1071 /* Include insn module translation function */ 1072 #include "insn_trans/trans_rvi.c.inc" 1073 #include "insn_trans/trans_rvm.c.inc" 1074 #include "insn_trans/trans_rva.c.inc" 1075 #include "insn_trans/trans_rvf.c.inc" 1076 #include "insn_trans/trans_rvd.c.inc" 1077 #include "insn_trans/trans_rvh.c.inc" 1078 #include "insn_trans/trans_rvv.c.inc" 1079 #include "insn_trans/trans_rvb.c.inc" 1080 #include "insn_trans/trans_rvzicond.c.inc" 1081 #include "insn_trans/trans_rvzawrs.c.inc" 1082 #include "insn_trans/trans_rvzicbo.c.inc" 1083 #include "insn_trans/trans_rvzfh.c.inc" 1084 #include "insn_trans/trans_rvk.c.inc" 1085 #include "insn_trans/trans_privileged.c.inc" 1086 #include "insn_trans/trans_svinval.c.inc" 1087 #include "decode-xthead.c.inc" 1088 #include "insn_trans/trans_xthead.c.inc" 1089 #include "insn_trans/trans_xventanacondops.c.inc" 1090 1091 /* Include the auto-generated decoder for 16 bit insn */ 1092 #include "decode-insn16.c.inc" 1093 #include "insn_trans/trans_rvzce.c.inc" 1094 1095 /* Include decoders for factored-out extensions */ 1096 #include "decode-XVentanaCondOps.c.inc" 1097 1098 /* The specification allows for longer insns, but not supported by qemu. */ 1099 #define MAX_INSN_LEN 4 1100 1101 static inline int insn_len(uint16_t first_word) 1102 { 1103 return (first_word & 3) == 3 ? 4 : 2; 1104 } 1105 1106 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1107 { 1108 /* 1109 * A table with predicate (i.e., guard) functions and decoder functions 1110 * that are tested in-order until a decoder matches onto the opcode. 1111 */ 1112 static const struct { 1113 bool (*guard_func)(DisasContext *); 1114 bool (*decode_func)(DisasContext *, uint32_t); 1115 } decoders[] = { 1116 { always_true_p, decode_insn32 }, 1117 { has_xthead_p, decode_xthead }, 1118 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1119 }; 1120 1121 ctx->virt_inst_excp = false; 1122 /* Check for compressed insn */ 1123 if (insn_len(opcode) == 2) { 1124 ctx->opcode = opcode; 1125 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1126 /* 1127 * The Zca extension is added as way to refer to instructions in the C 1128 * extension that do not include the floating-point loads and stores 1129 */ 1130 if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) { 1131 return; 1132 } 1133 } else { 1134 uint32_t opcode32 = opcode; 1135 opcode32 = deposit32(opcode32, 16, 16, 1136 translator_lduw(env, &ctx->base, 1137 ctx->base.pc_next + 2)); 1138 ctx->opcode = opcode32; 1139 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1140 1141 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1142 if (decoders[i].guard_func(ctx) && 1143 decoders[i].decode_func(ctx, opcode32)) { 1144 return; 1145 } 1146 } 1147 } 1148 1149 gen_exception_illegal(ctx); 1150 } 1151 1152 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1153 { 1154 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1155 CPURISCVState *env = cs->env_ptr; 1156 RISCVCPU *cpu = RISCV_CPU(cs); 1157 uint32_t tb_flags = ctx->base.tb->flags; 1158 1159 ctx->pc_succ_insn = ctx->base.pc_first; 1160 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 1161 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1162 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); 1163 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); 1164 ctx->priv_ver = env->priv_ver; 1165 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); 1166 ctx->misa_ext = env->misa_ext; 1167 ctx->frm = -1; /* unknown rounding mode */ 1168 ctx->cfg_ptr = &(cpu->cfg); 1169 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1170 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1171 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1172 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1173 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1174 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1175 ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); 1176 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1177 ctx->misa_mxl_max = env->misa_mxl_max; 1178 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1179 ctx->cs = cs; 1180 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1181 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1182 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1183 ctx->zero = tcg_constant_tl(0); 1184 ctx->virt_inst_excp = false; 1185 } 1186 1187 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1188 { 1189 } 1190 1191 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1192 { 1193 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1194 1195 tcg_gen_insn_start(ctx->base.pc_next, 0); 1196 ctx->insn_start = tcg_last_op(); 1197 } 1198 1199 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1200 { 1201 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1202 CPURISCVState *env = cpu->env_ptr; 1203 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1204 1205 ctx->ol = ctx->xl; 1206 decode_opc(env, ctx, opcode16); 1207 ctx->base.pc_next = ctx->pc_succ_insn; 1208 1209 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1210 if (ctx->base.is_jmp == DISAS_NEXT) { 1211 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1212 ctx->base.is_jmp = DISAS_TOO_MANY; 1213 } else { 1214 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1215 1216 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1217 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1218 int len = insn_len(next_insn); 1219 1220 if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { 1221 ctx->base.is_jmp = DISAS_TOO_MANY; 1222 } 1223 } 1224 } 1225 } 1226 } 1227 1228 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1229 { 1230 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1231 1232 switch (ctx->base.is_jmp) { 1233 case DISAS_TOO_MANY: 1234 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1235 break; 1236 case DISAS_NORETURN: 1237 break; 1238 default: 1239 g_assert_not_reached(); 1240 } 1241 } 1242 1243 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1244 CPUState *cpu, FILE *logfile) 1245 { 1246 #ifndef CONFIG_USER_ONLY 1247 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1248 CPURISCVState *env = &rvcpu->env; 1249 #endif 1250 1251 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1252 #ifndef CONFIG_USER_ONLY 1253 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n", 1254 env->priv, env->virt_enabled); 1255 #endif 1256 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1257 } 1258 1259 static const TranslatorOps riscv_tr_ops = { 1260 .init_disas_context = riscv_tr_init_disas_context, 1261 .tb_start = riscv_tr_tb_start, 1262 .insn_start = riscv_tr_insn_start, 1263 .translate_insn = riscv_tr_translate_insn, 1264 .tb_stop = riscv_tr_tb_stop, 1265 .disas_log = riscv_tr_disas_log, 1266 }; 1267 1268 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1269 target_ulong pc, void *host_pc) 1270 { 1271 DisasContext ctx; 1272 1273 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1274 } 1275 1276 void riscv_translate_init(void) 1277 { 1278 int i; 1279 1280 /* 1281 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1282 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1283 * unless you specifically block reads/writes to reg 0. 1284 */ 1285 cpu_gpr[0] = NULL; 1286 cpu_gprh[0] = NULL; 1287 1288 for (i = 1; i < 32; i++) { 1289 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1290 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1291 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1292 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1293 } 1294 1295 for (i = 0; i < 32; i++) { 1296 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1297 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1298 } 1299 1300 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1301 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1302 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1303 "vstart"); 1304 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1305 "load_res"); 1306 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1307 "load_val"); 1308 /* Assign PM CSRs to tcg globals */ 1309 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1310 "pmmask"); 1311 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1312 "pmbase"); 1313 } 1314