1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 #define HELPER_H "helper.h" 37 #include "exec/helper-info.c.inc" 38 #undef HELPER_H 39 40 /* global register indices */ 41 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 42 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 43 static TCGv load_res; 44 static TCGv load_val; 45 /* globals for PM CSRs */ 46 static TCGv pm_mask; 47 static TCGv pm_base; 48 49 /* 50 * If an operation is being performed on less than TARGET_LONG_BITS, 51 * it may require the inputs to be sign- or zero-extended; which will 52 * depend on the exact operation being performed. 53 */ 54 typedef enum { 55 EXT_NONE, 56 EXT_SIGN, 57 EXT_ZERO, 58 } DisasExtend; 59 60 typedef struct DisasContext { 61 DisasContextBase base; 62 target_ulong cur_insn_len; 63 target_ulong pc_save; 64 target_ulong priv_ver; 65 RISCVMXL misa_mxl_max; 66 RISCVMXL xl; 67 RISCVMXL address_xl; 68 uint32_t misa_ext; 69 uint32_t opcode; 70 RISCVExtStatus mstatus_fs; 71 RISCVExtStatus mstatus_vs; 72 uint32_t mem_idx; 73 uint32_t priv; 74 /* 75 * Remember the rounding mode encoded in the previous fp instruction, 76 * which we have already installed into env->fp_status. Or -1 for 77 * no previous fp instruction. Note that we exit the TB when writing 78 * to any system register, which includes CSR_FRM, so we do not have 79 * to reset this known value. 80 */ 81 int frm; 82 RISCVMXL ol; 83 bool virt_inst_excp; 84 bool virt_enabled; 85 const RISCVCPUConfig *cfg_ptr; 86 /* vector extension */ 87 bool vill; 88 /* 89 * Encode LMUL to lmul as follows: 90 * LMUL vlmul lmul 91 * 1 000 0 92 * 2 001 1 93 * 4 010 2 94 * 8 011 3 95 * - 100 - 96 * 1/8 101 -3 97 * 1/4 110 -2 98 * 1/2 111 -1 99 */ 100 int8_t lmul; 101 uint8_t sew; 102 uint8_t vta; 103 uint8_t vma; 104 bool cfg_vta_all_1s; 105 bool vstart_eq_zero; 106 bool vl_eq_vlmax; 107 CPUState *cs; 108 TCGv zero; 109 /* PointerMasking extension */ 110 bool pm_mask_enabled; 111 bool pm_base_enabled; 112 /* Ztso */ 113 bool ztso; 114 /* Use icount trigger for native debug */ 115 bool itrigger; 116 /* FRM is known to contain a valid value. */ 117 bool frm_valid; 118 /* TCG of the current insn_start */ 119 TCGOp *insn_start; 120 } DisasContext; 121 122 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 123 { 124 return ctx->misa_ext & ext; 125 } 126 127 #ifdef TARGET_RISCV32 128 #define get_xl(ctx) MXL_RV32 129 #elif defined(CONFIG_USER_ONLY) 130 #define get_xl(ctx) MXL_RV64 131 #else 132 #define get_xl(ctx) ((ctx)->xl) 133 #endif 134 135 #ifdef TARGET_RISCV32 136 #define get_address_xl(ctx) MXL_RV32 137 #elif defined(CONFIG_USER_ONLY) 138 #define get_address_xl(ctx) MXL_RV64 139 #else 140 #define get_address_xl(ctx) ((ctx)->address_xl) 141 #endif 142 143 /* The word size for this machine mode. */ 144 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 145 { 146 return 16 << get_xl(ctx); 147 } 148 149 /* The operation length, as opposed to the xlen. */ 150 #ifdef TARGET_RISCV32 151 #define get_ol(ctx) MXL_RV32 152 #else 153 #define get_ol(ctx) ((ctx)->ol) 154 #endif 155 156 static inline int get_olen(DisasContext *ctx) 157 { 158 return 16 << get_ol(ctx); 159 } 160 161 /* The maximum register length */ 162 #ifdef TARGET_RISCV32 163 #define get_xl_max(ctx) MXL_RV32 164 #else 165 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 166 #endif 167 168 /* 169 * RISC-V requires NaN-boxing of narrower width floating point values. 170 * This applies when a 32-bit value is assigned to a 64-bit FP register. 171 * For consistency and simplicity, we nanbox results even when the RVD 172 * extension is not present. 173 */ 174 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 175 { 176 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 177 } 178 179 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 180 { 181 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 182 } 183 184 /* 185 * A narrow n-bit operation, where n < FLEN, checks that input operands 186 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 187 * If so, the least-significant bits of the input are used, otherwise the 188 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 189 * 190 * Here, the result is always nan-boxed, even the canonical nan. 191 */ 192 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 193 { 194 TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull); 195 TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull); 196 197 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 198 } 199 200 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 201 { 202 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 203 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 204 205 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 206 } 207 208 static void decode_save_opc(DisasContext *ctx) 209 { 210 assert(ctx->insn_start != NULL); 211 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 212 ctx->insn_start = NULL; 213 } 214 215 static void gen_pc_plus_diff(TCGv target, DisasContext *ctx, 216 target_long diff) 217 { 218 target_ulong dest = ctx->base.pc_next + diff; 219 220 assert(ctx->pc_save != -1); 221 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 222 tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save); 223 if (get_xl(ctx) == MXL_RV32) { 224 tcg_gen_ext32s_tl(target, target); 225 } 226 } else { 227 if (get_xl(ctx) == MXL_RV32) { 228 dest = (int32_t)dest; 229 } 230 tcg_gen_movi_tl(target, dest); 231 } 232 } 233 234 static void gen_update_pc(DisasContext *ctx, target_long diff) 235 { 236 gen_pc_plus_diff(cpu_pc, ctx, diff); 237 ctx->pc_save = ctx->base.pc_next + diff; 238 } 239 240 static void generate_exception(DisasContext *ctx, int excp) 241 { 242 gen_update_pc(ctx, 0); 243 gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); 244 ctx->base.is_jmp = DISAS_NORETURN; 245 } 246 247 static void gen_exception_illegal(DisasContext *ctx) 248 { 249 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), tcg_env, 250 offsetof(CPURISCVState, bins)); 251 if (ctx->virt_inst_excp) { 252 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 253 } else { 254 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 255 } 256 } 257 258 static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target) 259 { 260 tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr)); 261 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 262 } 263 264 static void lookup_and_goto_ptr(DisasContext *ctx) 265 { 266 #ifndef CONFIG_USER_ONLY 267 if (ctx->itrigger) { 268 gen_helper_itrigger_match(tcg_env); 269 } 270 #endif 271 tcg_gen_lookup_and_goto_ptr(); 272 } 273 274 static void exit_tb(DisasContext *ctx) 275 { 276 #ifndef CONFIG_USER_ONLY 277 if (ctx->itrigger) { 278 gen_helper_itrigger_match(tcg_env); 279 } 280 #endif 281 tcg_gen_exit_tb(NULL, 0); 282 } 283 284 static void gen_goto_tb(DisasContext *ctx, int n, target_long diff) 285 { 286 target_ulong dest = ctx->base.pc_next + diff; 287 288 /* 289 * Under itrigger, instruction executes one by one like singlestep, 290 * direct block chain benefits will be small. 291 */ 292 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 293 /* 294 * For pcrel, the pc must always be up-to-date on entry to 295 * the linked TB, so that it can use simple additions for all 296 * further adjustments. For !pcrel, the linked TB is compiled 297 * to know its full virtual address, so we can delay the 298 * update to pc to the unlinked path. A long chain of links 299 * can thus avoid many updates to the PC. 300 */ 301 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 302 gen_update_pc(ctx, diff); 303 tcg_gen_goto_tb(n); 304 } else { 305 tcg_gen_goto_tb(n); 306 gen_update_pc(ctx, diff); 307 } 308 tcg_gen_exit_tb(ctx->base.tb, n); 309 } else { 310 gen_update_pc(ctx, diff); 311 lookup_and_goto_ptr(ctx); 312 } 313 } 314 315 /* 316 * Wrappers for getting reg values. 317 * 318 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 319 * constant zero as a source, and an uninitialized sink as destination. 320 * 321 * Further, we may provide an extension for word operations. 322 */ 323 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 324 { 325 TCGv t; 326 327 if (reg_num == 0) { 328 return ctx->zero; 329 } 330 331 switch (get_ol(ctx)) { 332 case MXL_RV32: 333 switch (ext) { 334 case EXT_NONE: 335 break; 336 case EXT_SIGN: 337 t = tcg_temp_new(); 338 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 339 return t; 340 case EXT_ZERO: 341 t = tcg_temp_new(); 342 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 343 return t; 344 default: 345 g_assert_not_reached(); 346 } 347 break; 348 case MXL_RV64: 349 case MXL_RV128: 350 break; 351 default: 352 g_assert_not_reached(); 353 } 354 return cpu_gpr[reg_num]; 355 } 356 357 static TCGv get_gprh(DisasContext *ctx, int reg_num) 358 { 359 assert(get_xl(ctx) == MXL_RV128); 360 if (reg_num == 0) { 361 return ctx->zero; 362 } 363 return cpu_gprh[reg_num]; 364 } 365 366 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 367 { 368 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 369 return tcg_temp_new(); 370 } 371 return cpu_gpr[reg_num]; 372 } 373 374 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 375 { 376 if (reg_num == 0) { 377 return tcg_temp_new(); 378 } 379 return cpu_gprh[reg_num]; 380 } 381 382 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 383 { 384 if (reg_num != 0) { 385 switch (get_ol(ctx)) { 386 case MXL_RV32: 387 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 388 break; 389 case MXL_RV64: 390 case MXL_RV128: 391 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 392 break; 393 default: 394 g_assert_not_reached(); 395 } 396 397 if (get_xl_max(ctx) == MXL_RV128) { 398 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 399 } 400 } 401 } 402 403 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 404 { 405 if (reg_num != 0) { 406 switch (get_ol(ctx)) { 407 case MXL_RV32: 408 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 409 break; 410 case MXL_RV64: 411 case MXL_RV128: 412 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 413 break; 414 default: 415 g_assert_not_reached(); 416 } 417 418 if (get_xl_max(ctx) == MXL_RV128) { 419 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 420 } 421 } 422 } 423 424 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 425 { 426 assert(get_ol(ctx) == MXL_RV128); 427 if (reg_num != 0) { 428 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 429 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 430 } 431 } 432 433 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 434 { 435 if (!ctx->cfg_ptr->ext_zfinx) { 436 return cpu_fpr[reg_num]; 437 } 438 439 if (reg_num == 0) { 440 return tcg_constant_i64(0); 441 } 442 switch (get_xl(ctx)) { 443 case MXL_RV32: 444 #ifdef TARGET_RISCV32 445 { 446 TCGv_i64 t = tcg_temp_new_i64(); 447 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 448 return t; 449 } 450 #else 451 /* fall through */ 452 case MXL_RV64: 453 return cpu_gpr[reg_num]; 454 #endif 455 default: 456 g_assert_not_reached(); 457 } 458 } 459 460 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 461 { 462 if (!ctx->cfg_ptr->ext_zfinx) { 463 return cpu_fpr[reg_num]; 464 } 465 466 if (reg_num == 0) { 467 return tcg_constant_i64(0); 468 } 469 switch (get_xl(ctx)) { 470 case MXL_RV32: 471 { 472 TCGv_i64 t = tcg_temp_new_i64(); 473 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 474 return t; 475 } 476 #ifdef TARGET_RISCV64 477 case MXL_RV64: 478 return cpu_gpr[reg_num]; 479 #endif 480 default: 481 g_assert_not_reached(); 482 } 483 } 484 485 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 486 { 487 if (!ctx->cfg_ptr->ext_zfinx) { 488 return cpu_fpr[reg_num]; 489 } 490 491 if (reg_num == 0) { 492 return tcg_temp_new_i64(); 493 } 494 495 switch (get_xl(ctx)) { 496 case MXL_RV32: 497 return tcg_temp_new_i64(); 498 #ifdef TARGET_RISCV64 499 case MXL_RV64: 500 return cpu_gpr[reg_num]; 501 #endif 502 default: 503 g_assert_not_reached(); 504 } 505 } 506 507 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ 508 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 509 { 510 if (!ctx->cfg_ptr->ext_zfinx) { 511 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 512 return; 513 } 514 if (reg_num != 0) { 515 switch (get_xl(ctx)) { 516 case MXL_RV32: 517 #ifdef TARGET_RISCV32 518 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 519 break; 520 #else 521 /* fall through */ 522 case MXL_RV64: 523 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 524 break; 525 #endif 526 default: 527 g_assert_not_reached(); 528 } 529 } 530 } 531 532 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 533 { 534 if (!ctx->cfg_ptr->ext_zfinx) { 535 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 536 return; 537 } 538 539 if (reg_num != 0) { 540 switch (get_xl(ctx)) { 541 case MXL_RV32: 542 #ifdef TARGET_RISCV32 543 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 544 break; 545 #else 546 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 547 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 548 break; 549 case MXL_RV64: 550 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 551 break; 552 #endif 553 default: 554 g_assert_not_reached(); 555 } 556 } 557 } 558 559 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 560 { 561 TCGv succ_pc = dest_gpr(ctx, rd); 562 563 /* check misaligned: */ 564 if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { 565 if ((imm & 0x3) != 0) { 566 TCGv target_pc = tcg_temp_new(); 567 gen_pc_plus_diff(target_pc, ctx, imm); 568 gen_exception_inst_addr_mis(ctx, target_pc); 569 return; 570 } 571 } 572 573 gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len); 574 gen_set_gpr(ctx, rd, succ_pc); 575 576 gen_goto_tb(ctx, 0, imm); /* must use this for safety */ 577 ctx->base.is_jmp = DISAS_NORETURN; 578 } 579 580 /* Compute a canonical address from a register plus offset. */ 581 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 582 { 583 TCGv addr = tcg_temp_new(); 584 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 585 586 tcg_gen_addi_tl(addr, src1, imm); 587 if (ctx->pm_mask_enabled) { 588 tcg_gen_andc_tl(addr, addr, pm_mask); 589 } else if (get_address_xl(ctx) == MXL_RV32) { 590 tcg_gen_ext32u_tl(addr, addr); 591 } 592 if (ctx->pm_base_enabled) { 593 tcg_gen_or_tl(addr, addr, pm_base); 594 } 595 596 return addr; 597 } 598 599 /* Compute a canonical address from a register plus reg offset. */ 600 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 601 { 602 TCGv addr = tcg_temp_new(); 603 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 604 605 tcg_gen_add_tl(addr, src1, offs); 606 if (ctx->pm_mask_enabled) { 607 tcg_gen_andc_tl(addr, addr, pm_mask); 608 } else if (get_xl(ctx) == MXL_RV32) { 609 tcg_gen_ext32u_tl(addr, addr); 610 } 611 if (ctx->pm_base_enabled) { 612 tcg_gen_or_tl(addr, addr, pm_base); 613 } 614 return addr; 615 } 616 617 #ifndef CONFIG_USER_ONLY 618 /* 619 * We will have already diagnosed disabled state, 620 * and need to turn initial/clean into dirty. 621 */ 622 static void mark_fs_dirty(DisasContext *ctx) 623 { 624 TCGv tmp; 625 626 if (!has_ext(ctx, RVF)) { 627 return; 628 } 629 630 if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { 631 /* Remember the state change for the rest of the TB. */ 632 ctx->mstatus_fs = EXT_STATUS_DIRTY; 633 634 tmp = tcg_temp_new(); 635 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 636 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 637 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 638 639 if (ctx->virt_enabled) { 640 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 641 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 642 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 643 } 644 } 645 } 646 #else 647 static inline void mark_fs_dirty(DisasContext *ctx) { } 648 #endif 649 650 #ifndef CONFIG_USER_ONLY 651 /* 652 * We will have already diagnosed disabled state, 653 * and need to turn initial/clean into dirty. 654 */ 655 static void mark_vs_dirty(DisasContext *ctx) 656 { 657 TCGv tmp; 658 659 if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { 660 /* Remember the state change for the rest of the TB. */ 661 ctx->mstatus_vs = EXT_STATUS_DIRTY; 662 663 tmp = tcg_temp_new(); 664 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 665 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 666 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 667 668 if (ctx->virt_enabled) { 669 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 670 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 671 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 672 } 673 } 674 } 675 #else 676 static inline void mark_vs_dirty(DisasContext *ctx) { } 677 #endif 678 679 static void finalize_rvv_inst(DisasContext *ctx) 680 { 681 mark_vs_dirty(ctx); 682 ctx->vstart_eq_zero = true; 683 } 684 685 static void gen_set_rm(DisasContext *ctx, int rm) 686 { 687 if (ctx->frm == rm) { 688 return; 689 } 690 ctx->frm = rm; 691 692 if (rm == RISCV_FRM_DYN) { 693 /* The helper will return only if frm valid. */ 694 ctx->frm_valid = true; 695 } 696 697 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 698 decode_save_opc(ctx); 699 gen_helper_set_rounding_mode(tcg_env, tcg_constant_i32(rm)); 700 } 701 702 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 703 { 704 if (ctx->frm == rm && ctx->frm_valid) { 705 return; 706 } 707 ctx->frm = rm; 708 ctx->frm_valid = true; 709 710 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 711 decode_save_opc(ctx); 712 gen_helper_set_rounding_mode_chkfrm(tcg_env, tcg_constant_i32(rm)); 713 } 714 715 static int ex_plus_1(DisasContext *ctx, int nf) 716 { 717 return nf + 1; 718 } 719 720 #define EX_SH(amount) \ 721 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 722 { \ 723 return imm << amount; \ 724 } 725 EX_SH(1) 726 EX_SH(2) 727 EX_SH(3) 728 EX_SH(4) 729 EX_SH(12) 730 731 #define REQUIRE_EXT(ctx, ext) do { \ 732 if (!has_ext(ctx, ext)) { \ 733 return false; \ 734 } \ 735 } while (0) 736 737 #define REQUIRE_32BIT(ctx) do { \ 738 if (get_xl(ctx) != MXL_RV32) { \ 739 return false; \ 740 } \ 741 } while (0) 742 743 #define REQUIRE_64BIT(ctx) do { \ 744 if (get_xl(ctx) != MXL_RV64) { \ 745 return false; \ 746 } \ 747 } while (0) 748 749 #define REQUIRE_128BIT(ctx) do { \ 750 if (get_xl(ctx) != MXL_RV128) { \ 751 return false; \ 752 } \ 753 } while (0) 754 755 #define REQUIRE_64_OR_128BIT(ctx) do { \ 756 if (get_xl(ctx) == MXL_RV32) { \ 757 return false; \ 758 } \ 759 } while (0) 760 761 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 762 if (!ctx->cfg_ptr->ext_##A && \ 763 !ctx->cfg_ptr->ext_##B) { \ 764 return false; \ 765 } \ 766 } while (0) 767 768 static int ex_rvc_register(DisasContext *ctx, int reg) 769 { 770 return 8 + reg; 771 } 772 773 static int ex_sreg_register(DisasContext *ctx, int reg) 774 { 775 return reg < 2 ? reg + 8 : reg + 16; 776 } 777 778 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 779 { 780 /* For RV128 a shamt of 0 means a shift by 64. */ 781 if (get_ol(ctx) == MXL_RV128) { 782 imm = imm ? imm : 64; 783 } 784 return imm; 785 } 786 787 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 788 { 789 /* 790 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 791 * shifts, the shamt is sign-extended. 792 */ 793 if (get_ol(ctx) == MXL_RV128) { 794 imm = imm | (imm & 32) << 1; 795 imm = imm ? imm : 64; 796 } 797 return imm; 798 } 799 800 /* Include the auto-generated decoder for 32 bit insn */ 801 #include "decode-insn32.c.inc" 802 803 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 804 void (*func)(TCGv, TCGv, target_long)) 805 { 806 TCGv dest = dest_gpr(ctx, a->rd); 807 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 808 809 func(dest, src1, a->imm); 810 811 if (get_xl(ctx) == MXL_RV128) { 812 TCGv src1h = get_gprh(ctx, a->rs1); 813 TCGv desth = dest_gprh(ctx, a->rd); 814 815 func(desth, src1h, -(a->imm < 0)); 816 gen_set_gpr128(ctx, a->rd, dest, desth); 817 } else { 818 gen_set_gpr(ctx, a->rd, dest); 819 } 820 821 return true; 822 } 823 824 static bool gen_logic(DisasContext *ctx, arg_r *a, 825 void (*func)(TCGv, TCGv, TCGv)) 826 { 827 TCGv dest = dest_gpr(ctx, a->rd); 828 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 829 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 830 831 func(dest, src1, src2); 832 833 if (get_xl(ctx) == MXL_RV128) { 834 TCGv src1h = get_gprh(ctx, a->rs1); 835 TCGv src2h = get_gprh(ctx, a->rs2); 836 TCGv desth = dest_gprh(ctx, a->rd); 837 838 func(desth, src1h, src2h); 839 gen_set_gpr128(ctx, a->rd, dest, desth); 840 } else { 841 gen_set_gpr(ctx, a->rd, dest); 842 } 843 844 return true; 845 } 846 847 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 848 void (*func)(TCGv, TCGv, target_long), 849 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 850 { 851 TCGv dest = dest_gpr(ctx, a->rd); 852 TCGv src1 = get_gpr(ctx, a->rs1, ext); 853 854 if (get_ol(ctx) < MXL_RV128) { 855 func(dest, src1, a->imm); 856 gen_set_gpr(ctx, a->rd, dest); 857 } else { 858 if (f128 == NULL) { 859 return false; 860 } 861 862 TCGv src1h = get_gprh(ctx, a->rs1); 863 TCGv desth = dest_gprh(ctx, a->rd); 864 865 f128(dest, desth, src1, src1h, a->imm); 866 gen_set_gpr128(ctx, a->rd, dest, desth); 867 } 868 return true; 869 } 870 871 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 872 void (*func)(TCGv, TCGv, TCGv), 873 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 874 { 875 TCGv dest = dest_gpr(ctx, a->rd); 876 TCGv src1 = get_gpr(ctx, a->rs1, ext); 877 TCGv src2 = tcg_constant_tl(a->imm); 878 879 if (get_ol(ctx) < MXL_RV128) { 880 func(dest, src1, src2); 881 gen_set_gpr(ctx, a->rd, dest); 882 } else { 883 if (f128 == NULL) { 884 return false; 885 } 886 887 TCGv src1h = get_gprh(ctx, a->rs1); 888 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 889 TCGv desth = dest_gprh(ctx, a->rd); 890 891 f128(dest, desth, src1, src1h, src2, src2h); 892 gen_set_gpr128(ctx, a->rd, dest, desth); 893 } 894 return true; 895 } 896 897 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 898 void (*func)(TCGv, TCGv, TCGv), 899 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 900 { 901 TCGv dest = dest_gpr(ctx, a->rd); 902 TCGv src1 = get_gpr(ctx, a->rs1, ext); 903 TCGv src2 = get_gpr(ctx, a->rs2, ext); 904 905 if (get_ol(ctx) < MXL_RV128) { 906 func(dest, src1, src2); 907 gen_set_gpr(ctx, a->rd, dest); 908 } else { 909 if (f128 == NULL) { 910 return false; 911 } 912 913 TCGv src1h = get_gprh(ctx, a->rs1); 914 TCGv src2h = get_gprh(ctx, a->rs2); 915 TCGv desth = dest_gprh(ctx, a->rd); 916 917 f128(dest, desth, src1, src1h, src2, src2h); 918 gen_set_gpr128(ctx, a->rd, dest, desth); 919 } 920 return true; 921 } 922 923 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 924 void (*f_tl)(TCGv, TCGv, TCGv), 925 void (*f_32)(TCGv, TCGv, TCGv), 926 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 927 { 928 int olen = get_olen(ctx); 929 930 if (olen != TARGET_LONG_BITS) { 931 if (olen == 32) { 932 f_tl = f_32; 933 } else if (olen != 128) { 934 g_assert_not_reached(); 935 } 936 } 937 return gen_arith(ctx, a, ext, f_tl, f_128); 938 } 939 940 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 941 void (*func)(TCGv, TCGv, target_long), 942 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 943 { 944 TCGv dest, src1; 945 int max_len = get_olen(ctx); 946 947 if (a->shamt >= max_len) { 948 return false; 949 } 950 951 dest = dest_gpr(ctx, a->rd); 952 src1 = get_gpr(ctx, a->rs1, ext); 953 954 if (max_len < 128) { 955 func(dest, src1, a->shamt); 956 gen_set_gpr(ctx, a->rd, dest); 957 } else { 958 TCGv src1h = get_gprh(ctx, a->rs1); 959 TCGv desth = dest_gprh(ctx, a->rd); 960 961 if (f128 == NULL) { 962 return false; 963 } 964 f128(dest, desth, src1, src1h, a->shamt); 965 gen_set_gpr128(ctx, a->rd, dest, desth); 966 } 967 return true; 968 } 969 970 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 971 DisasExtend ext, 972 void (*f_tl)(TCGv, TCGv, target_long), 973 void (*f_32)(TCGv, TCGv, target_long), 974 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 975 target_long)) 976 { 977 int olen = get_olen(ctx); 978 if (olen != TARGET_LONG_BITS) { 979 if (olen == 32) { 980 f_tl = f_32; 981 } else if (olen != 128) { 982 g_assert_not_reached(); 983 } 984 } 985 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 986 } 987 988 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 989 void (*func)(TCGv, TCGv, TCGv)) 990 { 991 TCGv dest, src1, src2; 992 int max_len = get_olen(ctx); 993 994 if (a->shamt >= max_len) { 995 return false; 996 } 997 998 dest = dest_gpr(ctx, a->rd); 999 src1 = get_gpr(ctx, a->rs1, ext); 1000 src2 = tcg_constant_tl(a->shamt); 1001 1002 func(dest, src1, src2); 1003 1004 gen_set_gpr(ctx, a->rd, dest); 1005 return true; 1006 } 1007 1008 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 1009 void (*func)(TCGv, TCGv, TCGv), 1010 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1011 { 1012 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1013 TCGv ext2 = tcg_temp_new(); 1014 int max_len = get_olen(ctx); 1015 1016 tcg_gen_andi_tl(ext2, src2, max_len - 1); 1017 1018 TCGv dest = dest_gpr(ctx, a->rd); 1019 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1020 1021 if (max_len < 128) { 1022 func(dest, src1, ext2); 1023 gen_set_gpr(ctx, a->rd, dest); 1024 } else { 1025 TCGv src1h = get_gprh(ctx, a->rs1); 1026 TCGv desth = dest_gprh(ctx, a->rd); 1027 1028 if (f128 == NULL) { 1029 return false; 1030 } 1031 f128(dest, desth, src1, src1h, ext2); 1032 gen_set_gpr128(ctx, a->rd, dest, desth); 1033 } 1034 return true; 1035 } 1036 1037 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1038 void (*f_tl)(TCGv, TCGv, TCGv), 1039 void (*f_32)(TCGv, TCGv, TCGv), 1040 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1041 { 1042 int olen = get_olen(ctx); 1043 if (olen != TARGET_LONG_BITS) { 1044 if (olen == 32) { 1045 f_tl = f_32; 1046 } else if (olen != 128) { 1047 g_assert_not_reached(); 1048 } 1049 } 1050 return gen_shift(ctx, a, ext, f_tl, f_128); 1051 } 1052 1053 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1054 void (*func)(TCGv, TCGv)) 1055 { 1056 TCGv dest = dest_gpr(ctx, a->rd); 1057 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1058 1059 func(dest, src1); 1060 1061 gen_set_gpr(ctx, a->rd, dest); 1062 return true; 1063 } 1064 1065 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1066 void (*f_tl)(TCGv, TCGv), 1067 void (*f_32)(TCGv, TCGv)) 1068 { 1069 int olen = get_olen(ctx); 1070 1071 if (olen != TARGET_LONG_BITS) { 1072 if (olen == 32) { 1073 f_tl = f_32; 1074 } else { 1075 g_assert_not_reached(); 1076 } 1077 } 1078 return gen_unary(ctx, a, ext, f_tl); 1079 } 1080 1081 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1082 { 1083 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1084 CPUState *cpu = ctx->cs; 1085 CPURISCVState *env = cpu_env(cpu); 1086 1087 return cpu_ldl_code(env, pc); 1088 } 1089 1090 /* Include insn module translation function */ 1091 #include "insn_trans/trans_rvi.c.inc" 1092 #include "insn_trans/trans_rvm.c.inc" 1093 #include "insn_trans/trans_rva.c.inc" 1094 #include "insn_trans/trans_rvf.c.inc" 1095 #include "insn_trans/trans_rvd.c.inc" 1096 #include "insn_trans/trans_rvh.c.inc" 1097 #include "insn_trans/trans_rvv.c.inc" 1098 #include "insn_trans/trans_rvb.c.inc" 1099 #include "insn_trans/trans_rvzicond.c.inc" 1100 #include "insn_trans/trans_rvzacas.c.inc" 1101 #include "insn_trans/trans_rvzawrs.c.inc" 1102 #include "insn_trans/trans_rvzicbo.c.inc" 1103 #include "insn_trans/trans_rvzfa.c.inc" 1104 #include "insn_trans/trans_rvzfh.c.inc" 1105 #include "insn_trans/trans_rvk.c.inc" 1106 #include "insn_trans/trans_rvvk.c.inc" 1107 #include "insn_trans/trans_privileged.c.inc" 1108 #include "insn_trans/trans_svinval.c.inc" 1109 #include "insn_trans/trans_rvbf16.c.inc" 1110 #include "decode-xthead.c.inc" 1111 #include "insn_trans/trans_xthead.c.inc" 1112 #include "insn_trans/trans_xventanacondops.c.inc" 1113 1114 /* Include the auto-generated decoder for 16 bit insn */ 1115 #include "decode-insn16.c.inc" 1116 #include "insn_trans/trans_rvzce.c.inc" 1117 1118 /* Include decoders for factored-out extensions */ 1119 #include "decode-XVentanaCondOps.c.inc" 1120 1121 /* The specification allows for longer insns, but not supported by qemu. */ 1122 #define MAX_INSN_LEN 4 1123 1124 static inline int insn_len(uint16_t first_word) 1125 { 1126 return (first_word & 3) == 3 ? 4 : 2; 1127 } 1128 1129 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1130 { 1131 /* 1132 * A table with predicate (i.e., guard) functions and decoder functions 1133 * that are tested in-order until a decoder matches onto the opcode. 1134 */ 1135 static const struct { 1136 bool (*guard_func)(const RISCVCPUConfig *); 1137 bool (*decode_func)(DisasContext *, uint32_t); 1138 } decoders[] = { 1139 { always_true_p, decode_insn32 }, 1140 { has_xthead_p, decode_xthead }, 1141 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1142 }; 1143 1144 ctx->virt_inst_excp = false; 1145 ctx->cur_insn_len = insn_len(opcode); 1146 /* Check for compressed insn */ 1147 if (ctx->cur_insn_len == 2) { 1148 ctx->opcode = opcode; 1149 /* 1150 * The Zca extension is added as way to refer to instructions in the C 1151 * extension that do not include the floating-point loads and stores 1152 */ 1153 if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) && 1154 decode_insn16(ctx, opcode)) { 1155 return; 1156 } 1157 } else { 1158 uint32_t opcode32 = opcode; 1159 opcode32 = deposit32(opcode32, 16, 16, 1160 translator_lduw(env, &ctx->base, 1161 ctx->base.pc_next + 2)); 1162 ctx->opcode = opcode32; 1163 1164 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1165 if (decoders[i].guard_func(ctx->cfg_ptr) && 1166 decoders[i].decode_func(ctx, opcode32)) { 1167 return; 1168 } 1169 } 1170 } 1171 1172 gen_exception_illegal(ctx); 1173 } 1174 1175 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1176 { 1177 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1178 CPURISCVState *env = cpu_env(cs); 1179 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); 1180 RISCVCPU *cpu = RISCV_CPU(cs); 1181 uint32_t tb_flags = ctx->base.tb->flags; 1182 1183 ctx->pc_save = ctx->base.pc_first; 1184 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 1185 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1186 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); 1187 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); 1188 ctx->priv_ver = env->priv_ver; 1189 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); 1190 ctx->misa_ext = env->misa_ext; 1191 ctx->frm = -1; /* unknown rounding mode */ 1192 ctx->cfg_ptr = &(cpu->cfg); 1193 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1194 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1195 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1196 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1197 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1198 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1199 ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); 1200 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1201 ctx->misa_mxl_max = mcc->misa_mxl_max; 1202 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1203 ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); 1204 ctx->cs = cs; 1205 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1206 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1207 ctx->ztso = cpu->cfg.ext_ztso; 1208 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1209 ctx->zero = tcg_constant_tl(0); 1210 ctx->virt_inst_excp = false; 1211 } 1212 1213 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1214 { 1215 } 1216 1217 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1218 { 1219 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1220 target_ulong pc_next = ctx->base.pc_next; 1221 1222 if (tb_cflags(dcbase->tb) & CF_PCREL) { 1223 pc_next &= ~TARGET_PAGE_MASK; 1224 } 1225 1226 tcg_gen_insn_start(pc_next, 0); 1227 ctx->insn_start = tcg_last_op(); 1228 } 1229 1230 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1231 { 1232 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1233 CPURISCVState *env = cpu_env(cpu); 1234 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1235 1236 ctx->ol = ctx->xl; 1237 decode_opc(env, ctx, opcode16); 1238 ctx->base.pc_next += ctx->cur_insn_len; 1239 1240 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1241 if (ctx->base.is_jmp == DISAS_NEXT) { 1242 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1243 ctx->base.is_jmp = DISAS_TOO_MANY; 1244 } else { 1245 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1246 1247 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1248 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1249 int len = insn_len(next_insn); 1250 1251 if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { 1252 ctx->base.is_jmp = DISAS_TOO_MANY; 1253 } 1254 } 1255 } 1256 } 1257 } 1258 1259 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1260 { 1261 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1262 1263 switch (ctx->base.is_jmp) { 1264 case DISAS_TOO_MANY: 1265 gen_goto_tb(ctx, 0, 0); 1266 break; 1267 case DISAS_NORETURN: 1268 break; 1269 default: 1270 g_assert_not_reached(); 1271 } 1272 } 1273 1274 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1275 CPUState *cpu, FILE *logfile) 1276 { 1277 #ifndef CONFIG_USER_ONLY 1278 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1279 CPURISCVState *env = &rvcpu->env; 1280 #endif 1281 1282 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1283 #ifndef CONFIG_USER_ONLY 1284 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n", 1285 env->priv, env->virt_enabled); 1286 #endif 1287 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1288 } 1289 1290 static const TranslatorOps riscv_tr_ops = { 1291 .init_disas_context = riscv_tr_init_disas_context, 1292 .tb_start = riscv_tr_tb_start, 1293 .insn_start = riscv_tr_insn_start, 1294 .translate_insn = riscv_tr_translate_insn, 1295 .tb_stop = riscv_tr_tb_stop, 1296 .disas_log = riscv_tr_disas_log, 1297 }; 1298 1299 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1300 vaddr pc, void *host_pc) 1301 { 1302 DisasContext ctx; 1303 1304 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1305 } 1306 1307 void riscv_translate_init(void) 1308 { 1309 int i; 1310 1311 /* 1312 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1313 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1314 * unless you specifically block reads/writes to reg 0. 1315 */ 1316 cpu_gpr[0] = NULL; 1317 cpu_gprh[0] = NULL; 1318 1319 for (i = 1; i < 32; i++) { 1320 cpu_gpr[i] = tcg_global_mem_new(tcg_env, 1321 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1322 cpu_gprh[i] = tcg_global_mem_new(tcg_env, 1323 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1324 } 1325 1326 for (i = 0; i < 32; i++) { 1327 cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env, 1328 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1329 } 1330 1331 cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc"); 1332 cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl"); 1333 cpu_vstart = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vstart), 1334 "vstart"); 1335 load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res), 1336 "load_res"); 1337 load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val), 1338 "load_val"); 1339 /* Assign PM CSRs to tcg globals */ 1340 pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask), 1341 "pmmask"); 1342 pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase), 1343 "pmbase"); 1344 } 1345