1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 #define HELPER_H "helper.h" 37 #include "exec/helper-info.c.inc" 38 #undef HELPER_H 39 40 /* global register indices */ 41 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 42 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 43 static TCGv load_res; 44 static TCGv load_val; 45 /* globals for PM CSRs */ 46 static TCGv pm_mask; 47 static TCGv pm_base; 48 49 /* 50 * If an operation is being performed on less than TARGET_LONG_BITS, 51 * it may require the inputs to be sign- or zero-extended; which will 52 * depend on the exact operation being performed. 53 */ 54 typedef enum { 55 EXT_NONE, 56 EXT_SIGN, 57 EXT_ZERO, 58 } DisasExtend; 59 60 typedef struct DisasContext { 61 DisasContextBase base; 62 target_ulong cur_insn_len; 63 target_ulong pc_save; 64 target_ulong priv_ver; 65 RISCVMXL misa_mxl_max; 66 RISCVMXL xl; 67 uint32_t misa_ext; 68 uint32_t opcode; 69 RISCVExtStatus mstatus_fs; 70 RISCVExtStatus mstatus_vs; 71 uint32_t mem_idx; 72 uint32_t priv; 73 /* 74 * Remember the rounding mode encoded in the previous fp instruction, 75 * which we have already installed into env->fp_status. Or -1 for 76 * no previous fp instruction. Note that we exit the TB when writing 77 * to any system register, which includes CSR_FRM, so we do not have 78 * to reset this known value. 79 */ 80 int frm; 81 RISCVMXL ol; 82 bool virt_inst_excp; 83 bool virt_enabled; 84 const RISCVCPUConfig *cfg_ptr; 85 /* vector extension */ 86 bool vill; 87 /* 88 * Encode LMUL to lmul as follows: 89 * LMUL vlmul lmul 90 * 1 000 0 91 * 2 001 1 92 * 4 010 2 93 * 8 011 3 94 * - 100 - 95 * 1/8 101 -3 96 * 1/4 110 -2 97 * 1/2 111 -1 98 */ 99 int8_t lmul; 100 uint8_t sew; 101 uint8_t vta; 102 uint8_t vma; 103 bool cfg_vta_all_1s; 104 bool vstart_eq_zero; 105 bool vl_eq_vlmax; 106 CPUState *cs; 107 TCGv zero; 108 /* PointerMasking extension */ 109 bool pm_mask_enabled; 110 bool pm_base_enabled; 111 /* Use icount trigger for native debug */ 112 bool itrigger; 113 /* FRM is known to contain a valid value. */ 114 bool frm_valid; 115 /* TCG of the current insn_start */ 116 TCGOp *insn_start; 117 } DisasContext; 118 119 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 120 { 121 return ctx->misa_ext & ext; 122 } 123 124 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 125 { 126 return true; 127 } 128 129 static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) 130 { 131 return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || 132 ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || 133 ctx->cfg_ptr->ext_xtheadcondmov || 134 ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || 135 ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || 136 ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; 137 } 138 139 #define MATERIALISE_EXT_PREDICATE(ext) \ 140 static bool has_ ## ext ## _p(DisasContext *ctx) \ 141 { \ 142 return ctx->cfg_ptr->ext_ ## ext ; \ 143 } 144 145 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 146 147 #ifdef TARGET_RISCV32 148 #define get_xl(ctx) MXL_RV32 149 #elif defined(CONFIG_USER_ONLY) 150 #define get_xl(ctx) MXL_RV64 151 #else 152 #define get_xl(ctx) ((ctx)->xl) 153 #endif 154 155 /* The word size for this machine mode. */ 156 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 157 { 158 return 16 << get_xl(ctx); 159 } 160 161 /* The operation length, as opposed to the xlen. */ 162 #ifdef TARGET_RISCV32 163 #define get_ol(ctx) MXL_RV32 164 #else 165 #define get_ol(ctx) ((ctx)->ol) 166 #endif 167 168 static inline int get_olen(DisasContext *ctx) 169 { 170 return 16 << get_ol(ctx); 171 } 172 173 /* The maximum register length */ 174 #ifdef TARGET_RISCV32 175 #define get_xl_max(ctx) MXL_RV32 176 #else 177 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 178 #endif 179 180 /* 181 * RISC-V requires NaN-boxing of narrower width floating point values. 182 * This applies when a 32-bit value is assigned to a 64-bit FP register. 183 * For consistency and simplicity, we nanbox results even when the RVD 184 * extension is not present. 185 */ 186 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 187 { 188 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 189 } 190 191 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 192 { 193 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 194 } 195 196 /* 197 * A narrow n-bit operation, where n < FLEN, checks that input operands 198 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 199 * If so, the least-significant bits of the input are used, otherwise the 200 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 201 * 202 * Here, the result is always nan-boxed, even the canonical nan. 203 */ 204 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 205 { 206 TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull); 207 TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull); 208 209 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 210 } 211 212 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 213 { 214 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 215 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 216 217 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 218 } 219 220 static void decode_save_opc(DisasContext *ctx) 221 { 222 assert(ctx->insn_start != NULL); 223 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 224 ctx->insn_start = NULL; 225 } 226 227 static void gen_pc_plus_diff(TCGv target, DisasContext *ctx, 228 target_long diff) 229 { 230 target_ulong dest = ctx->base.pc_next + diff; 231 232 assert(ctx->pc_save != -1); 233 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 234 tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save); 235 if (get_xl(ctx) == MXL_RV32) { 236 tcg_gen_ext32s_tl(target, target); 237 } 238 } else { 239 if (get_xl(ctx) == MXL_RV32) { 240 dest = (int32_t)dest; 241 } 242 tcg_gen_movi_tl(target, dest); 243 } 244 } 245 246 static void gen_update_pc(DisasContext *ctx, target_long diff) 247 { 248 gen_pc_plus_diff(cpu_pc, ctx, diff); 249 ctx->pc_save = ctx->base.pc_next + diff; 250 } 251 252 static void generate_exception(DisasContext *ctx, int excp) 253 { 254 gen_update_pc(ctx, 0); 255 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 256 ctx->base.is_jmp = DISAS_NORETURN; 257 } 258 259 static void gen_exception_illegal(DisasContext *ctx) 260 { 261 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 262 offsetof(CPURISCVState, bins)); 263 if (ctx->virt_inst_excp) { 264 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 265 } else { 266 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 267 } 268 } 269 270 static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target) 271 { 272 tcg_gen_st_tl(target, cpu_env, offsetof(CPURISCVState, badaddr)); 273 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 274 } 275 276 static void lookup_and_goto_ptr(DisasContext *ctx) 277 { 278 #ifndef CONFIG_USER_ONLY 279 if (ctx->itrigger) { 280 gen_helper_itrigger_match(cpu_env); 281 } 282 #endif 283 tcg_gen_lookup_and_goto_ptr(); 284 } 285 286 static void exit_tb(DisasContext *ctx) 287 { 288 #ifndef CONFIG_USER_ONLY 289 if (ctx->itrigger) { 290 gen_helper_itrigger_match(cpu_env); 291 } 292 #endif 293 tcg_gen_exit_tb(NULL, 0); 294 } 295 296 static void gen_goto_tb(DisasContext *ctx, int n, target_long diff) 297 { 298 target_ulong dest = ctx->base.pc_next + diff; 299 300 /* 301 * Under itrigger, instruction executes one by one like singlestep, 302 * direct block chain benefits will be small. 303 */ 304 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 305 /* 306 * For pcrel, the pc must always be up-to-date on entry to 307 * the linked TB, so that it can use simple additions for all 308 * further adjustments. For !pcrel, the linked TB is compiled 309 * to know its full virtual address, so we can delay the 310 * update to pc to the unlinked path. A long chain of links 311 * can thus avoid many updates to the PC. 312 */ 313 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 314 gen_update_pc(ctx, diff); 315 tcg_gen_goto_tb(n); 316 } else { 317 tcg_gen_goto_tb(n); 318 gen_update_pc(ctx, diff); 319 } 320 tcg_gen_exit_tb(ctx->base.tb, n); 321 } else { 322 gen_update_pc(ctx, diff); 323 lookup_and_goto_ptr(ctx); 324 } 325 } 326 327 /* 328 * Wrappers for getting reg values. 329 * 330 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 331 * constant zero as a source, and an uninitialized sink as destination. 332 * 333 * Further, we may provide an extension for word operations. 334 */ 335 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 336 { 337 TCGv t; 338 339 if (reg_num == 0) { 340 return ctx->zero; 341 } 342 343 switch (get_ol(ctx)) { 344 case MXL_RV32: 345 switch (ext) { 346 case EXT_NONE: 347 break; 348 case EXT_SIGN: 349 t = tcg_temp_new(); 350 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 351 return t; 352 case EXT_ZERO: 353 t = tcg_temp_new(); 354 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 355 return t; 356 default: 357 g_assert_not_reached(); 358 } 359 break; 360 case MXL_RV64: 361 case MXL_RV128: 362 break; 363 default: 364 g_assert_not_reached(); 365 } 366 return cpu_gpr[reg_num]; 367 } 368 369 static TCGv get_gprh(DisasContext *ctx, int reg_num) 370 { 371 assert(get_xl(ctx) == MXL_RV128); 372 if (reg_num == 0) { 373 return ctx->zero; 374 } 375 return cpu_gprh[reg_num]; 376 } 377 378 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 379 { 380 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 381 return tcg_temp_new(); 382 } 383 return cpu_gpr[reg_num]; 384 } 385 386 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 387 { 388 if (reg_num == 0) { 389 return tcg_temp_new(); 390 } 391 return cpu_gprh[reg_num]; 392 } 393 394 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 395 { 396 if (reg_num != 0) { 397 switch (get_ol(ctx)) { 398 case MXL_RV32: 399 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 400 break; 401 case MXL_RV64: 402 case MXL_RV128: 403 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 404 break; 405 default: 406 g_assert_not_reached(); 407 } 408 409 if (get_xl_max(ctx) == MXL_RV128) { 410 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 411 } 412 } 413 } 414 415 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 416 { 417 if (reg_num != 0) { 418 switch (get_ol(ctx)) { 419 case MXL_RV32: 420 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 421 break; 422 case MXL_RV64: 423 case MXL_RV128: 424 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 425 break; 426 default: 427 g_assert_not_reached(); 428 } 429 430 if (get_xl_max(ctx) == MXL_RV128) { 431 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 432 } 433 } 434 } 435 436 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 437 { 438 assert(get_ol(ctx) == MXL_RV128); 439 if (reg_num != 0) { 440 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 441 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 442 } 443 } 444 445 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 446 { 447 if (!ctx->cfg_ptr->ext_zfinx) { 448 return cpu_fpr[reg_num]; 449 } 450 451 if (reg_num == 0) { 452 return tcg_constant_i64(0); 453 } 454 switch (get_xl(ctx)) { 455 case MXL_RV32: 456 #ifdef TARGET_RISCV32 457 { 458 TCGv_i64 t = tcg_temp_new_i64(); 459 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 460 return t; 461 } 462 #else 463 /* fall through */ 464 case MXL_RV64: 465 return cpu_gpr[reg_num]; 466 #endif 467 default: 468 g_assert_not_reached(); 469 } 470 } 471 472 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 473 { 474 if (!ctx->cfg_ptr->ext_zfinx) { 475 return cpu_fpr[reg_num]; 476 } 477 478 if (reg_num == 0) { 479 return tcg_constant_i64(0); 480 } 481 switch (get_xl(ctx)) { 482 case MXL_RV32: 483 { 484 TCGv_i64 t = tcg_temp_new_i64(); 485 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 486 return t; 487 } 488 #ifdef TARGET_RISCV64 489 case MXL_RV64: 490 return cpu_gpr[reg_num]; 491 #endif 492 default: 493 g_assert_not_reached(); 494 } 495 } 496 497 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 498 { 499 if (!ctx->cfg_ptr->ext_zfinx) { 500 return cpu_fpr[reg_num]; 501 } 502 503 if (reg_num == 0) { 504 return tcg_temp_new_i64(); 505 } 506 507 switch (get_xl(ctx)) { 508 case MXL_RV32: 509 return tcg_temp_new_i64(); 510 #ifdef TARGET_RISCV64 511 case MXL_RV64: 512 return cpu_gpr[reg_num]; 513 #endif 514 default: 515 g_assert_not_reached(); 516 } 517 } 518 519 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ 520 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 521 { 522 if (!ctx->cfg_ptr->ext_zfinx) { 523 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 524 return; 525 } 526 if (reg_num != 0) { 527 switch (get_xl(ctx)) { 528 case MXL_RV32: 529 #ifdef TARGET_RISCV32 530 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 531 break; 532 #else 533 /* fall through */ 534 case MXL_RV64: 535 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 536 break; 537 #endif 538 default: 539 g_assert_not_reached(); 540 } 541 } 542 } 543 544 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 545 { 546 if (!ctx->cfg_ptr->ext_zfinx) { 547 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 548 return; 549 } 550 551 if (reg_num != 0) { 552 switch (get_xl(ctx)) { 553 case MXL_RV32: 554 #ifdef TARGET_RISCV32 555 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 556 break; 557 #else 558 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 559 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 560 break; 561 case MXL_RV64: 562 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 563 break; 564 #endif 565 default: 566 g_assert_not_reached(); 567 } 568 } 569 } 570 571 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 572 { 573 TCGv succ_pc = dest_gpr(ctx, rd); 574 575 /* check misaligned: */ 576 if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { 577 if ((imm & 0x3) != 0) { 578 TCGv target_pc = tcg_temp_new(); 579 gen_pc_plus_diff(target_pc, ctx, imm); 580 gen_exception_inst_addr_mis(ctx, target_pc); 581 return; 582 } 583 } 584 585 gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len); 586 gen_set_gpr(ctx, rd, succ_pc); 587 588 gen_goto_tb(ctx, 0, imm); /* must use this for safety */ 589 ctx->base.is_jmp = DISAS_NORETURN; 590 } 591 592 /* Compute a canonical address from a register plus offset. */ 593 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 594 { 595 TCGv addr = tcg_temp_new(); 596 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 597 598 tcg_gen_addi_tl(addr, src1, imm); 599 if (ctx->pm_mask_enabled) { 600 tcg_gen_andc_tl(addr, addr, pm_mask); 601 } else if (get_xl(ctx) == MXL_RV32) { 602 tcg_gen_ext32u_tl(addr, addr); 603 } 604 if (ctx->pm_base_enabled) { 605 tcg_gen_or_tl(addr, addr, pm_base); 606 } 607 return addr; 608 } 609 610 /* Compute a canonical address from a register plus reg offset. */ 611 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 612 { 613 TCGv addr = tcg_temp_new(); 614 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 615 616 tcg_gen_add_tl(addr, src1, offs); 617 if (ctx->pm_mask_enabled) { 618 tcg_gen_andc_tl(addr, addr, pm_mask); 619 } else if (get_xl(ctx) == MXL_RV32) { 620 tcg_gen_ext32u_tl(addr, addr); 621 } 622 if (ctx->pm_base_enabled) { 623 tcg_gen_or_tl(addr, addr, pm_base); 624 } 625 return addr; 626 } 627 628 #ifndef CONFIG_USER_ONLY 629 /* 630 * We will have already diagnosed disabled state, 631 * and need to turn initial/clean into dirty. 632 */ 633 static void mark_fs_dirty(DisasContext *ctx) 634 { 635 TCGv tmp; 636 637 if (!has_ext(ctx, RVF)) { 638 return; 639 } 640 641 if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { 642 /* Remember the state change for the rest of the TB. */ 643 ctx->mstatus_fs = EXT_STATUS_DIRTY; 644 645 tmp = tcg_temp_new(); 646 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 647 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 648 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 649 650 if (ctx->virt_enabled) { 651 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 652 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 653 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 654 } 655 } 656 } 657 #else 658 static inline void mark_fs_dirty(DisasContext *ctx) { } 659 #endif 660 661 #ifndef CONFIG_USER_ONLY 662 /* 663 * We will have already diagnosed disabled state, 664 * and need to turn initial/clean into dirty. 665 */ 666 static void mark_vs_dirty(DisasContext *ctx) 667 { 668 TCGv tmp; 669 670 if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { 671 /* Remember the state change for the rest of the TB. */ 672 ctx->mstatus_vs = EXT_STATUS_DIRTY; 673 674 tmp = tcg_temp_new(); 675 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 676 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 677 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 678 679 if (ctx->virt_enabled) { 680 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 681 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 682 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 683 } 684 } 685 } 686 #else 687 static inline void mark_vs_dirty(DisasContext *ctx) { } 688 #endif 689 690 static void gen_set_rm(DisasContext *ctx, int rm) 691 { 692 if (ctx->frm == rm) { 693 return; 694 } 695 ctx->frm = rm; 696 697 if (rm == RISCV_FRM_DYN) { 698 /* The helper will return only if frm valid. */ 699 ctx->frm_valid = true; 700 } 701 702 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 703 decode_save_opc(ctx); 704 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 705 } 706 707 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 708 { 709 if (ctx->frm == rm && ctx->frm_valid) { 710 return; 711 } 712 ctx->frm = rm; 713 ctx->frm_valid = true; 714 715 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 716 decode_save_opc(ctx); 717 gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); 718 } 719 720 static int ex_plus_1(DisasContext *ctx, int nf) 721 { 722 return nf + 1; 723 } 724 725 #define EX_SH(amount) \ 726 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 727 { \ 728 return imm << amount; \ 729 } 730 EX_SH(1) 731 EX_SH(2) 732 EX_SH(3) 733 EX_SH(4) 734 EX_SH(12) 735 736 #define REQUIRE_EXT(ctx, ext) do { \ 737 if (!has_ext(ctx, ext)) { \ 738 return false; \ 739 } \ 740 } while (0) 741 742 #define REQUIRE_32BIT(ctx) do { \ 743 if (get_xl(ctx) != MXL_RV32) { \ 744 return false; \ 745 } \ 746 } while (0) 747 748 #define REQUIRE_64BIT(ctx) do { \ 749 if (get_xl(ctx) != MXL_RV64) { \ 750 return false; \ 751 } \ 752 } while (0) 753 754 #define REQUIRE_128BIT(ctx) do { \ 755 if (get_xl(ctx) != MXL_RV128) { \ 756 return false; \ 757 } \ 758 } while (0) 759 760 #define REQUIRE_64_OR_128BIT(ctx) do { \ 761 if (get_xl(ctx) == MXL_RV32) { \ 762 return false; \ 763 } \ 764 } while (0) 765 766 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 767 if (!ctx->cfg_ptr->ext_##A && \ 768 !ctx->cfg_ptr->ext_##B) { \ 769 return false; \ 770 } \ 771 } while (0) 772 773 static int ex_rvc_register(DisasContext *ctx, int reg) 774 { 775 return 8 + reg; 776 } 777 778 static int ex_sreg_register(DisasContext *ctx, int reg) 779 { 780 return reg < 2 ? reg + 8 : reg + 16; 781 } 782 783 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 784 { 785 /* For RV128 a shamt of 0 means a shift by 64. */ 786 if (get_ol(ctx) == MXL_RV128) { 787 imm = imm ? imm : 64; 788 } 789 return imm; 790 } 791 792 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 793 { 794 /* 795 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 796 * shifts, the shamt is sign-extended. 797 */ 798 if (get_ol(ctx) == MXL_RV128) { 799 imm = imm | (imm & 32) << 1; 800 imm = imm ? imm : 64; 801 } 802 return imm; 803 } 804 805 /* Include the auto-generated decoder for 32 bit insn */ 806 #include "decode-insn32.c.inc" 807 808 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 809 void (*func)(TCGv, TCGv, target_long)) 810 { 811 TCGv dest = dest_gpr(ctx, a->rd); 812 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 813 814 func(dest, src1, a->imm); 815 816 if (get_xl(ctx) == MXL_RV128) { 817 TCGv src1h = get_gprh(ctx, a->rs1); 818 TCGv desth = dest_gprh(ctx, a->rd); 819 820 func(desth, src1h, -(a->imm < 0)); 821 gen_set_gpr128(ctx, a->rd, dest, desth); 822 } else { 823 gen_set_gpr(ctx, a->rd, dest); 824 } 825 826 return true; 827 } 828 829 static bool gen_logic(DisasContext *ctx, arg_r *a, 830 void (*func)(TCGv, TCGv, TCGv)) 831 { 832 TCGv dest = dest_gpr(ctx, a->rd); 833 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 834 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 835 836 func(dest, src1, src2); 837 838 if (get_xl(ctx) == MXL_RV128) { 839 TCGv src1h = get_gprh(ctx, a->rs1); 840 TCGv src2h = get_gprh(ctx, a->rs2); 841 TCGv desth = dest_gprh(ctx, a->rd); 842 843 func(desth, src1h, src2h); 844 gen_set_gpr128(ctx, a->rd, dest, desth); 845 } else { 846 gen_set_gpr(ctx, a->rd, dest); 847 } 848 849 return true; 850 } 851 852 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 853 void (*func)(TCGv, TCGv, target_long), 854 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 855 { 856 TCGv dest = dest_gpr(ctx, a->rd); 857 TCGv src1 = get_gpr(ctx, a->rs1, ext); 858 859 if (get_ol(ctx) < MXL_RV128) { 860 func(dest, src1, a->imm); 861 gen_set_gpr(ctx, a->rd, dest); 862 } else { 863 if (f128 == NULL) { 864 return false; 865 } 866 867 TCGv src1h = get_gprh(ctx, a->rs1); 868 TCGv desth = dest_gprh(ctx, a->rd); 869 870 f128(dest, desth, src1, src1h, a->imm); 871 gen_set_gpr128(ctx, a->rd, dest, desth); 872 } 873 return true; 874 } 875 876 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 877 void (*func)(TCGv, TCGv, TCGv), 878 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 879 { 880 TCGv dest = dest_gpr(ctx, a->rd); 881 TCGv src1 = get_gpr(ctx, a->rs1, ext); 882 TCGv src2 = tcg_constant_tl(a->imm); 883 884 if (get_ol(ctx) < MXL_RV128) { 885 func(dest, src1, src2); 886 gen_set_gpr(ctx, a->rd, dest); 887 } else { 888 if (f128 == NULL) { 889 return false; 890 } 891 892 TCGv src1h = get_gprh(ctx, a->rs1); 893 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 894 TCGv desth = dest_gprh(ctx, a->rd); 895 896 f128(dest, desth, src1, src1h, src2, src2h); 897 gen_set_gpr128(ctx, a->rd, dest, desth); 898 } 899 return true; 900 } 901 902 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 903 void (*func)(TCGv, TCGv, TCGv), 904 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 905 { 906 TCGv dest = dest_gpr(ctx, a->rd); 907 TCGv src1 = get_gpr(ctx, a->rs1, ext); 908 TCGv src2 = get_gpr(ctx, a->rs2, ext); 909 910 if (get_ol(ctx) < MXL_RV128) { 911 func(dest, src1, src2); 912 gen_set_gpr(ctx, a->rd, dest); 913 } else { 914 if (f128 == NULL) { 915 return false; 916 } 917 918 TCGv src1h = get_gprh(ctx, a->rs1); 919 TCGv src2h = get_gprh(ctx, a->rs2); 920 TCGv desth = dest_gprh(ctx, a->rd); 921 922 f128(dest, desth, src1, src1h, src2, src2h); 923 gen_set_gpr128(ctx, a->rd, dest, desth); 924 } 925 return true; 926 } 927 928 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 929 void (*f_tl)(TCGv, TCGv, TCGv), 930 void (*f_32)(TCGv, TCGv, TCGv), 931 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 932 { 933 int olen = get_olen(ctx); 934 935 if (olen != TARGET_LONG_BITS) { 936 if (olen == 32) { 937 f_tl = f_32; 938 } else if (olen != 128) { 939 g_assert_not_reached(); 940 } 941 } 942 return gen_arith(ctx, a, ext, f_tl, f_128); 943 } 944 945 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 946 void (*func)(TCGv, TCGv, target_long), 947 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 948 { 949 TCGv dest, src1; 950 int max_len = get_olen(ctx); 951 952 if (a->shamt >= max_len) { 953 return false; 954 } 955 956 dest = dest_gpr(ctx, a->rd); 957 src1 = get_gpr(ctx, a->rs1, ext); 958 959 if (max_len < 128) { 960 func(dest, src1, a->shamt); 961 gen_set_gpr(ctx, a->rd, dest); 962 } else { 963 TCGv src1h = get_gprh(ctx, a->rs1); 964 TCGv desth = dest_gprh(ctx, a->rd); 965 966 if (f128 == NULL) { 967 return false; 968 } 969 f128(dest, desth, src1, src1h, a->shamt); 970 gen_set_gpr128(ctx, a->rd, dest, desth); 971 } 972 return true; 973 } 974 975 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 976 DisasExtend ext, 977 void (*f_tl)(TCGv, TCGv, target_long), 978 void (*f_32)(TCGv, TCGv, target_long), 979 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 980 target_long)) 981 { 982 int olen = get_olen(ctx); 983 if (olen != TARGET_LONG_BITS) { 984 if (olen == 32) { 985 f_tl = f_32; 986 } else if (olen != 128) { 987 g_assert_not_reached(); 988 } 989 } 990 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 991 } 992 993 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 994 void (*func)(TCGv, TCGv, TCGv)) 995 { 996 TCGv dest, src1, src2; 997 int max_len = get_olen(ctx); 998 999 if (a->shamt >= max_len) { 1000 return false; 1001 } 1002 1003 dest = dest_gpr(ctx, a->rd); 1004 src1 = get_gpr(ctx, a->rs1, ext); 1005 src2 = tcg_constant_tl(a->shamt); 1006 1007 func(dest, src1, src2); 1008 1009 gen_set_gpr(ctx, a->rd, dest); 1010 return true; 1011 } 1012 1013 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 1014 void (*func)(TCGv, TCGv, TCGv), 1015 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1016 { 1017 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1018 TCGv ext2 = tcg_temp_new(); 1019 int max_len = get_olen(ctx); 1020 1021 tcg_gen_andi_tl(ext2, src2, max_len - 1); 1022 1023 TCGv dest = dest_gpr(ctx, a->rd); 1024 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1025 1026 if (max_len < 128) { 1027 func(dest, src1, ext2); 1028 gen_set_gpr(ctx, a->rd, dest); 1029 } else { 1030 TCGv src1h = get_gprh(ctx, a->rs1); 1031 TCGv desth = dest_gprh(ctx, a->rd); 1032 1033 if (f128 == NULL) { 1034 return false; 1035 } 1036 f128(dest, desth, src1, src1h, ext2); 1037 gen_set_gpr128(ctx, a->rd, dest, desth); 1038 } 1039 return true; 1040 } 1041 1042 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1043 void (*f_tl)(TCGv, TCGv, TCGv), 1044 void (*f_32)(TCGv, TCGv, TCGv), 1045 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1046 { 1047 int olen = get_olen(ctx); 1048 if (olen != TARGET_LONG_BITS) { 1049 if (olen == 32) { 1050 f_tl = f_32; 1051 } else if (olen != 128) { 1052 g_assert_not_reached(); 1053 } 1054 } 1055 return gen_shift(ctx, a, ext, f_tl, f_128); 1056 } 1057 1058 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1059 void (*func)(TCGv, TCGv)) 1060 { 1061 TCGv dest = dest_gpr(ctx, a->rd); 1062 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1063 1064 func(dest, src1); 1065 1066 gen_set_gpr(ctx, a->rd, dest); 1067 return true; 1068 } 1069 1070 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1071 void (*f_tl)(TCGv, TCGv), 1072 void (*f_32)(TCGv, TCGv)) 1073 { 1074 int olen = get_olen(ctx); 1075 1076 if (olen != TARGET_LONG_BITS) { 1077 if (olen == 32) { 1078 f_tl = f_32; 1079 } else { 1080 g_assert_not_reached(); 1081 } 1082 } 1083 return gen_unary(ctx, a, ext, f_tl); 1084 } 1085 1086 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1087 { 1088 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1089 CPUState *cpu = ctx->cs; 1090 CPURISCVState *env = cpu->env_ptr; 1091 1092 return cpu_ldl_code(env, pc); 1093 } 1094 1095 /* Include insn module translation function */ 1096 #include "insn_trans/trans_rvi.c.inc" 1097 #include "insn_trans/trans_rvm.c.inc" 1098 #include "insn_trans/trans_rva.c.inc" 1099 #include "insn_trans/trans_rvf.c.inc" 1100 #include "insn_trans/trans_rvd.c.inc" 1101 #include "insn_trans/trans_rvh.c.inc" 1102 #include "insn_trans/trans_rvv.c.inc" 1103 #include "insn_trans/trans_rvb.c.inc" 1104 #include "insn_trans/trans_rvzicond.c.inc" 1105 #include "insn_trans/trans_rvzawrs.c.inc" 1106 #include "insn_trans/trans_rvzicbo.c.inc" 1107 #include "insn_trans/trans_rvzfh.c.inc" 1108 #include "insn_trans/trans_rvk.c.inc" 1109 #include "insn_trans/trans_privileged.c.inc" 1110 #include "insn_trans/trans_svinval.c.inc" 1111 #include "decode-xthead.c.inc" 1112 #include "insn_trans/trans_xthead.c.inc" 1113 #include "insn_trans/trans_xventanacondops.c.inc" 1114 1115 /* Include the auto-generated decoder for 16 bit insn */ 1116 #include "decode-insn16.c.inc" 1117 #include "insn_trans/trans_rvzce.c.inc" 1118 1119 /* Include decoders for factored-out extensions */ 1120 #include "decode-XVentanaCondOps.c.inc" 1121 1122 /* The specification allows for longer insns, but not supported by qemu. */ 1123 #define MAX_INSN_LEN 4 1124 1125 static inline int insn_len(uint16_t first_word) 1126 { 1127 return (first_word & 3) == 3 ? 4 : 2; 1128 } 1129 1130 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1131 { 1132 /* 1133 * A table with predicate (i.e., guard) functions and decoder functions 1134 * that are tested in-order until a decoder matches onto the opcode. 1135 */ 1136 static const struct { 1137 bool (*guard_func)(DisasContext *); 1138 bool (*decode_func)(DisasContext *, uint32_t); 1139 } decoders[] = { 1140 { always_true_p, decode_insn32 }, 1141 { has_xthead_p, decode_xthead }, 1142 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1143 }; 1144 1145 ctx->virt_inst_excp = false; 1146 ctx->cur_insn_len = insn_len(opcode); 1147 /* Check for compressed insn */ 1148 if (ctx->cur_insn_len == 2) { 1149 ctx->opcode = opcode; 1150 /* 1151 * The Zca extension is added as way to refer to instructions in the C 1152 * extension that do not include the floating-point loads and stores 1153 */ 1154 if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) && 1155 decode_insn16(ctx, opcode)) { 1156 return; 1157 } 1158 } else { 1159 uint32_t opcode32 = opcode; 1160 opcode32 = deposit32(opcode32, 16, 16, 1161 translator_lduw(env, &ctx->base, 1162 ctx->base.pc_next + 2)); 1163 ctx->opcode = opcode32; 1164 1165 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1166 if (decoders[i].guard_func(ctx) && 1167 decoders[i].decode_func(ctx, opcode32)) { 1168 return; 1169 } 1170 } 1171 } 1172 1173 gen_exception_illegal(ctx); 1174 } 1175 1176 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1177 { 1178 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1179 CPURISCVState *env = cs->env_ptr; 1180 RISCVCPU *cpu = RISCV_CPU(cs); 1181 uint32_t tb_flags = ctx->base.tb->flags; 1182 1183 ctx->pc_save = ctx->base.pc_first; 1184 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 1185 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1186 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); 1187 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); 1188 ctx->priv_ver = env->priv_ver; 1189 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); 1190 ctx->misa_ext = env->misa_ext; 1191 ctx->frm = -1; /* unknown rounding mode */ 1192 ctx->cfg_ptr = &(cpu->cfg); 1193 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1194 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1195 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1196 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1197 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1198 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1199 ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); 1200 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1201 ctx->misa_mxl_max = env->misa_mxl_max; 1202 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1203 ctx->cs = cs; 1204 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1205 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1206 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1207 ctx->zero = tcg_constant_tl(0); 1208 ctx->virt_inst_excp = false; 1209 } 1210 1211 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1212 { 1213 } 1214 1215 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1216 { 1217 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1218 target_ulong pc_next = ctx->base.pc_next; 1219 1220 if (tb_cflags(dcbase->tb) & CF_PCREL) { 1221 pc_next &= ~TARGET_PAGE_MASK; 1222 } 1223 1224 tcg_gen_insn_start(pc_next, 0); 1225 ctx->insn_start = tcg_last_op(); 1226 } 1227 1228 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1229 { 1230 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1231 CPURISCVState *env = cpu->env_ptr; 1232 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1233 1234 ctx->ol = ctx->xl; 1235 decode_opc(env, ctx, opcode16); 1236 ctx->base.pc_next += ctx->cur_insn_len; 1237 1238 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1239 if (ctx->base.is_jmp == DISAS_NEXT) { 1240 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1241 ctx->base.is_jmp = DISAS_TOO_MANY; 1242 } else { 1243 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1244 1245 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1246 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1247 int len = insn_len(next_insn); 1248 1249 if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { 1250 ctx->base.is_jmp = DISAS_TOO_MANY; 1251 } 1252 } 1253 } 1254 } 1255 } 1256 1257 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1258 { 1259 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1260 1261 switch (ctx->base.is_jmp) { 1262 case DISAS_TOO_MANY: 1263 gen_goto_tb(ctx, 0, 0); 1264 break; 1265 case DISAS_NORETURN: 1266 break; 1267 default: 1268 g_assert_not_reached(); 1269 } 1270 } 1271 1272 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1273 CPUState *cpu, FILE *logfile) 1274 { 1275 #ifndef CONFIG_USER_ONLY 1276 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1277 CPURISCVState *env = &rvcpu->env; 1278 #endif 1279 1280 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1281 #ifndef CONFIG_USER_ONLY 1282 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n", 1283 env->priv, env->virt_enabled); 1284 #endif 1285 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1286 } 1287 1288 static const TranslatorOps riscv_tr_ops = { 1289 .init_disas_context = riscv_tr_init_disas_context, 1290 .tb_start = riscv_tr_tb_start, 1291 .insn_start = riscv_tr_insn_start, 1292 .translate_insn = riscv_tr_translate_insn, 1293 .tb_stop = riscv_tr_tb_stop, 1294 .disas_log = riscv_tr_disas_log, 1295 }; 1296 1297 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1298 target_ulong pc, void *host_pc) 1299 { 1300 DisasContext ctx; 1301 1302 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1303 } 1304 1305 void riscv_translate_init(void) 1306 { 1307 int i; 1308 1309 /* 1310 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1311 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1312 * unless you specifically block reads/writes to reg 0. 1313 */ 1314 cpu_gpr[0] = NULL; 1315 cpu_gprh[0] = NULL; 1316 1317 for (i = 1; i < 32; i++) { 1318 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1319 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1320 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1321 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1322 } 1323 1324 for (i = 0; i < 32; i++) { 1325 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1326 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1327 } 1328 1329 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1330 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1331 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1332 "vstart"); 1333 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1334 "load_res"); 1335 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1336 "load_val"); 1337 /* Assign PM CSRs to tcg globals */ 1338 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1339 "pmmask"); 1340 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1341 "pmbase"); 1342 } 1343