1 /* 2 * RISC-V Vector Extension Internals 3 * 4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef TARGET_RISCV_VECTOR_INTERNALS_H 20 #define TARGET_RISCV_VECTOR_INTERNALS_H 21 22 #include "qemu/bitops.h" 23 #include "cpu.h" 24 #include "tcg/tcg-gvec-desc.h" 25 #include "internals.h" 26 27 static inline uint32_t vext_nf(uint32_t desc) 28 { 29 return FIELD_EX32(simd_data(desc), VDATA, NF); 30 } 31 32 /* 33 * Note that vector data is stored in host-endian 64-bit chunks, 34 * so addressing units smaller than that needs a host-endian fixup. 35 */ 36 #if HOST_BIG_ENDIAN 37 #define H1(x) ((x) ^ 7) 38 #define H1_2(x) ((x) ^ 6) 39 #define H1_4(x) ((x) ^ 4) 40 #define H2(x) ((x) ^ 3) 41 #define H4(x) ((x) ^ 1) 42 #define H8(x) ((x)) 43 #else 44 #define H1(x) (x) 45 #define H1_2(x) (x) 46 #define H1_4(x) (x) 47 #define H2(x) (x) 48 #define H4(x) (x) 49 #define H8(x) (x) 50 #endif 51 52 /* 53 * Encode LMUL to lmul as following: 54 * LMUL vlmul lmul 55 * 1 000 0 56 * 2 001 1 57 * 4 010 2 58 * 8 011 3 59 * - 100 - 60 * 1/8 101 -3 61 * 1/4 110 -2 62 * 1/2 111 -1 63 */ 64 static inline int32_t vext_lmul(uint32_t desc) 65 { 66 return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); 67 } 68 69 static inline uint32_t vext_vm(uint32_t desc) 70 { 71 return FIELD_EX32(simd_data(desc), VDATA, VM); 72 } 73 74 static inline uint32_t vext_vma(uint32_t desc) 75 { 76 return FIELD_EX32(simd_data(desc), VDATA, VMA); 77 } 78 79 static inline uint32_t vext_vta(uint32_t desc) 80 { 81 return FIELD_EX32(simd_data(desc), VDATA, VTA); 82 } 83 84 static inline uint32_t vext_vta_all_1s(uint32_t desc) 85 { 86 return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); 87 } 88 89 /* 90 * Earlier designs (pre-0.9) had a varying number of bits 91 * per mask value (MLEN). In the 0.9 design, MLEN=1. 92 * (Section 4.5) 93 */ 94 static inline int vext_elem_mask(void *v0, int index) 95 { 96 int idx = index / 64; 97 int pos = index % 64; 98 return (((uint64_t *)v0)[idx] >> pos) & 1; 99 } 100 101 /* 102 * Get number of total elements, including prestart, body and tail elements. 103 * Note that when LMUL < 1, the tail includes the elements past VLMAX that 104 * are held in the same vector register. 105 */ 106 static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc, 107 uint32_t esz) 108 { 109 uint32_t vlenb = simd_maxsz(desc); 110 uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); 111 int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 : 112 ctzl(esz) - ctzl(sew) + vext_lmul(desc); 113 return (vlenb << emul) / esz; 114 } 115 116 /* set agnostic elements to 1s */ 117 void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, 118 uint32_t tot); 119 120 /* expand macro args before macro */ 121 #define RVVCALL(macro, ...) macro(__VA_ARGS__) 122 123 /* (TD, T2, TX2) */ 124 #define OP_UU_B uint8_t, uint8_t, uint8_t 125 #define OP_UU_H uint16_t, uint16_t, uint16_t 126 #define OP_UU_W uint32_t, uint32_t, uint32_t 127 #define OP_UU_D uint64_t, uint64_t, uint64_t 128 129 /* (TD, T1, T2, TX1, TX2) */ 130 #define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t 131 #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t 132 #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t 133 #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t 134 135 #define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ 136 static void do_##NAME(void *vd, void *vs2, int i) \ 137 { \ 138 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 139 *((TD *)vd + HD(i)) = OP(s2); \ 140 } 141 142 #define GEN_VEXT_V(NAME, ESZ) \ 143 void HELPER(NAME)(void *vd, void *v0, void *vs2, \ 144 CPURISCVState *env, uint32_t desc) \ 145 { \ 146 uint32_t vm = vext_vm(desc); \ 147 uint32_t vl = env->vl; \ 148 uint32_t total_elems = \ 149 vext_get_total_elems(env, desc, ESZ); \ 150 uint32_t vta = vext_vta(desc); \ 151 uint32_t vma = vext_vma(desc); \ 152 uint32_t i; \ 153 \ 154 for (i = env->vstart; i < vl; i++) { \ 155 if (!vm && !vext_elem_mask(v0, i)) { \ 156 /* set masked-off elements to 1s */ \ 157 vext_set_elems_1s(vd, vma, i * ESZ, \ 158 (i + 1) * ESZ); \ 159 continue; \ 160 } \ 161 do_##NAME(vd, vs2, i); \ 162 } \ 163 env->vstart = 0; \ 164 /* set tail elements to 1s */ \ 165 vext_set_elems_1s(vd, vta, vl * ESZ, \ 166 total_elems * ESZ); \ 167 } 168 169 /* operation of two vector elements */ 170 typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); 171 172 #define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ 173 static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ 174 { \ 175 TX1 s1 = *((T1 *)vs1 + HS1(i)); \ 176 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 177 *((TD *)vd + HD(i)) = OP(s2, s1); \ 178 } 179 180 void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, 181 CPURISCVState *env, uint32_t desc, 182 opivv2_fn *fn, uint32_t esz); 183 184 /* generate the helpers for OPIVV */ 185 #define GEN_VEXT_VV(NAME, ESZ) \ 186 void HELPER(NAME)(void *vd, void *v0, void *vs1, \ 187 void *vs2, CPURISCVState *env, \ 188 uint32_t desc) \ 189 { \ 190 do_vext_vv(vd, v0, vs1, vs2, env, desc, \ 191 do_##NAME, ESZ); \ 192 } 193 194 typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); 195 196 /* 197 * (T1)s1 gives the real operator type. 198 * (TX1)(T1)s1 expands the operator type of widen or narrow operations. 199 */ 200 #define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ 201 static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ 202 { \ 203 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 204 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \ 205 } 206 207 void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, 208 CPURISCVState *env, uint32_t desc, 209 opivx2_fn fn, uint32_t esz); 210 211 /* generate the helpers for OPIVX */ 212 #define GEN_VEXT_VX(NAME, ESZ) \ 213 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ 214 void *vs2, CPURISCVState *env, \ 215 uint32_t desc) \ 216 { \ 217 do_vext_vx(vd, v0, s1, vs2, env, desc, \ 218 do_##NAME, ESZ); \ 219 } 220 221 /* Three of the widening shortening macros: */ 222 /* (TD, T1, T2, TX1, TX2) */ 223 #define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t 224 #define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t 225 #define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t 226 227 #endif /* TARGET_RISCV_VECTOR_INTERNALS_H */ 228