1 /* 2 * RX emulation definition 3 * 4 * Copyright (c) 2019 Yoshinori Sato 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef RX_CPU_H 20 #define RX_CPU_H 21 22 #include "qemu/bitops.h" 23 #include "hw/registerfields.h" 24 #include "cpu-qom.h" 25 26 #include "exec/cpu-defs.h" 27 #include "qemu/cpu-float.h" 28 29 /* PSW define */ 30 REG32(PSW, 0) 31 FIELD(PSW, C, 0, 1) 32 FIELD(PSW, Z, 1, 1) 33 FIELD(PSW, S, 2, 1) 34 FIELD(PSW, O, 3, 1) 35 FIELD(PSW, I, 16, 1) 36 FIELD(PSW, U, 17, 1) 37 FIELD(PSW, PM, 20, 1) 38 FIELD(PSW, IPL, 24, 4) 39 40 /* FPSW define */ 41 REG32(FPSW, 0) 42 FIELD(FPSW, RM, 0, 2) 43 FIELD(FPSW, CV, 2, 1) 44 FIELD(FPSW, CO, 3, 1) 45 FIELD(FPSW, CZ, 4, 1) 46 FIELD(FPSW, CU, 5, 1) 47 FIELD(FPSW, CX, 6, 1) 48 FIELD(FPSW, CE, 7, 1) 49 FIELD(FPSW, CAUSE, 2, 6) 50 FIELD(FPSW, DN, 8, 1) 51 FIELD(FPSW, EV, 10, 1) 52 FIELD(FPSW, EO, 11, 1) 53 FIELD(FPSW, EZ, 12, 1) 54 FIELD(FPSW, EU, 13, 1) 55 FIELD(FPSW, EX, 14, 1) 56 FIELD(FPSW, ENABLE, 10, 5) 57 FIELD(FPSW, FV, 26, 1) 58 FIELD(FPSW, FO, 27, 1) 59 FIELD(FPSW, FZ, 28, 1) 60 FIELD(FPSW, FU, 29, 1) 61 FIELD(FPSW, FX, 30, 1) 62 FIELD(FPSW, FLAGS, 26, 4) 63 FIELD(FPSW, FS, 31, 1) 64 65 enum { 66 NUM_REGS = 16, 67 }; 68 69 typedef struct CPUArchState { 70 /* CPU registers */ 71 uint32_t regs[NUM_REGS]; /* general registers */ 72 uint32_t psw_o; /* O bit of status register */ 73 uint32_t psw_s; /* S bit of status register */ 74 uint32_t psw_z; /* Z bit of status register */ 75 uint32_t psw_c; /* C bit of status register */ 76 uint32_t psw_u; 77 uint32_t psw_i; 78 uint32_t psw_pm; 79 uint32_t psw_ipl; 80 uint32_t bpsw; /* backup status */ 81 uint32_t bpc; /* backup pc */ 82 uint32_t isp; /* global base register */ 83 uint32_t usp; /* vector base register */ 84 uint32_t pc; /* program counter */ 85 uint32_t intb; /* interrupt vector */ 86 uint32_t fintv; 87 uint32_t fpsw; 88 uint64_t acc; 89 90 /* Fields up to this point are cleared by a CPU reset */ 91 struct {} end_reset_fields; 92 93 /* Internal use */ 94 uint32_t in_sleep; 95 uint32_t req_irq; /* Requested interrupt no (hard) */ 96 uint32_t req_ipl; /* Requested interrupt level */ 97 uint32_t ack_irq; /* execute irq */ 98 uint32_t ack_ipl; /* execute ipl */ 99 float_status fp_status; 100 qemu_irq ack; /* Interrupt acknowledge */ 101 } CPURXState; 102 103 /* 104 * RXCPU: 105 * @env: #CPURXState 106 * 107 * A RX CPU 108 */ 109 struct ArchCPU { 110 CPUState parent_obj; 111 112 CPURXState env; 113 }; 114 115 /* 116 * RXCPUClass: 117 * @parent_realize: The parent class' realize handler. 118 * @parent_phases: The parent class' reset phase handlers. 119 * 120 * A RX CPU model. 121 */ 122 struct RXCPUClass { 123 CPUClass parent_class; 124 125 DeviceRealize parent_realize; 126 ResettablePhases parent_phases; 127 }; 128 129 #define CPU_RESOLVING_TYPE TYPE_RX_CPU 130 131 const char *rx_crname(uint8_t cr); 132 #ifndef CONFIG_USER_ONLY 133 void rx_cpu_do_interrupt(CPUState *cpu); 134 bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); 135 hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 136 #endif /* !CONFIG_USER_ONLY */ 137 void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 138 int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 139 int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 140 141 void rx_translate_init(void); 142 void rx_cpu_list(void); 143 void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); 144 145 #define cpu_list rx_cpu_list 146 147 #include "exec/cpu-all.h" 148 149 #define CPU_INTERRUPT_SOFT CPU_INTERRUPT_TGT_INT_0 150 #define CPU_INTERRUPT_FIR CPU_INTERRUPT_TGT_INT_1 151 152 #define RX_CPU_IRQ 0 153 #define RX_CPU_FIR 1 154 155 static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, 156 uint64_t *cs_base, uint32_t *flags) 157 { 158 *pc = env->pc; 159 *cs_base = 0; 160 *flags = FIELD_DP32(0, PSW, PM, env->psw_pm); 161 *flags = FIELD_DP32(*flags, PSW, U, env->psw_u); 162 } 163 164 static inline int cpu_mmu_index(CPURXState *env, bool ifetch) 165 { 166 return 0; 167 } 168 169 static inline uint32_t rx_cpu_pack_psw(CPURXState *env) 170 { 171 uint32_t psw = 0; 172 psw = FIELD_DP32(psw, PSW, IPL, env->psw_ipl); 173 psw = FIELD_DP32(psw, PSW, PM, env->psw_pm); 174 psw = FIELD_DP32(psw, PSW, U, env->psw_u); 175 psw = FIELD_DP32(psw, PSW, I, env->psw_i); 176 psw = FIELD_DP32(psw, PSW, O, env->psw_o >> 31); 177 psw = FIELD_DP32(psw, PSW, S, env->psw_s >> 31); 178 psw = FIELD_DP32(psw, PSW, Z, env->psw_z == 0); 179 psw = FIELD_DP32(psw, PSW, C, env->psw_c); 180 return psw; 181 } 182 183 #endif /* RX_CPU_H */ 184