1 /* 2 * S/390 virtual CPU header 3 * 4 * Copyright (c) 2009 Ulrich Hecht 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * Contributions after 2012-10-29 are licensed under the terms of the 17 * GNU GPL, version 2 or (at your option) any later version. 18 * 19 * You should have received a copy of the GNU (Lesser) General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifndef S390X_CPU_H 24 #define S390X_CPU_H 25 26 #include "qemu-common.h" 27 #include "cpu-qom.h" 28 #include "cpu_models.h" 29 30 #define TARGET_LONG_BITS 64 31 32 #define ELF_MACHINE_UNAME "S390X" 33 34 #define CPUArchState struct CPUS390XState 35 36 #include "exec/cpu-defs.h" 37 #define TARGET_PAGE_BITS 12 38 39 #define TARGET_PHYS_ADDR_SPACE_BITS 64 40 #define TARGET_VIRT_ADDR_SPACE_BITS 64 41 42 #include "exec/cpu-all.h" 43 44 #include "fpu/softfloat.h" 45 46 #define NB_MMU_MODES 4 47 #define TARGET_INSN_START_EXTRA_WORDS 1 48 49 #define MMU_MODE0_SUFFIX _primary 50 #define MMU_MODE1_SUFFIX _secondary 51 #define MMU_MODE2_SUFFIX _home 52 #define MMU_MODE3_SUFFIX _real 53 54 #define MMU_USER_IDX 0 55 56 #define MAX_EXT_QUEUE 16 57 #define MAX_IO_QUEUE 16 58 #define MAX_MCHK_QUEUE 16 59 60 #define PSW_MCHK_MASK 0x0004000000000000 61 #define PSW_IO_MASK 0x0200000000000000 62 63 #define S390_MAX_CPUS 248 64 65 typedef struct PSW { 66 uint64_t mask; 67 uint64_t addr; 68 } PSW; 69 70 typedef struct ExtQueue { 71 uint32_t code; 72 uint32_t param; 73 uint32_t param64; 74 } ExtQueue; 75 76 typedef struct IOIntQueue { 77 uint16_t id; 78 uint16_t nr; 79 uint32_t parm; 80 uint32_t word; 81 } IOIntQueue; 82 83 typedef struct MchkQueue { 84 uint16_t type; 85 } MchkQueue; 86 87 struct CPUS390XState { 88 uint64_t regs[16]; /* GP registers */ 89 /* 90 * The floating point registers are part of the vector registers. 91 * vregs[0][0] -> vregs[15][0] are 16 floating point registers 92 */ 93 CPU_DoubleU vregs[32][2]; /* vector registers */ 94 uint32_t aregs[16]; /* access registers */ 95 uint8_t riccb[64]; /* runtime instrumentation control */ 96 uint64_t gscb[4]; /* guarded storage control */ 97 98 /* Fields up to this point are not cleared by initial CPU reset */ 99 struct {} start_initial_reset_fields; 100 101 uint32_t fpc; /* floating-point control register */ 102 uint32_t cc_op; 103 104 float_status fpu_status; /* passed to softfloat lib */ 105 106 /* The low part of a 128-bit return, or remainder of a divide. */ 107 uint64_t retxl; 108 109 PSW psw; 110 111 uint64_t cc_src; 112 uint64_t cc_dst; 113 uint64_t cc_vr; 114 115 uint64_t ex_value; 116 117 uint64_t __excp_addr; 118 uint64_t psa; 119 120 uint32_t int_pgm_code; 121 uint32_t int_pgm_ilen; 122 123 uint32_t int_svc_code; 124 uint32_t int_svc_ilen; 125 126 uint64_t per_address; 127 uint16_t per_perc_atmid; 128 129 uint64_t cregs[16]; /* control registers */ 130 131 ExtQueue ext_queue[MAX_EXT_QUEUE]; 132 IOIntQueue io_queue[MAX_IO_QUEUE][8]; 133 MchkQueue mchk_queue[MAX_MCHK_QUEUE]; 134 135 int pending_int; 136 int ext_index; 137 int io_index[8]; 138 int mchk_index; 139 140 uint64_t ckc; 141 uint64_t cputm; 142 uint32_t todpr; 143 144 uint64_t pfault_token; 145 uint64_t pfault_compare; 146 uint64_t pfault_select; 147 148 uint64_t gbea; 149 uint64_t pp; 150 151 /* Fields up to this point are cleared by a CPU reset */ 152 struct {} end_reset_fields; 153 154 CPU_COMMON 155 156 #if !defined(CONFIG_USER_ONLY) 157 uint32_t core_id; /* PoP "CPU address", same as cpu_index */ 158 uint64_t cpuid; 159 #endif 160 161 uint64_t tod_offset; 162 uint64_t tod_basetime; 163 QEMUTimer *tod_timer; 164 165 QEMUTimer *cpu_timer; 166 167 /* 168 * The cpu state represents the logical state of a cpu. In contrast to other 169 * architectures, there is a difference between a halt and a stop on s390. 170 * If all cpus are either stopped (including check stop) or in the disabled 171 * wait state, the vm can be shut down. 172 */ 173 #define CPU_STATE_UNINITIALIZED 0x00 174 #define CPU_STATE_STOPPED 0x01 175 #define CPU_STATE_CHECK_STOP 0x02 176 #define CPU_STATE_OPERATING 0x03 177 #define CPU_STATE_LOAD 0x04 178 uint8_t cpu_state; 179 180 /* currently processed sigp order */ 181 uint8_t sigp_order; 182 183 }; 184 185 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr) 186 { 187 return &cs->vregs[nr][0]; 188 } 189 190 /** 191 * S390CPU: 192 * @env: #CPUS390XState. 193 * 194 * An S/390 CPU. 195 */ 196 struct S390CPU { 197 /*< private >*/ 198 CPUState parent_obj; 199 /*< public >*/ 200 201 CPUS390XState env; 202 S390CPUModel *model; 203 /* needed for live migration */ 204 void *irqstate; 205 uint32_t irqstate_saved_size; 206 }; 207 208 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env) 209 { 210 return container_of(env, S390CPU, env); 211 } 212 213 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e)) 214 215 #define ENV_OFFSET offsetof(S390CPU, env) 216 217 #ifndef CONFIG_USER_ONLY 218 extern const struct VMStateDescription vmstate_s390_cpu; 219 #endif 220 221 /* distinguish between 24 bit and 31 bit addressing */ 222 #define HIGH_ORDER_BIT 0x80000000 223 224 /* Interrupt Codes */ 225 /* Program Interrupts */ 226 #define PGM_OPERATION 0x0001 227 #define PGM_PRIVILEGED 0x0002 228 #define PGM_EXECUTE 0x0003 229 #define PGM_PROTECTION 0x0004 230 #define PGM_ADDRESSING 0x0005 231 #define PGM_SPECIFICATION 0x0006 232 #define PGM_DATA 0x0007 233 #define PGM_FIXPT_OVERFLOW 0x0008 234 #define PGM_FIXPT_DIVIDE 0x0009 235 #define PGM_DEC_OVERFLOW 0x000a 236 #define PGM_DEC_DIVIDE 0x000b 237 #define PGM_HFP_EXP_OVERFLOW 0x000c 238 #define PGM_HFP_EXP_UNDERFLOW 0x000d 239 #define PGM_HFP_SIGNIFICANCE 0x000e 240 #define PGM_HFP_DIVIDE 0x000f 241 #define PGM_SEGMENT_TRANS 0x0010 242 #define PGM_PAGE_TRANS 0x0011 243 #define PGM_TRANS_SPEC 0x0012 244 #define PGM_SPECIAL_OP 0x0013 245 #define PGM_OPERAND 0x0015 246 #define PGM_TRACE_TABLE 0x0016 247 #define PGM_SPACE_SWITCH 0x001c 248 #define PGM_HFP_SQRT 0x001d 249 #define PGM_PC_TRANS_SPEC 0x001f 250 #define PGM_AFX_TRANS 0x0020 251 #define PGM_ASX_TRANS 0x0021 252 #define PGM_LX_TRANS 0x0022 253 #define PGM_EX_TRANS 0x0023 254 #define PGM_PRIM_AUTH 0x0024 255 #define PGM_SEC_AUTH 0x0025 256 #define PGM_ALET_SPEC 0x0028 257 #define PGM_ALEN_SPEC 0x0029 258 #define PGM_ALE_SEQ 0x002a 259 #define PGM_ASTE_VALID 0x002b 260 #define PGM_ASTE_SEQ 0x002c 261 #define PGM_EXT_AUTH 0x002d 262 #define PGM_STACK_FULL 0x0030 263 #define PGM_STACK_EMPTY 0x0031 264 #define PGM_STACK_SPEC 0x0032 265 #define PGM_STACK_TYPE 0x0033 266 #define PGM_STACK_OP 0x0034 267 #define PGM_ASCE_TYPE 0x0038 268 #define PGM_REG_FIRST_TRANS 0x0039 269 #define PGM_REG_SEC_TRANS 0x003a 270 #define PGM_REG_THIRD_TRANS 0x003b 271 #define PGM_MONITOR 0x0040 272 #define PGM_PER 0x0080 273 #define PGM_CRYPTO 0x0119 274 275 /* External Interrupts */ 276 #define EXT_INTERRUPT_KEY 0x0040 277 #define EXT_CLOCK_COMP 0x1004 278 #define EXT_CPU_TIMER 0x1005 279 #define EXT_MALFUNCTION 0x1200 280 #define EXT_EMERGENCY 0x1201 281 #define EXT_EXTERNAL_CALL 0x1202 282 #define EXT_ETR 0x1406 283 #define EXT_SERVICE 0x2401 284 #define EXT_VIRTIO 0x2603 285 286 /* PSW defines */ 287 #undef PSW_MASK_PER 288 #undef PSW_MASK_DAT 289 #undef PSW_MASK_IO 290 #undef PSW_MASK_EXT 291 #undef PSW_MASK_KEY 292 #undef PSW_SHIFT_KEY 293 #undef PSW_MASK_MCHECK 294 #undef PSW_MASK_WAIT 295 #undef PSW_MASK_PSTATE 296 #undef PSW_MASK_ASC 297 #undef PSW_SHIFT_ASC 298 #undef PSW_MASK_CC 299 #undef PSW_MASK_PM 300 #undef PSW_SHIFT_MASK_PM 301 #undef PSW_MASK_64 302 #undef PSW_MASK_32 303 #undef PSW_MASK_ESA_ADDR 304 305 #define PSW_MASK_PER 0x4000000000000000ULL 306 #define PSW_MASK_DAT 0x0400000000000000ULL 307 #define PSW_MASK_IO 0x0200000000000000ULL 308 #define PSW_MASK_EXT 0x0100000000000000ULL 309 #define PSW_MASK_KEY 0x00F0000000000000ULL 310 #define PSW_SHIFT_KEY 52 311 #define PSW_MASK_MCHECK 0x0004000000000000ULL 312 #define PSW_MASK_WAIT 0x0002000000000000ULL 313 #define PSW_MASK_PSTATE 0x0001000000000000ULL 314 #define PSW_MASK_ASC 0x0000C00000000000ULL 315 #define PSW_SHIFT_ASC 46 316 #define PSW_MASK_CC 0x0000300000000000ULL 317 #define PSW_MASK_PM 0x00000F0000000000ULL 318 #define PSW_SHIFT_MASK_PM 40 319 #define PSW_MASK_64 0x0000000100000000ULL 320 #define PSW_MASK_32 0x0000000080000000ULL 321 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL 322 323 #undef PSW_ASC_PRIMARY 324 #undef PSW_ASC_ACCREG 325 #undef PSW_ASC_SECONDARY 326 #undef PSW_ASC_HOME 327 328 #define PSW_ASC_PRIMARY 0x0000000000000000ULL 329 #define PSW_ASC_ACCREG 0x0000400000000000ULL 330 #define PSW_ASC_SECONDARY 0x0000800000000000ULL 331 #define PSW_ASC_HOME 0x0000C00000000000ULL 332 333 /* the address space values shifted */ 334 #define AS_PRIMARY 0 335 #define AS_ACCREG 1 336 #define AS_SECONDARY 2 337 #define AS_HOME 3 338 339 /* tb flags */ 340 341 #define FLAG_MASK_PSW_SHIFT 31 342 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) 343 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) 344 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) 345 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) 346 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) 347 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \ 348 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) 349 350 /* Control register 0 bits */ 351 #define CR0_LOWPROT 0x0000000010000000ULL 352 #define CR0_SECONDARY 0x0000000004000000ULL 353 #define CR0_EDAT 0x0000000000800000ULL 354 355 /* MMU */ 356 #define MMU_PRIMARY_IDX 0 357 #define MMU_SECONDARY_IDX 1 358 #define MMU_HOME_IDX 2 359 #define MMU_REAL_IDX 3 360 361 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) 362 { 363 switch (env->psw.mask & PSW_MASK_ASC) { 364 case PSW_ASC_PRIMARY: 365 return MMU_PRIMARY_IDX; 366 case PSW_ASC_SECONDARY: 367 return MMU_SECONDARY_IDX; 368 case PSW_ASC_HOME: 369 return MMU_HOME_IDX; 370 case PSW_ASC_ACCREG: 371 /* Fallthrough: access register mode is not yet supported */ 372 default: 373 abort(); 374 } 375 } 376 377 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, 378 target_ulong *cs_base, uint32_t *flags) 379 { 380 *pc = env->psw.addr; 381 *cs_base = env->ex_value; 382 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; 383 } 384 385 /* PER bits from control register 9 */ 386 #define PER_CR9_EVENT_BRANCH 0x80000000 387 #define PER_CR9_EVENT_IFETCH 0x40000000 388 #define PER_CR9_EVENT_STORE 0x20000000 389 #define PER_CR9_EVENT_STORE_REAL 0x08000000 390 #define PER_CR9_EVENT_NULLIFICATION 0x01000000 391 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 392 #define PER_CR9_CONTROL_ALTERATION 0x00200000 393 394 /* PER bits from the PER CODE/ATMID/AI in lowcore */ 395 #define PER_CODE_EVENT_BRANCH 0x8000 396 #define PER_CODE_EVENT_IFETCH 0x4000 397 #define PER_CODE_EVENT_STORE 0x2000 398 #define PER_CODE_EVENT_STORE_REAL 0x0800 399 #define PER_CODE_EVENT_NULLIFICATION 0x0100 400 401 #define EXCP_EXT 1 /* external interrupt */ 402 #define EXCP_SVC 2 /* supervisor call (syscall) */ 403 #define EXCP_PGM 3 /* program interruption */ 404 #define EXCP_IO 7 /* I/O interrupt */ 405 #define EXCP_MCHK 8 /* machine check */ 406 407 #define INTERRUPT_EXT (1 << 0) 408 #define INTERRUPT_TOD (1 << 1) 409 #define INTERRUPT_CPUTIMER (1 << 2) 410 #define INTERRUPT_IO (1 << 3) 411 #define INTERRUPT_MCHK (1 << 4) 412 413 /* Program Status Word. */ 414 #define S390_PSWM_REGNUM 0 415 #define S390_PSWA_REGNUM 1 416 /* General Purpose Registers. */ 417 #define S390_R0_REGNUM 2 418 #define S390_R1_REGNUM 3 419 #define S390_R2_REGNUM 4 420 #define S390_R3_REGNUM 5 421 #define S390_R4_REGNUM 6 422 #define S390_R5_REGNUM 7 423 #define S390_R6_REGNUM 8 424 #define S390_R7_REGNUM 9 425 #define S390_R8_REGNUM 10 426 #define S390_R9_REGNUM 11 427 #define S390_R10_REGNUM 12 428 #define S390_R11_REGNUM 13 429 #define S390_R12_REGNUM 14 430 #define S390_R13_REGNUM 15 431 #define S390_R14_REGNUM 16 432 #define S390_R15_REGNUM 17 433 /* Total Core Registers. */ 434 #define S390_NUM_CORE_REGS 18 435 436 static inline void setcc(S390CPU *cpu, uint64_t cc) 437 { 438 CPUS390XState *env = &cpu->env; 439 440 env->psw.mask &= ~(3ull << 44); 441 env->psw.mask |= (cc & 3) << 44; 442 env->cc_op = cc; 443 } 444 445 /* STSI */ 446 #define STSI_LEVEL_MASK 0x00000000f0000000ULL 447 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL 448 #define STSI_LEVEL_1 0x0000000010000000ULL 449 #define STSI_LEVEL_2 0x0000000020000000ULL 450 #define STSI_LEVEL_3 0x0000000030000000ULL 451 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL 452 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL 453 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL 454 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL 455 456 /* Basic Machine Configuration */ 457 struct sysib_111 { 458 uint32_t res1[8]; 459 uint8_t manuf[16]; 460 uint8_t type[4]; 461 uint8_t res2[12]; 462 uint8_t model[16]; 463 uint8_t sequence[16]; 464 uint8_t plant[4]; 465 uint8_t res3[156]; 466 }; 467 468 /* Basic Machine CPU */ 469 struct sysib_121 { 470 uint32_t res1[80]; 471 uint8_t sequence[16]; 472 uint8_t plant[4]; 473 uint8_t res2[2]; 474 uint16_t cpu_addr; 475 uint8_t res3[152]; 476 }; 477 478 /* Basic Machine CPUs */ 479 struct sysib_122 { 480 uint8_t res1[32]; 481 uint32_t capability; 482 uint16_t total_cpus; 483 uint16_t active_cpus; 484 uint16_t standby_cpus; 485 uint16_t reserved_cpus; 486 uint16_t adjustments[2026]; 487 }; 488 489 /* LPAR CPU */ 490 struct sysib_221 { 491 uint32_t res1[80]; 492 uint8_t sequence[16]; 493 uint8_t plant[4]; 494 uint16_t cpu_id; 495 uint16_t cpu_addr; 496 uint8_t res3[152]; 497 }; 498 499 /* LPAR CPUs */ 500 struct sysib_222 { 501 uint32_t res1[32]; 502 uint16_t lpar_num; 503 uint8_t res2; 504 uint8_t lcpuc; 505 uint16_t total_cpus; 506 uint16_t conf_cpus; 507 uint16_t standby_cpus; 508 uint16_t reserved_cpus; 509 uint8_t name[8]; 510 uint32_t caf; 511 uint8_t res3[16]; 512 uint16_t dedicated_cpus; 513 uint16_t shared_cpus; 514 uint8_t res4[180]; 515 }; 516 517 /* VM CPUs */ 518 struct sysib_322 { 519 uint8_t res1[31]; 520 uint8_t count; 521 struct { 522 uint8_t res2[4]; 523 uint16_t total_cpus; 524 uint16_t conf_cpus; 525 uint16_t standby_cpus; 526 uint16_t reserved_cpus; 527 uint8_t name[8]; 528 uint32_t caf; 529 uint8_t cpi[16]; 530 uint8_t res5[3]; 531 uint8_t ext_name_encoding; 532 uint32_t res3; 533 uint8_t uuid[16]; 534 } vm[8]; 535 uint8_t res4[1504]; 536 uint8_t ext_names[8][256]; 537 }; 538 539 /* MMU defines */ 540 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */ 541 #define _ASCE_SUBSPACE 0x200 /* subspace group control */ 542 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 543 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 544 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 545 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 546 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 547 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 548 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 549 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 550 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 551 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 552 553 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */ 554 #define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */ 555 #define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */ 556 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ 557 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ 558 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 559 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 560 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 561 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 562 563 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */ 564 #define _SEGMENT_ENTRY_FC 0x400 /* format control */ 565 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 566 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 567 568 #define VADDR_PX 0xff000 /* page index bits */ 569 570 #define _PAGE_RO 0x200 /* HW read-only bit */ 571 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 572 #define _PAGE_RES0 0x800 /* bit must be zero */ 573 574 #define SK_C (0x1 << 1) 575 #define SK_R (0x1 << 2) 576 #define SK_F (0x1 << 3) 577 #define SK_ACC_MASK (0xf << 4) 578 579 /* SIGP order codes */ 580 #define SIGP_SENSE 0x01 581 #define SIGP_EXTERNAL_CALL 0x02 582 #define SIGP_EMERGENCY 0x03 583 #define SIGP_START 0x04 584 #define SIGP_STOP 0x05 585 #define SIGP_RESTART 0x06 586 #define SIGP_STOP_STORE_STATUS 0x09 587 #define SIGP_INITIAL_CPU_RESET 0x0b 588 #define SIGP_CPU_RESET 0x0c 589 #define SIGP_SET_PREFIX 0x0d 590 #define SIGP_STORE_STATUS_ADDR 0x0e 591 #define SIGP_SET_ARCH 0x12 592 #define SIGP_STORE_ADTL_STATUS 0x17 593 594 /* SIGP condition codes */ 595 #define SIGP_CC_ORDER_CODE_ACCEPTED 0 596 #define SIGP_CC_STATUS_STORED 1 597 #define SIGP_CC_BUSY 2 598 #define SIGP_CC_NOT_OPERATIONAL 3 599 600 /* SIGP status bits */ 601 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL 602 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL 603 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL 604 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL 605 #define SIGP_STAT_STOPPED 0x00000040UL 606 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL 607 #define SIGP_STAT_CHECK_STOP 0x00000010UL 608 #define SIGP_STAT_INOPERATIVE 0x00000004UL 609 #define SIGP_STAT_INVALID_ORDER 0x00000002UL 610 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL 611 612 /* SIGP SET ARCHITECTURE modes */ 613 #define SIGP_MODE_ESA_S390 0 614 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1 615 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2 616 617 /* SIGP order code mask corresponding to bit positions 56-63 */ 618 #define SIGP_ORDER_MASK 0x000000ff 619 620 /* from s390-virtio-ccw */ 621 #define MEM_SECTION_SIZE 0x10000000UL 622 #define MAX_AVAIL_SLOTS 32 623 624 /* machine check interruption code */ 625 626 /* subclasses */ 627 #define MCIC_SC_SD 0x8000000000000000ULL 628 #define MCIC_SC_PD 0x4000000000000000ULL 629 #define MCIC_SC_SR 0x2000000000000000ULL 630 #define MCIC_SC_CD 0x0800000000000000ULL 631 #define MCIC_SC_ED 0x0400000000000000ULL 632 #define MCIC_SC_DG 0x0100000000000000ULL 633 #define MCIC_SC_W 0x0080000000000000ULL 634 #define MCIC_SC_CP 0x0040000000000000ULL 635 #define MCIC_SC_SP 0x0020000000000000ULL 636 #define MCIC_SC_CK 0x0010000000000000ULL 637 638 /* subclass modifiers */ 639 #define MCIC_SCM_B 0x0002000000000000ULL 640 #define MCIC_SCM_DA 0x0000000020000000ULL 641 #define MCIC_SCM_AP 0x0000000000080000ULL 642 643 /* storage errors */ 644 #define MCIC_SE_SE 0x0000800000000000ULL 645 #define MCIC_SE_SC 0x0000400000000000ULL 646 #define MCIC_SE_KE 0x0000200000000000ULL 647 #define MCIC_SE_DS 0x0000100000000000ULL 648 #define MCIC_SE_IE 0x0000000080000000ULL 649 650 /* validity bits */ 651 #define MCIC_VB_WP 0x0000080000000000ULL 652 #define MCIC_VB_MS 0x0000040000000000ULL 653 #define MCIC_VB_PM 0x0000020000000000ULL 654 #define MCIC_VB_IA 0x0000010000000000ULL 655 #define MCIC_VB_FA 0x0000008000000000ULL 656 #define MCIC_VB_VR 0x0000004000000000ULL 657 #define MCIC_VB_EC 0x0000002000000000ULL 658 #define MCIC_VB_FP 0x0000001000000000ULL 659 #define MCIC_VB_GR 0x0000000800000000ULL 660 #define MCIC_VB_CR 0x0000000400000000ULL 661 #define MCIC_VB_ST 0x0000000100000000ULL 662 #define MCIC_VB_AR 0x0000000040000000ULL 663 #define MCIC_VB_GS 0x0000000008000000ULL 664 #define MCIC_VB_PR 0x0000000000200000ULL 665 #define MCIC_VB_FC 0x0000000000100000ULL 666 #define MCIC_VB_CT 0x0000000000020000ULL 667 #define MCIC_VB_CC 0x0000000000010000ULL 668 669 670 /* cpu.c */ 671 int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low); 672 int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low); 673 void s390_crypto_reset(void); 674 bool s390_get_squash_mcss(void); 675 int s390_get_memslot_count(void); 676 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit); 677 void s390_cmma_reset(void); 678 int s390_cpu_restart(S390CPU *cpu); 679 void s390_enable_css_support(S390CPU *cpu); 680 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, 681 int vq, bool assign); 682 #ifndef CONFIG_USER_ONLY 683 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); 684 #else 685 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) 686 { 687 return 0; 688 } 689 #endif /* CONFIG_USER_ONLY */ 690 691 692 /* cpu_models.c */ 693 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf); 694 #define cpu_list s390_cpu_list 695 696 /* helper.c */ 697 #define cpu_init(cpu_model) cpu_generic_init(TYPE_S390_CPU, cpu_model) 698 S390CPU *s390x_new_cpu(const char *typename, uint32_t core_id, Error **errp); 699 700 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU 701 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) 702 703 /* you can call this signal handler from your SIGBUS and SIGSEGV 704 signal handlers to inform the virtual CPU of exceptions. non zero 705 is returned if the signal was handled by the virtual CPU. */ 706 int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); 707 #define cpu_signal_handler cpu_s390x_signal_handler 708 709 710 /* interrupt.c */ 711 void s390_crw_mchk(void); 712 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr, 713 uint32_t io_int_parm, uint32_t io_int_word); 714 /* automatically detect the instruction length */ 715 #define ILEN_AUTO 0xff 716 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen); 717 /* service interrupts are floating therefore we must not pass an cpustate */ 718 void s390_sclp_extint(uint32_t parm); 719 720 721 /* mmu_helper.c */ 722 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 723 int len, bool is_write); 724 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ 725 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) 726 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ 727 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) 728 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ 729 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) 730 731 732 /* outside of target/s390x/ */ 733 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); 734 735 #endif 736