1 /* 2 * QEMU SuperH CPU 3 * 4 * Copyright (c) 2005 Samuel Tardieu 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see 19 * <http://www.gnu.org/licenses/lgpl-2.1.html> 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu/qemu-print.h" 25 #include "cpu.h" 26 #include "migration/vmstate.h" 27 #include "exec/exec-all.h" 28 #include "fpu/softfloat-helpers.h" 29 #include "tcg/tcg.h" 30 31 static void superh_cpu_set_pc(CPUState *cs, vaddr value) 32 { 33 SuperHCPU *cpu = SUPERH_CPU(cs); 34 35 cpu->env.pc = value; 36 } 37 38 static vaddr superh_cpu_get_pc(CPUState *cs) 39 { 40 SuperHCPU *cpu = SUPERH_CPU(cs); 41 42 return cpu->env.pc; 43 } 44 45 static void superh_cpu_synchronize_from_tb(CPUState *cs, 46 const TranslationBlock *tb) 47 { 48 SuperHCPU *cpu = SUPERH_CPU(cs); 49 50 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 51 cpu->env.pc = tb->pc; 52 cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; 53 } 54 55 static void superh_restore_state_to_opc(CPUState *cs, 56 const TranslationBlock *tb, 57 const uint64_t *data) 58 { 59 SuperHCPU *cpu = SUPERH_CPU(cs); 60 61 cpu->env.pc = data[0]; 62 cpu->env.flags = data[1]; 63 /* 64 * Theoretically delayed_pc should also be restored. In practice the 65 * branch instruction is re-executed after exception, so the delayed 66 * branch target will be recomputed. 67 */ 68 } 69 70 #ifndef CONFIG_USER_ONLY 71 static bool superh_io_recompile_replay_branch(CPUState *cs, 72 const TranslationBlock *tb) 73 { 74 SuperHCPU *cpu = SUPERH_CPU(cs); 75 CPUSH4State *env = &cpu->env; 76 77 if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) 78 && !(cs->tcg_cflags & CF_PCREL) && env->pc != tb->pc) { 79 env->pc -= 2; 80 env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND); 81 return true; 82 } 83 return false; 84 } 85 #endif 86 87 static bool superh_cpu_has_work(CPUState *cs) 88 { 89 return cs->interrupt_request & CPU_INTERRUPT_HARD; 90 } 91 92 static void superh_cpu_reset_hold(Object *obj) 93 { 94 CPUState *s = CPU(obj); 95 SuperHCPU *cpu = SUPERH_CPU(s); 96 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); 97 CPUSH4State *env = &cpu->env; 98 99 if (scc->parent_phases.hold) { 100 scc->parent_phases.hold(obj); 101 } 102 103 memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); 104 105 env->pc = 0xA0000000; 106 #if defined(CONFIG_USER_ONLY) 107 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ 108 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ 109 #else 110 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) | 111 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0); 112 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ 113 set_float_rounding_mode(float_round_to_zero, &env->fp_status); 114 set_flush_to_zero(1, &env->fp_status); 115 #endif 116 set_default_nan_mode(1, &env->fp_status); 117 } 118 119 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 120 { 121 info->mach = bfd_mach_sh4; 122 info->print_insn = print_insn_sh; 123 } 124 125 static void superh_cpu_list_entry(gpointer data, gpointer user_data) 126 { 127 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 128 int len = strlen(typename) - strlen(SUPERH_CPU_TYPE_SUFFIX); 129 130 qemu_printf("%.*s\n", len, typename); 131 } 132 133 void sh4_cpu_list(void) 134 { 135 GSList *list; 136 137 list = object_class_get_list_sorted(TYPE_SUPERH_CPU, false); 138 g_slist_foreach(list, superh_cpu_list_entry, NULL); 139 g_slist_free(list); 140 } 141 142 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) 143 { 144 ObjectClass *oc; 145 char *s, *typename = NULL; 146 147 s = g_ascii_strdown(cpu_model, -1); 148 if (strcmp(s, "any") == 0) { 149 oc = object_class_by_name(TYPE_SH7750R_CPU); 150 goto out; 151 } 152 153 typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s); 154 oc = object_class_by_name(typename); 155 156 out: 157 g_free(s); 158 g_free(typename); 159 return oc; 160 } 161 162 static void sh7750r_cpu_initfn(Object *obj) 163 { 164 SuperHCPU *cpu = SUPERH_CPU(obj); 165 CPUSH4State *env = &cpu->env; 166 167 env->id = SH_CPU_SH7750R; 168 env->features = SH_FEATURE_BCR3_AND_BCR4; 169 } 170 171 static void sh7750r_class_init(ObjectClass *oc, void *data) 172 { 173 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 174 175 scc->pvr = 0x00050000; 176 scc->prr = 0x00000100; 177 scc->cvr = 0x00110000; 178 } 179 180 static void sh7751r_cpu_initfn(Object *obj) 181 { 182 SuperHCPU *cpu = SUPERH_CPU(obj); 183 CPUSH4State *env = &cpu->env; 184 185 env->id = SH_CPU_SH7751R; 186 env->features = SH_FEATURE_BCR3_AND_BCR4; 187 } 188 189 static void sh7751r_class_init(ObjectClass *oc, void *data) 190 { 191 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 192 193 scc->pvr = 0x04050005; 194 scc->prr = 0x00000113; 195 scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ 196 } 197 198 static void sh7785_cpu_initfn(Object *obj) 199 { 200 SuperHCPU *cpu = SUPERH_CPU(obj); 201 CPUSH4State *env = &cpu->env; 202 203 env->id = SH_CPU_SH7785; 204 env->features = SH_FEATURE_SH4A; 205 } 206 207 static void sh7785_class_init(ObjectClass *oc, void *data) 208 { 209 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 210 211 scc->pvr = 0x10300700; 212 scc->prr = 0x00000200; 213 scc->cvr = 0x71440211; 214 } 215 216 static void superh_cpu_realizefn(DeviceState *dev, Error **errp) 217 { 218 CPUState *cs = CPU(dev); 219 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); 220 Error *local_err = NULL; 221 222 cpu_exec_realizefn(cs, &local_err); 223 if (local_err != NULL) { 224 error_propagate(errp, local_err); 225 return; 226 } 227 228 cpu_reset(cs); 229 qemu_init_vcpu(cs); 230 231 scc->parent_realize(dev, errp); 232 } 233 234 static void superh_cpu_initfn(Object *obj) 235 { 236 SuperHCPU *cpu = SUPERH_CPU(obj); 237 CPUSH4State *env = &cpu->env; 238 239 env->movcal_backup_tail = &(env->movcal_backup); 240 } 241 242 #ifndef CONFIG_USER_ONLY 243 static const VMStateDescription vmstate_sh_cpu = { 244 .name = "cpu", 245 .unmigratable = 1, 246 }; 247 248 #include "hw/core/sysemu-cpu-ops.h" 249 250 static const struct SysemuCPUOps sh4_sysemu_ops = { 251 .get_phys_page_debug = superh_cpu_get_phys_page_debug, 252 }; 253 #endif 254 255 #include "hw/core/tcg-cpu-ops.h" 256 257 static const struct TCGCPUOps superh_tcg_ops = { 258 .initialize = sh4_translate_init, 259 .synchronize_from_tb = superh_cpu_synchronize_from_tb, 260 .restore_state_to_opc = superh_restore_state_to_opc, 261 262 #ifndef CONFIG_USER_ONLY 263 .tlb_fill = superh_cpu_tlb_fill, 264 .cpu_exec_interrupt = superh_cpu_exec_interrupt, 265 .do_interrupt = superh_cpu_do_interrupt, 266 .do_unaligned_access = superh_cpu_do_unaligned_access, 267 .io_recompile_replay_branch = superh_io_recompile_replay_branch, 268 #endif /* !CONFIG_USER_ONLY */ 269 }; 270 271 static void superh_cpu_class_init(ObjectClass *oc, void *data) 272 { 273 DeviceClass *dc = DEVICE_CLASS(oc); 274 CPUClass *cc = CPU_CLASS(oc); 275 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 276 ResettableClass *rc = RESETTABLE_CLASS(oc); 277 278 device_class_set_parent_realize(dc, superh_cpu_realizefn, 279 &scc->parent_realize); 280 281 resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL, 282 &scc->parent_phases); 283 284 cc->class_by_name = superh_cpu_class_by_name; 285 cc->has_work = superh_cpu_has_work; 286 cc->dump_state = superh_cpu_dump_state; 287 cc->set_pc = superh_cpu_set_pc; 288 cc->get_pc = superh_cpu_get_pc; 289 cc->gdb_read_register = superh_cpu_gdb_read_register; 290 cc->gdb_write_register = superh_cpu_gdb_write_register; 291 #ifndef CONFIG_USER_ONLY 292 cc->sysemu_ops = &sh4_sysemu_ops; 293 dc->vmsd = &vmstate_sh_cpu; 294 #endif 295 cc->disas_set_info = superh_cpu_disas_set_info; 296 297 cc->gdb_num_core_regs = 59; 298 cc->tcg_ops = &superh_tcg_ops; 299 } 300 301 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ 302 { \ 303 .name = type_name, \ 304 .parent = TYPE_SUPERH_CPU, \ 305 .class_init = cinit, \ 306 .instance_init = initfn, \ 307 } 308 static const TypeInfo superh_cpu_type_infos[] = { 309 { 310 .name = TYPE_SUPERH_CPU, 311 .parent = TYPE_CPU, 312 .instance_size = sizeof(SuperHCPU), 313 .instance_align = __alignof(SuperHCPU), 314 .instance_init = superh_cpu_initfn, 315 .abstract = true, 316 .class_size = sizeof(SuperHCPUClass), 317 .class_init = superh_cpu_class_init, 318 }, 319 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init, 320 sh7750r_cpu_initfn), 321 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init, 322 sh7751r_cpu_initfn), 323 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init, 324 sh7785_cpu_initfn), 325 326 }; 327 328 DEFINE_TYPES(superh_cpu_type_infos) 329