1 /* 2 * SH4 emulation 3 * 4 * Copyright (c) 2005 Samuel Tardieu 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef SH4_CPU_H 21 #define SH4_CPU_H 22 23 #include "qemu-common.h" 24 #include "cpu-qom.h" 25 26 #define TARGET_LONG_BITS 32 27 #define ALIGNED_ONLY 28 29 /* CPU Subtypes */ 30 #define SH_CPU_SH7750 (1 << 0) 31 #define SH_CPU_SH7750S (1 << 1) 32 #define SH_CPU_SH7750R (1 << 2) 33 #define SH_CPU_SH7751 (1 << 3) 34 #define SH_CPU_SH7751R (1 << 4) 35 #define SH_CPU_SH7785 (1 << 5) 36 #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R) 37 #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R) 38 39 #define CPUArchState struct CPUSH4State 40 41 #include "exec/cpu-defs.h" 42 43 #include "fpu/softfloat.h" 44 45 #define TARGET_PAGE_BITS 12 /* 4k XXXXX */ 46 47 #define TARGET_PHYS_ADDR_SPACE_BITS 32 48 #define TARGET_VIRT_ADDR_SPACE_BITS 32 49 50 #define SR_MD 30 51 #define SR_RB 29 52 #define SR_BL 28 53 #define SR_FD 15 54 #define SR_M 9 55 #define SR_Q 8 56 #define SR_I3 7 57 #define SR_I2 6 58 #define SR_I1 5 59 #define SR_I0 4 60 #define SR_S 1 61 #define SR_T 0 62 63 #define FPSCR_MASK (0x003fffff) 64 #define FPSCR_FR (1 << 21) 65 #define FPSCR_SZ (1 << 20) 66 #define FPSCR_PR (1 << 19) 67 #define FPSCR_DN (1 << 18) 68 #define FPSCR_CAUSE_MASK (0x3f << 12) 69 #define FPSCR_CAUSE_SHIFT (12) 70 #define FPSCR_CAUSE_E (1 << 17) 71 #define FPSCR_CAUSE_V (1 << 16) 72 #define FPSCR_CAUSE_Z (1 << 15) 73 #define FPSCR_CAUSE_O (1 << 14) 74 #define FPSCR_CAUSE_U (1 << 13) 75 #define FPSCR_CAUSE_I (1 << 12) 76 #define FPSCR_ENABLE_MASK (0x1f << 7) 77 #define FPSCR_ENABLE_SHIFT (7) 78 #define FPSCR_ENABLE_V (1 << 11) 79 #define FPSCR_ENABLE_Z (1 << 10) 80 #define FPSCR_ENABLE_O (1 << 9) 81 #define FPSCR_ENABLE_U (1 << 8) 82 #define FPSCR_ENABLE_I (1 << 7) 83 #define FPSCR_FLAG_MASK (0x1f << 2) 84 #define FPSCR_FLAG_SHIFT (2) 85 #define FPSCR_FLAG_V (1 << 6) 86 #define FPSCR_FLAG_Z (1 << 5) 87 #define FPSCR_FLAG_O (1 << 4) 88 #define FPSCR_FLAG_U (1 << 3) 89 #define FPSCR_FLAG_I (1 << 2) 90 #define FPSCR_RM_MASK (0x03 << 0) 91 #define FPSCR_RM_NEAREST (0 << 0) 92 #define FPSCR_RM_ZERO (1 << 0) 93 94 #define DELAY_SLOT_MASK 0x7 95 #define DELAY_SLOT (1 << 0) 96 #define DELAY_SLOT_CONDITIONAL (1 << 1) 97 #define DELAY_SLOT_RTE (1 << 2) 98 99 #define TB_FLAG_PENDING_MOVCA (1 << 3) 100 101 #define GUSA_SHIFT 4 102 #ifdef CONFIG_USER_ONLY 103 #define GUSA_EXCLUSIVE (1 << 12) 104 #define GUSA_MASK ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE) 105 #else 106 /* Provide dummy versions of the above to allow tests against tbflags 107 to be elided while avoiding ifdefs. */ 108 #define GUSA_EXCLUSIVE 0 109 #define GUSA_MASK 0 110 #endif 111 112 #define TB_FLAG_ENVFLAGS_MASK (DELAY_SLOT_MASK | GUSA_MASK) 113 114 typedef struct tlb_t { 115 uint32_t vpn; /* virtual page number */ 116 uint32_t ppn; /* physical page number */ 117 uint32_t size; /* mapped page size in bytes */ 118 uint8_t asid; /* address space identifier */ 119 uint8_t v:1; /* validity */ 120 uint8_t sz:2; /* page size */ 121 uint8_t sh:1; /* share status */ 122 uint8_t c:1; /* cacheability */ 123 uint8_t pr:2; /* protection key */ 124 uint8_t d:1; /* dirty */ 125 uint8_t wt:1; /* write through */ 126 uint8_t sa:3; /* space attribute (PCMCIA) */ 127 uint8_t tc:1; /* timing control */ 128 } tlb_t; 129 130 #define UTLB_SIZE 64 131 #define ITLB_SIZE 4 132 133 #define NB_MMU_MODES 2 134 #define TARGET_INSN_START_EXTRA_WORDS 1 135 136 enum sh_features { 137 SH_FEATURE_SH4A = 1, 138 SH_FEATURE_BCR3_AND_BCR4 = 2, 139 }; 140 141 typedef struct memory_content { 142 uint32_t address; 143 uint32_t value; 144 struct memory_content *next; 145 } memory_content; 146 147 typedef struct CPUSH4State { 148 uint32_t flags; /* general execution flags */ 149 uint32_t gregs[24]; /* general registers */ 150 float32 fregs[32]; /* floating point registers */ 151 uint32_t sr; /* status register (with T split out) */ 152 uint32_t sr_m; /* M bit of status register */ 153 uint32_t sr_q; /* Q bit of status register */ 154 uint32_t sr_t; /* T bit of status register */ 155 uint32_t ssr; /* saved status register */ 156 uint32_t spc; /* saved program counter */ 157 uint32_t gbr; /* global base register */ 158 uint32_t vbr; /* vector base register */ 159 uint32_t sgr; /* saved global register 15 */ 160 uint32_t dbr; /* debug base register */ 161 uint32_t pc; /* program counter */ 162 uint32_t delayed_pc; /* target of delayed branch */ 163 uint32_t delayed_cond; /* condition of delayed branch */ 164 uint32_t mach; /* multiply and accumulate high */ 165 uint32_t macl; /* multiply and accumulate low */ 166 uint32_t pr; /* procedure register */ 167 uint32_t fpscr; /* floating point status/control register */ 168 uint32_t fpul; /* floating point communication register */ 169 170 /* float point status register */ 171 float_status fp_status; 172 173 /* Those belong to the specific unit (SH7750) but are handled here */ 174 uint32_t mmucr; /* MMU control register */ 175 uint32_t pteh; /* page table entry high register */ 176 uint32_t ptel; /* page table entry low register */ 177 uint32_t ptea; /* page table entry assistance register */ 178 uint32_t ttb; /* tranlation table base register */ 179 uint32_t tea; /* TLB exception address register */ 180 uint32_t tra; /* TRAPA exception register */ 181 uint32_t expevt; /* exception event register */ 182 uint32_t intevt; /* interrupt event register */ 183 184 tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ 185 tlb_t utlb[UTLB_SIZE]; /* unified translation table */ 186 187 uint32_t ldst; 188 189 /* Fields up to this point are cleared by a CPU reset */ 190 struct {} end_reset_fields; 191 192 CPU_COMMON 193 194 /* Fields from here on are preserved over CPU reset. */ 195 int id; /* CPU model */ 196 197 /* The features that we should emulate. See sh_features above. */ 198 uint32_t features; 199 200 void *intc_handle; 201 int in_sleep; /* SR_BL ignored during sleep */ 202 memory_content *movcal_backup; 203 memory_content **movcal_backup_tail; 204 } CPUSH4State; 205 206 /** 207 * SuperHCPU: 208 * @env: #CPUSH4State 209 * 210 * A SuperH CPU. 211 */ 212 struct SuperHCPU { 213 /*< private >*/ 214 CPUState parent_obj; 215 /*< public >*/ 216 217 CPUSH4State env; 218 }; 219 220 static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env) 221 { 222 return container_of(env, SuperHCPU, env); 223 } 224 225 #define ENV_GET_CPU(e) CPU(sh_env_get_cpu(e)) 226 227 #define ENV_OFFSET offsetof(SuperHCPU, env) 228 229 void superh_cpu_do_interrupt(CPUState *cpu); 230 bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); 231 void superh_cpu_dump_state(CPUState *cpu, FILE *f, 232 fprintf_function cpu_fprintf, int flags); 233 hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 234 int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 235 int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 236 void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 237 MMUAccessType access_type, 238 int mmu_idx, uintptr_t retaddr); 239 240 void sh4_translate_init(void); 241 SuperHCPU *cpu_sh4_init(const char *cpu_model); 242 int cpu_sh4_signal_handler(int host_signum, void *pinfo, 243 void *puc); 244 int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, 245 int mmu_idx); 246 247 void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf); 248 #if !defined(CONFIG_USER_ONLY) 249 void cpu_sh4_invalidate_tlb(CPUSH4State *s); 250 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, 251 hwaddr addr); 252 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr, 253 uint32_t mem_value); 254 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s, 255 hwaddr addr); 256 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr, 257 uint32_t mem_value); 258 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s, 259 hwaddr addr); 260 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, 261 uint32_t mem_value); 262 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, 263 hwaddr addr); 264 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, 265 uint32_t mem_value); 266 #endif 267 268 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr); 269 270 void cpu_load_tlb(CPUSH4State * env); 271 272 #define cpu_init(cpu_model) CPU(cpu_sh4_init(cpu_model)) 273 274 #define cpu_signal_handler cpu_sh4_signal_handler 275 #define cpu_list sh4_cpu_list 276 277 /* MMU modes definitions */ 278 #define MMU_MODE0_SUFFIX _kernel 279 #define MMU_MODE1_SUFFIX _user 280 #define MMU_USER_IDX 1 281 static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch) 282 { 283 /* The instruction in a RTE delay slot is fetched in privileged 284 mode, but executed in user mode. */ 285 if (ifetch && (env->flags & DELAY_SLOT_RTE)) { 286 return 0; 287 } else { 288 return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0; 289 } 290 } 291 292 #include "exec/cpu-all.h" 293 294 /* Memory access type */ 295 enum { 296 /* Privilege */ 297 ACCESS_PRIV = 0x01, 298 /* Direction */ 299 ACCESS_WRITE = 0x02, 300 /* Type of instruction */ 301 ACCESS_CODE = 0x10, 302 ACCESS_INT = 0x20 303 }; 304 305 /* MMU control register */ 306 #define MMUCR 0x1F000010 307 #define MMUCR_AT (1<<0) 308 #define MMUCR_TI (1<<2) 309 #define MMUCR_SV (1<<8) 310 #define MMUCR_URC_BITS (6) 311 #define MMUCR_URC_OFFSET (10) 312 #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS) 313 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET) 314 static inline int cpu_mmucr_urc (uint32_t mmucr) 315 { 316 return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET); 317 } 318 319 /* PTEH : Page Translation Entry High register */ 320 #define PTEH_ASID_BITS (8) 321 #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS) 322 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1) 323 #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK) 324 #define PTEH_VPN_BITS (22) 325 #define PTEH_VPN_OFFSET (10) 326 #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS) 327 #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET) 328 static inline int cpu_pteh_vpn (uint32_t pteh) 329 { 330 return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET); 331 } 332 333 /* PTEL : Page Translation Entry Low register */ 334 #define PTEL_V (1 << 8) 335 #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8) 336 #define PTEL_C (1 << 3) 337 #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3) 338 #define PTEL_D (1 << 2) 339 #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2) 340 #define PTEL_SH (1 << 1) 341 #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1) 342 #define PTEL_WT (1 << 0) 343 #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT) 344 345 #define PTEL_SZ_HIGH_OFFSET (7) 346 #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET) 347 #define PTEL_SZ_LOW_OFFSET (4) 348 #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET) 349 static inline int cpu_ptel_sz (uint32_t ptel) 350 { 351 int sz; 352 sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET; 353 sz <<= 1; 354 sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET; 355 return sz; 356 } 357 358 #define PTEL_PPN_BITS (19) 359 #define PTEL_PPN_OFFSET (10) 360 #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS) 361 #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET) 362 static inline int cpu_ptel_ppn (uint32_t ptel) 363 { 364 return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET); 365 } 366 367 #define PTEL_PR_BITS (2) 368 #define PTEL_PR_OFFSET (5) 369 #define PTEL_PR_SIZE (1 << PTEL_PR_BITS) 370 #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET) 371 static inline int cpu_ptel_pr (uint32_t ptel) 372 { 373 return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET); 374 } 375 376 /* PTEA : Page Translation Entry Assistance register */ 377 #define PTEA_SA_BITS (3) 378 #define PTEA_SA_SIZE (1 << PTEA_SA_BITS) 379 #define PTEA_SA_MASK (PTEA_SA_SIZE - 1) 380 #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK) 381 #define PTEA_TC (1 << 3) 382 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3) 383 384 static inline target_ulong cpu_read_sr(CPUSH4State *env) 385 { 386 return env->sr | (env->sr_m << SR_M) | 387 (env->sr_q << SR_Q) | 388 (env->sr_t << SR_T); 389 } 390 391 static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr) 392 { 393 env->sr_m = (sr >> SR_M) & 1; 394 env->sr_q = (sr >> SR_Q) & 1; 395 env->sr_t = (sr >> SR_T) & 1; 396 env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); 397 } 398 399 static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, 400 target_ulong *cs_base, uint32_t *flags) 401 { 402 *pc = env->pc; 403 /* For a gUSA region, notice the end of the region. */ 404 *cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0; 405 *flags = env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */ 406 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */ 407 | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */ 408 | (env->sr & (1u << SR_FD)) /* Bit 15 */ 409 | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ 410 } 411 412 #endif /* SH4_CPU_H */ 413