1 #ifndef SPARC_CPU_H 2 #define SPARC_CPU_H 3 4 #include "qemu-common.h" 5 #include "qemu/bswap.h" 6 #include "cpu-qom.h" 7 8 #define ALIGNED_ONLY 9 10 #if !defined(TARGET_SPARC64) 11 #define TARGET_LONG_BITS 32 12 #define TARGET_DPREGS 16 13 #define TARGET_PAGE_BITS 12 /* 4k */ 14 #define TARGET_PHYS_ADDR_SPACE_BITS 36 15 #define TARGET_VIRT_ADDR_SPACE_BITS 32 16 #else 17 #define TARGET_LONG_BITS 64 18 #define TARGET_DPREGS 32 19 #define TARGET_PAGE_BITS 13 /* 8k */ 20 #define TARGET_PHYS_ADDR_SPACE_BITS 41 21 # ifdef TARGET_ABI32 22 # define TARGET_VIRT_ADDR_SPACE_BITS 32 23 # else 24 # define TARGET_VIRT_ADDR_SPACE_BITS 44 25 # endif 26 #endif 27 28 #define CPUArchState struct CPUSPARCState 29 30 #include "exec/cpu-defs.h" 31 32 #include "fpu/softfloat.h" 33 34 /*#define EXCP_INTERRUPT 0x100*/ 35 36 /* trap definitions */ 37 #ifndef TARGET_SPARC64 38 #define TT_TFAULT 0x01 39 #define TT_ILL_INSN 0x02 40 #define TT_PRIV_INSN 0x03 41 #define TT_NFPU_INSN 0x04 42 #define TT_WIN_OVF 0x05 43 #define TT_WIN_UNF 0x06 44 #define TT_UNALIGNED 0x07 45 #define TT_FP_EXCP 0x08 46 #define TT_DFAULT 0x09 47 #define TT_TOVF 0x0a 48 #define TT_EXTINT 0x10 49 #define TT_CODE_ACCESS 0x21 50 #define TT_UNIMP_FLUSH 0x25 51 #define TT_DATA_ACCESS 0x29 52 #define TT_DIV_ZERO 0x2a 53 #define TT_NCP_INSN 0x24 54 #define TT_TRAP 0x80 55 #else 56 #define TT_POWER_ON_RESET 0x01 57 #define TT_TFAULT 0x08 58 #define TT_CODE_ACCESS 0x0a 59 #define TT_ILL_INSN 0x10 60 #define TT_UNIMP_FLUSH TT_ILL_INSN 61 #define TT_PRIV_INSN 0x11 62 #define TT_NFPU_INSN 0x20 63 #define TT_FP_EXCP 0x21 64 #define TT_TOVF 0x23 65 #define TT_CLRWIN 0x24 66 #define TT_DIV_ZERO 0x28 67 #define TT_DFAULT 0x30 68 #define TT_DATA_ACCESS 0x32 69 #define TT_UNALIGNED 0x34 70 #define TT_PRIV_ACT 0x37 71 #define TT_INSN_REAL_TRANSLATION_MISS 0x3e 72 #define TT_DATA_REAL_TRANSLATION_MISS 0x3f 73 #define TT_EXTINT 0x40 74 #define TT_IVEC 0x60 75 #define TT_TMISS 0x64 76 #define TT_DMISS 0x68 77 #define TT_DPROT 0x6c 78 #define TT_SPILL 0x80 79 #define TT_FILL 0xc0 80 #define TT_WOTHER (1 << 5) 81 #define TT_TRAP 0x100 82 #define TT_HTRAP 0x180 83 #endif 84 85 #define PSR_NEG_SHIFT 23 86 #define PSR_NEG (1 << PSR_NEG_SHIFT) 87 #define PSR_ZERO_SHIFT 22 88 #define PSR_ZERO (1 << PSR_ZERO_SHIFT) 89 #define PSR_OVF_SHIFT 21 90 #define PSR_OVF (1 << PSR_OVF_SHIFT) 91 #define PSR_CARRY_SHIFT 20 92 #define PSR_CARRY (1 << PSR_CARRY_SHIFT) 93 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) 94 #if !defined(TARGET_SPARC64) 95 #define PSR_EF (1<<12) 96 #define PSR_PIL 0xf00 97 #define PSR_S (1<<7) 98 #define PSR_PS (1<<6) 99 #define PSR_ET (1<<5) 100 #define PSR_CWP 0x1f 101 #endif 102 103 #define CC_SRC (env->cc_src) 104 #define CC_SRC2 (env->cc_src2) 105 #define CC_DST (env->cc_dst) 106 #define CC_OP (env->cc_op) 107 108 /* Even though lazy evaluation of CPU condition codes tends to be less 109 * important on RISC systems where condition codes are only updated 110 * when explicitly requested, SPARC uses it to update 32-bit and 64-bit 111 * condition codes. 112 */ 113 enum { 114 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 115 CC_OP_FLAGS, /* all cc are back in status register */ 116 CC_OP_DIV, /* modify N, Z and V, C = 0*/ 117 CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 118 CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 119 CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 120 CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */ 121 CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 122 CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 123 CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 124 CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */ 125 CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */ 126 CC_OP_NB, 127 }; 128 129 /* Trap base register */ 130 #define TBR_BASE_MASK 0xfffff000 131 132 #if defined(TARGET_SPARC64) 133 #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ 134 #define PS_IG (1<<11) /* v9, zero on UA2007 */ 135 #define PS_MG (1<<10) /* v9, zero on UA2007 */ 136 #define PS_CLE (1<<9) /* UA2007 */ 137 #define PS_TLE (1<<8) /* UA2007 */ 138 #define PS_RMO (1<<7) 139 #define PS_RED (1<<5) /* v9, zero on UA2007 */ 140 #define PS_PEF (1<<4) /* enable fpu */ 141 #define PS_AM (1<<3) /* address mask */ 142 #define PS_PRIV (1<<2) 143 #define PS_IE (1<<1) 144 #define PS_AG (1<<0) /* v9, zero on UA2007 */ 145 146 #define FPRS_FEF (1<<2) 147 148 #define HS_PRIV (1<<2) 149 #endif 150 151 /* Fcc */ 152 #define FSR_RD1 (1ULL << 31) 153 #define FSR_RD0 (1ULL << 30) 154 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) 155 #define FSR_RD_NEAREST 0 156 #define FSR_RD_ZERO FSR_RD0 157 #define FSR_RD_POS FSR_RD1 158 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) 159 160 #define FSR_NVM (1ULL << 27) 161 #define FSR_OFM (1ULL << 26) 162 #define FSR_UFM (1ULL << 25) 163 #define FSR_DZM (1ULL << 24) 164 #define FSR_NXM (1ULL << 23) 165 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) 166 167 #define FSR_NVA (1ULL << 9) 168 #define FSR_OFA (1ULL << 8) 169 #define FSR_UFA (1ULL << 7) 170 #define FSR_DZA (1ULL << 6) 171 #define FSR_NXA (1ULL << 5) 172 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 173 174 #define FSR_NVC (1ULL << 4) 175 #define FSR_OFC (1ULL << 3) 176 #define FSR_UFC (1ULL << 2) 177 #define FSR_DZC (1ULL << 1) 178 #define FSR_NXC (1ULL << 0) 179 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) 180 181 #define FSR_FTT2 (1ULL << 16) 182 #define FSR_FTT1 (1ULL << 15) 183 #define FSR_FTT0 (1ULL << 14) 184 //gcc warns about constant overflow for ~FSR_FTT_MASK 185 //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) 186 #ifdef TARGET_SPARC64 187 #define FSR_FTT_NMASK 0xfffffffffffe3fffULL 188 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL 189 #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL 190 #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL 191 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL 192 #else 193 #define FSR_FTT_NMASK 0xfffe3fffULL 194 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL 195 #define FSR_LDFSR_OLDMASK 0x000fc000ULL 196 #endif 197 #define FSR_LDFSR_MASK 0xcfc00fffULL 198 #define FSR_FTT_IEEE_EXCP (1ULL << 14) 199 #define FSR_FTT_UNIMPFPOP (3ULL << 14) 200 #define FSR_FTT_SEQ_ERROR (4ULL << 14) 201 #define FSR_FTT_INVAL_FPR (6ULL << 14) 202 203 #define FSR_FCC1_SHIFT 11 204 #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) 205 #define FSR_FCC0_SHIFT 10 206 #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) 207 208 /* MMU */ 209 #define MMU_E (1<<0) 210 #define MMU_NF (1<<1) 211 212 #define PTE_ENTRYTYPE_MASK 3 213 #define PTE_ACCESS_MASK 0x1c 214 #define PTE_ACCESS_SHIFT 2 215 #define PTE_PPN_SHIFT 7 216 #define PTE_ADDR_MASK 0xffffff00 217 218 #define PG_ACCESSED_BIT 5 219 #define PG_MODIFIED_BIT 6 220 #define PG_CACHE_BIT 7 221 222 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 223 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) 224 #define PG_CACHE_MASK (1 << PG_CACHE_BIT) 225 226 /* 3 <= NWINDOWS <= 32. */ 227 #define MIN_NWINDOWS 3 228 #define MAX_NWINDOWS 32 229 230 #if !defined(TARGET_SPARC64) 231 #define NB_MMU_MODES 3 232 #else 233 #define NB_MMU_MODES 6 234 typedef struct trap_state { 235 uint64_t tpc; 236 uint64_t tnpc; 237 uint64_t tstate; 238 uint32_t tt; 239 } trap_state; 240 #endif 241 #define TARGET_INSN_START_EXTRA_WORDS 1 242 243 struct sparc_def_t { 244 const char *name; 245 target_ulong iu_version; 246 uint32_t fpu_version; 247 uint32_t mmu_version; 248 uint32_t mmu_bm; 249 uint32_t mmu_ctpr_mask; 250 uint32_t mmu_cxr_mask; 251 uint32_t mmu_sfsr_mask; 252 uint32_t mmu_trcr_mask; 253 uint32_t mxcc_version; 254 uint32_t features; 255 uint32_t nwindows; 256 uint32_t maxtl; 257 }; 258 259 #define CPU_FEATURE_FLOAT (1 << 0) 260 #define CPU_FEATURE_FLOAT128 (1 << 1) 261 #define CPU_FEATURE_SWAP (1 << 2) 262 #define CPU_FEATURE_MUL (1 << 3) 263 #define CPU_FEATURE_DIV (1 << 4) 264 #define CPU_FEATURE_FLUSH (1 << 5) 265 #define CPU_FEATURE_FSQRT (1 << 6) 266 #define CPU_FEATURE_FMUL (1 << 7) 267 #define CPU_FEATURE_VIS1 (1 << 8) 268 #define CPU_FEATURE_VIS2 (1 << 9) 269 #define CPU_FEATURE_FSMULD (1 << 10) 270 #define CPU_FEATURE_HYPV (1 << 11) 271 #define CPU_FEATURE_CMT (1 << 12) 272 #define CPU_FEATURE_GL (1 << 13) 273 #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */ 274 #define CPU_FEATURE_ASR17 (1 << 15) 275 #define CPU_FEATURE_CACHE_CTRL (1 << 16) 276 #define CPU_FEATURE_POWERDOWN (1 << 17) 277 #define CPU_FEATURE_CASA (1 << 18) 278 279 #ifndef TARGET_SPARC64 280 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ 281 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 282 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ 283 CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) 284 #else 285 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ 286 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 287 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ 288 CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ 289 CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \ 290 CPU_FEATURE_CASA) 291 enum { 292 mmu_us_12, // Ultrasparc < III (64 entry TLB) 293 mmu_us_3, // Ultrasparc III (512 entry TLB) 294 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) 295 mmu_sun4v, // T1, T2 296 }; 297 #endif 298 299 #define TTE_VALID_BIT (1ULL << 63) 300 #define TTE_NFO_BIT (1ULL << 60) 301 #define TTE_USED_BIT (1ULL << 41) 302 #define TTE_LOCKED_BIT (1ULL << 6) 303 #define TTE_SIDEEFFECT_BIT (1ULL << 3) 304 #define TTE_PRIV_BIT (1ULL << 2) 305 #define TTE_W_OK_BIT (1ULL << 1) 306 #define TTE_GLOBAL_BIT (1ULL << 0) 307 308 #define TTE_NFO_BIT_UA2005 (1ULL << 62) 309 #define TTE_USED_BIT_UA2005 (1ULL << 47) 310 #define TTE_LOCKED_BIT_UA2005 (1ULL << 61) 311 #define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11) 312 #define TTE_PRIV_BIT_UA2005 (1ULL << 8) 313 #define TTE_W_OK_BIT_UA2005 (1ULL << 6) 314 315 #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) 316 #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) 317 #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) 318 #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) 319 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) 320 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 321 #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) 322 #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) 323 324 #define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005) 325 #define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005) 326 #define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005) 327 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 328 #define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005) 329 #define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005) 330 331 #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) 332 333 #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) 334 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) 335 336 #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) 337 #define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) 338 #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) 339 340 /* UltraSPARC T1 specific */ 341 #define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */ 342 #define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */ 343 344 #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ 345 #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ 346 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ 347 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */ 348 #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */ 349 #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */ 350 #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */ 351 #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */ 352 #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */ 353 #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */ 354 #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */ 355 #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */ 356 #define SFSR_VALID_BIT (1ULL << 0) /* status valid */ 357 358 #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */ 359 #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT) 360 #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */ 361 #define SFSR_CT_SECONDARY (1ULL << 4) 362 #define SFSR_CT_NUCLEUS (2ULL << 4) 363 #define SFSR_CT_NOTRANS (3ULL << 4) 364 #define SFSR_CT_MASK (3ULL << 4) 365 366 /* Leon3 cache control */ 367 368 /* Cache control: emulate the behavior of cache control registers but without 369 any effect on the emulated */ 370 371 #define CACHE_STATE_MASK 0x3 372 #define CACHE_DISABLED 0x0 373 #define CACHE_FROZEN 0x1 374 #define CACHE_ENABLED 0x3 375 376 /* Cache Control register fields */ 377 378 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ 379 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ 380 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ 381 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ 382 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ 383 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ 384 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ 385 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ 386 387 #define CONVERT_BIT(X, SRC, DST) \ 388 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) 389 390 typedef struct SparcTLBEntry { 391 uint64_t tag; 392 uint64_t tte; 393 } SparcTLBEntry; 394 395 struct CPUTimer 396 { 397 const char *name; 398 uint32_t frequency; 399 uint32_t disabled; 400 uint64_t disabled_mask; 401 uint32_t npt; 402 uint64_t npt_mask; 403 int64_t clock_offset; 404 QEMUTimer *qtimer; 405 }; 406 407 typedef struct CPUTimer CPUTimer; 408 409 typedef struct CPUSPARCState CPUSPARCState; 410 #if defined(TARGET_SPARC64) 411 typedef union { 412 uint64_t mmuregs[16]; 413 struct { 414 uint64_t tsb_tag_target; 415 uint64_t mmu_primary_context; 416 uint64_t mmu_secondary_context; 417 uint64_t sfsr; 418 uint64_t sfar; 419 uint64_t tsb; 420 uint64_t tag_access; 421 uint64_t virtual_watchpoint; 422 uint64_t physical_watchpoint; 423 uint64_t sun4v_ctx_config[2]; 424 uint64_t sun4v_tsb_pointers[4]; 425 }; 426 } SparcV9MMU; 427 #endif 428 struct CPUSPARCState { 429 target_ulong gregs[8]; /* general registers */ 430 target_ulong *regwptr; /* pointer to current register window */ 431 target_ulong pc; /* program counter */ 432 target_ulong npc; /* next program counter */ 433 target_ulong y; /* multiply/divide register */ 434 435 /* emulator internal flags handling */ 436 target_ulong cc_src, cc_src2; 437 target_ulong cc_dst; 438 uint32_t cc_op; 439 440 target_ulong cond; /* conditional branch result (XXX: save it in a 441 temporary register when possible) */ 442 443 uint32_t psr; /* processor state register */ 444 target_ulong fsr; /* FPU state register */ 445 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ 446 uint32_t cwp; /* index of current register window (extracted 447 from PSR) */ 448 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) 449 uint32_t wim; /* window invalid mask */ 450 #endif 451 target_ulong tbr; /* trap base register */ 452 #if !defined(TARGET_SPARC64) 453 int psrs; /* supervisor mode (extracted from PSR) */ 454 int psrps; /* previous supervisor mode */ 455 int psret; /* enable traps */ 456 #endif 457 uint32_t psrpil; /* interrupt blocking level */ 458 uint32_t pil_in; /* incoming interrupt level bitmap */ 459 #if !defined(TARGET_SPARC64) 460 int psref; /* enable fpu */ 461 #endif 462 int interrupt_index; 463 /* NOTE: we allow 8 more registers to handle wrapping */ 464 target_ulong regbase[MAX_NWINDOWS * 16 + 8]; 465 466 /* Fields up to this point are cleared by a CPU reset */ 467 struct {} end_reset_fields; 468 469 CPU_COMMON 470 471 /* Fields from here on are preserved across CPU reset. */ 472 target_ulong version; 473 uint32_t nwindows; 474 475 /* MMU regs */ 476 #if defined(TARGET_SPARC64) 477 uint64_t lsu; 478 #define DMMU_E 0x8 479 #define IMMU_E 0x4 480 SparcV9MMU immu; 481 SparcV9MMU dmmu; 482 SparcTLBEntry itlb[64]; 483 SparcTLBEntry dtlb[64]; 484 uint32_t mmu_version; 485 #else 486 uint32_t mmuregs[32]; 487 uint64_t mxccdata[4]; 488 uint64_t mxccregs[8]; 489 uint32_t mmubpctrv, mmubpctrc, mmubpctrs; 490 uint64_t mmubpaction; 491 uint64_t mmubpregs[4]; 492 uint64_t prom_addr; 493 #endif 494 /* temporary float registers */ 495 float128 qt0, qt1; 496 float_status fp_status; 497 #if defined(TARGET_SPARC64) 498 #define MAXTL_MAX 8 499 #define MAXTL_MASK (MAXTL_MAX - 1) 500 trap_state ts[MAXTL_MAX]; 501 uint32_t xcc; /* Extended integer condition codes */ 502 uint32_t asi; 503 uint32_t pstate; 504 uint32_t tl; 505 uint32_t maxtl; 506 uint32_t cansave, canrestore, otherwin, wstate, cleanwin; 507 uint64_t agregs[8]; /* alternate general registers */ 508 uint64_t bgregs[8]; /* backup for normal global registers */ 509 uint64_t igregs[8]; /* interrupt general registers */ 510 uint64_t mgregs[8]; /* mmu general registers */ 511 uint64_t glregs[8 * MAXTL_MAX]; 512 uint64_t fprs; 513 uint64_t tick_cmpr, stick_cmpr; 514 CPUTimer *tick, *stick; 515 #define TICK_NPT_MASK 0x8000000000000000ULL 516 #define TICK_INT_DIS 0x8000000000000000ULL 517 uint64_t gsr; 518 uint32_t gl; // UA2005 519 /* UA 2005 hyperprivileged registers */ 520 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; 521 uint64_t scratch[8]; 522 CPUTimer *hstick; // UA 2005 523 /* Interrupt vector registers */ 524 uint64_t ivec_status; 525 uint64_t ivec_data[3]; 526 uint32_t softint; 527 #define SOFTINT_TIMER 1 528 #define SOFTINT_STIMER (1 << 16) 529 #define SOFTINT_INTRMASK (0xFFFE) 530 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) 531 #endif 532 sparc_def_t def; 533 534 void *irq_manager; 535 void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno); 536 537 /* Leon3 cache control */ 538 uint32_t cache_control; 539 }; 540 541 /** 542 * SPARCCPU: 543 * @env: #CPUSPARCState 544 * 545 * A SPARC CPU. 546 */ 547 struct SPARCCPU { 548 /*< private >*/ 549 CPUState parent_obj; 550 /*< public >*/ 551 552 CPUSPARCState env; 553 }; 554 555 static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env) 556 { 557 return container_of(env, SPARCCPU, env); 558 } 559 560 #define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e)) 561 562 #define ENV_OFFSET offsetof(SPARCCPU, env) 563 564 #ifndef CONFIG_USER_ONLY 565 extern const struct VMStateDescription vmstate_sparc_cpu; 566 #endif 567 568 void sparc_cpu_do_interrupt(CPUState *cpu); 569 void sparc_cpu_dump_state(CPUState *cpu, FILE *f, 570 fprintf_function cpu_fprintf, int flags); 571 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 572 int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 573 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 574 void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 575 MMUAccessType access_type, 576 int mmu_idx, 577 uintptr_t retaddr); 578 void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN; 579 580 #ifndef NO_CPU_IO_DEFS 581 /* cpu_init.c */ 582 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); 583 void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf); 584 /* mmu_helper.c */ 585 int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, 586 int mmu_idx); 587 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); 588 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env); 589 590 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 591 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 592 uint8_t *buf, int len, bool is_write); 593 #endif 594 595 596 /* translate.c */ 597 void gen_intermediate_code_init(CPUSPARCState *env); 598 599 /* cpu-exec.c */ 600 601 /* win_helper.c */ 602 target_ulong cpu_get_psr(CPUSPARCState *env1); 603 void cpu_put_psr(CPUSPARCState *env1, target_ulong val); 604 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); 605 #ifdef TARGET_SPARC64 606 target_ulong cpu_get_ccr(CPUSPARCState *env1); 607 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); 608 target_ulong cpu_get_cwp64(CPUSPARCState *env1); 609 void cpu_put_cwp64(CPUSPARCState *env1, int cwp); 610 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); 611 void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl); 612 #endif 613 int cpu_cwp_inc(CPUSPARCState *env1, int cwp); 614 int cpu_cwp_dec(CPUSPARCState *env1, int cwp); 615 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); 616 617 /* int_helper.c */ 618 void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno); 619 620 /* sun4m.c, sun4u.c */ 621 void cpu_check_irqs(CPUSPARCState *env); 622 623 /* leon3.c */ 624 void leon3_irq_ack(void *irq_manager, int intno); 625 626 #if defined (TARGET_SPARC64) 627 628 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) 629 { 630 return (x & mask) == (y & mask); 631 } 632 633 #define MMU_CONTEXT_BITS 13 634 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) 635 636 static inline int tlb_compare_context(const SparcTLBEntry *tlb, 637 uint64_t context) 638 { 639 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); 640 } 641 642 #endif 643 #endif 644 645 /* cpu-exec.c */ 646 #if !defined(CONFIG_USER_ONLY) 647 void sparc_cpu_unassigned_access(CPUState *cpu, hwaddr addr, 648 bool is_write, bool is_exec, int is_asi, 649 unsigned size); 650 #if defined(TARGET_SPARC64) 651 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, 652 int mmu_idx); 653 #endif 654 #endif 655 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); 656 657 #ifndef NO_CPU_IO_DEFS 658 #define cpu_init(cpu_model) cpu_generic_init(TYPE_SPARC_CPU, cpu_model) 659 #endif 660 661 #define cpu_signal_handler cpu_sparc_signal_handler 662 #define cpu_list sparc_cpu_list 663 664 /* MMU modes definitions */ 665 #if defined (TARGET_SPARC64) 666 #define MMU_USER_IDX 0 667 #define MMU_USER_SECONDARY_IDX 1 668 #define MMU_KERNEL_IDX 2 669 #define MMU_KERNEL_SECONDARY_IDX 3 670 #define MMU_NUCLEUS_IDX 4 671 #define MMU_PHYS_IDX 5 672 #else 673 #define MMU_USER_IDX 0 674 #define MMU_KERNEL_IDX 1 675 #define MMU_PHYS_IDX 2 676 #endif 677 678 #if defined (TARGET_SPARC64) 679 static inline int cpu_has_hypervisor(CPUSPARCState *env1) 680 { 681 return env1->def.features & CPU_FEATURE_HYPV; 682 } 683 684 static inline int cpu_hypervisor_mode(CPUSPARCState *env1) 685 { 686 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); 687 } 688 689 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 690 { 691 return env1->pstate & PS_PRIV; 692 } 693 #else 694 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 695 { 696 return env1->psrs; 697 } 698 #endif 699 700 static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) 701 { 702 #if defined(CONFIG_USER_ONLY) 703 return MMU_USER_IDX; 704 #elif !defined(TARGET_SPARC64) 705 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ 706 return MMU_PHYS_IDX; 707 } else { 708 return env->psrs; 709 } 710 #else 711 /* IMMU or DMMU disabled. */ 712 if (ifetch 713 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 714 : (env->lsu & DMMU_E) == 0) { 715 return MMU_PHYS_IDX; 716 } else if (cpu_hypervisor_mode(env)) { 717 return MMU_PHYS_IDX; 718 } else if (env->tl > 0) { 719 return MMU_NUCLEUS_IDX; 720 } else if (cpu_supervisor_mode(env)) { 721 return MMU_KERNEL_IDX; 722 } else { 723 return MMU_USER_IDX; 724 } 725 #endif 726 } 727 728 static inline int cpu_interrupts_enabled(CPUSPARCState *env1) 729 { 730 #if !defined (TARGET_SPARC64) 731 if (env1->psret != 0) 732 return 1; 733 #else 734 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) { 735 return 1; 736 } 737 #endif 738 739 return 0; 740 } 741 742 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) 743 { 744 #if !defined(TARGET_SPARC64) 745 /* level 15 is non-maskable on sparc v8 */ 746 return pil == 15 || pil > env1->psrpil; 747 #else 748 return pil > env1->psrpil; 749 #endif 750 } 751 752 #include "exec/cpu-all.h" 753 754 #ifdef TARGET_SPARC64 755 /* sun4u.c */ 756 void cpu_tick_set_count(CPUTimer *timer, uint64_t count); 757 uint64_t cpu_tick_get_count(CPUTimer *timer); 758 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); 759 trap_state* cpu_tsptr(CPUSPARCState* env); 760 #endif 761 762 #define TB_FLAG_MMU_MASK 7 763 #define TB_FLAG_FPU_ENABLED (1 << 4) 764 #define TB_FLAG_AM_ENABLED (1 << 5) 765 #define TB_FLAG_SUPER (1 << 6) 766 #define TB_FLAG_HYPER (1 << 7) 767 #define TB_FLAG_ASI_SHIFT 24 768 769 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, 770 target_ulong *cs_base, uint32_t *pflags) 771 { 772 uint32_t flags; 773 *pc = env->pc; 774 *cs_base = env->npc; 775 flags = cpu_mmu_index(env, false); 776 #ifndef CONFIG_USER_ONLY 777 if (cpu_supervisor_mode(env)) { 778 flags |= TB_FLAG_SUPER; 779 } 780 #endif 781 #ifdef TARGET_SPARC64 782 #ifndef CONFIG_USER_ONLY 783 if (cpu_hypervisor_mode(env)) { 784 flags |= TB_FLAG_HYPER; 785 } 786 #endif 787 if (env->pstate & PS_AM) { 788 flags |= TB_FLAG_AM_ENABLED; 789 } 790 if ((env->def.features & CPU_FEATURE_FLOAT) 791 && (env->pstate & PS_PEF) 792 && (env->fprs & FPRS_FEF)) { 793 flags |= TB_FLAG_FPU_ENABLED; 794 } 795 flags |= env->asi << TB_FLAG_ASI_SHIFT; 796 #else 797 if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) { 798 flags |= TB_FLAG_FPU_ENABLED; 799 } 800 #endif 801 *pflags = flags; 802 } 803 804 static inline bool tb_fpu_enabled(int tb_flags) 805 { 806 #if defined(CONFIG_USER_ONLY) 807 return true; 808 #else 809 return tb_flags & TB_FLAG_FPU_ENABLED; 810 #endif 811 } 812 813 static inline bool tb_am_enabled(int tb_flags) 814 { 815 #ifndef TARGET_SPARC64 816 return false; 817 #else 818 return tb_flags & TB_FLAG_AM_ENABLED; 819 #endif 820 } 821 822 #endif 823