1 /* 2 * Sparc64 interrupt helpers 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/helper-proto.h" 23 #include "exec/log.h" 24 #include "trace.h" 25 26 #define DEBUG_PCALL 27 28 #ifdef DEBUG_PCALL 29 static const char * const excp_names[0x80] = { 30 [TT_TFAULT] = "Instruction Access Fault", 31 [TT_TMISS] = "Instruction Access MMU Miss", 32 [TT_CODE_ACCESS] = "Instruction Access Error", 33 [TT_ILL_INSN] = "Illegal Instruction", 34 [TT_PRIV_INSN] = "Privileged Instruction", 35 [TT_NFPU_INSN] = "FPU Disabled", 36 [TT_FP_EXCP] = "FPU Exception", 37 [TT_TOVF] = "Tag Overflow", 38 [TT_CLRWIN] = "Clean Windows", 39 [TT_DIV_ZERO] = "Division By Zero", 40 [TT_DFAULT] = "Data Access Fault", 41 [TT_DMISS] = "Data Access MMU Miss", 42 [TT_DATA_ACCESS] = "Data Access Error", 43 [TT_DPROT] = "Data Protection Error", 44 [TT_UNALIGNED] = "Unaligned Memory Access", 45 [TT_PRIV_ACT] = "Privileged Action", 46 [TT_EXTINT | 0x1] = "External Interrupt 1", 47 [TT_EXTINT | 0x2] = "External Interrupt 2", 48 [TT_EXTINT | 0x3] = "External Interrupt 3", 49 [TT_EXTINT | 0x4] = "External Interrupt 4", 50 [TT_EXTINT | 0x5] = "External Interrupt 5", 51 [TT_EXTINT | 0x6] = "External Interrupt 6", 52 [TT_EXTINT | 0x7] = "External Interrupt 7", 53 [TT_EXTINT | 0x8] = "External Interrupt 8", 54 [TT_EXTINT | 0x9] = "External Interrupt 9", 55 [TT_EXTINT | 0xa] = "External Interrupt 10", 56 [TT_EXTINT | 0xb] = "External Interrupt 11", 57 [TT_EXTINT | 0xc] = "External Interrupt 12", 58 [TT_EXTINT | 0xd] = "External Interrupt 13", 59 [TT_EXTINT | 0xe] = "External Interrupt 14", 60 [TT_EXTINT | 0xf] = "External Interrupt 15", 61 }; 62 #endif 63 64 void sparc_cpu_do_interrupt(CPUState *cs) 65 { 66 SPARCCPU *cpu = SPARC_CPU(cs); 67 CPUSPARCState *env = &cpu->env; 68 int intno = cs->exception_index; 69 trap_state *tsptr; 70 71 /* Compute PSR before exposing state. */ 72 if (env->cc_op != CC_OP_FLAGS) { 73 cpu_get_psr(env); 74 } 75 76 #ifdef DEBUG_PCALL 77 if (qemu_loglevel_mask(CPU_LOG_INT)) { 78 static int count; 79 const char *name; 80 81 if (intno < 0 || intno >= 0x180) { 82 name = "Unknown"; 83 } else if (intno >= 0x100) { 84 name = "Trap Instruction"; 85 } else if (intno >= 0xc0) { 86 name = "Window Fill"; 87 } else if (intno >= 0x80) { 88 name = "Window Spill"; 89 } else { 90 name = excp_names[intno]; 91 if (!name) { 92 name = "Unknown"; 93 } 94 } 95 96 qemu_log("%6d: %s (v=%04x)\n", count, name, intno); 97 log_cpu_state(cs, 0); 98 #if 0 99 { 100 int i; 101 uint8_t *ptr; 102 103 qemu_log(" code="); 104 ptr = (uint8_t *)env->pc; 105 for (i = 0; i < 16; i++) { 106 qemu_log(" %02x", ldub(ptr + i)); 107 } 108 qemu_log("\n"); 109 } 110 #endif 111 count++; 112 } 113 #endif 114 #if !defined(CONFIG_USER_ONLY) 115 if (env->tl >= env->maxtl) { 116 cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," 117 " Error state", cs->exception_index, env->tl, env->maxtl); 118 return; 119 } 120 #endif 121 if (env->tl < env->maxtl - 1) { 122 env->tl++; 123 } else { 124 env->pstate |= PS_RED; 125 if (env->tl < env->maxtl) { 126 env->tl++; 127 } 128 } 129 tsptr = cpu_tsptr(env); 130 131 tsptr->tstate = (cpu_get_ccr(env) << 32) | 132 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | 133 cpu_get_cwp64(env); 134 tsptr->tpc = env->pc; 135 tsptr->tnpc = env->npc; 136 tsptr->tt = intno; 137 138 switch (intno) { 139 case TT_IVEC: 140 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG); 141 break; 142 case TT_TFAULT: 143 case TT_DFAULT: 144 case TT_TMISS ... TT_TMISS + 3: 145 case TT_DMISS ... TT_DMISS + 3: 146 case TT_DPROT ... TT_DPROT + 3: 147 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG); 148 break; 149 default: 150 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG); 151 break; 152 } 153 154 if (intno == TT_CLRWIN) { 155 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1)); 156 } else if ((intno & 0x1c0) == TT_SPILL) { 157 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); 158 } else if ((intno & 0x1c0) == TT_FILL) { 159 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1)); 160 } 161 env->pc = env->tbr & ~0x7fffULL; 162 env->pc |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); 163 env->npc = env->pc + 4; 164 cs->exception_index = -1; 165 } 166 167 trap_state *cpu_tsptr(CPUSPARCState* env) 168 { 169 return &env->ts[env->tl & MAXTL_MASK]; 170 } 171 172 static bool do_modify_softint(CPUSPARCState *env, uint32_t value) 173 { 174 if (env->softint != value) { 175 env->softint = value; 176 #if !defined(CONFIG_USER_ONLY) 177 if (cpu_interrupts_enabled(env)) { 178 cpu_check_irqs(env); 179 } 180 #endif 181 return true; 182 } 183 return false; 184 } 185 186 void helper_set_softint(CPUSPARCState *env, uint64_t value) 187 { 188 if (do_modify_softint(env, env->softint | (uint32_t)value)) { 189 trace_int_helper_set_softint(env->softint); 190 } 191 } 192 193 void helper_clear_softint(CPUSPARCState *env, uint64_t value) 194 { 195 if (do_modify_softint(env, env->softint & (uint32_t)~value)) { 196 trace_int_helper_clear_softint(env->softint); 197 } 198 } 199 200 void helper_write_softint(CPUSPARCState *env, uint64_t value) 201 { 202 if (do_modify_softint(env, (uint32_t)value)) { 203 trace_int_helper_write_softint(env->softint); 204 } 205 } 206